From nobody Sun Nov 10 21:21:45 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id D61CBC74A5B for ; Fri, 17 Mar 2023 08:12:44 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231451AbjCQIMm (ORCPT ); Fri, 17 Mar 2023 04:12:42 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:35380 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231355AbjCQIMQ (ORCPT ); Fri, 17 Mar 2023 04:12:16 -0400 Received: from mailgw01.mediatek.com (unknown [60.244.123.138]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 1BE03D5152; Fri, 17 Mar 2023 01:11:29 -0700 (PDT) X-UUID: 3781f7b4c49b11ed91027fb02e0f1d65-20230317 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=mMpfXTEQJ9Ytroylcl1siFLt80SppSy24Prqwo7sAbE=; b=o4TI7kp7c+8QU3LFhgYsv6ARjiglo/IvSsxVqZzngJcKYPclG+9zGTrmIarMpjn0troBttqcuvZG+R+EeLWJrhf0O9jiRp4HVchnxf7pTzwyT8QK0GLy6QoPKPMoNyDNnUAkM87z4RjYEZPdmOvRe6fI73d2f22aI2vjMOtEBsA=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.21,REQID:1c53ea38-01c1-43b0-81a4-d6f64839eb98,IP:0,U RL:0,TC:0,Content:-25,EDM:0,RT:0,SF:95,FILE:0,BULK:0,RULE:Release_Ham,ACTI ON:release,TS:70 X-CID-INFO: VERSION:1.1.21,REQID:1c53ea38-01c1-43b0-81a4-d6f64839eb98,IP:0,URL :0,TC:0,Content:-25,EDM:0,RT:0,SF:95,FILE:0,BULK:0,RULE:Spam_GS981B3D,ACTI ON:quarantine,TS:70 X-CID-META: VersionHash:83295aa,CLOUDID:7033ac28-564d-42d9-9875-7c868ee415ec,B ulkID:230317161047NHITUCQG,BulkQuantity:0,Recheck:0,SF:38|29|28|17|19|48,T C:nil,Content:0,EDM:-3,IP:nil,URL:11|1,File:nil,Bulk:nil,QS:nil,BEC:nil,CO L:0,OSI:0,OSA:0,AV:0 X-CID-BVR: 0,NGT X-CID-BAS: 0,NGT,0,_ X-UUID: 3781f7b4c49b11ed91027fb02e0f1d65-20230317 Received: from mtkmbs10n1.mediatek.inc [(172.21.101.34)] by mailgw01.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 2028494913; Fri, 17 Mar 2023 16:10:44 +0800 Received: from mtkmbs11n2.mediatek.inc (172.21.101.187) by mtkmbs13n2.mediatek.inc (172.21.101.108) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.25; Fri, 17 Mar 2023 16:10:43 +0800 Received: from mcddlt001.gcn.mediatek.inc (10.19.240.15) by mtkmbs11n2.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.1118.25 via Frontend Transport; Fri, 17 Mar 2023 16:10:41 +0800 From: Yanchao Yang To: Loic Poulain , Sergey Ryazanov , Johannes Berg , "David S . Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , netdev ML , kernel ML CC: Intel experts , Chetan , MTK ML , Liang Lu , Haijun Liu , Hua Yang , Ting Wang , Felix Chen , Mingliang Xu , Min Dong , Aiden Wang , Guohao Zhang , Chris Feng , Yanchao Yang , Lambert Wang , Mingchuang Qiao , Xiayu Zhang , Haozhe Chang Subject: [PATCH net-next v4 01/10] net: wwan: tmi: Add PCIe core Date: Fri, 17 Mar 2023 16:09:33 +0800 Message-ID: <20230317080942.183514-2-yanchao.yang@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20230317080942.183514-1-yanchao.yang@mediatek.com> References: <20230317080942.183514-1-yanchao.yang@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Registers the TMI device driver with the kernel. Set up all the fundamental configurations for the device: PCIe layer, Modem Host Cross Core Interface (MHCCIF), Reset Generation Unit (RGU), modem common control operations and build infrastructure. * PCIe layer code implements driver probe and removal, MSI-X interrupt initialization and de-initialization, and the way of resetting the device. * MHCCIF provides interrupt channels to communicate events such as handshak= e, PM and port enumeration. * RGU provides interrupt channels to generate notifications from the device so that the TMI driver could get the device reset. * Modem common control operations provide the basic read/write functions of the device's hardware registers, mask/unmask/get/clear functions of the device's interrupt registers and inquiry functions of the device's status. Signed-off-by: Yanchao Yang Signed-off-by: Ting Wang --- drivers/net/wwan/Kconfig | 14 + drivers/net/wwan/Makefile | 1 + drivers/net/wwan/mediatek/Makefile | 8 + drivers/net/wwan/mediatek/mtk_dev.h | 203 ++++++ drivers/net/wwan/mediatek/pcie/mtk_pci.c | 887 +++++++++++++++++++++++ drivers/net/wwan/mediatek/pcie/mtk_pci.h | 144 ++++ drivers/net/wwan/mediatek/pcie/mtk_reg.h | 69 ++ 7 files changed, 1326 insertions(+) create mode 100644 drivers/net/wwan/mediatek/Makefile create mode 100644 drivers/net/wwan/mediatek/mtk_dev.h create mode 100644 drivers/net/wwan/mediatek/pcie/mtk_pci.c create mode 100644 drivers/net/wwan/mediatek/pcie/mtk_pci.h create mode 100644 drivers/net/wwan/mediatek/pcie/mtk_reg.h diff --git a/drivers/net/wwan/Kconfig b/drivers/net/wwan/Kconfig index 410b0245114e..085562aa8682 100644 --- a/drivers/net/wwan/Kconfig +++ b/drivers/net/wwan/Kconfig @@ -120,6 +120,20 @@ config MTK_T7XX =20 If unsure, say N. =20 +config MTK_TMI + tristate "TMI Driver for Mediatek T-series Device" + depends on (PCI && ACPI) + select RELAY if WWAN_DEBUGFS + help + This driver enables Mediatek T-series WWAN Device communication. + The TMI is intended for t8xx T-series modem chips. Currently, t7xx + is not supported. + + If you have one of those Mediatek T-series WWAN Modules and wish to + use it in Linux say Y/M here. + + If unsure, say N. + endif # WWAN =20 endmenu diff --git a/drivers/net/wwan/Makefile b/drivers/net/wwan/Makefile index 3960c0ae2445..198d8074851f 100644 --- a/drivers/net/wwan/Makefile +++ b/drivers/net/wwan/Makefile @@ -14,3 +14,4 @@ obj-$(CONFIG_QCOM_BAM_DMUX) +=3D qcom_bam_dmux.o obj-$(CONFIG_RPMSG_WWAN_CTRL) +=3D rpmsg_wwan_ctrl.o obj-$(CONFIG_IOSM) +=3D iosm/ obj-$(CONFIG_MTK_T7XX) +=3D t7xx/ +obj-$(CONFIG_MTK_TMI) +=3D mediatek/ diff --git a/drivers/net/wwan/mediatek/Makefile b/drivers/net/wwan/mediatek= /Makefile new file mode 100644 index 000000000000..b74192eee432 --- /dev/null +++ b/drivers/net/wwan/mediatek/Makefile @@ -0,0 +1,8 @@ +# SPDX-License-Identifier: BSD-3-Clause-Clear + +MODULE_NAME :=3D mtk_tmi + +mtk_tmi-y =3D \ + pcie/mtk_pci.o + +obj-$(CONFIG_MTK_TMI) +=3D mtk_tmi.o diff --git a/drivers/net/wwan/mediatek/mtk_dev.h b/drivers/net/wwan/mediate= k/mtk_dev.h new file mode 100644 index 000000000000..acda9ccf05f1 --- /dev/null +++ b/drivers/net/wwan/mediatek/mtk_dev.h @@ -0,0 +1,203 @@ +/* SPDX-License-Identifier: BSD-3-Clause-Clear + * + * Copyright (c) 2022, MediaTek Inc. + */ + +#ifndef __MTK_DEV_H__ +#define __MTK_DEV_H__ + +#include +#include + +#define MTK_DEV_STR_LEN 16 + +enum mtk_irq_src { + MTK_IRQ_SRC_MIN, + MTK_IRQ_SRC_MHCCIF, + MTK_IRQ_SRC_SAP_RGU, + MTK_IRQ_SRC_DPMAIF, + MTK_IRQ_SRC_DPMAIF2, + MTK_IRQ_SRC_CLDMA0, + MTK_IRQ_SRC_CLDMA1, + MTK_IRQ_SRC_CLDMA2, + MTK_IRQ_SRC_CLDMA3, + MTK_IRQ_SRC_PM_LOCK, + MTK_IRQ_SRC_DPMAIF3, + MTK_IRQ_SRC_MAX +}; + +enum mtk_user_id { + MTK_USER_HW, + MTK_USER_CTRL, + MTK_USER_DPMAIF, + MTK_USER_PM, + MTK_USER_EXCEPT, + MTK_USER_MAX +}; + +enum mtk_l1ss_grp { + L1SS_PM, + L1SS_EXT_EVT, +}; + +#define L1SS_BIT_L1(grp) BIT(((grp) << 2) + 1) +#define L1SS_BIT_L1_1(grp) BIT(((grp) << 2) + 2) +#define L1SS_BIT_L1_2(grp) BIT(((grp) << 2) + 3) + +struct mtk_md_dev; + +/** + * struct mtk_hw_ops - The HW layer operations provided to transaction lay= er. + * @read32: Callback to read 32-bit register. + * Read value from MD. For PCIe, it's BAR 2/3 MMIO read. + * @write32: Callback to write 32-bit register. + * Write value to MD. For PCIe, it's BAR 2/3 MMIO write. + * @get_dev_state: Callback to get the device's state. + * @ack_dev_state: Callback to acknowledge device state. + * @get_irq_id: Callback to get the irq id specific IP on a chip. + * @get_virq_id: Callback to get the system virtual IRQ. + * @register_irq: Callback to register callback function to specific har= dware IP. + * @unregister_irq: Callback to unregister callback function to specific h= ardware IP. + * @mask_irq: Callback to mask the interrupt of specific hardware IP. + * @unmask_irq: Callback to unmask the interrupt of specific hardware = IP. + * @clear_irq: Callback to clear the interrupt of specific hardware I= P. + * @register_ext_evt:Callback to register HW Layer external event. + * @unregister_ext_evt:Callback to unregister HW Layer external event. + * @mask_ext_evt: Callback to mask HW Layer external event. + * @unmask_ext_evt: Callback to unmask HW Layer external event. + * @clear_ext_evt: Callback to clear HW Layer external event status. + * @send_ext_evt: Callback to send HW Layer external event. + * @get_ext_evt_status:Callback to get HW Layer external event status. + * @get_hp_status: Callback to get link hotplug status. + */ +struct mtk_hw_ops { + u32 (*read32)(struct mtk_md_dev *mdev, u64 addr); + void (*write32)(struct mtk_md_dev *mdev, u64 addr, u32 val); + u32 (*get_dev_state)(struct mtk_md_dev *mdev); + void (*ack_dev_state)(struct mtk_md_dev *mdev, u32 state); + int (*get_irq_id)(struct mtk_md_dev *mdev, enum mtk_irq_src irq_src); + int (*get_virq_id)(struct mtk_md_dev *mdev, int irq_id); + int (*register_irq)(struct mtk_md_dev *mdev, int irq_id, + int (*irq_cb)(int irq_id, void *data), void *data); + int (*unregister_irq)(struct mtk_md_dev *mdev, int irq_id); + int (*mask_irq)(struct mtk_md_dev *mdev, int irq_id); + int (*unmask_irq)(struct mtk_md_dev *mdev, int irq_id); + int (*clear_irq)(struct mtk_md_dev *mdev, int irq_id); + int (*register_ext_evt)(struct mtk_md_dev *mdev, u32 chs, + int (*evt_cb)(u32 status, void *data), void *data); + int (*unregister_ext_evt)(struct mtk_md_dev *mdev, u32 chs); + void (*mask_ext_evt)(struct mtk_md_dev *mdev, u32 chs); + void (*unmask_ext_evt)(struct mtk_md_dev *mdev, u32 chs); + void (*clear_ext_evt)(struct mtk_md_dev *mdev, u32 chs); + int (*send_ext_evt)(struct mtk_md_dev *mdev, u32 ch); + u32 (*get_ext_evt_status)(struct mtk_md_dev *mdev); + int (*get_hp_status)(struct mtk_md_dev *mdev); +}; + +struct mtk_md_dev { + struct device *dev; + const struct mtk_hw_ops *hw_ops; + void *hw_priv; + u32 hw_ver; + int msi_nvecs; + char dev_str[MTK_DEV_STR_LEN]; +}; + +static inline u32 mtk_hw_read32(struct mtk_md_dev *mdev, u64 addr) +{ + return mdev->hw_ops->read32(mdev, addr); +} + +static inline void mtk_hw_write32(struct mtk_md_dev *mdev, u64 addr, u32 v= al) +{ + mdev->hw_ops->write32(mdev, addr, val); +} + +static inline u32 mtk_hw_get_dev_state(struct mtk_md_dev *mdev) +{ + return mdev->hw_ops->get_dev_state(mdev); +} + +static inline void mtk_hw_ack_dev_state(struct mtk_md_dev *mdev, u32 state) +{ + mdev->hw_ops->ack_dev_state(mdev, state); +} + +static inline int mtk_hw_get_irq_id(struct mtk_md_dev *mdev, enum mtk_irq_= src irq_src) +{ + return mdev->hw_ops->get_irq_id(mdev, irq_src); +} + +static inline int mtk_hw_get_virq_id(struct mtk_md_dev *mdev, int irq_id) +{ + return mdev->hw_ops->get_virq_id(mdev, irq_id); +} + +static inline int mtk_hw_register_irq(struct mtk_md_dev *mdev, int irq_id, + int (*irq_cb)(int irq_id, void *data), void *data) +{ + return mdev->hw_ops->register_irq(mdev, irq_id, irq_cb, data); +} + +static inline int mtk_hw_unregister_irq(struct mtk_md_dev *mdev, int irq_i= d) +{ + return mdev->hw_ops->unregister_irq(mdev, irq_id); +} + +static inline int mtk_hw_mask_irq(struct mtk_md_dev *mdev, int irq_id) +{ + return mdev->hw_ops->mask_irq(mdev, irq_id); +} + +static inline int mtk_hw_unmask_irq(struct mtk_md_dev *mdev, int irq_id) +{ + return mdev->hw_ops->unmask_irq(mdev, irq_id); +} + +static inline int mtk_hw_clear_irq(struct mtk_md_dev *mdev, int irq_id) +{ + return mdev->hw_ops->clear_irq(mdev, irq_id); +} + +static inline int mtk_hw_register_ext_evt(struct mtk_md_dev *mdev, u32 chs, + int (*evt_cb)(u32 status, void *data), void *data) +{ + return mdev->hw_ops->register_ext_evt(mdev, chs, evt_cb, data); +} + +static inline int mtk_hw_unregister_ext_evt(struct mtk_md_dev *mdev, u32 c= hs) +{ + return mdev->hw_ops->unregister_ext_evt(mdev, chs); +} + +static inline void mtk_hw_mask_ext_evt(struct mtk_md_dev *mdev, u32 chs) +{ + mdev->hw_ops->mask_ext_evt(mdev, chs); +} + +static inline void mtk_hw_unmask_ext_evt(struct mtk_md_dev *mdev, u32 chs) +{ + mdev->hw_ops->unmask_ext_evt(mdev, chs); +} + +static inline void mtk_hw_clear_ext_evt(struct mtk_md_dev *mdev, u32 chs) +{ + mdev->hw_ops->clear_ext_evt(mdev, chs); +} + +static inline int mtk_hw_send_ext_evt(struct mtk_md_dev *mdev, u32 ch) +{ + return mdev->hw_ops->send_ext_evt(mdev, ch); +} + +static inline u32 mtk_hw_get_ext_evt_status(struct mtk_md_dev *mdev) +{ + return mdev->hw_ops->get_ext_evt_status(mdev); +} + +static inline int mtk_hw_get_hp_status(struct mtk_md_dev *mdev) +{ + return mdev->hw_ops->get_hp_status(mdev); +} + +#endif /* __MTK_DEV_H__ */ diff --git a/drivers/net/wwan/mediatek/pcie/mtk_pci.c b/drivers/net/wwan/me= diatek/pcie/mtk_pci.c new file mode 100644 index 000000000000..f8590d7319a8 --- /dev/null +++ b/drivers/net/wwan/mediatek/pcie/mtk_pci.c @@ -0,0 +1,887 @@ +// SPDX-License-Identifier: BSD-3-Clause-Clear +/* + * Copyright (c) 2022, MediaTek Inc. + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +#include "mtk_pci.h" +#include "mtk_reg.h" + +#define MTK_PCI_TRANSPARENT_ATR_SIZE (0x3F) + +static u32 mtk_pci_mac_read32(struct mtk_pci_priv *priv, u64 addr) +{ + return ioread32(priv->mac_reg_base + addr); +} + +static void mtk_pci_mac_write32(struct mtk_pci_priv *priv, u64 addr, u32 v= al) +{ + iowrite32(val, priv->mac_reg_base + addr); +} + +static void mtk_pci_set_msix_merged(struct mtk_pci_priv *priv, int irq_cnt) +{ + mtk_pci_mac_write32(priv, REG_PCIE_CFG_MSIX, ffs(irq_cnt) * 2 - 1); +} + +static int mtk_pci_setup_atr(struct mtk_md_dev *mdev, struct mtk_atr_cfg *= cfg) +{ + struct mtk_pci_priv *priv =3D mdev->hw_priv; + u32 addr, val, size_h, size_l; + int atr_size, pos, offset; + + if (cfg->transparent) { + atr_size =3D MTK_PCI_TRANSPARENT_ATR_SIZE; /* No address conversion is p= erformed */ + } else { + if (cfg->src_addr & (cfg->size - 1)) { + dev_err(mdev->dev, "Invalid atr src addr is not aligned to size\n"); + return -EFAULT; + } + if (cfg->trsl_addr & (cfg->size - 1)) { + dev_err(mdev->dev, + "Invalid atr trsl addr is not aligned to size, %llx, %llx\n", + cfg->trsl_addr, + cfg->size - 1); + return -EFAULT; + } + + size_l =3D FIELD_GET(GENMASK_ULL(31, 0), cfg->size); + size_h =3D FIELD_GET(GENMASK_ULL(63, 32), cfg->size); + + pos =3D ffs(size_l); + if (pos) { + /* Address Translate Space Size is equal to 2^(atr_size+1). + * "-2" means "-1-1", the first "-1" is because of the atr_size registe= r, + * the second is because of the ffs() will increase by one. + */ + atr_size =3D pos - 2; + } else { + pos =3D ffs(size_h); + /* "+30" means "+32-1-1", the meaning of "-1-1" is same as above, + * "+32" is because atr_size is large, exceeding 32-bits. + */ + atr_size =3D pos + 30; + } + } + + /* Calculate table offset */ + offset =3D ATR_PORT_OFFSET * cfg->port + ATR_TABLE_OFFSET * cfg->table; + /* SRC_ADDR_H */ + addr =3D REG_ATR_PCIE_WIN0_T0_SRC_ADDR_MSB + offset; + val =3D (u32)(cfg->src_addr >> 32); + mtk_pci_mac_write32(priv, addr, val); + /* SRC_ADDR_L */ + addr =3D REG_ATR_PCIE_WIN0_T0_SRC_ADDR_LSB + offset; + val =3D (u32)(cfg->src_addr & 0xFFFFF000) | (atr_size << 1) | 0x1; + mtk_pci_mac_write32(priv, addr, val); + + /* TRSL_ADDR_H */ + addr =3D REG_ATR_PCIE_WIN0_T0_TRSL_ADDR_MSB + offset; + val =3D (u32)(cfg->trsl_addr >> 32); + mtk_pci_mac_write32(priv, addr, val); + /* TRSL_ADDR_L */ + addr =3D REG_ATR_PCIE_WIN0_T0_TRSL_ADDR_LSB + offset; + val =3D (u32)(cfg->trsl_addr & 0xFFFFF000); + mtk_pci_mac_write32(priv, addr, val); + + /* TRSL_PARAM */ + addr =3D REG_ATR_PCIE_WIN0_T0_TRSL_PARAM + offset; + val =3D (cfg->trsl_param << 16) | cfg->trsl_id; + mtk_pci_mac_write32(priv, addr, val); + + return 0; +} + +static void mtk_pci_atr_disable(struct mtk_pci_priv *priv) +{ + int port, tbl, offset; + + /* Disable all ATR table for all ports */ + for (port =3D ATR_SRC_PCI_WIN0; port <=3D ATR_SRC_AXIS_3; port++) + for (tbl =3D 0; tbl < ATR_TABLE_NUM_PER_ATR; tbl++) { + /* Calculate table offset */ + offset =3D ATR_PORT_OFFSET * port + ATR_TABLE_OFFSET * tbl; + /* Disable table by SRC_ADDR_L */ + mtk_pci_mac_write32(priv, REG_ATR_PCIE_WIN0_T0_SRC_ADDR_LSB + offset, 0= ); + } +} + +static int mtk_pci_atr_init(struct mtk_md_dev *mdev) +{ + struct pci_dev *pdev =3D to_pci_dev(mdev->dev); + struct mtk_pci_priv *priv =3D mdev->hw_priv; + struct mtk_atr_cfg cfg; + int port, ret; + + mtk_pci_atr_disable(priv); + + /* Config ATR for RC to access device's register */ + cfg.src_addr =3D pci_resource_start(pdev, MTK_BAR_2_3_IDX); + cfg.size =3D ATR_PCIE_REG_SIZE; + cfg.trsl_addr =3D ATR_PCIE_REG_TRSL_ADDR; + cfg.type =3D ATR_PCI2AXI; + cfg.port =3D ATR_PCIE_REG_PORT; + cfg.table =3D ATR_PCIE_REG_TABLE_NUM; + cfg.trsl_id =3D ATR_PCIE_REG_TRSL_PORT; + cfg.trsl_param =3D 0x0; + cfg.transparent =3D 0x0; + ret =3D mtk_pci_setup_atr(mdev, &cfg); + if (ret) + return ret; + + /* Config ATR for MHCCIF */ + cfg.src_addr =3D pci_resource_start(pdev, MTK_BAR_2_3_IDX); + cfg.src_addr +=3D priv->cfg->mhccif_rc_base_addr - ATR_PCIE_REG_TRSL_ADDR; + cfg.size =3D priv->cfg->mhccif_trsl_size; + cfg.trsl_addr =3D priv->cfg->mhccif_rc_reg_trsl_addr; + cfg.type =3D ATR_PCI2AXI; + cfg.port =3D ATR_PCIE_REG_PORT; + cfg.table =3D ART_PCIE_REG_MHCCIF_TABLE_NUM; + cfg.trsl_id =3D ATR_PCIE_REG_TRSL_PORT; + cfg.trsl_param =3D 0x0; + cfg.transparent =3D 0x0; + ret =3D mtk_pci_setup_atr(mdev, &cfg); + if (ret) + return ret; + + /* Config ATR for EP to access RC's memory */ + for (port =3D ATR_PCIE_DEV_DMA_PORT_START; port <=3D ATR_PCIE_DEV_DMA_POR= T_END; port++) { + cfg.src_addr =3D ATR_PCIE_DEV_DMA_SRC_ADDR; + cfg.size =3D ATR_PCIE_DEV_DMA_SIZE; + cfg.trsl_addr =3D ATR_PCIE_DEV_DMA_TRSL_ADDR; + cfg.type =3D ATR_AXI2PCI; + cfg.port =3D port; + cfg.table =3D ATR_PCIE_DEV_DMA_TABLE_NUM; + cfg.trsl_id =3D ATR_DST_PCI_TRX; + cfg.trsl_param =3D 0x0; + /* Enable transparent translation */ + cfg.transparent =3D ATR_PCIE_DEV_DMA_TRANSPARENT; + ret =3D mtk_pci_setup_atr(mdev, &cfg); + if (ret) + return ret; + } + + return 0; +} + +static u32 mtk_pci_read32(struct mtk_md_dev *mdev, u64 addr) +{ + struct mtk_pci_priv *priv =3D mdev->hw_priv; + + return ioread32(priv->ext_reg_base + addr); +} + +static void mtk_pci_write32(struct mtk_md_dev *mdev, u64 addr, u32 val) +{ + struct mtk_pci_priv *priv =3D mdev->hw_priv; + + iowrite32(val, priv->ext_reg_base + addr); +} + +static u32 mtk_pci_get_dev_state(struct mtk_md_dev *mdev) +{ + return mtk_pci_mac_read32(mdev->hw_priv, REG_PCIE_DEBUG_DUMMY_7); +} + +static void mtk_pci_ack_dev_state(struct mtk_md_dev *mdev, u32 state) +{ + mtk_pci_mac_write32(mdev->hw_priv, REG_PCIE_DEBUG_DUMMY_7, state); +} + +static int mtk_pci_get_irq_id(struct mtk_md_dev *mdev, enum mtk_irq_src ir= q_src) +{ + struct mtk_pci_priv *priv =3D mdev->hw_priv; + const int *irq_tbl =3D priv->cfg->irq_tbl; + int irq_id =3D -EINVAL; + + if (irq_src > MTK_IRQ_SRC_MIN && irq_src < MTK_IRQ_SRC_MAX) { + irq_id =3D irq_tbl[irq_src]; + if (unlikely(irq_id < 0 || irq_id >=3D MTK_IRQ_CNT_MAX)) + irq_id =3D -EINVAL; + } + + return irq_id; +} + +static int mtk_pci_get_virq_id(struct mtk_md_dev *mdev, int irq_id) +{ + struct pci_dev *pdev =3D to_pci_dev(mdev->dev); + int nr =3D 0; + + if (pdev->msix_enabled) + nr =3D irq_id % mdev->msi_nvecs; + + return pci_irq_vector(pdev, nr); +} + +static int mtk_pci_register_irq(struct mtk_md_dev *mdev, int irq_id, + int (*irq_cb)(int irq_id, void *data), void *data) +{ + struct mtk_pci_priv *priv =3D mdev->hw_priv; + + if (unlikely((irq_id < 0 || irq_id >=3D MTK_IRQ_CNT_MAX) || !irq_cb)) + return -EINVAL; + + if (priv->irq_cb_list[irq_id]) { + dev_err(mdev->dev, + "Unable to register irq, irq_id=3D%d, it's already been register by %ps= .\n", + irq_id, priv->irq_cb_list[irq_id]); + return -EFAULT; + } + priv->irq_cb_list[irq_id] =3D irq_cb; + priv->irq_cb_data[irq_id] =3D data; + + return 0; +} + +static int mtk_pci_unregister_irq(struct mtk_md_dev *mdev, int irq_id) +{ + struct mtk_pci_priv *priv =3D mdev->hw_priv; + + if (unlikely(irq_id < 0 || irq_id >=3D MTK_IRQ_CNT_MAX)) + return -EINVAL; + + if (!priv->irq_cb_list[irq_id]) { + dev_err(mdev->dev, "irq_id=3D%d has not been registered\n", irq_id); + return -EFAULT; + } + priv->irq_cb_list[irq_id] =3D NULL; + priv->irq_cb_data[irq_id] =3D NULL; + + return 0; +} + +static int mtk_pci_mask_irq(struct mtk_md_dev *mdev, int irq_id) +{ + struct mtk_pci_priv *priv =3D mdev->hw_priv; + + if (unlikely((irq_id < 0 || irq_id >=3D MTK_IRQ_CNT_MAX) || priv->irq_typ= e !=3D PCI_IRQ_MSIX)) { + dev_err(mdev->dev, "Failed to mask irq: input irq_id=3D%d\n", irq_id); + return -EINVAL; + } + + mtk_pci_mac_write32(priv, REG_IMASK_HOST_MSIX_CLR_GRP0_0, BIT(irq_id)); + + return 0; +} + +static int mtk_pci_unmask_irq(struct mtk_md_dev *mdev, int irq_id) +{ + struct mtk_pci_priv *priv =3D mdev->hw_priv; + + if (unlikely((irq_id < 0 || irq_id >=3D MTK_IRQ_CNT_MAX) || priv->irq_typ= e !=3D PCI_IRQ_MSIX)) { + dev_err(mdev->dev, "Failed to unmask irq: input irq_id=3D%d\n", irq_id); + return -EINVAL; + } + + mtk_pci_mac_write32(priv, REG_IMASK_HOST_MSIX_SET_GRP0_0, BIT(irq_id)); + + return 0; +} + +static int mtk_pci_clear_irq(struct mtk_md_dev *mdev, int irq_id) +{ + struct mtk_pci_priv *priv =3D mdev->hw_priv; + + if (unlikely((irq_id < 0 || irq_id >=3D MTK_IRQ_CNT_MAX) || priv->irq_typ= e !=3D PCI_IRQ_MSIX)) { + dev_err(mdev->dev, "Failed to clear irq: input irq_id=3D%d\n", irq_id); + return -EINVAL; + } + + mtk_pci_mac_write32(priv, REG_MSIX_ISTATUS_HOST_GRP0_0, BIT(irq_id)); + + return 0; +} + +static int mtk_mhccif_register_evt(struct mtk_md_dev *mdev, u32 chs, + int (*evt_cb)(u32 status, void *data), void *data) +{ + struct mtk_pci_priv *priv =3D mdev->hw_priv; + struct mtk_mhccif_cb *cb; + unsigned long flag; + int ret =3D 0; + + if (!chs || !evt_cb) + return -EINVAL; + + spin_lock_irqsave(&priv->mhccif_lock, flag); + list_for_each_entry(cb, &priv->mhccif_cb_list, entry) { + if (cb->chs & chs) { + ret =3D -EFAULT; + dev_err(mdev->dev, + "Unable to register evt, chs=3D0x%08X&0x%08X registered_cb=3D%ps\n", + chs, cb->chs, cb->evt_cb); + goto err; + } + } + cb =3D devm_kzalloc(mdev->dev, sizeof(*cb), GFP_ATOMIC); + if (!cb) { + ret =3D -ENOMEM; + goto err; + } + cb->evt_cb =3D evt_cb; + cb->data =3D data; + cb->chs =3D chs; + list_add_tail(&cb->entry, &priv->mhccif_cb_list); + +err: + spin_unlock_irqrestore(&priv->mhccif_lock, flag); + + return ret; +} + +static int mtk_mhccif_unregister_evt(struct mtk_md_dev *mdev, u32 chs) +{ + struct mtk_pci_priv *priv =3D mdev->hw_priv; + struct mtk_mhccif_cb *cb, *next; + unsigned long flag; + int ret =3D 0; + + if (!chs) + return -EINVAL; + + spin_lock_irqsave(&priv->mhccif_lock, flag); + list_for_each_entry_safe(cb, next, &priv->mhccif_cb_list, entry) { + if (cb->chs =3D=3D chs) { + list_del(&cb->entry); + devm_kfree(mdev->dev, cb); + goto out; + } + } + ret =3D -EFAULT; + dev_warn(mdev->dev, "Unable to unregister evt, no chs=3D0x%08X has been r= egistered.\n", chs); +out: + spin_unlock_irqrestore(&priv->mhccif_lock, flag); + + return ret; +} + +static void mtk_mhccif_mask_evt(struct mtk_md_dev *mdev, u32 chs) +{ + struct mtk_pci_priv *priv =3D mdev->hw_priv; + + mtk_pci_write32(mdev, priv->cfg->mhccif_rc_base_addr + + MHCCIF_EP2RC_SW_INT_EAP_MASK_SET, chs); +} + +static void mtk_mhccif_unmask_evt(struct mtk_md_dev *mdev, u32 chs) +{ + struct mtk_pci_priv *priv =3D mdev->hw_priv; + + mtk_pci_write32(mdev, priv->cfg->mhccif_rc_base_addr + + MHCCIF_EP2RC_SW_INT_EAP_MASK_CLR, chs); +} + +static void mtk_mhccif_clear_evt(struct mtk_md_dev *mdev, u32 chs) +{ + struct mtk_pci_priv *priv =3D mdev->hw_priv; + + mtk_pci_write32(mdev, priv->cfg->mhccif_rc_base_addr + + MHCCIF_EP2RC_SW_INT_ACK, chs); +} + +static int mtk_mhccif_send_evt(struct mtk_md_dev *mdev, u32 ch) +{ + struct mtk_pci_priv *priv =3D mdev->hw_priv; + u32 rc_base; + + rc_base =3D priv->cfg->mhccif_rc_base_addr; + /* Only allow one ch to be triggered at a time */ + if ((ch & (ch - 1)) || !ch) { + dev_err(mdev->dev, "Unsupported ext evt ch=3D0x%08X\n", ch); + return -EINVAL; + } + + mtk_pci_write32(mdev, rc_base + MHCCIF_RC2EP_SW_BSY, ch); + mtk_pci_write32(mdev, rc_base + MHCCIF_RC2EP_SW_TCHNUM, ffs(ch) - 1); + + return 0; +} + +static u32 mtk_mhccif_get_evt_status(struct mtk_md_dev *mdev) +{ + struct mtk_pci_priv *priv =3D mdev->hw_priv; + + return mtk_pci_read32(mdev, priv->cfg->mhccif_rc_base_addr + MHCCIF_EP2RC= _SW_INT_STS); +} + +static int mtk_pci_acpi_reset(struct mtk_md_dev *mdev, char *fn_name) +{ +#ifdef CONFIG_ACPI + struct acpi_buffer buffer =3D { ACPI_ALLOCATE_BUFFER, NULL }; + acpi_status acpi_ret; + acpi_handle handle; + int ret =3D 0; + + handle =3D ACPI_HANDLE(mdev->dev); + if (!handle) { + dev_err(mdev->dev, "Unsupported, acpi handle isn't found\n"); + ret =3D -ENODEV; + goto err; + } + if (!acpi_has_method(handle, fn_name)) { + dev_err(mdev->dev, "Unsupported, _RST method isn't found\n"); + ret =3D -ENODEV; + goto err; + } + acpi_ret =3D acpi_evaluate_object(handle, fn_name, NULL, &buffer); + if (ACPI_FAILURE(acpi_ret)) { + dev_err(mdev->dev, "Failed to execute %s method: %s\n", + fn_name, + acpi_format_exception(acpi_ret)); + ret =3D -EFAULT; + goto err; + } + dev_info(mdev->dev, "FLDR execute successfully\n"); + acpi_os_free(buffer.pointer); +err: + return ret; +#else + dev_err(mdev->dev, "Unsupported, CONFIG ACPI hasn't been set to 'y'\n"); + return -ENODEV; +#endif +} + +static int mtk_pci_fldr(struct mtk_md_dev *mdev) +{ + return mtk_pci_acpi_reset(mdev, "_RST"); +} + +static bool mtk_pci_link_check(struct mtk_md_dev *mdev) +{ + return !pci_device_is_present(to_pci_dev(mdev->dev)); +} + +static int mtk_pci_get_hp_status(struct mtk_md_dev *mdev) +{ + struct mtk_pci_priv *priv =3D mdev->hw_priv; + + return priv->rc_hp_on; +} + +static const struct mtk_hw_ops mtk_pci_ops =3D { + .read32 =3D mtk_pci_read32, + .write32 =3D mtk_pci_write32, + .get_dev_state =3D mtk_pci_get_dev_state, + .ack_dev_state =3D mtk_pci_ack_dev_state, + .get_irq_id =3D mtk_pci_get_irq_id, + .get_virq_id =3D mtk_pci_get_virq_id, + .register_irq =3D mtk_pci_register_irq, + .unregister_irq =3D mtk_pci_unregister_irq, + .mask_irq =3D mtk_pci_mask_irq, + .unmask_irq =3D mtk_pci_unmask_irq, + .clear_irq =3D mtk_pci_clear_irq, + .register_ext_evt =3D mtk_mhccif_register_evt, + .unregister_ext_evt =3D mtk_mhccif_unregister_evt, + .mask_ext_evt =3D mtk_mhccif_mask_evt, + .unmask_ext_evt =3D mtk_mhccif_unmask_evt, + .clear_ext_evt =3D mtk_mhccif_clear_evt, + .send_ext_evt =3D mtk_mhccif_send_evt, + .get_ext_evt_status =3D mtk_mhccif_get_evt_status, + .get_hp_status =3D mtk_pci_get_hp_status, +}; + +static void mtk_mhccif_isr_work(struct work_struct *work) +{ + struct mtk_pci_priv *priv =3D container_of(work, struct mtk_pci_priv, mhc= cif_work); + struct mtk_md_dev *mdev =3D priv->irq_desc->mdev; + struct mtk_mhccif_cb *cb; + unsigned long flag; + u32 stat, mask; + + stat =3D mtk_mhccif_get_evt_status(mdev); + mask =3D mtk_pci_read32(mdev, priv->cfg->mhccif_rc_base_addr + + MHCCIF_EP2RC_SW_INT_EAP_MASK); + dev_dbg(mdev->dev, "External events: mhccif_stat=3D0x%08X mask=3D0x%08X\n= ", stat, mask); + + if (unlikely(stat =3D=3D U32_MAX && mtk_pci_link_check(mdev))) { + /* When link failed, we don't need to unmask/clear. */ + dev_err(mdev->dev, "Failed to check link in MHCCIF handler.\n"); + return; + } + + stat &=3D ~mask; + spin_lock_irqsave(&priv->mhccif_lock, flag); + list_for_each_entry(cb, &priv->mhccif_cb_list, entry) { + if (cb->chs & stat) + cb->evt_cb(cb->chs & stat, cb->data); + } + spin_unlock_irqrestore(&priv->mhccif_lock, flag); + + mtk_pci_clear_irq(mdev, priv->mhccif_irq_id); + mtk_pci_unmask_irq(mdev, priv->mhccif_irq_id); +} + +static const struct mtk_pci_dev_cfg mtk_dev_cfg_0800 =3D { + .mhccif_rc_base_addr =3D 0x10012000, + .mhccif_trsl_size =3D 0x2000, + .mhccif_rc_reg_trsl_addr =3D 0x12020000, + .istatus_host_ctrl_addr =3D REG_ISTATUS_HOST_CTRL_NEW, + .irq_tbl =3D { + [MTK_IRQ_SRC_DPMAIF] =3D 24, + [MTK_IRQ_SRC_CLDMA0] =3D 25, + [MTK_IRQ_SRC_CLDMA1] =3D 26, + [MTK_IRQ_SRC_CLDMA2] =3D 27, + [MTK_IRQ_SRC_MHCCIF] =3D 28, + [MTK_IRQ_SRC_DPMAIF2] =3D 29, + [MTK_IRQ_SRC_SAP_RGU] =3D 30, + [MTK_IRQ_SRC_CLDMA3] =3D 31, + [MTK_IRQ_SRC_PM_LOCK] =3D 0, + [MTK_IRQ_SRC_DPMAIF3] =3D 7, + }, +}; + +static const struct pci_device_id mtk_pci_ids[] =3D { + MTK_PCI_DEV_CFG(0x0800, mtk_dev_cfg_0800), + { /* end: all zeroes */ } +}; +MODULE_DEVICE_TABLE(pci, mtk_pci_ids); + +static int mtk_pci_bar_init(struct mtk_md_dev *mdev) +{ + struct pci_dev *pdev =3D to_pci_dev(mdev->dev); + struct mtk_pci_priv *priv =3D mdev->hw_priv; + int ret; + + ret =3D pcim_iomap_regions(pdev, MTK_REQUESTED_BARS, mdev->dev_str); + if (ret) { + dev_err(mdev->dev, "Failed to init MMIO. ret=3D%d\n", ret); + return ret; + } + + /* get ioremapped memory */ + priv->mac_reg_base =3D pcim_iomap_table(pdev)[MTK_BAR_0_1_IDX]; + priv->bar23_addr =3D pcim_iomap_table(pdev)[MTK_BAR_2_3_IDX]; + dev_info(mdev->dev, "BAR0/1 Addr=3D0x%p, BAR2/3 Addr=3D0x%p\n", + priv->mac_reg_base, priv->bar23_addr); + /* We use MD view base address "0" to observe registers */ + priv->ext_reg_base =3D priv->bar23_addr - ATR_PCIE_REG_TRSL_ADDR; + + return 0; +} + +static void mtk_pci_bar_exit(struct mtk_md_dev *mdev) +{ + pcim_iounmap_regions(to_pci_dev(mdev->dev), MTK_REQUESTED_BARS); +} + +static int mtk_mhccif_irq_cb(int irq_id, void *data) +{ + struct mtk_md_dev *mdev =3D data; + struct mtk_pci_priv *priv; + + priv =3D mdev->hw_priv; + queue_work(system_highpri_wq, &priv->mhccif_work); + + return 0; +} + +static int mtk_mhccif_init(struct mtk_md_dev *mdev) +{ + struct mtk_pci_priv *priv =3D mdev->hw_priv; + int ret; + + INIT_LIST_HEAD(&priv->mhccif_cb_list); + spin_lock_init(&priv->mhccif_lock); + INIT_WORK(&priv->mhccif_work, mtk_mhccif_isr_work); + + ret =3D mtk_pci_get_irq_id(mdev, MTK_IRQ_SRC_MHCCIF); + if (ret < 0) { + dev_err(mdev->dev, "Failed to get mhccif_irq_id. ret=3D%d\n", ret); + goto err; + } + priv->mhccif_irq_id =3D ret; + + ret =3D mtk_pci_register_irq(mdev, priv->mhccif_irq_id, mtk_mhccif_irq_cb= , mdev); + if (ret) { + dev_err(mdev->dev, "Failed to register mhccif_irq callback\n"); + goto err; + } + + /* To check if the device rebooted. + * The reboot of some PC doesn't cause the device power cycle. + */ + mtk_pci_read32(mdev, priv->cfg->mhccif_rc_base_addr + MHCCIF_EP2RC_SW_INT= _EAP_MASK); + +err: + return ret; +} + +static void mtk_mhccif_exit(struct mtk_md_dev *mdev) +{ + struct mtk_pci_priv *priv =3D mdev->hw_priv; + + mtk_pci_unregister_irq(mdev, priv->mhccif_irq_id); + cancel_work_sync(&priv->mhccif_work); +} + +static irqreturn_t mtk_pci_irq_handler(struct mtk_md_dev *mdev, u32 irq_st= ate) +{ + struct mtk_pci_priv *priv =3D mdev->hw_priv; + int irq_id; + + /* Check whether each set bit has a callback, if has, call it */ + do { + irq_id =3D fls(irq_state) - 1; + irq_state &=3D ~BIT(irq_id); + if (likely(priv->irq_cb_list[irq_id])) + priv->irq_cb_list[irq_id](irq_id, priv->irq_cb_data[irq_id]); + else + dev_err(mdev->dev, "Unhandled irq_id=3D%d, no callback for it.\n", irq_= id); + } while (irq_state); + + return IRQ_HANDLED; +} + +static irqreturn_t mtk_pci_irq_msix(int irq, void *data) +{ + struct mtk_pci_irq_desc *irq_desc =3D data; + struct mtk_md_dev *mdev =3D irq_desc->mdev; + struct mtk_pci_priv *priv; + u32 irq_state, irq_enable; + + priv =3D mdev->hw_priv; + irq_state =3D mtk_pci_mac_read32(priv, REG_MSIX_ISTATUS_HOST_GRP0_0); + irq_enable =3D mtk_pci_mac_read32(priv, REG_IMASK_HOST_MSIX_GRP0_0); + dev_dbg(mdev->dev, "irq_state=3D0x%08X, irq_enable=3D0x%08X, msix_bits=3D= 0x%08X\n", + irq_state, irq_enable, irq_desc->msix_bits); + irq_state &=3D irq_enable; + + if (unlikely(!irq_state) || + unlikely(!((irq_state % GENMASK(priv->irq_cnt - 1, 0)) & irq_desc->ms= ix_bits))) + return IRQ_NONE; + + /* Mask the bit and user needs to unmask by itself */ + mtk_pci_mac_write32(priv, REG_IMASK_HOST_MSIX_CLR_GRP0_0, irq_state & ~BI= T(30)); + + return mtk_pci_irq_handler(mdev, irq_state); +} + +static int mtk_pci_request_irq_msix(struct mtk_md_dev *mdev, int irq_cnt_a= llocated) +{ + struct mtk_pci_priv *priv =3D mdev->hw_priv; + struct mtk_pci_irq_desc *irq_desc; + struct pci_dev *pdev; + int irq_cnt; + int ret, i; + + /* calculate the nearest 2's power number */ + irq_cnt =3D BIT(fls(irq_cnt_allocated) - 1); + pdev =3D to_pci_dev(mdev->dev); + irq_desc =3D priv->irq_desc; + for (i =3D 0; i < irq_cnt; i++) { + irq_desc[i].mdev =3D mdev; + irq_desc[i].msix_bits =3D BIT(i); + snprintf(irq_desc[i].name, MTK_IRQ_NAME_LEN, "msix%d-%s", + i, pci_name(to_pci_dev(mdev->dev))); + ret =3D pci_request_irq(pdev, i, mtk_pci_irq_msix, NULL, + &irq_desc[i], irq_desc[i].name); + if (ret) { + dev_err(mdev->dev, "Failed to request %s: ret=3D%d\n", irq_desc[i].name= , ret); + for (i--; i >=3D 0; i--) + pci_free_irq(pdev, i, &irq_desc[i]); + return ret; + } + } + priv->irq_cnt =3D irq_cnt; + priv->irq_type =3D PCI_IRQ_MSIX; + + if (irq_cnt !=3D MTK_IRQ_CNT_MAX) + mtk_pci_set_msix_merged(priv, irq_cnt); + + return 0; +} + +static int mtk_pci_request_irq(struct mtk_md_dev *mdev) +{ + struct pci_dev *pdev =3D to_pci_dev(mdev->dev); + int irq_cnt; + + irq_cnt =3D pci_alloc_irq_vectors(pdev, MTK_IRQ_CNT_MIN, MTK_IRQ_CNT_MAX,= PCI_IRQ_MSIX); + mdev->msi_nvecs =3D irq_cnt; + + if (irq_cnt < MTK_IRQ_CNT_MIN) { + dev_err(mdev->dev, + "Unable to alloc pci irq vectors. ret=3D%d maxirqcnt=3D%d irqtype=3D0x%= x\n", + irq_cnt, MTK_IRQ_CNT_MAX, PCI_IRQ_MSIX); + return -EFAULT; + } + + return mtk_pci_request_irq_msix(mdev, irq_cnt); +} + +static void mtk_pci_free_irq(struct mtk_md_dev *mdev) +{ + struct pci_dev *pdev =3D to_pci_dev(mdev->dev); + struct mtk_pci_priv *priv =3D mdev->hw_priv; + int i; + + for (i =3D 0; i < priv->irq_cnt; i++) + pci_free_irq(pdev, i, &priv->irq_desc[i]); + + pci_free_irq_vectors(pdev); +} + +static int mtk_pci_probe(struct pci_dev *pdev, const struct pci_device_id = *id) +{ + struct device *dev =3D &pdev->dev; + struct mtk_pci_priv *priv; + struct mtk_md_dev *mdev; + int ret; + + mdev =3D devm_kzalloc(dev, sizeof(*mdev), GFP_KERNEL); + if (!mdev) { + ret =3D -ENOMEM; + goto exit; + } + + priv =3D devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); + if (!priv) { + ret =3D -ENOMEM; + goto free_cntx_data; + } + + pci_set_drvdata(pdev, mdev); + priv->cfg =3D (struct mtk_pci_dev_cfg *)id->driver_data; + priv->mdev =3D mdev; + mdev->hw_ver =3D pdev->device; + mdev->hw_ops =3D &mtk_pci_ops; + mdev->hw_priv =3D priv; + mdev->dev =3D dev; + snprintf(mdev->dev_str, MTK_DEV_STR_LEN, "%02x%02x%d", + pdev->bus->number, PCI_SLOT(pdev->devfn), PCI_FUNC(pdev->devfn)); + + dev_info(mdev->dev, "Start probe 0x%x, state_saved[%d]\n", + mdev->hw_ver, pdev->state_saved); + + if (pdev->state_saved) + pci_restore_state(pdev); + + /* enable host to device access. */ + ret =3D pcim_enable_device(pdev); + if (ret) { + dev_err(mdev->dev, "Failed to enable pci device.\n"); + goto free_priv_data; + } + + ret =3D dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64)); + if (ret) { + dev_err(mdev->dev, "Failed to set DMA Mask and Coherent. (ret=3D%d)\n", = ret); + goto disable_device; + } + + ret =3D mtk_pci_bar_init(mdev); + if (ret) + goto disable_device; + + ret =3D mtk_pci_atr_init(mdev); + if (ret) + goto free_bar; + + ret =3D mtk_mhccif_init(mdev); + if (ret) + goto free_bar; + + ret =3D mtk_pci_request_irq(mdev); + if (ret) + goto free_mhccif; + + /* enable device to host interrupt. */ + pci_set_master(pdev); + + mtk_pci_unmask_irq(mdev, priv->mhccif_irq_id); + + dev_info(mdev->dev, "Probe done hw_ver=3D0x%x\n", mdev->hw_ver); + return 0; + +free_mhccif: + mtk_mhccif_exit(mdev); +free_bar: + mtk_pci_bar_exit(mdev); +disable_device: + pci_disable_device(pdev); +free_priv_data: + devm_kfree(dev, priv); +free_cntx_data: + devm_kfree(dev, mdev); +exit: + + return ret; +} + +static void mtk_pci_remove(struct pci_dev *pdev) +{ + struct mtk_md_dev *mdev =3D pci_get_drvdata(pdev); + struct mtk_pci_priv *priv =3D mdev->hw_priv; + struct device *dev =3D &pdev->dev; + int ret; + + mtk_pci_mask_irq(mdev, priv->mhccif_irq_id); + + ret =3D mtk_pci_fldr(mdev); + if (ret) + mtk_mhccif_send_evt(mdev, EXT_EVT_H2D_DEVICE_RESET); + + pci_clear_master(pdev); + mtk_mhccif_exit(mdev); + mtk_pci_free_irq(mdev); + mtk_pci_bar_exit(mdev); + pci_disable_device(pdev); + pci_load_and_free_saved_state(pdev, &priv->saved_state); + devm_kfree(dev, priv); + devm_kfree(dev, mdev); + dev_info(dev, "Remove done, state_saved[%d]\n", pdev->state_saved); +} + +static pci_ers_result_t mtk_pci_error_detected(struct pci_dev *pdev, + pci_channel_state_t state) +{ + return PCI_ERS_RESULT_NEED_RESET; +} + +static pci_ers_result_t mtk_pci_slot_reset(struct pci_dev *pdev) +{ + return PCI_ERS_RESULT_RECOVERED; +} + +static void mtk_pci_io_resume(struct pci_dev *pdev) +{ +} + +static const struct pci_error_handlers mtk_pci_err_handler =3D { + .error_detected =3D mtk_pci_error_detected, + .slot_reset =3D mtk_pci_slot_reset, + .resume =3D mtk_pci_io_resume, +}; + +static struct pci_driver mtk_pci_drv =3D { + .name =3D "mtk_pci_drv", + .id_table =3D mtk_pci_ids, + + .probe =3D mtk_pci_probe, + .remove =3D mtk_pci_remove, + + .err_handler =3D &mtk_pci_err_handler +}; + +static int __init mtk_drv_init(void) +{ + return pci_register_driver(&mtk_pci_drv); +} +module_init(mtk_drv_init); + +static void __exit mtk_drv_exit(void) +{ + pci_unregister_driver(&mtk_pci_drv); +} +module_exit(mtk_drv_exit); + +MODULE_LICENSE("GPL"); diff --git a/drivers/net/wwan/mediatek/pcie/mtk_pci.h b/drivers/net/wwan/me= diatek/pcie/mtk_pci.h new file mode 100644 index 000000000000..b487ca9b302e --- /dev/null +++ b/drivers/net/wwan/mediatek/pcie/mtk_pci.h @@ -0,0 +1,144 @@ +/* SPDX-License-Identifier: BSD-3-Clause-Clear + * + * Copyright (c) 2022, MediaTek Inc. + */ + +#ifndef __MTK_PCI_H__ +#define __MTK_PCI_H__ + +#include +#include + +#include "../mtk_dev.h" + +enum mtk_atr_type { + ATR_PCI2AXI =3D 0, + ATR_AXI2PCI +}; + +enum mtk_atr_src_port { + ATR_SRC_PCI_WIN0 =3D 0, + ATR_SRC_AXIS_0 =3D 2, + ATR_SRC_AXIS_2 =3D 3, + ATR_SRC_AXIS_3 =3D 4, +}; + +enum mtk_atr_dst_port { + ATR_DST_PCI_TRX =3D 0, + ATR_DST_AXIM_0 =3D 4, +}; + +#define ATR_PORT_OFFSET 0x100 +#define ATR_TABLE_OFFSET 0x20 +#define ATR_TABLE_NUM_PER_ATR 8 +#define ATR_WIN0_SRC_ADDR_LSB_DEFT 0x0000007f +#define ATR_PCIE_REG_TRSL_ADDR 0x10000000 +#define ATR_PCIE_REG_SIZE 0x00400000 +#define ATR_PCIE_REG_PORT ATR_SRC_PCI_WIN0 +#define ATR_PCIE_REG_TABLE_NUM 1 +#define ART_PCIE_REG_MHCCIF_TABLE_NUM 0 +#define ATR_PCIE_REG_TRSL_PORT ATR_DST_AXIM_0 +#define ATR_PCIE_DEV_DMA_PORT_START ATR_SRC_AXIS_0 +#define ATR_PCIE_DEV_DMA_PORT_END ATR_SRC_AXIS_2 +#define ATR_PCIE_DEV_DMA_SRC_ADDR 0x00000000 +#define ATR_PCIE_DEV_DMA_TRANSPARENT 1 +#define ATR_PCIE_DEV_DMA_SIZE 0 +#define ATR_PCIE_DEV_DMA_TABLE_NUM 0 +#define ATR_PCIE_DEV_DMA_TRSL_ADDR 0x00000000 + +#define MTK_BAR_0_1_IDX 0 +#define MTK_BAR_2_3_IDX 2 +/* Only use BAR0/1 and 2/3, so we should input 0b0101 for the two bar, + * Input 0xf would cause error. + */ +#define MTK_REQUESTED_BARS ((1 << MTK_BAR_0_1_IDX) | (1 << MTK_BAR_2_3= _IDX)) + +#define MTK_IRQ_CNT_MIN 1 +#define MTK_IRQ_CNT_MAX 32 +#define MTK_IRQ_NAME_LEN 20 + +#define MTK_INVAL_IRQ_SRC -1 + +#define MTK_FORCE_MAC_ACTIVE_BIT BIT(6) +#define MTK_DS_LOCK_REG_BIT BIT(7) + +/* mhccif registers */ +#define MHCCIF_RC2EP_SW_BSY 0x4 +#define MHCCIF_RC2EP_SW_INT_START 0x8 +#define MHCCIF_RC2EP_SW_TCHNUM 0xC +#define MHCCIF_EP2RC_SW_INT_STS 0x10 +#define MHCCIF_EP2RC_SW_INT_ACK 0x14 +#define MHCCIF_EP2RC_SW_INT_EAP_MASK 0x20 +#define MHCCIF_EP2RC_SW_INT_EAP_MASK_SET 0x30 +#define MHCCIF_EP2RC_SW_INT_EAP_MASK_CLR 0x40 +#define MHCCIF_RC2EP_PCIE_PM_COUNTER 0x12C + +#define MTK_PCI_CLASS 0x0D4000 +#define MTK_PCI_VENDOR_ID 0x14C3 + +#define MTK_DISABLE_DS_BIT(grp) BIT(grp) +#define MTK_ENABLE_DS_BIT(grp) BIT((grp) << 8) + +#define MTK_PCI_DEV_CFG(id, cfg) \ +{ \ + PCI_DEVICE(MTK_PCI_VENDOR_ID, id), \ + MTK_PCI_CLASS, PCI_ANY_ID, \ + .driver_data =3D (kernel_ulong_t)&(cfg), \ +} + +struct mtk_pci_dev_cfg { + u32 flag; + u32 mhccif_rc_base_addr; + u32 mhccif_rc_reg_trsl_addr; + u32 mhccif_trsl_size; + u32 istatus_host_ctrl_addr; + int irq_tbl[MTK_IRQ_SRC_MAX]; +}; + +struct mtk_pci_irq_desc { + struct mtk_md_dev *mdev; + u32 msix_bits; + char name[MTK_IRQ_NAME_LEN]; +}; + +struct mtk_pci_priv { + const struct mtk_pci_dev_cfg *cfg; + void *mdev; + void __iomem *bar23_addr; + void __iomem *mac_reg_base; + void __iomem *ext_reg_base; + int rc_hp_on; /* Bridge hotplug status */ + int irq_cnt; + int irq_type; + void *irq_cb_data[MTK_IRQ_CNT_MAX]; + + int (*irq_cb_list[MTK_IRQ_CNT_MAX])(int irq_id, void *data); + struct mtk_pci_irq_desc irq_desc[MTK_IRQ_CNT_MAX]; + struct list_head mhccif_cb_list; + /* mhccif_lock: lock to protect mhccif_cb_list */ + spinlock_t mhccif_lock; + struct work_struct mhccif_work; + int mhccif_irq_id; + struct pci_saved_state *saved_state; +}; + +struct mtk_mhccif_cb { + struct list_head entry; + int (*evt_cb)(u32 status, void *data); + void *data; + u32 chs; +}; + +struct mtk_atr_cfg { + u64 src_addr; + u64 trsl_addr; + u64 size; + u32 type; /* Port type */ + u32 port; /* Port number */ + u32 table; /* Table number (8 tables for each port) */ + u32 trsl_id; + u32 trsl_param; + u32 transparent; +}; + +#endif /* __MTK_PCI_H__ */ diff --git a/drivers/net/wwan/mediatek/pcie/mtk_reg.h b/drivers/net/wwan/me= diatek/pcie/mtk_reg.h new file mode 100644 index 000000000000..23fa7fd9518e --- /dev/null +++ b/drivers/net/wwan/mediatek/pcie/mtk_reg.h @@ -0,0 +1,69 @@ +/* SPDX-License-Identifier: BSD-3-Clause-Clear + * + * Copyright (c) 2022, MediaTek Inc. + */ + +#ifndef __MTK_REG_H__ +#define __MTK_REG_H__ + +enum mtk_ext_evt_h2d { + EXT_EVT_H2D_EXCEPT_ACK =3D 1 << 1, + EXT_EVT_H2D_EXCEPT_CLEARQ_ACK =3D 1 << 2, + EXT_EVT_H2D_PCIE_DS_LOCK =3D 1 << 3, + EXT_EVT_H2D_RESERVED_FOR_DPMAIF =3D 1 << 8, + EXT_EVT_H2D_PCIE_PM_SUSPEND_REQ =3D 1 << 9, + EXT_EVT_H2D_PCIE_PM_RESUME_REQ =3D 1 << 10, + EXT_EVT_H2D_PCIE_PM_SUSPEND_REQ_AP =3D 1 << 11, + EXT_EVT_H2D_PCIE_PM_RESUME_REQ_AP =3D 1 << 12, + EXT_EVT_H2D_DEVICE_RESET =3D 1 << 13, +}; + +#define REG_PCIE_SW_TRIG_INT 0x00BC +#define REG_PCIE_LTSSM_STATUS 0x0150 +#define REG_IMASK_LOCAL 0x0180 +#define REG_ISTATUS_LOCAL 0x0184 +#define REG_INT_ENABLE_HOST 0x0188 +#define REG_ISTATUS_HOST 0x018C +#define REG_PCIE_LOW_POWER_CTRL 0x0194 +#define REG_ISTATUS_HOST_CTRL 0x01AC +#define REG_ISTATUS_PENDING_ADT 0x01D4 +#define REG_INT_ENABLE_HOST_SET 0x01F0 +#define REG_INT_ENABLE_HOST_CLR 0x01F4 +#define REG_PCIE_DMA_DUMMY_0 0x01F8 +#define REG_ISTATUS_HOST_CTRL_NEW 0x031C +#define REG_PCIE_MISC_CTRL 0x0348 +#define REG_PCIE_DUMMY_0 0x03C0 +#define REG_SW_TRIG_INTR_SET 0x03C8 +#define REG_SW_TRIG_INTR_CLR 0x03CC +#define REG_PCIE_CFG_MSIX 0x03EC +#define REG_ATR_PCIE_WIN0_T0_SRC_ADDR_LSB 0x0600 +#define REG_ATR_PCIE_WIN0_T0_SRC_ADDR_MSB 0x0604 +#define REG_ATR_PCIE_WIN0_T0_TRSL_ADDR_LSB 0x0608 +#define REG_ATR_PCIE_WIN0_T0_TRSL_ADDR_MSB 0x060C +#define REG_ATR_PCIE_WIN0_T0_TRSL_PARAM 0x0610 +#define REG_PCIE_DEBUG_DUMMY_0 0x0D00 +#define REG_PCIE_DEBUG_DUMMY_1 0x0D04 +#define REG_PCIE_DEBUG_DUMMY_2 0x0D08 +#define REG_PCIE_DEBUG_DUMMY_3 0x0D0C +#define REG_PCIE_DEBUG_DUMMY_4 0x0D10 +#define REG_PCIE_DEBUG_DUMMY_5 0x0D14 +#define REG_PCIE_DEBUG_DUMMY_6 0x0D18 +#define REG_PCIE_DEBUG_DUMMY_7 0x0D1C +#define REG_PCIE_RESOURCE_STATUS 0x0D28 +#define REG_RC2EP_SW_TRIG_LOCAL_INTR_STAT 0x0D94 +#define REG_RC2EP_SW_TRIG_LOCAL_INTR_SET 0x0D98 +#define REG_RC2EP_SW_TRIG_LOCAL_INTR_CLR 0x0D9C +#define REG_DIS_ASPM_LOWPWR_SET_0 0x0E50 +#define REG_DIS_ASPM_LOWPWR_CLR_0 0x0E54 +#define REG_DIS_ASPM_LOWPWR_SET_1 0x0E58 +#define REG_DIS_ASPM_LOWPWR_CLR_1 0x0E5C +#define REG_DIS_ASPM_LOWPWR_STS_0 0x0E60 +#define REG_DIS_ASPM_LOWPWR_STS_1 0x0E64 +#define REG_PCIE_PEXTP_MAC_SLEEP_CTRL 0x0E70 +#define REG_MSIX_SW_TRIG_SET_GRP0_0 0x0E80 +#define REG_MSIX_ISTATUS_HOST_GRP0_0 0x0F00 +#define REG_IMASK_HOST_MSIX_SET_GRP0_0 0x3000 +#define REG_IMASK_HOST_MSIX_CLR_GRP0_0 0x3080 +#define REG_IMASK_HOST_MSIX_GRP0_0 0x3100 +#define REG_DEV_INFRA_BASE 0x10001000 +#endif /* __MTK_REG_H__ */ --=20 2.32.0