From nobody Sun Nov 10 19:17:02 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7A9EDC6FD1F for ; Thu, 16 Mar 2023 13:17:24 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230103AbjCPNRW (ORCPT ); Thu, 16 Mar 2023 09:17:22 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:58726 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230088AbjCPNRO (ORCPT ); Thu, 16 Mar 2023 09:17:14 -0400 Received: from mout.kundenserver.de (mout.kundenserver.de [212.227.126.135]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 40850C2D85; Thu, 16 Mar 2023 06:16:59 -0700 (PDT) Received: from maxwell.localdomain ([213.61.141.186]) by mrelayeu.kundenserver.de (mreue012 [213.165.67.97]) with ESMTPSA (Nemesis) id 1MT7ip-1q5m9U3jBf-00UeqB; Thu, 16 Mar 2023 14:15:24 +0100 From: Jochen Henneberg To: netdev@vger.kernel.org Cc: Jochen Henneberg , Giuseppe Cavallaro , Alexandre Torgue , Jose Abreu , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Maxime Coquelin , Shawn Guo , Sascha Hauer , Pengutronix Kernel Team , Fabio Estevam , NXP Linux Team , Matthias Brugger , AngeloGioacchino Del Regno , Wong Vee Khee , Kurt Kanzenbach , Revanth Kumar Uppala , Andrey Konovalov , Tan Tee Min , Voon Weifeng , Mohammad Athari Bin Ismail , linux-stm32@st-md-mailman.stormreply.com, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-mediatek@lists.infradead.org Subject: [PATCH net V2] net: stmmac: Fix for mismatched host/device DMA address width Date: Thu, 16 Mar 2023 14:15:03 +0100 Message-Id: <20230316131503.738933-1-jh@henneberg-systemdesign.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230316095306.721255-1-jh@henneberg-systemdesign.com> References: <20230316095306.721255-1-jh@henneberg-systemdesign.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Provags-ID: V03:K1:bfLeLJD9lJ3G3iT5iYg7UEsU81bVboCAdkEgfok56g7FNBxUgCq LNgriGZGnkbYpSN3KWkzpEvU7GSOnbMFpLmKOCO0dQlJ6nZ3SEAWl2vPzYr7b1PCKE9xX7A aPk4aLnMk+J7XvkK6quh9VuPhDfM7FPOfbpeXDOzde1tKmTBHkEwx7dDHdiTnMCJo5DNtU5 GvEy4RijTXnk/8jpaUPKw== UI-OutboundReport: notjunk:1;M01:P0:IsJsY91fw44=;Sez0sKu91tpF1iMfVXGvU+Bl/CE swTEhlRDPsrBdyqVk/cIuntzl1S4uGGV7oI3rfn8x3tkSbY2JSa6tDr6AXOBq+V420HYSv0pU GGgAVL8cBWSKuEF6IdLPH1+35DvXBzA0uZEukMJX5dwAsrXWchvZEqxSxqiGGr1gcLaYdJBrX hU9/wJ0jQ/lGSH9P+IViv0xIIld7dtJcBY51vbEY0v+yf8HePgpYvWnsKaJ1q9198tm4UbG3m 4WUMgKzmeB4ZuMX+74A3tzn1kqWQFtge/epSAfJhsMhF42IY5F15lVPZ4RDwFTFjurOsUVXW9 vJbs//H6kVZ1kWEHNXPS61/75VMSKuMDS2c1bpOWrWQ1OusiRwF7mjqYPkjrKWZLIVTlWouIe yIH2oGUxvEBA7jat6GxL9aHv5y3Y9hWjWbeh2sgTm7EWWQlmNlt8hJ+FrM66oEGMOCpeagMJc 587m1GDGXJcubTbM0Z1s/F0BckvEg1VbGwvFlEdkbMzzi/Clgj4SlEFlq781kMMgcpqbMF80r eNDNta59fIKIF6e+brSFukkbXUMaaUehIwuPCeWExGX3LrEY6DyS+j1K83KPLVCKx2Y5HKM3o 7HOxMzY4ADS+kX5FYJj4uNvdfAeleajn07wI2TQCqVo5FyZKXIk5mm+zgGzn8HgewF2LKGwE6 /NLSDb6cdeuDIciBT4qQB/+n0TgB0Gtcn7EnDKNcgw== Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Currently DMA address width is either read from a RO device register or force set from the platform data. This breaks DMA when the host DMA address width is <=3D32it but the device is >32bit. Right now the driver may decide to use a 2nd DMA descriptor for another buffer (happens in case of TSO xmit) assuming that 32bit addressing is used due to platform configuration but the device will still use both descriptor addresses as one address. This can be observed with the Intel EHL platform driver that sets 32bit for addr64 but the MAC reports 40bit. The TX queue gets stuck in case of TCP with iptables NAT configuration on TSO packets. The logic should be like this: Whatever we do on the host side (memory allocation GFP flags) should happen with the host DMA width, whenever we decide how to set addresses on the device registers we must use the device DMA address width. This patch renames the platform address width field from addr64 (term used in device datasheet) to host_addr and uses this value exclusively for host side operations while all chip operations consider the device DMA width as read from the device register. Fixes: 7cfc4486e7ea ("stmmac: intel: Configure EHL PSE0 GbE and PSE1 GbE to= 32 bits DMA addressing") Signed-off-by: Jochen Henneberg --- V2: Fixes from checkpatch.pl for commit message drivers/net/ethernet/stmicro/stmmac/common.h | 1 + .../net/ethernet/stmicro/stmmac/dwmac-imx.c | 2 +- .../net/ethernet/stmicro/stmmac/dwmac-intel.c | 4 +-- .../ethernet/stmicro/stmmac/dwmac-mediatek.c | 2 +- .../net/ethernet/stmicro/stmmac/stmmac_main.c | 30 ++++++++++--------- include/linux/stmmac.h | 2 +- 6 files changed, 22 insertions(+), 19 deletions(-) diff --git a/drivers/net/ethernet/stmicro/stmmac/common.h b/drivers/net/eth= ernet/stmicro/stmmac/common.h index 6b5d96bced47..55a728b1b708 100644 --- a/drivers/net/ethernet/stmicro/stmmac/common.h +++ b/drivers/net/ethernet/stmicro/stmmac/common.h @@ -418,6 +418,7 @@ struct dma_features { unsigned int frpbs; unsigned int frpes; unsigned int addr64; + unsigned int host_addr; unsigned int rssen; unsigned int vlhash; unsigned int sphen; diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-imx.c b/drivers/net/= ethernet/stmicro/stmmac/dwmac-imx.c index ac8580f501e2..bc06c517df9c 100644 --- a/drivers/net/ethernet/stmicro/stmmac/dwmac-imx.c +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-imx.c @@ -289,7 +289,7 @@ static int imx_dwmac_probe(struct platform_device *pdev) goto err_parse_dt; } =20 - plat_dat->addr64 =3D dwmac->ops->addr_width; + plat_dat->host_addr =3D dwmac->ops->addr_width; plat_dat->init =3D imx_dwmac_init; plat_dat->exit =3D imx_dwmac_exit; plat_dat->clks_config =3D imx_dwmac_clks_config; diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-intel.c b/drivers/ne= t/ethernet/stmicro/stmmac/dwmac-intel.c index 7deb1f817dac..193c3a842500 100644 --- a/drivers/net/ethernet/stmicro/stmmac/dwmac-intel.c +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-intel.c @@ -684,7 +684,7 @@ static int ehl_pse0_common_data(struct pci_dev *pdev, =20 intel_priv->is_pse =3D true; plat->bus_id =3D 2; - plat->addr64 =3D 32; + plat->host_dma_addr =3D 32; =20 plat->clk_ptp_rate =3D 200000000; =20 @@ -725,7 +725,7 @@ static int ehl_pse1_common_data(struct pci_dev *pdev, =20 intel_priv->is_pse =3D true; plat->bus_id =3D 3; - plat->addr64 =3D 32; + plat->host_dma_addr =3D 32; =20 plat->clk_ptp_rate =3D 200000000; =20 diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-mediatek.c b/drivers= /net/ethernet/stmicro/stmmac/dwmac-mediatek.c index 2f7d8e4561d9..968c8172c5bd 100644 --- a/drivers/net/ethernet/stmicro/stmmac/dwmac-mediatek.c +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-mediatek.c @@ -591,7 +591,7 @@ static int mediatek_dwmac_common_data(struct platform_d= evice *pdev, plat->use_phy_wol =3D priv_plat->mac_wol ? 0 : 1; plat->riwt_off =3D 1; plat->maxmtu =3D ETH_DATA_LEN; - plat->addr64 =3D priv_plat->variant->dma_bit_mask; + plat->host_dma_addr =3D priv_plat->variant->dma_bit_mask; plat->bsp_priv =3D priv_plat; plat->init =3D mediatek_dwmac_init; plat->clks_config =3D mediatek_dwmac_clks_config; diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c b/drivers/ne= t/ethernet/stmicro/stmmac/stmmac_main.c index 4886668a54c5..9f9cad178360 100644 --- a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c +++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c @@ -1430,7 +1430,7 @@ static int stmmac_init_rx_buffers(struct stmmac_priv = *priv, struct stmmac_rx_buffer *buf =3D &rx_q->buf_pool[i]; gfp_t gfp =3D (GFP_ATOMIC | __GFP_NOWARN); =20 - if (priv->dma_cap.addr64 <=3D 32) + if (priv->dma_cap.host_addr <=3D 32) gfp |=3D GFP_DMA32; =20 if (!buf->page) { @@ -4586,7 +4586,7 @@ static inline void stmmac_rx_refill(struct stmmac_pri= v *priv, u32 queue) unsigned int entry =3D rx_q->dirty_rx; gfp_t gfp =3D (GFP_ATOMIC | __GFP_NOWARN); =20 - if (priv->dma_cap.addr64 <=3D 32) + if (priv->dma_cap.host_addr <=3D 32) gfp |=3D GFP_DMA32; =20 while (dirty-- > 0) { @@ -6204,7 +6204,7 @@ static int stmmac_dma_cap_show(struct seq_file *seq, = void *v) seq_printf(seq, "\tFlexible RX Parser: %s\n", priv->dma_cap.frpsel ? "Y" : "N"); seq_printf(seq, "\tEnhanced Addressing: %d\n", - priv->dma_cap.addr64); + priv->dma_cap.host_addr); seq_printf(seq, "\tReceive Side Scaling: %s\n", priv->dma_cap.rssen ? "Y" : "N"); seq_printf(seq, "\tVLAN Hash Filtering: %s\n", @@ -7177,20 +7177,22 @@ int stmmac_dvr_probe(struct device *device, dev_info(priv->device, "SPH feature enabled\n"); } =20 - /* The current IP register MAC_HW_Feature1[ADDR64] only define - * 32/40/64 bit width, but some SOC support others like i.MX8MP - * support 34 bits but it map to 40 bits width in MAC_HW_Feature1[ADDR64]. - * So overwrite dma_cap.addr64 according to HW real design. + /* Ideally our host DMA address width is the same as for the + * device. However, it may differ and then we have to use our + * host DMA width for allocation and the device DMA width for + * register handling. */ - if (priv->plat->addr64) - priv->dma_cap.addr64 =3D priv->plat->addr64; + if (priv->plat->host_dma_addr) + priv->dma_cap.host_addr =3D priv->plat->host_dma_addr; + else + priv->dma_cap.host_addr =3D priv->dma_cap.addr64; =20 - if (priv->dma_cap.addr64) { + if (priv->dma_cap.host_addr) { ret =3D dma_set_mask_and_coherent(device, - DMA_BIT_MASK(priv->dma_cap.addr64)); + DMA_BIT_MASK(priv->dma_cap.host_addr)); if (!ret) { - dev_info(priv->device, "Using %d bits DMA width\n", - priv->dma_cap.addr64); + dev_info(priv->device, "Using %d/%d bits DMA host/device width\n", + priv->dma_cap.host_addr, priv->dma_cap.addr64); =20 /* * If more than 32 bits can be addressed, make sure to @@ -7205,7 +7207,7 @@ int stmmac_dvr_probe(struct device *device, goto error_hw_init; } =20 - priv->dma_cap.addr64 =3D 32; + priv->dma_cap.host_addr =3D 32; } } =20 diff --git a/include/linux/stmmac.h b/include/linux/stmmac.h index a152678b82b7..1cc4d61d6155 100644 --- a/include/linux/stmmac.h +++ b/include/linux/stmmac.h @@ -215,7 +215,7 @@ struct plat_stmmacenet_data { int unicast_filter_entries; int tx_fifo_size; int rx_fifo_size; - u32 addr64; + u32 host_dma_addr; u32 rx_queues_to_use; u32 tx_queues_to_use; u8 rx_sched_algorithm; --=20 2.39.2