From nobody Wed Feb 11 13:13:44 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id F0BB0C7619A for ; Wed, 15 Mar 2023 06:45:04 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231443AbjCOGpD (ORCPT ); Wed, 15 Mar 2023 02:45:03 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:59594 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231444AbjCOGoh (ORCPT ); Wed, 15 Mar 2023 02:44:37 -0400 Received: from mail-pj1-x1034.google.com (mail-pj1-x1034.google.com [IPv6:2607:f8b0:4864:20::1034]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 9346F62B7A for ; Tue, 14 Mar 2023 23:44:07 -0700 (PDT) Received: by mail-pj1-x1034.google.com with SMTP id y2so17750997pjg.3 for ; Tue, 14 Mar 2023 23:44:07 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1678862640; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=rQx6P2mfh2qDcHF7hB2MhMZ3flZiY/yvDBCNUwZGTWw=; b=rjD1zy/F5hXJTiuuiIQFngXWyQ5K2q6XbeqK4/QWvR3muGAGZiKHPmRq2va7TYy5TF lVIflj2GN5OQyCOjW/sPHNzu/XTecZFM8WlJC6Tv6mqrHPsVdetKjzftZeI299HhhUs2 SODVf9uXNJpVTRWGzpA8kJ4dQergz6TQvjIePNcsUtBKKtxVjZm1baunlkl4Fe7kApnp 9auWfQOU5D4eY0aY+EnfVK8iSAw1te2w5RxmpPs4ilW/MdsKfKx2Oked/yIXIxok7HPa oySlie5HHTjzFhdWh7u8vYssDbt0c9fJQN2pQEkb0npYDk8LrpbDloT/w8OgX/tRTkHS IK8g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1678862640; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=rQx6P2mfh2qDcHF7hB2MhMZ3flZiY/yvDBCNUwZGTWw=; b=SbXUL4p1khzxIjU7OcyiviXlmPOaaDIie0Gz8XVeH6UDcEF259LmOMJndyX8iF5yFO 2JXMS//agnfeRggIu/p0Fi1itq++CGeRTUNuZQ0k9h8CDOvCVoXyi89zs3c3KaMzGiFX nWcl9S1Znnm5gWeI+KoorAvFVIzTpyOe7vT2eif/EPUIdQj54HGkCqYyxiJD0lW2MS4j GJF714W3Inze27ihl+mKn4+CuASgn59I1nZ3W6ewgM4ymm4ZWNCj8phDgWuR+Hape/O9 jBH4V8+kxsui9k/BhsioqkeKcx+sf6Grzeq88wQo3IyetL8R/X5nA49qqKTGaRarZAPv jYuw== X-Gm-Message-State: AO0yUKXPx78eNDqQ1aO2y7cuoLPW8fcJcA1mTNwNpBcJ4hVPsGwxWHC+ IJH9RhclXrW8bZIX0W4W7XLN X-Google-Smtp-Source: AK7set89pwSckHBA6X0mvuFRK86wOtioV9O69BOlzyKpMn6yWtysatSdVFzJhAzfCzfhMB/bpcpc2Q== X-Received: by 2002:a17:90b:4b4b:b0:233:a6b7:3770 with SMTP id mi11-20020a17090b4b4b00b00233a6b73770mr41430916pjb.14.1678862640195; Tue, 14 Mar 2023 23:44:00 -0700 (PDT) Received: from localhost.localdomain ([117.217.182.35]) by smtp.gmail.com with ESMTPSA id u4-20020a17090a6a8400b002367325203fsm550747pjj.50.2023.03.14.23.43.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 14 Mar 2023 23:43:59 -0700 (PDT) From: Manivannan Sadhasivam To: andersson@kernel.org, lpieralisi@kernel.org, kw@linux.com, krzysztof.kozlowski+dt@linaro.org, robh@kernel.org Cc: konrad.dybcio@linaro.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, quic_srichara@quicinc.com, Manivannan Sadhasivam Subject: [PATCH v4 13/18] PCI: qcom: Rename qcom_pcie_config_sid_sm8250() to reflect IP version Date: Wed, 15 Mar 2023 12:12:50 +0530 Message-Id: <20230315064255.15591-14-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230315064255.15591-1-manivannan.sadhasivam@linaro.org> References: <20230315064255.15591-1-manivannan.sadhasivam@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" qcom_pcie_config_sid_sm8250() function no longer applies only to SM8250. So let's rename it to reflect the actual IP version and also move its definition to keep it sorted as per IP revisions. Signed-off-by: Manivannan Sadhasivam --- drivers/pci/controller/dwc/pcie-qcom.c | 143 ++++++++++++------------- 1 file changed, 71 insertions(+), 72 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controlle= r/dwc/pcie-qcom.c index e1180c84f0fa..e47fdae3918c 100644 --- a/drivers/pci/controller/dwc/pcie-qcom.c +++ b/drivers/pci/controller/dwc/pcie-qcom.c @@ -963,6 +963,76 @@ static void qcom_pcie_deinit_2_7_0(struct qcom_pcie *p= cie) regulator_bulk_disable(ARRAY_SIZE(res->supplies), res->supplies); } =20 +static int qcom_pcie_config_sid_1_9_0(struct qcom_pcie *pcie) +{ + /* iommu map structure */ + struct { + u32 bdf; + u32 phandle; + u32 smmu_sid; + u32 smmu_sid_len; + } *map; + void __iomem *bdf_to_sid_base =3D pcie->parf + PARF_BDF_TO_SID_TABLE_N; + struct device *dev =3D pcie->pci->dev; + u8 qcom_pcie_crc8_table[CRC8_TABLE_SIZE]; + int i, nr_map, size =3D 0; + u32 smmu_sid_base; + + of_get_property(dev->of_node, "iommu-map", &size); + if (!size) + return 0; + + map =3D kzalloc(size, GFP_KERNEL); + if (!map) + return -ENOMEM; + + of_property_read_u32_array(dev->of_node, "iommu-map", (u32 *)map, + size / sizeof(u32)); + + nr_map =3D size / (sizeof(*map)); + + crc8_populate_msb(qcom_pcie_crc8_table, QCOM_PCIE_CRC8_POLYNOMIAL); + + /* Registers need to be zero out first */ + memset_io(bdf_to_sid_base, 0, CRC8_TABLE_SIZE * sizeof(u32)); + + /* Extract the SMMU SID base from the first entry of iommu-map */ + smmu_sid_base =3D map[0].smmu_sid; + + /* Look for an available entry to hold the mapping */ + for (i =3D 0; i < nr_map; i++) { + __be16 bdf_be =3D cpu_to_be16(map[i].bdf); + u32 val; + u8 hash; + + hash =3D crc8(qcom_pcie_crc8_table, (u8 *)&bdf_be, sizeof(bdf_be), 0); + + val =3D readl(bdf_to_sid_base + hash * sizeof(u32)); + + /* If the register is already populated, look for next available entry */ + while (val) { + u8 current_hash =3D hash++; + u8 next_mask =3D 0xff; + + /* If NEXT field is NULL then update it with next hash */ + if (!(val & next_mask)) { + val |=3D (u32)hash; + writel(val, bdf_to_sid_base + current_hash * sizeof(u32)); + } + + val =3D readl(bdf_to_sid_base + hash * sizeof(u32)); + } + + /* BDF [31:16] | SID [15:8] | NEXT [7:0] */ + val =3D map[i].bdf << 16 | (map[i].smmu_sid - smmu_sid_base) << 8 | 0; + writel(val, bdf_to_sid_base + hash * sizeof(u32)); + } + + kfree(map); + + return 0; +} + static int qcom_pcie_get_resources_2_9_0(struct qcom_pcie *pcie) { struct qcom_pcie_resources_2_9_0 *res =3D &pcie->res.v2_9_0; @@ -1077,77 +1147,6 @@ static int qcom_pcie_link_up(struct dw_pcie *pci) return !!(val & PCI_EXP_LNKSTA_DLLLA); } =20 -static int qcom_pcie_config_sid_sm8250(struct qcom_pcie *pcie) -{ - /* iommu map structure */ - struct { - u32 bdf; - u32 phandle; - u32 smmu_sid; - u32 smmu_sid_len; - } *map; - void __iomem *bdf_to_sid_base =3D pcie->parf + PARF_BDF_TO_SID_TABLE_N; - struct device *dev =3D pcie->pci->dev; - u8 qcom_pcie_crc8_table[CRC8_TABLE_SIZE]; - int i, nr_map, size =3D 0; - u32 smmu_sid_base; - - of_get_property(dev->of_node, "iommu-map", &size); - if (!size) - return 0; - - map =3D kzalloc(size, GFP_KERNEL); - if (!map) - return -ENOMEM; - - of_property_read_u32_array(dev->of_node, - "iommu-map", (u32 *)map, size / sizeof(u32)); - - nr_map =3D size / (sizeof(*map)); - - crc8_populate_msb(qcom_pcie_crc8_table, QCOM_PCIE_CRC8_POLYNOMIAL); - - /* Registers need to be zero out first */ - memset_io(bdf_to_sid_base, 0, CRC8_TABLE_SIZE * sizeof(u32)); - - /* Extract the SMMU SID base from the first entry of iommu-map */ - smmu_sid_base =3D map[0].smmu_sid; - - /* Look for an available entry to hold the mapping */ - for (i =3D 0; i < nr_map; i++) { - __be16 bdf_be =3D cpu_to_be16(map[i].bdf); - u32 val; - u8 hash; - - hash =3D crc8(qcom_pcie_crc8_table, (u8 *)&bdf_be, sizeof(bdf_be), - 0); - - val =3D readl(bdf_to_sid_base + hash * sizeof(u32)); - - /* If the register is already populated, look for next available entry */ - while (val) { - u8 current_hash =3D hash++; - u8 next_mask =3D 0xff; - - /* If NEXT field is NULL then update it with next hash */ - if (!(val & next_mask)) { - val |=3D (u32)hash; - writel(val, bdf_to_sid_base + current_hash * sizeof(u32)); - } - - val =3D readl(bdf_to_sid_base + hash * sizeof(u32)); - } - - /* BDF [31:16] | SID [15:8] | NEXT [7:0] */ - val =3D map[i].bdf << 16 | (map[i].smmu_sid - smmu_sid_base) << 8 | 0; - writel(val, bdf_to_sid_base + hash * sizeof(u32)); - } - - kfree(map); - - return 0; -} - static int qcom_pcie_host_init(struct dw_pcie_rp *pp) { struct dw_pcie *pci =3D to_dw_pcie_from_pp(pp); @@ -1268,7 +1267,7 @@ static const struct qcom_pcie_ops ops_1_9_0 =3D { .init =3D qcom_pcie_init_2_7_0, .deinit =3D qcom_pcie_deinit_2_7_0, .ltssm_enable =3D qcom_pcie_2_3_2_ltssm_enable, - .config_sid =3D qcom_pcie_config_sid_sm8250, + .config_sid =3D qcom_pcie_config_sid_1_9_0, }; =20 /* Qcom IP rev.: 2.9.0 Synopsys IP rev.: 5.00a */ --=20 2.25.1