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[83.9.29.190]) by smtp.gmail.com with ESMTPSA id x1-20020ac25dc1000000b004f64b8eee61sm2088406lfq.97.2023.06.14.04.35.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 14 Jun 2023 04:35:56 -0700 (PDT) From: Konrad Dybcio Date: Wed, 14 Jun 2023 13:35:36 +0200 Subject: [PATCH v2 5/7] arm64: dts: qcom: sm6350: Add GPU nodes MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20230315-topic-lagoon_gpu-v2-5-afcdfb18bb13@linaro.org> References: <20230315-topic-lagoon_gpu-v2-0-afcdfb18bb13@linaro.org> In-Reply-To: <20230315-topic-lagoon_gpu-v2-0-afcdfb18bb13@linaro.org> To: Bjorn Andersson , Andy Gross , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , AngeloGioacchino Del Regno , Conor Dooley Cc: Marijn Suijten , Rob Herring , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Konrad Dybcio , Konrad Dybcio , Luca Weiss X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1686742545; l=4658; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=hebgvqDxcP5/jpVdGp5qyd6v0S/XcOR8k6z5qijdwvg=; b=Vslq+h8v6Ug4FxssYmahe0vqA8WKjBotTiq84VPW7dcNRIX6r6L/p5w1L/JqBNLQ9ccdcHfHC XFE2LLf5NqAB4fOBJiSiZCUrfoBZbcLGpgMireMDLERCvldwhzEOGVF X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Konrad Dybcio Add Adreno, GPU SMMU and GMU nodes to hook up everything that the A619 needs to function properly. Co-developed-by: Luca Weiss Signed-off-by: Konrad Dybcio Signed-off-by: Luca Weiss Signed-off-by: Konrad Dybcio --- arch/arm64/boot/dts/qcom/sm6350.dtsi | 139 +++++++++++++++++++++++++++++++= ++++ 1 file changed, 139 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm6350.dtsi b/arch/arm64/boot/dts/qco= m/sm6350.dtsi index c0f34bc1d78c..d928e64e33ae 100644 --- a/arch/arm64/boot/dts/qcom/sm6350.dtsi +++ b/arch/arm64/boot/dts/qcom/sm6350.dtsi @@ -1321,6 +1321,145 @@ compute-cb@5 { }; }; =20 + gpu: gpu@3d00000 { + compatible =3D "qcom,adreno-619.0", "qcom,adreno"; + reg =3D <0 0x03d00000 0 0x40000>, + <0 0x03d9e000 0 0x1000>; + reg-names =3D "kgsl_3d0_reg_memory", + "cx_mem"; + interrupts =3D ; + + iommus =3D <&adreno_smmu 0>; + operating-points-v2 =3D <&gpu_opp_table>; + qcom,gmu =3D <&gmu>; + nvmem-cells =3D <&gpu_speed_bin>; + nvmem-cell-names =3D "speed_bin"; + + status =3D "disabled"; + + zap-shader { + memory-region =3D <&pil_gpu_mem>; + }; + + gpu_opp_table: opp-table { + compatible =3D "operating-points-v2"; + + opp-850000000 { + opp-hz =3D /bits/ 64 <850000000>; + opp-level =3D ; + opp-supported-hw =3D <0x02>; + }; + + opp-800000000 { + opp-hz =3D /bits/ 64 <800000000>; + opp-level =3D ; + opp-supported-hw =3D <0x04>; + }; + + opp-650000000 { + opp-hz =3D /bits/ 64 <650000000>; + opp-level =3D ; + opp-supported-hw =3D <0x08>; + }; + + opp-565000000 { + opp-hz =3D /bits/ 64 <565000000>; + opp-level =3D ; + opp-supported-hw =3D <0x10>; + }; + + opp-430000000 { + opp-hz =3D /bits/ 64 <430000000>; + opp-level =3D ; + opp-supported-hw =3D <0xff>; + }; + + opp-355000000 { + opp-hz =3D /bits/ 64 <355000000>; + opp-level =3D ; + opp-supported-hw =3D <0xff>; + }; + + opp-253000000 { + opp-hz =3D /bits/ 64 <253000000>; + opp-level =3D ; + opp-supported-hw =3D <0xff>; + }; + }; + }; + + adreno_smmu: iommu@3d40000 { + compatible =3D "qcom,sm6350-smmu-v2", "qcom,adreno-smmu", "qcom,smmu-v2= "; + reg =3D <0 0x03d40000 0 0x10000>; + #iommu-cells =3D <1>; + #global-interrupts =3D <2>; + interrupts =3D , + , + , + , + , + , + , + , + , + ; + + clocks =3D <&gpucc GPU_CC_AHB_CLK>, + <&gcc GCC_GPU_MEMNOC_GFX_CLK>, + <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>; + clock-names =3D "ahb", + "bus", + "iface"; + + power-domains =3D <&gpucc GPU_CX_GDSC>; + }; + + gmu: gmu@3d6a000 { + compatible =3D "qcom,adreno-gmu-619.0", "qcom,adreno-gmu"; + reg =3D <0 0x03d6a000 0 0x31000>, + <0 0x0b290000 0 0x10000>, + <0 0x0b490000 0 0x10000>; + reg-names =3D "gmu", + "gmu_pdc", + "gmu_pdc_seq"; + + interrupts =3D , + ; + interrupt-names =3D "hfi", + "gmu"; + + clocks =3D <&gpucc GPU_CC_AHB_CLK>, + <&gpucc GPU_CC_CX_GMU_CLK>, + <&gpucc GPU_CC_CXO_CLK>, + <&gcc GCC_DDRSS_GPU_AXI_CLK>, + <&gcc GCC_GPU_MEMNOC_GFX_CLK>; + clock-names =3D "ahb", + "gmu", + "cxo", + "axi", + "memnoc"; + + power-domains =3D <&gpucc GPU_CX_GDSC>, + <&gpucc GPU_GX_GDSC>; + power-domain-names =3D "cx", + "gx"; + + iommus =3D <&adreno_smmu 5>; + + operating-points-v2 =3D <&gmu_opp_table>; + + status =3D "disabled"; + + gmu_opp_table: opp-table { + compatible =3D "operating-points-v2"; + + opp-200000000 { + opp-hz =3D /bits/ 64 <200000000>; + opp-level =3D ; + }; + }; + }; + gpucc: clock-controller@3d90000 { compatible =3D "qcom,sm6350-gpucc"; reg =3D <0 0x03d90000 0 0x9000>; --=20 2.41.0