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[83.9.29.190]) by smtp.gmail.com with ESMTPSA id x1-20020ac25dc1000000b004f64b8eee61sm2088406lfq.97.2023.06.14.04.35.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 14 Jun 2023 04:35:50 -0700 (PDT) From: Konrad Dybcio Date: Wed, 14 Jun 2023 13:35:33 +0200 Subject: [PATCH v2 2/7] clk: qcom: gpucc-sm6350: Fix clock source names MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20230315-topic-lagoon_gpu-v2-2-afcdfb18bb13@linaro.org> References: <20230315-topic-lagoon_gpu-v2-0-afcdfb18bb13@linaro.org> In-Reply-To: <20230315-topic-lagoon_gpu-v2-0-afcdfb18bb13@linaro.org> To: Bjorn Andersson , Andy Gross , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , AngeloGioacchino Del Regno , Conor Dooley Cc: Marijn Suijten , Rob Herring , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Konrad Dybcio , Konrad Dybcio X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1686742545; l=1472; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=Um2mvoH0hgq2pxMG9SLY6mhwWzANPWf1u6+3THUrEME=; b=2C90kfo8MN0j6VNDnSDnGoAxAhAtouxdKh8jKaNG5fneNrIb81w/UW4+kwXuSrKmvexCRr9cz 8duNdf3C0VPCiFGebaCghiTiKRhyqiQs/KLXoL4Y3Rso3YuoKiDg1TT X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org fw_name for GCC inputs didn't match the bindings. Fix it. Fixes: 013804a727a0 ("clk: qcom: Add GPU clock controller driver for SM6350= ") Signed-off-by: Konrad Dybcio --- drivers/clk/qcom/gpucc-sm6350.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/clk/qcom/gpucc-sm6350.c b/drivers/clk/qcom/gpucc-sm635= 0.c index a9887d1f0ed7..0bcbba2a2943 100644 --- a/drivers/clk/qcom/gpucc-sm6350.c +++ b/drivers/clk/qcom/gpucc-sm6350.c @@ -132,8 +132,8 @@ static const struct clk_parent_data gpu_cc_parent_data_= 0[] =3D { { .index =3D DT_BI_TCXO, .fw_name =3D "bi_tcxo" }, { .hw =3D &gpu_cc_pll0.clkr.hw }, { .hw =3D &gpu_cc_pll1.clkr.hw }, - { .index =3D DT_GPLL0_OUT_MAIN, .fw_name =3D "gcc_gpu_gpll0_clk" }, - { .index =3D DT_GPLL0_OUT_MAIN_DIV, .fw_name =3D "gcc_gpu_gpll0_div_clk" = }, + { .index =3D DT_GPLL0_OUT_MAIN, .fw_name =3D "gcc_gpu_gpll0_clk_src" }, + { .index =3D DT_GPLL0_OUT_MAIN_DIV, .fw_name =3D "gcc_gpu_gpll0_div_clk_s= rc" }, }; =20 static const struct parent_map gpu_cc_parent_map_1[] =3D { @@ -151,7 +151,7 @@ static const struct clk_parent_data gpu_cc_parent_data_= 1[] =3D { { .hw =3D &gpu_cc_pll0.clkr.hw }, { .hw =3D &gpu_cc_pll1.clkr.hw }, { .hw =3D &gpu_cc_pll1.clkr.hw }, - { .index =3D DT_GPLL0_OUT_MAIN, .fw_name =3D "gcc_gpu_gpll0_clk" }, + { .index =3D DT_GPLL0_OUT_MAIN, .fw_name =3D "gcc_gpu_gpll0_clk_src" }, }; =20 static const struct freq_tbl ftbl_gpu_cc_gmu_clk_src[] =3D { --=20 2.41.0