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[83.9.29.190]) by smtp.gmail.com with ESMTPSA id x1-20020ac25dc1000000b004f64b8eee61sm2088406lfq.97.2023.06.14.04.35.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 14 Jun 2023 04:35:49 -0700 (PDT) From: Konrad Dybcio Date: Wed, 14 Jun 2023 13:35:32 +0200 Subject: [PATCH v2 1/7] clk: qcom: gpucc-sm6350: Introduce index-based clk lookup MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20230315-topic-lagoon_gpu-v2-1-afcdfb18bb13@linaro.org> References: <20230315-topic-lagoon_gpu-v2-0-afcdfb18bb13@linaro.org> In-Reply-To: <20230315-topic-lagoon_gpu-v2-0-afcdfb18bb13@linaro.org> To: Bjorn Andersson , Andy Gross , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , AngeloGioacchino Del Regno , Conor Dooley Cc: Marijn Suijten , Rob Herring , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Konrad Dybcio , Konrad Dybcio X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1686742545; l=2501; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=TaMoHmTX5YmIOUIdAoElMKm2cSA2iQeh1gPxDTztMHU=; b=SuDstwjNjC4hB4jFdESHz9+jus8boaBzbYU+NNQHiLZongyDXxnapKuBEHAt5EBMcs95Y2i/H TdQqQNj02JUCwkN8winp20RjQqBJuUrth0siHnCXo/wmoKj7gHVe7RQ X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add the nowadays-prefered and marginally faster way of looking up parent clocks in the device tree. It also allows for clock-names-independent operation, so long as the order (which is enforced by schema) is kept. Signed-off-by: Konrad Dybcio --- drivers/clk/qcom/gpucc-sm6350.c | 18 +++++++++++++----- 1 file changed, 13 insertions(+), 5 deletions(-) diff --git a/drivers/clk/qcom/gpucc-sm6350.c b/drivers/clk/qcom/gpucc-sm635= 0.c index ef15185a99c3..a9887d1f0ed7 100644 --- a/drivers/clk/qcom/gpucc-sm6350.c +++ b/drivers/clk/qcom/gpucc-sm6350.c @@ -24,6 +24,12 @@ #define CX_GMU_CBCR_WAKE_MASK 0xF #define CX_GMU_CBCR_WAKE_SHIFT 8 =20 +enum { + DT_BI_TCXO, + DT_GPLL0_OUT_MAIN, + DT_GPLL0_OUT_MAIN_DIV, +}; + enum { P_BI_TCXO, P_GPLL0_OUT_MAIN, @@ -61,6 +67,7 @@ static struct clk_alpha_pll gpu_cc_pll0 =3D { .hw.init =3D &(struct clk_init_data){ .name =3D "gpu_cc_pll0", .parent_data =3D &(const struct clk_parent_data){ + .index =3D DT_BI_TCXO, .fw_name =3D "bi_tcxo", }, .num_parents =3D 1, @@ -104,6 +111,7 @@ static struct clk_alpha_pll gpu_cc_pll1 =3D { .hw.init =3D &(struct clk_init_data){ .name =3D "gpu_cc_pll1", .parent_data =3D &(const struct clk_parent_data){ + .index =3D DT_BI_TCXO, .fw_name =3D "bi_tcxo", }, .num_parents =3D 1, @@ -121,11 +129,11 @@ static const struct parent_map gpu_cc_parent_map_0[] = =3D { }; =20 static const struct clk_parent_data gpu_cc_parent_data_0[] =3D { - { .fw_name =3D "bi_tcxo" }, + { .index =3D DT_BI_TCXO, .fw_name =3D "bi_tcxo" }, { .hw =3D &gpu_cc_pll0.clkr.hw }, { .hw =3D &gpu_cc_pll1.clkr.hw }, - { .fw_name =3D "gcc_gpu_gpll0_clk" }, - { .fw_name =3D "gcc_gpu_gpll0_div_clk" }, + { .index =3D DT_GPLL0_OUT_MAIN, .fw_name =3D "gcc_gpu_gpll0_clk" }, + { .index =3D DT_GPLL0_OUT_MAIN_DIV, .fw_name =3D "gcc_gpu_gpll0_div_clk" = }, }; =20 static const struct parent_map gpu_cc_parent_map_1[] =3D { @@ -138,12 +146,12 @@ static const struct parent_map gpu_cc_parent_map_1[] = =3D { }; =20 static const struct clk_parent_data gpu_cc_parent_data_1[] =3D { - { .fw_name =3D "bi_tcxo" }, + { .index =3D DT_BI_TCXO, .fw_name =3D "bi_tcxo" }, { .hw =3D &crc_div.hw }, { .hw =3D &gpu_cc_pll0.clkr.hw }, { .hw =3D &gpu_cc_pll1.clkr.hw }, { .hw =3D &gpu_cc_pll1.clkr.hw }, - { .fw_name =3D "gcc_gpu_gpll0_clk" }, + { .index =3D DT_GPLL0_OUT_MAIN, .fw_name =3D "gcc_gpu_gpll0_clk" }, }; =20 static const struct freq_tbl ftbl_gpu_cc_gmu_clk_src[] =3D { --=20 2.41.0 From nobody Sun Feb 8 04:52:26 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 030B0C001B0 for ; Wed, 14 Jun 2023 11:36:04 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S244114AbjFNLgC (ORCPT ); Wed, 14 Jun 2023 07:36:02 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:49406 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S244049AbjFNLfz (ORCPT ); Wed, 14 Jun 2023 07:35:55 -0400 Received: from mail-lf1-x136.google.com (mail-lf1-x136.google.com [IPv6:2a00:1450:4864:20::136]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 251951BC3 for ; Wed, 14 Jun 2023 04:35:53 -0700 (PDT) Received: by mail-lf1-x136.google.com with SMTP id 2adb3069b0e04-4f6255ad8aeso8446610e87.2 for ; Wed, 14 Jun 2023 04:35:53 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1686742551; x=1689334551; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=qQ877MkpC4ehMBHierpFme4jBSlXee3tho/1k2lPnrc=; b=uI93E48Udehbrc1xQ5FKCcryJu31IKfTe3ArGksSM8duqIQR2ZrmfLpdNQ+qIFOTz3 SncRrViURipzqRAPlpCfr0FC/92IC2vwjuwbLJW0jMVN4xS0uvzRZDdjiw3BWTRuunmD 74bsU98nNPnMyWJxVjcoiiUjAVYZX3Fjxw9pD9ouFNVvk7R2iXYvkBYUYUMnXvRsEQNy Z2NMYKU4vWUsz3jOQB6+DLg9JUqt8JaSXmg/MiW7SpM1Eypph8+bYHzYLnjZ0DSE9HqF E/P5NG1+ueIKjdibYHTm68Qn36j/UGY7i0FvcMaKNkYjnpwn9GUr4txXLSnYcnNMGN3e Mv2A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1686742551; x=1689334551; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=qQ877MkpC4ehMBHierpFme4jBSlXee3tho/1k2lPnrc=; b=DeEFfwtYrUMKaOj6ZW3hGxWy6CYqEKU0evoa1NRJZcu0D69o62xGo9hkfk4WQ2ZKoK n8FSMLH3oD82mHNic7SLf4jywwsq9njqg9FyGzXzhY9qCDC5u915cxO6g5U8DSPocDpF WCOYVzayrFMPBh9lycmXCHHQiJgUG55r/I/AX29uhzasu+CxUABBFXNddJsO07qnZr2r 4/2M621RMqnvTVbqxzDHUEcXt8uz8et1MoVEsAj/O2wM0SnrlvuaC6hNyPT9SbY09yfe m5WyMzFX6dEFEi9PR1v/27edo7SYiGBbIJ+4+2w/1E7gz/dky6zuqSabgekZELd4ACVo xNTg== X-Gm-Message-State: AC+VfDxg4kICCmXyyiHAXDQDH2+CmCT2pvDW9I5XU10kGD21hxeuMQ5U +9y2w4zRuQSYKWWTJDX5d+OgzQ== X-Google-Smtp-Source: ACHHUZ60YXB+ZseJWIdpv6oeU1CgzUgucbhQDO4MpnIaed7403UQGhY/Ck461aIqR+24CTGdjBT+iw== X-Received: by 2002:a19:e344:0:b0:4f7:5d2d:337e with SMTP id c4-20020a19e344000000b004f75d2d337emr2291524lfk.15.1686742551189; Wed, 14 Jun 2023 04:35:51 -0700 (PDT) Received: from [192.168.1.101] (abyj190.neoplus.adsl.tpnet.pl. [83.9.29.190]) by smtp.gmail.com with ESMTPSA id x1-20020ac25dc1000000b004f64b8eee61sm2088406lfq.97.2023.06.14.04.35.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 14 Jun 2023 04:35:50 -0700 (PDT) From: Konrad Dybcio Date: Wed, 14 Jun 2023 13:35:33 +0200 Subject: [PATCH v2 2/7] clk: qcom: gpucc-sm6350: Fix clock source names MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20230315-topic-lagoon_gpu-v2-2-afcdfb18bb13@linaro.org> References: <20230315-topic-lagoon_gpu-v2-0-afcdfb18bb13@linaro.org> In-Reply-To: <20230315-topic-lagoon_gpu-v2-0-afcdfb18bb13@linaro.org> To: Bjorn Andersson , Andy Gross , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , AngeloGioacchino Del Regno , Conor Dooley Cc: Marijn Suijten , Rob Herring , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Konrad Dybcio , Konrad Dybcio X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1686742545; l=1472; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=Um2mvoH0hgq2pxMG9SLY6mhwWzANPWf1u6+3THUrEME=; b=2C90kfo8MN0j6VNDnSDnGoAxAhAtouxdKh8jKaNG5fneNrIb81w/UW4+kwXuSrKmvexCRr9cz 8duNdf3C0VPCiFGebaCghiTiKRhyqiQs/KLXoL4Y3Rso3YuoKiDg1TT X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org fw_name for GCC inputs didn't match the bindings. Fix it. Fixes: 013804a727a0 ("clk: qcom: Add GPU clock controller driver for SM6350= ") Signed-off-by: Konrad Dybcio --- drivers/clk/qcom/gpucc-sm6350.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/clk/qcom/gpucc-sm6350.c b/drivers/clk/qcom/gpucc-sm635= 0.c index a9887d1f0ed7..0bcbba2a2943 100644 --- a/drivers/clk/qcom/gpucc-sm6350.c +++ b/drivers/clk/qcom/gpucc-sm6350.c @@ -132,8 +132,8 @@ static const struct clk_parent_data gpu_cc_parent_data_= 0[] =3D { { .index =3D DT_BI_TCXO, .fw_name =3D "bi_tcxo" }, { .hw =3D &gpu_cc_pll0.clkr.hw }, { .hw =3D &gpu_cc_pll1.clkr.hw }, - { .index =3D DT_GPLL0_OUT_MAIN, .fw_name =3D "gcc_gpu_gpll0_clk" }, - { .index =3D DT_GPLL0_OUT_MAIN_DIV, .fw_name =3D "gcc_gpu_gpll0_div_clk" = }, + { .index =3D DT_GPLL0_OUT_MAIN, .fw_name =3D "gcc_gpu_gpll0_clk_src" }, + { .index =3D DT_GPLL0_OUT_MAIN_DIV, .fw_name =3D "gcc_gpu_gpll0_div_clk_s= rc" }, }; =20 static const struct parent_map gpu_cc_parent_map_1[] =3D { @@ -151,7 +151,7 @@ static const struct clk_parent_data gpu_cc_parent_data_= 1[] =3D { { .hw =3D &gpu_cc_pll0.clkr.hw }, { .hw =3D &gpu_cc_pll1.clkr.hw }, { .hw =3D &gpu_cc_pll1.clkr.hw }, - { .index =3D DT_GPLL0_OUT_MAIN, .fw_name =3D "gcc_gpu_gpll0_clk" }, + { .index =3D DT_GPLL0_OUT_MAIN, .fw_name =3D "gcc_gpu_gpll0_clk_src" }, }; =20 static const struct freq_tbl ftbl_gpu_cc_gmu_clk_src[] =3D { --=20 2.41.0 From nobody Sun Feb 8 04:52:26 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id ED2D1EB64D9 for ; Wed, 14 Jun 2023 11:36:07 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S244123AbjFNLgH (ORCPT ); Wed, 14 Jun 2023 07:36:07 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:49436 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S244076AbjFNLf5 (ORCPT ); Wed, 14 Jun 2023 07:35:57 -0400 Received: from mail-lf1-x131.google.com (mail-lf1-x131.google.com [IPv6:2a00:1450:4864:20::131]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 098F91BF3 for ; Wed, 14 Jun 2023 04:35:54 -0700 (PDT) Received: by mail-lf1-x131.google.com with SMTP id 2adb3069b0e04-4f122ff663eso8379081e87.2 for ; Wed, 14 Jun 2023 04:35:54 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1686742553; x=1689334553; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=PbHzuVw9djUb2dacqpTuChV+YchmANRy5455/F4AJp0=; b=hEudXtbM1Xo4XzWv1z7MyF9xYSMji7u4xEYfRPu5GR0wTH9rs51Q9yuKQq35iwFxcj 73la0nxq5ikY9Y3UvLzihT386Lc6JUJnCndhTddBtiTZ8e5DP29IK8TadpedbH1tN4Ej PtKxxbZiSTxH2+nKJLiByE1VyHrySrnAR8W0IgY9TTtkCQgHMwTYQhYAVPzVShVOx3Oi 8GkX6sE9mktM2Nv8zPs0zTNj/7oz3HUv6oJDofHjB9E8owHPTJQr09n7juaBxDX6PrF4 41V3c3zIp9cSp/ku/uYeV2Onu97dJ0rrCnJCTqmvFljBrdTQ8EgHh4tfAtgijSlKdwVy 37bg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1686742553; x=1689334553; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=PbHzuVw9djUb2dacqpTuChV+YchmANRy5455/F4AJp0=; b=TD5IHBYUiGxjp/UCrzMqrd/o1SUkrDpkp4sJd1UNxNetzOhCJvSBUjVDsrNDORKQ4b GOem4PaKYXgfL+z8Uq2cL2guliV9JoffTpOSyVB26h3OcqKIYc8/STe4cOCQ4y9NzcgH hEzkugFqXuPoBV5r1jgh79jp/s6hYy1/z/af9HTO1ti5C/19z8tA3uweSEdT09FIFx+j GHOZKynXtPCI1UhxeExTHiGyBJeOpC+w7ejxoRMIPa0YrMg6IM3oApIn742NQiY7m1Sf wVcDPrVR83imjOt9dkyrunAJAg9UmVw0XH0BJOYiBmH8cB+d8yuB73o7Gf1TqJdK0yAc 57LA== X-Gm-Message-State: AC+VfDxurPv42hxmEdZ7dxIbAwJkbwfvwWv21VKyS2NnFwiOCAi3q8vC wO3Lb/mON3JHC1fNTH8W6oq8yA== X-Google-Smtp-Source: ACHHUZ4+vaLtAihNVuosK3H1gbrAOEACwkJ9nMi9/2tAJspUX+ZYen/zFcnjt7IZgjHS+iQNSeaCEw== X-Received: by 2002:a19:ab01:0:b0:4f1:3bd7:e53a with SMTP id u1-20020a19ab01000000b004f13bd7e53amr7569927lfe.49.1686742553068; Wed, 14 Jun 2023 04:35:53 -0700 (PDT) Received: from [192.168.1.101] (abyj190.neoplus.adsl.tpnet.pl. [83.9.29.190]) by smtp.gmail.com with ESMTPSA id x1-20020ac25dc1000000b004f64b8eee61sm2088406lfq.97.2023.06.14.04.35.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 14 Jun 2023 04:35:52 -0700 (PDT) From: Konrad Dybcio Date: Wed, 14 Jun 2023 13:35:34 +0200 Subject: [PATCH v2 3/7] arm64: dts: qcom: sm6350: Add GPUCC node MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20230315-topic-lagoon_gpu-v2-3-afcdfb18bb13@linaro.org> References: <20230315-topic-lagoon_gpu-v2-0-afcdfb18bb13@linaro.org> In-Reply-To: <20230315-topic-lagoon_gpu-v2-0-afcdfb18bb13@linaro.org> To: Bjorn Andersson , Andy Gross , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , AngeloGioacchino Del Regno , Conor Dooley Cc: Marijn Suijten , Rob Herring , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Konrad Dybcio , Konrad Dybcio , Luca Weiss X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1686742545; l=1415; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=gsjvRRutg0p4O5/y2LMtWAUeMOWVStHD9z6YTRu1r8w=; b=ci/KzkaFWmBtpokctHZ0kQ1lRBx7DZqVYmrgzDc9/fI22dpniJyL96eFOt8B1wrTgBrY6DuQ4 TshDj9C0V5nDHLSxV12rpBEq6e+82I1p5hR0QeK08Hr8LJZx6qX4F1n X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Konrad Dybcio Add and configure a node for the GPU clock controller. Signed-off-by: Konrad Dybcio Reviewed-by: Luca Weiss Signed-off-by: Konrad Dybcio --- arch/arm64/boot/dts/qcom/sm6350.dtsi | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm6350.dtsi b/arch/arm64/boot/dts/qco= m/sm6350.dtsi index 30e77010aed5..fd35810bcfb5 100644 --- a/arch/arm64/boot/dts/qcom/sm6350.dtsi +++ b/arch/arm64/boot/dts/qcom/sm6350.dtsi @@ -5,6 +5,7 @@ */ =20 #include +#include #include #include #include @@ -1308,6 +1309,20 @@ compute-cb@5 { }; }; =20 + gpucc: clock-controller@3d90000 { + compatible =3D "qcom,sm6350-gpucc"; + reg =3D <0 0x03d90000 0 0x9000>; + clocks =3D <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_GPU_GPLL0_CLK>, + <&gcc GCC_GPU_GPLL0_DIV_CLK>; + clock-names =3D "bi_tcxo", + "gcc_gpu_gpll0_clk_src", + "gcc_gpu_gpll0_div_clk_src"; + #clock-cells =3D <1>; + #reset-cells =3D <1>; + #power-domain-cells =3D <1>; + }; + mpss: remoteproc@4080000 { compatible =3D "qcom,sm6350-mpss-pas"; reg =3D <0x0 0x04080000 0x0 0x4040>; --=20 2.41.0 From nobody Sun Feb 8 04:52:26 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id A9A34C001B0 for ; Wed, 14 Jun 2023 11:36:15 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S244189AbjFNLgO (ORCPT ); Wed, 14 Jun 2023 07:36:14 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:49426 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S244082AbjFNLf5 (ORCPT ); Wed, 14 Jun 2023 07:35:57 -0400 Received: from mail-lf1-x135.google.com (mail-lf1-x135.google.com [IPv6:2a00:1450:4864:20::135]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id AC5E71BF7 for ; Wed, 14 Jun 2023 04:35:56 -0700 (PDT) Received: by mail-lf1-x135.google.com with SMTP id 2adb3069b0e04-4f6370ddd27so8404104e87.0 for ; Wed, 14 Jun 2023 04:35:56 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1686742555; x=1689334555; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=BT0FhlQTqZJwPJ3Zh5frLeDreQMYYDJ2nQ7BrmaR2ho=; b=YEDYdRbkwtTcCZpnfO3XSRU5W8zNnW9TGdiUJIewFY6rzAh9+ldajb/ReUCuiVqvgu Co2qOHiv+8hSJ4be6PuIo4zh6iE5g+u6w66GUdOyaeTamMB+uaKZiOVSfN/HFH6B4Rht yoDKyE7W7mYYnpNSPWkRSokjT/7VqBUxxJoEUN8h9t/SMu277sLP5MzdEZnNmvwOr2em zrt/O8RaX2vCiUruKiV74yzcHsYok1wJ2fpTsB/xiL+pOSH996r1YHQI7E8A/s+XHTjb 9phkL2s5Um4Z8wtijDyWaX8pszunlfjOCAzeJVJmh6WY+ICpALWrR8EJsPPoOYNNc2zz qffA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1686742555; x=1689334555; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=BT0FhlQTqZJwPJ3Zh5frLeDreQMYYDJ2nQ7BrmaR2ho=; b=WVxT55E+EAiQLxvXfzyHvYs1rfuZJdps+tlbTtf/4OnNTMUzXQXxSDf5a8m6FnvxuJ Ve8fZ8y2kvUlX6qJoK7IDaYKkfhy+eSUeKjcRMEhKUwMcI3nWxQR8VBjgh1khtBex+0p CAxuaYA2o3eVMTpV9YLaFqvS0PwykNp+VV98ykFwJWmb7dnV1zOyuTcWIlYfOO/2d6bu dG8o8DSBIrEX1DJBF9ocQLaMmDcHHR8twW1Ya7B3FxQp3pncA7+PXYt6dK2wFzt2t/5A EH4jQmnKUl9GQLJT0vnvd1p8MmUq3e/rBLcDBbYkrB2VKiaGi2hwGebLs+T2pUslS+aA OMCQ== X-Gm-Message-State: AC+VfDwptWKzkq2zIZgD2drLJpiX2nWGfptfgw2cBUrCx/uGb5zJnZ6F tp7iuG6gW/nfjhsQ3hRcOkKq2g== X-Google-Smtp-Source: ACHHUZ5muu6w2LniG99CPtvkiIdie2btUG3ZPtShEgWaaBJcDaXpYP+5e6eN9kTFS0cXrcIWIF/2CA== X-Received: by 2002:ac2:5f9b:0:b0:4ed:d2cf:857b with SMTP id r27-20020ac25f9b000000b004edd2cf857bmr7373622lfe.5.1686742554922; Wed, 14 Jun 2023 04:35:54 -0700 (PDT) Received: from [192.168.1.101] (abyj190.neoplus.adsl.tpnet.pl. [83.9.29.190]) by smtp.gmail.com with ESMTPSA id x1-20020ac25dc1000000b004f64b8eee61sm2088406lfq.97.2023.06.14.04.35.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 14 Jun 2023 04:35:54 -0700 (PDT) From: Konrad Dybcio Date: Wed, 14 Jun 2023 13:35:35 +0200 Subject: [PATCH v2 4/7] arm64: dts: qcom: sm6350: Add QFPROM node MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20230315-topic-lagoon_gpu-v2-4-afcdfb18bb13@linaro.org> References: <20230315-topic-lagoon_gpu-v2-0-afcdfb18bb13@linaro.org> In-Reply-To: <20230315-topic-lagoon_gpu-v2-0-afcdfb18bb13@linaro.org> To: Bjorn Andersson , Andy Gross , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , AngeloGioacchino Del Regno , Conor Dooley Cc: Marijn Suijten , Rob Herring , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Konrad Dybcio , Konrad Dybcio , Luca Weiss X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1686742545; l=1015; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=TggODcqRcO65aCiU+0R8QACbCdlm3fHtH5g6iGTdYXg=; b=eik+ywxR3TJ0062wxnoAh1itVOjRVx4cRNY4gXrs+/1XC65DLXtb0Ai5VgZ+8NbsHdhKiX2fv efNQbzK5jJtDtCRmhKZ7FbMXdmy4/CU6bsEIIyIZbL4xOvpJmUac82E X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Konrad Dybcio Add a node for the QFPROM NVMEM hw and define the GPU fuse. Signed-off-by: Konrad Dybcio Reviewed-by: Luca Weiss Signed-off-by: Konrad Dybcio --- arch/arm64/boot/dts/qcom/sm6350.dtsi | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm6350.dtsi b/arch/arm64/boot/dts/qco= m/sm6350.dtsi index fd35810bcfb5..c0f34bc1d78c 100644 --- a/arch/arm64/boot/dts/qcom/sm6350.dtsi +++ b/arch/arm64/boot/dts/qcom/sm6350.dtsi @@ -805,6 +805,18 @@ ipcc: mailbox@408000 { #mbox-cells =3D <2>; }; =20 + qfprom: qfprom@784000 { + compatible =3D "qcom,sm6350-qfprom", "qcom,qfprom"; + reg =3D <0 0x00784000 0 0x3000>; + #address-cells =3D <1>; + #size-cells =3D <1>; + + gpu_speed_bin: gpu-speed-bin@2015 { + reg =3D <0x2015 0x1>; + bits =3D <0 8>; + }; + }; + rng: rng@793000 { compatible =3D "qcom,prng-ee"; reg =3D <0 0x00793000 0 0x1000>; --=20 2.41.0 From nobody Sun Feb 8 04:52:26 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 221C1C001DF for ; Wed, 14 Jun 2023 11:36:18 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S244138AbjFNLgQ (ORCPT ); Wed, 14 Jun 2023 07:36:16 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:49436 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S244090AbjFNLgB (ORCPT ); Wed, 14 Jun 2023 07:36:01 -0400 Received: from mail-lf1-x135.google.com (mail-lf1-x135.google.com [IPv6:2a00:1450:4864:20::135]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 7835D10D5 for ; Wed, 14 Jun 2023 04:35:58 -0700 (PDT) Received: by mail-lf1-x135.google.com with SMTP id 2adb3069b0e04-4f63ea7bfb6so7941200e87.3 for ; Wed, 14 Jun 2023 04:35:58 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1686742557; x=1689334557; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=5jaKkGkIsypo/HND0DbQ6vruiMEF8kdTc0ValZyEYo8=; b=iCkpWb6ESeD2lHxHwEtzgffY7572pjXjOE/aA6VVDfXo9MkWkRuwDGXDzfEoHsvHAK vqyMsDGWBLJbMS3Gx/tajd1faVH8MwR3FrAxvcvcVhxMgimslgs09j0zUB0rPUQ1e7j7 nc+tQtdGtLIqnimT5KhfwQnSO1dUlFN9azJMovFXBqsrfzVjwx7FktrZSiz4Joi/FQU2 pKWEmCQJWTpJH7RxZ3rbvEo7IQqe7uEqHCmEVE0AKWJtASfdXhkBIjh27qvNFTslMqFB h9HSy57dy2rlzOEaTgBa7udscq9IP4crUgiYpeZCF/iYfL/yY1ozCIuikvYRTS1eSXYk PW5Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1686742557; x=1689334557; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=5jaKkGkIsypo/HND0DbQ6vruiMEF8kdTc0ValZyEYo8=; b=JbMyS4VOyH7r/DwBTYqAWz+rlAyN8chQShR6biSkK4CbW0qL+5fN2GPt5Vpp3VcdSD kyhJrFQvKH1adevikrCMAsUkog++V0DICeXt2x0HGcpXCGwcBRH1xOgaVyCJZEAHVNrM /DR4fOrpKAFed3HTZRSdd9l7mXhfpUAD0DBprkhvJL6InQFLSystaUpGHEqbqwssuYUj bt7GU6HpvWHfquxiI4z1dOGE56cTVsS+LYjWtzLgUwSe1RnrWmgnOuyPPbg/REkgUE6I fVaWFhQC14koo+wULoo64v/24xJ16BDETLwN4v3nFS7APONF41+3jU9znxWoUlP0g4tP udAA== X-Gm-Message-State: AC+VfDy2Bcqa69y2Yf+S+Kvz2rNDycsbjIb9vWqMFGjebLD6wmSaBP3O ZxjjCFAs2QxQsopvP881Uoa/rQ== X-Google-Smtp-Source: ACHHUZ6/AtzF7ETM0NRzAi7oezIomSTjXVRgU6gaC6zW8ovyirb/eHe01y/JBm/zmilnHjK3WSNmGA== X-Received: by 2002:a19:6747:0:b0:4f3:b520:e0af with SMTP id e7-20020a196747000000b004f3b520e0afmr6845188lfj.13.1686742556849; Wed, 14 Jun 2023 04:35:56 -0700 (PDT) Received: from [192.168.1.101] (abyj190.neoplus.adsl.tpnet.pl. [83.9.29.190]) by smtp.gmail.com with ESMTPSA id x1-20020ac25dc1000000b004f64b8eee61sm2088406lfq.97.2023.06.14.04.35.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 14 Jun 2023 04:35:56 -0700 (PDT) From: Konrad Dybcio Date: Wed, 14 Jun 2023 13:35:36 +0200 Subject: [PATCH v2 5/7] arm64: dts: qcom: sm6350: Add GPU nodes MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20230315-topic-lagoon_gpu-v2-5-afcdfb18bb13@linaro.org> References: <20230315-topic-lagoon_gpu-v2-0-afcdfb18bb13@linaro.org> In-Reply-To: <20230315-topic-lagoon_gpu-v2-0-afcdfb18bb13@linaro.org> To: Bjorn Andersson , Andy Gross , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , AngeloGioacchino Del Regno , Conor Dooley Cc: Marijn Suijten , Rob Herring , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Konrad Dybcio , Konrad Dybcio , Luca Weiss X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1686742545; l=4658; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=hebgvqDxcP5/jpVdGp5qyd6v0S/XcOR8k6z5qijdwvg=; b=Vslq+h8v6Ug4FxssYmahe0vqA8WKjBotTiq84VPW7dcNRIX6r6L/p5w1L/JqBNLQ9ccdcHfHC XFE2LLf5NqAB4fOBJiSiZCUrfoBZbcLGpgMireMDLERCvldwhzEOGVF X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Konrad Dybcio Add Adreno, GPU SMMU and GMU nodes to hook up everything that the A619 needs to function properly. Co-developed-by: Luca Weiss Signed-off-by: Konrad Dybcio Signed-off-by: Luca Weiss Signed-off-by: Konrad Dybcio --- arch/arm64/boot/dts/qcom/sm6350.dtsi | 139 +++++++++++++++++++++++++++++++= ++++ 1 file changed, 139 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm6350.dtsi b/arch/arm64/boot/dts/qco= m/sm6350.dtsi index c0f34bc1d78c..d928e64e33ae 100644 --- a/arch/arm64/boot/dts/qcom/sm6350.dtsi +++ b/arch/arm64/boot/dts/qcom/sm6350.dtsi @@ -1321,6 +1321,145 @@ compute-cb@5 { }; }; =20 + gpu: gpu@3d00000 { + compatible =3D "qcom,adreno-619.0", "qcom,adreno"; + reg =3D <0 0x03d00000 0 0x40000>, + <0 0x03d9e000 0 0x1000>; + reg-names =3D "kgsl_3d0_reg_memory", + "cx_mem"; + interrupts =3D ; + + iommus =3D <&adreno_smmu 0>; + operating-points-v2 =3D <&gpu_opp_table>; + qcom,gmu =3D <&gmu>; + nvmem-cells =3D <&gpu_speed_bin>; + nvmem-cell-names =3D "speed_bin"; + + status =3D "disabled"; + + zap-shader { + memory-region =3D <&pil_gpu_mem>; + }; + + gpu_opp_table: opp-table { + compatible =3D "operating-points-v2"; + + opp-850000000 { + opp-hz =3D /bits/ 64 <850000000>; + opp-level =3D ; + opp-supported-hw =3D <0x02>; + }; + + opp-800000000 { + opp-hz =3D /bits/ 64 <800000000>; + opp-level =3D ; + opp-supported-hw =3D <0x04>; + }; + + opp-650000000 { + opp-hz =3D /bits/ 64 <650000000>; + opp-level =3D ; + opp-supported-hw =3D <0x08>; + }; + + opp-565000000 { + opp-hz =3D /bits/ 64 <565000000>; + opp-level =3D ; + opp-supported-hw =3D <0x10>; + }; + + opp-430000000 { + opp-hz =3D /bits/ 64 <430000000>; + opp-level =3D ; + opp-supported-hw =3D <0xff>; + }; + + opp-355000000 { + opp-hz =3D /bits/ 64 <355000000>; + opp-level =3D ; + opp-supported-hw =3D <0xff>; + }; + + opp-253000000 { + opp-hz =3D /bits/ 64 <253000000>; + opp-level =3D ; + opp-supported-hw =3D <0xff>; + }; + }; + }; + + adreno_smmu: iommu@3d40000 { + compatible =3D "qcom,sm6350-smmu-v2", "qcom,adreno-smmu", "qcom,smmu-v2= "; + reg =3D <0 0x03d40000 0 0x10000>; + #iommu-cells =3D <1>; + #global-interrupts =3D <2>; + interrupts =3D , + , + , + , + , + , + , + , + , + ; + + clocks =3D <&gpucc GPU_CC_AHB_CLK>, + <&gcc GCC_GPU_MEMNOC_GFX_CLK>, + <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>; + clock-names =3D "ahb", + "bus", + "iface"; + + power-domains =3D <&gpucc GPU_CX_GDSC>; + }; + + gmu: gmu@3d6a000 { + compatible =3D "qcom,adreno-gmu-619.0", "qcom,adreno-gmu"; + reg =3D <0 0x03d6a000 0 0x31000>, + <0 0x0b290000 0 0x10000>, + <0 0x0b490000 0 0x10000>; + reg-names =3D "gmu", + "gmu_pdc", + "gmu_pdc_seq"; + + interrupts =3D , + ; + interrupt-names =3D "hfi", + "gmu"; + + clocks =3D <&gpucc GPU_CC_AHB_CLK>, + <&gpucc GPU_CC_CX_GMU_CLK>, + <&gpucc GPU_CC_CXO_CLK>, + <&gcc GCC_DDRSS_GPU_AXI_CLK>, + <&gcc GCC_GPU_MEMNOC_GFX_CLK>; + clock-names =3D "ahb", + "gmu", + "cxo", + "axi", + "memnoc"; + + power-domains =3D <&gpucc GPU_CX_GDSC>, + <&gpucc GPU_GX_GDSC>; + power-domain-names =3D "cx", + "gx"; + + iommus =3D <&adreno_smmu 5>; + + operating-points-v2 =3D <&gmu_opp_table>; + + status =3D "disabled"; + + gmu_opp_table: opp-table { + compatible =3D "operating-points-v2"; + + opp-200000000 { + opp-hz =3D /bits/ 64 <200000000>; + opp-level =3D ; + }; + }; + }; + gpucc: clock-controller@3d90000 { compatible =3D "qcom,sm6350-gpucc"; reg =3D <0 0x03d90000 0 0x9000>; --=20 2.41.0 From nobody Sun Feb 8 04:52:26 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id CB34AEB64D9 for ; Wed, 14 Jun 2023 11:36:21 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S244190AbjFNLgS (ORCPT ); Wed, 14 Jun 2023 07:36:18 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:49526 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S244112AbjFNLgC (ORCPT ); Wed, 14 Jun 2023 07:36:02 -0400 Received: from mail-lf1-x135.google.com (mail-lf1-x135.google.com [IPv6:2a00:1450:4864:20::135]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 5FCFC1FC2 for ; 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[83.9.29.190]) by smtp.gmail.com with ESMTPSA id x1-20020ac25dc1000000b004f64b8eee61sm2088406lfq.97.2023.06.14.04.35.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 14 Jun 2023 04:35:58 -0700 (PDT) From: Konrad Dybcio Date: Wed, 14 Jun 2023 13:35:37 +0200 Subject: [PATCH v2 6/7] arm64: dts: qcom: sm6350: Fix ZAP region MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20230315-topic-lagoon_gpu-v2-6-afcdfb18bb13@linaro.org> References: <20230315-topic-lagoon_gpu-v2-0-afcdfb18bb13@linaro.org> In-Reply-To: <20230315-topic-lagoon_gpu-v2-0-afcdfb18bb13@linaro.org> To: Bjorn Andersson , Andy Gross , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , AngeloGioacchino Del Regno , Conor Dooley Cc: Marijn Suijten , Rob Herring , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Konrad Dybcio , Konrad Dybcio , Luca Weiss X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1686742545; l=1250; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=wA9dheoyA1ln4NvQBVP3cvzvxEDd9mOV0aNi6Nn+GZc=; b=jpOGbEnm0du6ha9Dcj9SzfnJzFLTmhh2bU0tQrKoZpzbTa8fxnpwnKcaeYhjNrLL1MxllBZxs I+/waT1dv17BdkxDs6nu341aPbP793c+5b2GtbPrSYjqkseyh55ky7G X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Konrad Dybcio The previous ZAP region definition was wrong. Fix it. Note this is not a device-specific fixup, but a fixup to the generic PIL load address. Fixes: 5f82b9cda61e ("arm64: dts: qcom: Add SM6350 device tree") Signed-off-by: Konrad Dybcio Reviewed-by: Luca Weiss Signed-off-by: Konrad Dybcio --- arch/arm64/boot/dts/qcom/sm6350.dtsi | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm6350.dtsi b/arch/arm64/boot/dts/qco= m/sm6350.dtsi index d928e64e33ae..cc72c4b4e7c0 100644 --- a/arch/arm64/boot/dts/qcom/sm6350.dtsi +++ b/arch/arm64/boot/dts/qcom/sm6350.dtsi @@ -634,11 +634,6 @@ pil_ipa_gsi_mem: memory@8b710000 { no-map; }; =20 - pil_gpu_mem: memory@8b715400 { - reg =3D <0 0x8b715400 0 0x2000>; - no-map; - }; - pil_modem_mem: memory@8b800000 { reg =3D <0 0x8b800000 0 0xf800000>; no-map; @@ -659,6 +654,11 @@ removed_region: memory@c0000000 { no-map; }; =20 + pil_gpu_mem: memory@f0d00000 { + reg =3D <0 0xf0d00000 0 0x1000>; + no-map; + }; + debug_region: memory@ffb00000 { reg =3D <0 0xffb00000 0 0xc0000>; no-map; --=20 2.41.0 From nobody Sun Feb 8 04:52:26 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2FBB9EB64D9 for ; Wed, 14 Jun 2023 11:36:27 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S244200AbjFNLgZ (ORCPT ); Wed, 14 Jun 2023 07:36:25 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:49666 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235967AbjFNLgL (ORCPT ); Wed, 14 Jun 2023 07:36:11 -0400 Received: from mail-lf1-x12f.google.com (mail-lf1-x12f.google.com [IPv6:2a00:1450:4864:20::12f]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 443061BF3 for ; Wed, 14 Jun 2023 04:36:02 -0700 (PDT) Received: by mail-lf1-x12f.google.com with SMTP id 2adb3069b0e04-4f61d79b0f2so8726491e87.3 for ; Wed, 14 Jun 2023 04:36:02 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1686742560; x=1689334560; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=OK0KHsEEJflt/PIWV1+p8wHbMvB3nj/Mo8p4VCQArys=; b=wkPePS6iqDnIoUgLTrHk1JbxyjqKjQE6dTMivQwJ2Uagbn22PSycxc2kHNuw5Wnh0K A872mUKQGzaS1r4627zJ+7zR3Tqlt4hOPeIi8YhTbxI+Sh+38uXCViQFweLYD1aeom12 Mo/XWxSavm/n0EyVxaaTQKPA0DX7OIXpyvh1SiZ4QdIDETow9gurc1YqcZhqfNcMfEDI s1zn3JovHSyc6Ciiw8iI44YKEOGd9rSfUmJx2HtBslicjJFTCtxfgjOretdnPK2qhN53 dzPVLrC9OEj8iJqDg5cAZpn1nADuta4WpRx0BWDq9wKSWxiNX6OyE64HbJWe/tw6gbgt bkJA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1686742560; x=1689334560; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=OK0KHsEEJflt/PIWV1+p8wHbMvB3nj/Mo8p4VCQArys=; b=HylmrqwX5On7CjDJFf8VawknUrdutYJqoSlLJxIr8qm3XoKLmEsBu8W877EgBn+7No L8jyrqv/+Mny9SUlDUl8uhZf0XTZAelTYaOdywMqV/OPNqEPZEjgm09GEp2jBmZbczXl ZYnzhkabkvpwBfFFAKAKLwL46wYIxA9wBpOXLsMZv7Tb9kXAi/e9aZKVIAnumqe6q2Ux dJr9Qt047ZgwlnW4W9++rxUv8KdR1xX2YtGjNU5qMDwYjDwxDqRRNbYa5sb7AEaI2lIW gt4mnFyVTAzJgxmXG3PQvPJBY3PX3/eW9JdHFUyjEg/EOmpgJNwPqki3vh/NQ/ATOfY3 YUnA== X-Gm-Message-State: AC+VfDzn3tE/Yre35uco+QXHjxeM1s8hMcdsNHOm6JqCWuzr+04bOWt+ wk28/Z+7IJqIGRPTWZtd7cZWsA== X-Google-Smtp-Source: ACHHUZ6Jv2L4/laQwdvAL25VVQQcOYd7w/VONldqarBguPEoXB8kYEYUYufUH8sUlPFOxoJeyAJ+mA== X-Received: by 2002:a19:3814:0:b0:4f7:66cc:6c91 with SMTP id f20-20020a193814000000b004f766cc6c91mr725672lfa.51.1686742560614; Wed, 14 Jun 2023 04:36:00 -0700 (PDT) Received: from [192.168.1.101] (abyj190.neoplus.adsl.tpnet.pl. [83.9.29.190]) by smtp.gmail.com with ESMTPSA id x1-20020ac25dc1000000b004f64b8eee61sm2088406lfq.97.2023.06.14.04.35.58 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 14 Jun 2023 04:36:00 -0700 (PDT) From: Konrad Dybcio Date: Wed, 14 Jun 2023 13:35:38 +0200 Subject: [PATCH v2 7/7] arm64: dts: qcom: sm6350: Add DPU1 nodes MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20230315-topic-lagoon_gpu-v2-7-afcdfb18bb13@linaro.org> References: <20230315-topic-lagoon_gpu-v2-0-afcdfb18bb13@linaro.org> In-Reply-To: <20230315-topic-lagoon_gpu-v2-0-afcdfb18bb13@linaro.org> To: Bjorn Andersson , Andy Gross , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , AngeloGioacchino Del Regno , Conor Dooley Cc: Marijn Suijten , Rob Herring , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Konrad Dybcio , Konrad Dybcio X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1686742545; l=6597; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=bsnWCyLq477XRxbXa0duMpQVLlZ96KNWwe53+HWkyB8=; b=5m91ZIomh7uCzHHK4pGHxRokpxD7jUD6gGr3KVRapmAWyvlSqLoShF+hl2KJrjb+QO+wBNG7V 65EWxfz0B2OC0J30+k8Cf1KXcWsgHojKoEZFel1vB4H6/3fwpK8+Sre X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Konrad Dybcio Add nodes required to enable MDSS/DPU1 on SM6350. There seem to be no additional changes required to support the derivative SoCs, such as SM7225. Signed-off-by: Konrad Dybcio Signed-off-by: Konrad Dybcio --- arch/arm64/boot/dts/qcom/sm6350.dtsi | 218 +++++++++++++++++++++++++++++++= ++++ 1 file changed, 218 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm6350.dtsi b/arch/arm64/boot/dts/qco= m/sm6350.dtsi index cc72c4b4e7c0..7af6278d6b23 100644 --- a/arch/arm64/boot/dts/qcom/sm6350.dtsi +++ b/arch/arm64/boot/dts/qcom/sm6350.dtsi @@ -4,6 +4,7 @@ * Copyright (c) 2022, Luca Weiss */ =20 +#include #include #include #include @@ -1869,6 +1870,223 @@ camcc: clock-controller@ad00000 { #power-domain-cells =3D <1>; }; =20 + mdss: display-subsystem@ae00000 { + compatible =3D "qcom,sm6350-mdss"; + reg =3D <0 0x0ae00000 0 0x1000>; + reg-names =3D "mdss"; + + interrupts =3D ; + interrupt-controller; + #interrupt-cells =3D <1>; + + clocks =3D <&gcc GCC_DISP_AHB_CLK>, + <&gcc GCC_DISP_AXI_CLK>, + <&dispcc DISP_CC_MDSS_MDP_CLK>; + clock-names =3D "iface", + "bus", + "core"; + + power-domains =3D <&dispcc MDSS_GDSC>; + iommus =3D <&apps_smmu 0x800 0x2>; + + #address-cells =3D <2>; + #size-cells =3D <2>; + ranges; + + status =3D "disabled"; + + mdss_mdp: display-controller@ae01000 { + compatible =3D "qcom,sm6350-dpu"; + reg =3D <0 0x0ae01000 0 0x8f000>, + <0 0x0aeb0000 0 0x2008>; + reg-names =3D "mdp", "vbif"; + + interrupt-parent =3D <&mdss>; + interrupts =3D <0>; + + clocks =3D <&gcc GCC_DISP_AXI_CLK>, + <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&dispcc DISP_CC_MDSS_ROT_CLK>, + <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>, + <&dispcc DISP_CC_MDSS_MDP_CLK>, + <&dispcc DISP_CC_MDSS_VSYNC_CLK>; + clock-names =3D "bus", + "iface", + "rot", + "lut", + "core", + "vsync"; + + assigned-clocks =3D <&dispcc DISP_CC_MDSS_VSYNC_CLK>; + assigned-clock-rates =3D <19200000>; + + operating-points-v2 =3D <&mdp_opp_table>; + power-domains =3D <&rpmhpd SM6350_CX>; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + + dpu_intf1_out: endpoint { + remote-endpoint =3D <&mdss_dsi0_in>; + }; + }; + }; + + mdp_opp_table: opp-table { + compatible =3D "operating-points-v2"; + + opp-19200000 { + opp-hz =3D /bits/ 64 <19200000>; + required-opps =3D <&rpmhpd_opp_min_svs>; + }; + + opp-200000000 { + opp-hz =3D /bits/ 64 <200000000>; + required-opps =3D <&rpmhpd_opp_low_svs>; + }; + + opp-300000000 { + opp-hz =3D /bits/ 64 <300000000>; + required-opps =3D <&rpmhpd_opp_svs>; + }; + + opp-373333333 { + opp-hz =3D /bits/ 64 <373333333>; + required-opps =3D <&rpmhpd_opp_svs_l1>; + }; + + opp-448000000 { + opp-hz =3D /bits/ 64 <448000000>; + required-opps =3D <&rpmhpd_opp_nom>; + }; + + opp-560000000 { + opp-hz =3D /bits/ 64 <560000000>; + required-opps =3D <&rpmhpd_opp_turbo>; + }; + }; + }; + + mdss_dsi0: dsi@ae94000 { + compatible =3D "qcom,sm6350-dsi-ctrl", "qcom,mdss-dsi-ctrl"; + reg =3D <0 0x0ae94000 0 0x400>; + reg-names =3D "dsi_ctrl"; + + interrupt-parent =3D <&mdss>; + interrupts =3D <4>; + + clocks =3D <&dispcc DISP_CC_MDSS_BYTE0_CLK>, + <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>, + <&dispcc DISP_CC_MDSS_PCLK0_CLK>, + <&dispcc DISP_CC_MDSS_ESC0_CLK>, + <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&gcc GCC_DISP_AXI_CLK>; + clock-names =3D "byte", + "byte_intf", + "pixel", + "core", + "iface", + "bus"; + + assigned-clocks =3D <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, + <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>; + assigned-clock-parents =3D <&mdss_dsi0_phy 0>, <&mdss_dsi0_phy 1>; + + operating-points-v2 =3D <&mdss_dsi_opp_table>; + power-domains =3D <&rpmhpd SM6350_MX>; + + phys =3D <&mdss_dsi0_phy>; + phy-names =3D "dsi"; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + status =3D "disabled"; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + + mdss_dsi0_in: endpoint { + remote-endpoint =3D <&dpu_intf1_out>; + }; + }; + + port@1 { + reg =3D <1>; + + mdss_dsi0_out: endpoint { + }; + }; + }; + + mdss_dsi_opp_table: opp-table { + compatible =3D "operating-points-v2"; + + opp-187500000 { + opp-hz =3D /bits/ 64 <187500000>; + required-opps =3D <&rpmhpd_opp_low_svs>; + }; + + opp-300000000 { + opp-hz =3D /bits/ 64 <300000000>; + required-opps =3D <&rpmhpd_opp_svs>; + }; + + opp-358000000 { + opp-hz =3D /bits/ 64 <358000000>; + required-opps =3D <&rpmhpd_opp_svs_l1>; + }; + }; + }; + + mdss_dsi0_phy: phy@ae94400 { + compatible =3D "qcom,dsi-phy-10nm"; + reg =3D <0 0x0ae94400 0 0x200>, + <0 0x0ae94600 0 0x280>, + <0 0x0ae94a00 0 0x1e0>; + reg-names =3D "dsi_phy", + "dsi_phy_lane", + "dsi_pll"; + + #clock-cells =3D <1>; + #phy-cells =3D <0>; + + clocks =3D <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&rpmhcc RPMH_CXO_CLK>; + clock-names =3D "iface", "ref"; + + status =3D "disabled"; + }; + }; + + dispcc: clock-controller@af00000 { + compatible =3D "qcom,sm6350-dispcc"; + reg =3D <0 0x0af00000 0 0x20000>; + clocks =3D <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_DISP_GPLL0_CLK>, + <&mdss_dsi0_phy 0>, + <&mdss_dsi0_phy 1>, + <&usb_1_qmpphy QMP_USB43DP_DP_LINK_CLK>, + <&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>; + clock-names =3D "bi_tcxo", + "gcc_disp_gpll0_clk", + "dsi0_phy_pll_out_byteclk", + "dsi0_phy_pll_out_dsiclk", + "dp_phy_pll_link_clk", + "dp_phy_pll_vco_div_clk"; + #clock-cells =3D <1>; + #reset-cells =3D <1>; + #power-domain-cells =3D <1>; + }; + pdc: interrupt-controller@b220000 { compatible =3D "qcom,sm6350-pdc", "qcom,pdc"; reg =3D <0 0x0b220000 0 0x30000>, <0 0x17c000f0 0 0x64>; --=20 2.41.0