From nobody Wed Feb 11 13:13:14 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id E6673C6FD1C for ; Tue, 14 Mar 2023 15:26:31 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231598AbjCNP03 (ORCPT ); Tue, 14 Mar 2023 11:26:29 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:52800 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231221AbjCNP0Y (ORCPT ); Tue, 14 Mar 2023 11:26:24 -0400 Received: from lelv0143.ext.ti.com (lelv0143.ext.ti.com [198.47.23.248]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 5BA7AA8EBB; Tue, 14 Mar 2023 08:26:21 -0700 (PDT) Received: from lelv0265.itg.ti.com ([10.180.67.224]) by lelv0143.ext.ti.com (8.15.2/8.15.2) with ESMTP id 32EFQEHk033130; Tue, 14 Mar 2023 10:26:14 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1678807574; bh=9iZDmzGcYKdwnzSPR5idaD1Gp7AU/u25eDWk+ChwTkc=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=Z23FOTdia8b1so6KxFsPf+4n6p54g0hW2/KAQopEc2ucRk9dVk4l+iXOl6h4k3kfl ZJHYsqFP2JXkl+mHJhik+RnVXMMj8iC0wykesbLCx83zYkBnRcR4hz3drG7e8/Bg89 l4JLaOj/LGypNZJSAKCFpL0aISUeafwyAj3+kD1s= Received: from DFLE108.ent.ti.com (dfle108.ent.ti.com [10.64.6.29]) by lelv0265.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 32EFQEF8007507 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Tue, 14 Mar 2023 10:26:14 -0500 Received: from DFLE103.ent.ti.com (10.64.6.24) by DFLE108.ent.ti.com (10.64.6.29) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.16; Tue, 14 Mar 2023 10:26:14 -0500 Received: from lelv0327.itg.ti.com (10.180.67.183) by DFLE103.ent.ti.com (10.64.6.24) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.16 via Frontend Transport; Tue, 14 Mar 2023 10:26:13 -0500 Received: from localhost (ileaxei01-snat.itg.ti.com [10.180.69.5]) by lelv0327.itg.ti.com (8.15.2/8.15.2) with ESMTP id 32EFQD3X059623; Tue, 14 Mar 2023 10:26:13 -0500 From: Jayesh Choudhary To: , CC: , , , , , , , , , Subject: [PATCH v2 1/2] arm64: dts: ti: k3-j784s4-*: Add 'ti,sci-dev-id' for NAVSS nodes Date: Tue, 14 Mar 2023 20:56:10 +0530 Message-ID: <20230314152611.140969-2-j-choudhary@ti.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230314152611.140969-1-j-choudhary@ti.com> References: <20230314152611.140969-1-j-choudhary@ti.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" TISCI device ID for main_navss and mcu_navss nodes are missing in the device tree. Add them. Fixes: 4664ebd8346a ("arm64: dts: ti: Add initial support for J784S4 SoC") Signed-off-by: Jayesh Choudhary Reviewed-by: Kamlesh Gurudasani --- arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi | 1 + arch/arm64/boot/dts/ti/k3-j784s4-mcu-wakeup.dtsi | 1 + 2 files changed, 2 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi b/arch/arm64/boot/d= ts/ti/k3-j784s4-main.dtsi index 7edf324ac159..80a1b08c51a8 100644 --- a/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi @@ -398,6 +398,7 @@ main_navss: bus@30000000 { #address-cells =3D <2>; #size-cells =3D <2>; ranges =3D <0x00 0x30000000 0x00 0x30000000 0x00 0x0c400000>; + ti,sci-dev-id =3D <280>; dma-coherent; dma-ranges; =20 diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-mcu-wakeup.dtsi b/arch/arm64/= boot/dts/ti/k3-j784s4-mcu-wakeup.dtsi index 93952af618f6..64bd3dee14aa 100644 --- a/arch/arm64/boot/dts/ti/k3-j784s4-mcu-wakeup.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j784s4-mcu-wakeup.dtsi @@ -209,6 +209,7 @@ mcu_navss: bus@28380000{ #address-cells =3D <2>; #size-cells =3D <2>; ranges =3D <0x00 0x28380000 0x00 0x28380000 0x00 0x03880000>; + ti,sci-dev-id =3D <323>; dma-coherent; dma-ranges; =20 --=20 2.25.1 From nobody Wed Feb 11 13:13:14 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 764A1C6FD1C for ; Tue, 14 Mar 2023 15:26:35 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231670AbjCNP0e (ORCPT ); Tue, 14 Mar 2023 11:26:34 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:53030 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231588AbjCNP02 (ORCPT ); Tue, 14 Mar 2023 11:26:28 -0400 Received: from fllv0016.ext.ti.com (fllv0016.ext.ti.com [198.47.19.142]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id A4E72A90AF; Tue, 14 Mar 2023 08:26:24 -0700 (PDT) Received: from lelv0265.itg.ti.com ([10.180.67.224]) by fllv0016.ext.ti.com (8.15.2/8.15.2) with ESMTP id 32EFQFvp034003; Tue, 14 Mar 2023 10:26:15 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1678807575; bh=bUlS1XDh1SiyLkHKtty1uerUX/cPuFQFnrDu+X2hbBU=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=v1ROpvPoYgZhvmN0kmxNO7/Ua/Gt/K9VQ+BEewFnfIIu6Txs5LJC4wn06hKOTzRBO CBPSjPbJvi4V5AVl8Ia7eJ6d6MlZ10AiG9JqjaE49nngPVPaY+yiFJUF9sFf+1BmNG 8vjWe/zJeFimZ8qv/GM8l1GNX5an2wmxqY6aBKwY= Received: from DLEE104.ent.ti.com (dlee104.ent.ti.com [157.170.170.34]) by lelv0265.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 32EFQFQa007520 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Tue, 14 Mar 2023 10:26:15 -0500 Received: from DLEE112.ent.ti.com (157.170.170.23) by DLEE104.ent.ti.com (157.170.170.34) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.16; Tue, 14 Mar 2023 10:26:15 -0500 Received: from lelv0326.itg.ti.com (10.180.67.84) by DLEE112.ent.ti.com (157.170.170.23) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.16 via Frontend Transport; Tue, 14 Mar 2023 10:26:15 -0500 Received: from localhost (ileaxei01-snat2.itg.ti.com [10.180.69.6]) by lelv0326.itg.ti.com (8.15.2/8.15.2) with ESMTP id 32EFQEAv017680; Tue, 14 Mar 2023 10:26:15 -0500 From: Jayesh Choudhary To: , CC: , , , , , , , , , Subject: [PATCH v2 2/2] arm64: dts: ti: k3-j784s4-main: Enable crypto accelerator Date: Tue, 14 Mar 2023 20:56:11 +0530 Message-ID: <20230314152611.140969-3-j-choudhary@ti.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230314152611.140969-1-j-choudhary@ti.com> References: <20230314152611.140969-1-j-choudhary@ti.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add the node for SA2UL to support hardware crypto algorithms, including SHA-1/256/512, AES, 3DES and AEAD suites. Add rng node for hardware random number generator. Signed-off-by: Jayesh Choudhary Reviewed-by: Kamlesh Gurudasani --- arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi b/arch/arm64/boot/d= ts/ti/k3-j784s4-main.dtsi index 80a1b08c51a8..8c1474a7bd0f 100644 --- a/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi @@ -72,6 +72,25 @@ main_pmx0: pinctrl@11c000 { pinctrl-single,function-mask =3D <0xffffffff>; }; =20 + main_crypto: crypto@4e00000 { + compatible =3D "ti,j721e-sa2ul"; + reg =3D <0x00 0x4e00000 0x00 0x1200>; + power-domains =3D <&k3_pds 369 TI_SCI_PD_EXCLUSIVE>; + #address-cells =3D <2>; + #size-cells =3D <2>; + ranges =3D <0x00 0x04e00000 0x00 0x04e00000 0x00 0x30000>; + + dmas =3D <&main_udmap 0xca40>, <&main_udmap 0x4a40>, + <&main_udmap 0x4a41>; + dma-names =3D "tx", "rx1", "rx2"; + + rng: rng@4e10000 { + compatible =3D "inside-secure,safexcel-eip76"; + reg =3D <0x00 0x4e10000 0x00 0x7d>; + interrupts =3D ; + }; + }; + main_uart0: serial@2800000 { compatible =3D "ti,j721e-uart", "ti,am654-uart"; reg =3D <0x00 0x02800000 0x00 0x200>; --=20 2.25.1