From nobody Sun Sep 14 20:25:45 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9B083C6FD1C for ; Tue, 14 Mar 2023 08:05:05 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229456AbjCNIFD (ORCPT ); Tue, 14 Mar 2023 04:05:03 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:37868 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230333AbjCNIFB (ORCPT ); Tue, 14 Mar 2023 04:05:01 -0400 Received: from mail-pj1-x102a.google.com (mail-pj1-x102a.google.com [IPv6:2607:f8b0:4864:20::102a]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 73DD92B604 for ; Tue, 14 Mar 2023 01:04:59 -0700 (PDT) Received: by mail-pj1-x102a.google.com with SMTP id j3-20020a17090adc8300b0023d09aea4a6so5182581pjv.5 for ; Tue, 14 Mar 2023 01:04:59 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1678781099; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=e2qLWiEu+kwQHNuuyN9RiYgLYwjEZFKFrGhRPUZl538=; b=kUttmv50P6JaqbAfZWMvjFT69NXu1Mn44b5z8H5CQIUokMJkaddWBjXPbDl4gno60y bzBIGnQNDD5UZSDt3gbM/Izp479BCMnLTG9AfGHJlfC2C6B+iAqZABelML15p2Dzt+b0 d2Klm4DT5X8GEJLoh9Sc6MyStWYXaOmXq/+e5p1LhRac/IkExM2EQR9XaQ+aSi1MgmTM 7ynbySiUWnTa8veOsW7b6wy+WRLB7uU0qosh61Ki3QCwzcC6W1ka89KiBkDjqtOCkHcn y1MdyIDsSP8mPcxj7zIbI2Grt7m/m9tuuhiTnEkY8LKZ7ghH1MXeo3tOEnw9DdUhwCyW 330Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1678781099; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=e2qLWiEu+kwQHNuuyN9RiYgLYwjEZFKFrGhRPUZl538=; b=tzNICqfSdeXmOBcHcBUt9RKjtRgKrH19BJWoDu+tzXBk4+LghjHNwx6B5VTVQ+kM7T 1R5Io/80brEWiO+V31TaoNY0VayUkdqOLx1NBU2IU+vU0YcnDHJGOtPEiE+WkxSJd4tM A9L8Ao5TaAfGlzYWymMZRDqrxv5EXnv91Hr2OktWXb3BKMC8qZedxOvqhLxp0e2mBAgf U6XJrHAumN14uUzc2cm8srcqpW4V8Zc1QEUgCcm8KAu1MZ3HSwh23ccE5RipVeN7dM0D 3oRZSYEfAaOFWSpHrsiSgXAnkM/SF2CaRBQSJPPaHwRicz5gs3Ah+UGpj2WMGN4GY8Ng F2wA== X-Gm-Message-State: AO0yUKUzh1Oqwhd7Obg6Xx+RfEgxpLEZcJgd0zexyqC+JkbhRFFr+Zm6 zCwZss8r5gW7jDaKT+Q2DnQe X-Google-Smtp-Source: AK7set/Wuc2f6xzJUbp88JtCtHXmKq6x8/IUFkEzI3k5FSxbK7fOxSRzO6ogfiwCrJFmPAUMq5dQpg== X-Received: by 2002:a17:902:c949:b0:19a:59d1:389e with SMTP id i9-20020a170902c94900b0019a59d1389emr14167228pla.23.1678781098879; Tue, 14 Mar 2023 01:04:58 -0700 (PDT) Received: from localhost.localdomain ([117.217.177.49]) by smtp.gmail.com with ESMTPSA id l8-20020a170902f68800b001994a0f3380sm1078022plg.265.2023.03.14.01.04.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 14 Mar 2023 01:04:58 -0700 (PDT) From: Manivannan Sadhasivam To: andersson@kernel.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, bp@alien8.de, tony.luck@intel.com Cc: konrad.dybcio@linaro.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, james.morse@arm.com, mchehab@kernel.org, rric@kernel.org, linux-edac@vger.kernel.org, quic_ppareek@quicinc.com, luca.weiss@fairphone.com, ahalaney@redhat.com, steev@kali.org, Manivannan Sadhasivam Subject: [PATCH v8 01/14] dt-bindings: arm: msm: Update the maintainers for LLCC Date: Tue, 14 Mar 2023 13:34:30 +0530 Message-Id: <20230314080443.64635-2-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230314080443.64635-1-manivannan.sadhasivam@linaro.org> References: <20230314080443.64635-1-manivannan.sadhasivam@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Both Rishabh and Sai have left Qualcomm, and there is no evidence of them maintaining with a new identity. So their entry needs to be removed. Listed Bjorn as the interim maintainer until someone volunteers to maintain this binding. Signed-off-by: Manivannan Sadhasivam Acked-by: Krzysztof Kozlowski --- Documentation/devicetree/bindings/arm/msm/qcom,llcc.yaml | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/arm/msm/qcom,llcc.yaml b/Doc= umentation/devicetree/bindings/arm/msm/qcom,llcc.yaml index 38efcad56dbd..6570b808fd0d 100644 --- a/Documentation/devicetree/bindings/arm/msm/qcom,llcc.yaml +++ b/Documentation/devicetree/bindings/arm/msm/qcom,llcc.yaml @@ -7,8 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: Last Level Cache Controller =20 maintainers: - - Rishabh Bhatnagar - - Sai Prakash Ranjan + - Bjorn Andersson =20 description: | LLCC (Last Level Cache Controller) provides last level of cache memory i= n SoC, --=20 2.25.1 From nobody Sun Sep 14 20:25:45 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9D306C7618A for ; Tue, 14 Mar 2023 08:05:15 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230013AbjCNIFO (ORCPT ); Tue, 14 Mar 2023 04:05:14 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:38222 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230378AbjCNIFJ (ORCPT ); Tue, 14 Mar 2023 04:05:09 -0400 Received: from mail-pl1-x632.google.com (mail-pl1-x632.google.com [IPv6:2607:f8b0:4864:20::632]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id BB24877CBA for ; Tue, 14 Mar 2023 01:05:05 -0700 (PDT) Received: by mail-pl1-x632.google.com with SMTP id p20so15677242plw.13 for ; Tue, 14 Mar 2023 01:05:05 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1678781105; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=E3ynFMYwQcpfXg1vBUZGiwqSjOZbWEHjnhI8PWp4GCE=; b=j7xvaNy2aA+o+3gb3Dvuc5Gw42SQp4fw7wM3jyYBLIU+W2YQWfLA3pC7l/N1UA8/BE BkoZsjVK32Wfus2lsJfzYjm550ld0xIFD5JvEEcEDbuMspSarOq54iEz0WTn59NegK0J RM6T4zNBgRYgRi75maX+ZIr5qv3tGSDQcGRQs1nv8c2LMDPmOerqVbACYaP8dWQ5CpbT WPToLBnPAf+emWdkUaXPDOeVxPYlBq9I7dvStU2ZdaiMUmMbinG414mp9y/duh7F0FI0 Ac055n7DGUye+GOoEk5pNTt8tM5m0Ej88zqCpoWtaZt4Mw6Fer45C8j1XmBaocofZNgz ITBQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1678781105; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=E3ynFMYwQcpfXg1vBUZGiwqSjOZbWEHjnhI8PWp4GCE=; b=njuT3VJjlTtWaxmsWW07mey08oXAmTweVAEboTRWpsKt51XxlOIuuC0oZTjmb3UmF5 RLnNZsMs/YV0hhTguuDKMNX9wChFST45Vg6z5CDv/JNf4/SAPCMHoabg8z9qlrE3xxdo OHXoMMs/Cm5frzAvL4NRhp1BD/3wk5GT4vg6FFhJwu7nMg1eCYvstdrR+qUDY5FPHWrA GMz4gGmHjV3HnxF9yve7JVFg/dGi3ewFPiiCKAKN0RQiMnGOh5r9DbkDPb0kgtOdDG/I vsl6b2A4B5QUV20s0iRWl6m45TG9xhwnPZ5EQ2sSkx913apNgXpF5B3DQOMee7rFj7OR 59BA== X-Gm-Message-State: AO0yUKW81NvjgePC8Rb648ABLImf8boPnunb+ct6NDcTy6zrtnEsP4Cj kLyca/H3CaoXttz7cNdrzMGh X-Google-Smtp-Source: AK7set+dn8942e/cqeFhAuAmJLdev5Ni6BMCm2yi8gCsc2582luPHUX9sBl743YZQEgf2T+6vQLv3w== X-Received: by 2002:a17:902:c949:b0:19e:416e:abf5 with SMTP id i9-20020a170902c94900b0019e416eabf5mr13643147pla.34.1678781104771; Tue, 14 Mar 2023 01:05:04 -0700 (PDT) Received: from localhost.localdomain ([117.217.177.49]) by smtp.gmail.com with ESMTPSA id l8-20020a170902f68800b001994a0f3380sm1078022plg.265.2023.03.14.01.04.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 14 Mar 2023 01:05:03 -0700 (PDT) From: Manivannan Sadhasivam To: andersson@kernel.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, bp@alien8.de, tony.luck@intel.com Cc: konrad.dybcio@linaro.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, james.morse@arm.com, mchehab@kernel.org, rric@kernel.org, linux-edac@vger.kernel.org, quic_ppareek@quicinc.com, luca.weiss@fairphone.com, ahalaney@redhat.com, steev@kali.org, Manivannan Sadhasivam , Krzysztof Kozlowski Subject: [PATCH v8 02/14] dt-bindings: arm: msm: Fix register regions used for LLCC banks Date: Tue, 14 Mar 2023 13:34:31 +0530 Message-Id: <20230314080443.64635-3-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230314080443.64635-1-manivannan.sadhasivam@linaro.org> References: <20230314080443.64635-1-manivannan.sadhasivam@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Register regions of the LLCC banks are located at different addresses. Currently, the binding just lists the LLCC0 base address and tries to cover all the banks using a single size. This is entirely wrong as there are other register regions that happen to lie inside the size covered by the binding such as the memory controller and holes. So this needs to be fixed by specifying the base address of individual LLCC banks. This approach will break the existing users of this binding as the register regions are split and the drivers now cannot use LLCC0 register region for accessing rest of the banks (which is wrong anyway). But considering the fact that the binding was wrong from the day one and also the device drivers going wrong by the binding, this breakage is acceptable. Reported-by: Parikshit Pareek Reviewed-by: Krzysztof Kozlowski Signed-off-by: Manivannan Sadhasivam --- .../bindings/arm/msm/qcom,llcc.yaml | 125 ++++++++++++++++-- 1 file changed, 114 insertions(+), 11 deletions(-) diff --git a/Documentation/devicetree/bindings/arm/msm/qcom,llcc.yaml b/Doc= umentation/devicetree/bindings/arm/msm/qcom,llcc.yaml index 6570b808fd0d..93b977428a14 100644 --- a/Documentation/devicetree/bindings/arm/msm/qcom,llcc.yaml +++ b/Documentation/devicetree/bindings/arm/msm/qcom,llcc.yaml @@ -33,14 +33,12 @@ properties: - qcom,sm8550-llcc =20 reg: - items: - - description: LLCC base register region - - description: LLCC broadcast base register region + minItems: 2 + maxItems: 9 =20 reg-names: - items: - - const: llcc_base - - const: llcc_broadcast_base + minItems: 2 + maxItems: 9 =20 interrupts: maxItems: 1 @@ -50,15 +48,120 @@ required: - reg - reg-names =20 +allOf: + - if: + properties: + compatible: + contains: + enum: + - qcom,sc7180-llcc + - qcom,sm6350-llcc + then: + properties: + reg: + items: + - description: LLCC0 base register region + - description: LLCC broadcast base register region + reg-names: + items: + - const: llcc0_base + - const: llcc_broadcast_base + + - if: + properties: + compatible: + contains: + enum: + - qcom,sc7280-llcc + then: + properties: + reg: + items: + - description: LLCC0 base register region + - description: LLCC1 base register region + - description: LLCC broadcast base register region + reg-names: + items: + - const: llcc0_base + - const: llcc1_base + - const: llcc_broadcast_base + + - if: + properties: + compatible: + contains: + enum: + - qcom,sc8180x-llcc + - qcom,sc8280xp-llcc + then: + properties: + reg: + items: + - description: LLCC0 base register region + - description: LLCC1 base register region + - description: LLCC2 base register region + - description: LLCC3 base register region + - description: LLCC4 base register region + - description: LLCC5 base register region + - description: LLCC6 base register region + - description: LLCC7 base register region + - description: LLCC broadcast base register region + reg-names: + items: + - const: llcc0_base + - const: llcc1_base + - const: llcc2_base + - const: llcc3_base + - const: llcc4_base + - const: llcc5_base + - const: llcc6_base + - const: llcc7_base + - const: llcc_broadcast_base + + - if: + properties: + compatible: + contains: + enum: + - qcom,sdm845-llcc + - qcom,sm8150-llcc + - qcom,sm8250-llcc + - qcom,sm8350-llcc + - qcom,sm8450-llcc + then: + properties: + reg: + items: + - description: LLCC0 base register region + - description: LLCC1 base register region + - description: LLCC2 base register region + - description: LLCC3 base register region + - description: LLCC broadcast base register region + reg-names: + items: + - const: llcc0_base + - const: llcc1_base + - const: llcc2_base + - const: llcc3_base + - const: llcc_broadcast_base + additionalProperties: false =20 examples: - | #include =20 - system-cache-controller@1100000 { - compatible =3D "qcom,sdm845-llcc"; - reg =3D <0x1100000 0x200000>, <0x1300000 0x50000> ; - reg-names =3D "llcc_base", "llcc_broadcast_base"; - interrupts =3D ; + soc { + #address-cells =3D <2>; + #size-cells =3D <2>; + + system-cache-controller@1100000 { + compatible =3D "qcom,sdm845-llcc"; + reg =3D <0 0x01100000 0 0x50000>, <0 0x01180000 0 0x50000>, + <0 0x01200000 0 0x50000>, <0 0x01280000 0 0x50000>, + <0 0x01300000 0 0x50000>; + reg-names =3D "llcc0_base", "llcc1_base", "llcc2_base", + "llcc3_base", "llcc_broadcast_base"; + interrupts =3D ; + }; }; --=20 2.25.1 From nobody Sun Sep 14 20:25:45 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id B9090C6FD1C for ; Tue, 14 Mar 2023 08:05:43 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230415AbjCNIFm (ORCPT ); Tue, 14 Mar 2023 04:05:42 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:38686 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230408AbjCNIFU (ORCPT ); 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Tue, 14 Mar 2023 01:05:11 -0700 (PDT) From: Manivannan Sadhasivam To: andersson@kernel.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, bp@alien8.de, tony.luck@intel.com Cc: konrad.dybcio@linaro.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, james.morse@arm.com, mchehab@kernel.org, rric@kernel.org, linux-edac@vger.kernel.org, quic_ppareek@quicinc.com, luca.weiss@fairphone.com, ahalaney@redhat.com, steev@kali.org, Manivannan Sadhasivam Subject: [PATCH v8 03/14] arm64: dts: qcom: sdm845: Fix the base addresses of LLCC banks Date: Tue, 14 Mar 2023 13:34:32 +0530 Message-Id: <20230314080443.64635-4-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230314080443.64635-1-manivannan.sadhasivam@linaro.org> References: <20230314080443.64635-1-manivannan.sadhasivam@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" The LLCC block has several banks each with a different base address and holes in between. So it is not a correct approach to cover these banks with a single offset/size. Instead, the individual bank's base address needs to be specified in devicetree with the exact size. On SDM845, the size of the LLCC bank 0 needs to be reduced to 0x4500 as there are LLCC BWMON registers located after this range. Reported-by: Parikshit Pareek Signed-off-by: Manivannan Sadhasivam --- arch/arm64/boot/dts/qcom/sdm845.dtsi | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qco= m/sdm845.dtsi index 479859bd8ab3..3bf95a12ebb9 100644 --- a/arch/arm64/boot/dts/qcom/sdm845.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi @@ -2192,8 +2192,11 @@ uart15: serial@a9c000 { =20 llcc: system-cache-controller@1100000 { compatible =3D "qcom,sdm845-llcc"; - reg =3D <0 0x01100000 0 0x31000>, <0 0x01300000 0 0x50000>; - reg-names =3D "llcc_base", "llcc_broadcast_base"; + reg =3D <0 0x01100000 0 0x45000>, <0 0x01180000 0 0x50000>, + <0 0x01200000 0 0x50000>, <0 0x01280000 0 0x50000>, + <0 0x01300000 0 0x50000>; + reg-names =3D "llcc0_base", "llcc1_base", "llcc2_base", + "llcc3_base", "llcc_broadcast_base"; interrupts =3D ; }; =20 --=20 2.25.1 From nobody Sun Sep 14 20:25:45 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4A647C6FD1F for ; Tue, 14 Mar 2023 08:05:56 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230231AbjCNIFz (ORCPT ); Tue, 14 Mar 2023 04:05:55 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:38628 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230250AbjCNIFb (ORCPT ); Tue, 14 Mar 2023 04:05:31 -0400 Received: from mail-pl1-x636.google.com (mail-pl1-x636.google.com [IPv6:2607:f8b0:4864:20::636]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id DF3DA7BA06 for ; Tue, 14 Mar 2023 01:05:18 -0700 (PDT) Received: by mail-pl1-x636.google.com with SMTP id h8so15691505plf.10 for ; Tue, 14 Mar 2023 01:05:18 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1678781118; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=5/ORW+ZG5QT+TPocYHNFiE88/XBOJZ36UEuAeSGiS3k=; b=Ah5xLrCNiduHUWjN3eAaifuW7SBx2eBFJQeZCeBpzAd9oCHrqH41XV5WJgUV0AsMtm 4rFmJW5lhmSwbaMxXEahhhQYnOGfaYmMMNUHCooR3qE64bce+IQ65e3+TGIqQ12kP5tM xzxXWOmF9wYI+IbWiTbGptEVE3FvQJqhOXOSTciVyyDBxfP6YACrSuszlmGCR4Vh8DRj JW5AVs8F5x3wiVXTZnaTOmWoC22marNdES2xjvcZQmUSJq8Pjrk2EaN0V7rm0UzRjRAC DeVJXmF5Dj0VKvxSL6UD9eWJkhdqQlw3zpiL/pVYrOazSIeGCh7kFRBK48KAW3vceflV G1tg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1678781118; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=5/ORW+ZG5QT+TPocYHNFiE88/XBOJZ36UEuAeSGiS3k=; b=xasroluE+4ek5kWfkHhCXK4LeXxL61bonosrZy8l6uHCnP+NKQvM9t0jBqmeGjFqGZ ab+e+y/Mopu5F3f0W5pNilu/n4a/3zCSys9UP1PkM7Rgf0xnrfhYJq/YLumTEP4DYwMG Qxgs3+CquYlyHMc4UVnHSNgXthZqVaf/nmHlB5ZC3Uxhh4MoV8RheJIC2cStEK8lbUoS tqocGffd88xYUx41fXNsNwCYd0qPxFoJEPKxPl7P/27dsgY1cTNebAD1v/sM6Ijb9qt6 KKI+m+QRS5Yacli/qHBla8PrP37W5WCmwGi6zSNdH21GDjXTN4LvHIDefyu8pU2HXzzL KPnQ== X-Gm-Message-State: AO0yUKUK1aZQOq2WDwiq3Ek7Yp3I1GU6VDAWvKMXpc8xUKsAMnvVecCH uPqUI2SroVKSErU0/u0MEOAn X-Google-Smtp-Source: AK7set/SOSxTXU7eeyeseVznLYWE+Jvg5yOMvsbQOS7f2n2I04NMPOPYimkWYhhIQlGQw1/+K/sEAQ== X-Received: by 2002:a17:902:e748:b0:19e:82d5:634c with SMTP id p8-20020a170902e74800b0019e82d5634cmr40549164plf.53.1678781118418; Tue, 14 Mar 2023 01:05:18 -0700 (PDT) Received: from localhost.localdomain ([117.217.177.49]) by smtp.gmail.com with ESMTPSA id l8-20020a170902f68800b001994a0f3380sm1078022plg.265.2023.03.14.01.05.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 14 Mar 2023 01:05:17 -0700 (PDT) From: Manivannan Sadhasivam To: andersson@kernel.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, bp@alien8.de, tony.luck@intel.com Cc: konrad.dybcio@linaro.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, james.morse@arm.com, mchehab@kernel.org, rric@kernel.org, linux-edac@vger.kernel.org, quic_ppareek@quicinc.com, luca.weiss@fairphone.com, ahalaney@redhat.com, steev@kali.org, Manivannan Sadhasivam Subject: [PATCH v8 04/14] arm64: dts: qcom: sc7180: Fix the base addresses of LLCC banks Date: Tue, 14 Mar 2023 13:34:33 +0530 Message-Id: <20230314080443.64635-5-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230314080443.64635-1-manivannan.sadhasivam@linaro.org> References: <20230314080443.64635-1-manivannan.sadhasivam@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" The LLCC block has several banks each with a different base address and holes in between. So it is not a correct approach to cover these banks with a single offset/size. Instead, the individual bank's base address needs to be specified in devicetree with the exact size. On SC7180, there is only one LLCC bank available. So let's just pass that as "llcc0_base". Reported-by: Parikshit Pareek Signed-off-by: Manivannan Sadhasivam --- arch/arm64/boot/dts/qcom/sc7180.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sc7180.dtsi b/arch/arm64/boot/dts/qco= m/sc7180.dtsi index ebfa21e9ed8a..62cc9eb4882d 100644 --- a/arch/arm64/boot/dts/qcom/sc7180.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7180.dtsi @@ -2760,7 +2760,7 @@ dc_noc: interconnect@9160000 { system-cache-controller@9200000 { compatible =3D "qcom,sc7180-llcc"; reg =3D <0 0x09200000 0 0x50000>, <0 0x09600000 0 0x50000>; - reg-names =3D "llcc_base", "llcc_broadcast_base"; + reg-names =3D "llcc0_base", "llcc_broadcast_base"; interrupts =3D ; }; =20 --=20 2.25.1 From nobody Sun Sep 14 20:25:45 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 19114C74A44 for ; Tue, 14 Mar 2023 08:06:06 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230034AbjCNIGF (ORCPT ); Tue, 14 Mar 2023 04:06:05 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:38258 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230464AbjCNIFk (ORCPT ); Tue, 14 Mar 2023 04:05:40 -0400 Received: from mail-pj1-x102e.google.com (mail-pj1-x102e.google.com [IPv6:2607:f8b0:4864:20::102e]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 09A5D7F039 for ; Tue, 14 Mar 2023 01:05:24 -0700 (PDT) Received: by mail-pj1-x102e.google.com with SMTP id y15-20020a17090aa40f00b00237ad8ee3a0so14318962pjp.2 for ; Tue, 14 Mar 2023 01:05:24 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1678781124; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=H3jjAvyClxqCSaG5sOi6OveXFyY33UJ9o9fFaRGOIoU=; b=TPe49wQ55ZzjXtL1UhusZl5uDaWHm9T2bYehPMS/MgB1zXGYXYXd+Il8eMkq3hVezK Jxl0H1dW3Z4Dh4DnVnxdD0GHDOrGhsqNw4XajjmEk5hadqij+8/HsaCK9GeAJPmn6L8k fE6nt06k4eCKMBmVEkHElAN+09cYJ54nbpSIlZ9OChY5I+SEjKp/b6pTMc/MYOSJr2CZ zCbaVqG1lIED2bPKylCCmXu3LWAUAMeJLRF8aW/v/SAuhl0RwicXXGaR1xT0ryQ9omzu bzYWCTAN81C88SbdXaG3t1p7iCLwuqq4cmJJEOv92d/SWrW42hyHuijuBC0tcAlzQFP+ 3rTQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1678781124; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=H3jjAvyClxqCSaG5sOi6OveXFyY33UJ9o9fFaRGOIoU=; b=tNo5Ypr/pbvpFSdfJ5ku9XDwWT1Q5uTeeGXkI2n89R6ap2tTUQ81y0Yc53qmZGOl0+ t09jkITOArgk3tqEH1SLWwD3BMcNRc3yuO7jrT2THx7nXOa2tSaPxt0IPEG5F9/rMZLW /CCqvKcanciTc2rPcN3AXfLkgfoDCzAQgzCbo9EVc9IrofLkTSBvPUE8RJchl4jxTJp3 RYW1h3VByq5xjQvQdzYvu5iVJ9ODXbBE+8nvXcE1vMr/WCi4P6h1yCV0bDcud3n9uBIS Dkl8WxMHLTu4oZTSeBRP3kTUz7idmj1fNOLDjiojvHdEXyRMk9jYzu4dbHZgrfbNhALO S5uQ== X-Gm-Message-State: AO0yUKXzFxOP+sFRr2E7rm1XJSUUpkCm8V/ogblnRa309UHptHUTRmrL sq3ODkbh/473OFXH08BAx9RP X-Google-Smtp-Source: AK7set/YSOsQvqiPeL9DG52pW06edvX1Z7qaNl3Bn0+V0f31PkjxqRhu0MdFbr9SW/n2qr7smeYKQw== X-Received: by 2002:a17:903:41c9:b0:19f:380e:9cca with SMTP id u9-20020a17090341c900b0019f380e9ccamr7917000ple.20.1678781124191; Tue, 14 Mar 2023 01:05:24 -0700 (PDT) Received: from localhost.localdomain ([117.217.177.49]) by smtp.gmail.com with ESMTPSA id l8-20020a170902f68800b001994a0f3380sm1078022plg.265.2023.03.14.01.05.18 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 14 Mar 2023 01:05:23 -0700 (PDT) From: Manivannan Sadhasivam To: andersson@kernel.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, bp@alien8.de, tony.luck@intel.com Cc: konrad.dybcio@linaro.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, james.morse@arm.com, mchehab@kernel.org, rric@kernel.org, linux-edac@vger.kernel.org, quic_ppareek@quicinc.com, luca.weiss@fairphone.com, ahalaney@redhat.com, steev@kali.org, Manivannan Sadhasivam Subject: [PATCH v8 05/14] arm64: dts: qcom: sc7280: Fix the base addresses of LLCC banks Date: Tue, 14 Mar 2023 13:34:34 +0530 Message-Id: <20230314080443.64635-6-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230314080443.64635-1-manivannan.sadhasivam@linaro.org> References: <20230314080443.64635-1-manivannan.sadhasivam@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" The LLCC block has several banks each with a different base address and holes in between. So it is not a correct approach to cover these banks with a single offset/size. Instead, the individual bank's base address needs to be specified in devicetree with the exact size. While at it, let's also fix the size of the llcc_broadcast_base to cover the whole region. Reported-by: Parikshit Pareek Signed-off-by: Manivannan Sadhasivam --- arch/arm64/boot/dts/qcom/sc7280.dtsi | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qco= m/sc7280.dtsi index bdcb74925313..afe74db1f5ae 100644 --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi @@ -3582,8 +3582,9 @@ gem_noc: interconnect@9100000 { =20 system-cache-controller@9200000 { compatible =3D "qcom,sc7280-llcc"; - reg =3D <0 0x09200000 0 0xd0000>, <0 0x09600000 0 0x50000>; - reg-names =3D "llcc_base", "llcc_broadcast_base"; + reg =3D <0 0x09200000 0 0x58000>, <0 0x09280000 0 0x58000>, + <0 0x09600000 0 0x58000>; + reg-names =3D "llcc0_base", "llcc1_base", "llcc_broadcast_base"; interrupts =3D ; }; =20 --=20 2.25.1 From nobody Sun Sep 14 20:25:45 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id EE566C6FD1C for ; Tue, 14 Mar 2023 08:06:15 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231132AbjCNIGO (ORCPT ); Tue, 14 Mar 2023 04:06:14 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:39278 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230378AbjCNIFo (ORCPT ); Tue, 14 Mar 2023 04:05:44 -0400 Received: from mail-pj1-x1036.google.com (mail-pj1-x1036.google.com [IPv6:2607:f8b0:4864:20::1036]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 1E31382A88 for ; Tue, 14 Mar 2023 01:05:30 -0700 (PDT) Received: by mail-pj1-x1036.google.com with SMTP id gp15-20020a17090adf0f00b0023d1bbd9f9eso4086828pjb.0 for ; Tue, 14 Mar 2023 01:05:30 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1678781129; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=FI19SzWU19Jvwkg3ef2zRaEcka9BD7PAMWjZH4lQqmU=; b=qCnt+YG+qSCaRi++SQygc4LCMyUIQsxhksIdbvNciJyOVAeYykxxs4ROH0hhxvE57E QuaZ+ecJcx/P7AQqaoMNSEK3RutjcmXZdn1GlRlUha9fYBb2j4GVrs2WzfgALjIRGEwG u7m7iyLjATF5PMDivCktX/K3zQlGAIrn72F78AhCjjNofQd8e4oH0k7l2Hcge0p1npPC wMUS8z5W2Ofc6NxtslNY6WWtAauHalb1SpXHXX6OHfI+cUOltmlOt3bgpq/3PUPFoOmS hr7iXvJfzjqNVT4p/v8HaK19oMNnyLpJJECozQqNyaPrbESvtrajCpP4dJ1J69Wut8D5 +cqg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1678781129; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=FI19SzWU19Jvwkg3ef2zRaEcka9BD7PAMWjZH4lQqmU=; b=ptrGgR7mqtvB11cQcbiaV7Kix4lowNeDadP1Tvt8mRN4MTLvLy+ApM07HQovrA1PE0 RcVKJB8605bN/6p+0W0ZXb3gIV/9cFRuhG4AfVBlRxkNr8YvbHdkJuZzYhPoaolrooC6 IIOJZIftsWtOXY0xufG26H4Yzn4RjDgDw5kJ5itx3pG5BnmXo2eW6yl5pWALVF6AlF3T yRjKhYfA7sjxgjkTsgNJbqez0rJovJ9oVxRKynWfRSihzD7TlGFd4OBTWWCo54w+lxwU xCx+Lr6pqdbbU4V4yOq4/1fcEN2TLvElHLAJNtQn1e3GiP6AWHwl/WiJAZSJ+7CKBASJ TRPQ== X-Gm-Message-State: AO0yUKXHFDq1K79YSDYKKrXrLJ9UYZiM54lWgmh7ymKJDNj60Ay/yw3Q BhgNOu/+8sO/C0qYqLzlSMqv X-Google-Smtp-Source: AK7set9ahRcqSzmMuTWPUwwKEQQs0DkjVKyIH86u9FkvGD/p55MmA5aua1BQ+w63Ue4Pp4Fmbz0P9A== X-Received: by 2002:a17:90b:1645:b0:236:a4bc:222 with SMTP id il5-20020a17090b164500b00236a4bc0222mr37579028pjb.38.1678781129601; Tue, 14 Mar 2023 01:05:29 -0700 (PDT) Received: from localhost.localdomain ([117.217.177.49]) by smtp.gmail.com with ESMTPSA id l8-20020a170902f68800b001994a0f3380sm1078022plg.265.2023.03.14.01.05.24 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 14 Mar 2023 01:05:29 -0700 (PDT) From: Manivannan Sadhasivam To: andersson@kernel.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, bp@alien8.de, tony.luck@intel.com Cc: konrad.dybcio@linaro.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, james.morse@arm.com, mchehab@kernel.org, rric@kernel.org, linux-edac@vger.kernel.org, quic_ppareek@quicinc.com, luca.weiss@fairphone.com, ahalaney@redhat.com, steev@kali.org, Manivannan Sadhasivam Subject: [PATCH v8 06/14] arm64: dts: qcom: sc8280xp: Fix the base addresses of LLCC banks Date: Tue, 14 Mar 2023 13:34:35 +0530 Message-Id: <20230314080443.64635-7-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230314080443.64635-1-manivannan.sadhasivam@linaro.org> References: <20230314080443.64635-1-manivannan.sadhasivam@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" The LLCC block has several banks each with a different base address and holes in between. So it is not a correct approach to cover these banks with a single offset/size. Instead, the individual bank's base address needs to be specified in devicetree with the exact size. Reported-by: Parikshit Pareek Tested-by: Steev Klimaszewski # Thinkpad X13s Tested-by: Andrew Halaney # sa8540p-ride Signed-off-by: Manivannan Sadhasivam --- arch/arm64/boot/dts/qcom/sc8280xp.dtsi | 10 ++++++++-- 1 file changed, 8 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi b/arch/arm64/boot/dts/q= com/sc8280xp.dtsi index 0d02599d8867..f5262ac64a36 100644 --- a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi +++ b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi @@ -2983,8 +2983,14 @@ opp-6 { =20 system-cache-controller@9200000 { compatible =3D "qcom,sc8280xp-llcc"; - reg =3D <0 0x09200000 0 0x58000>, <0 0x09600000 0 0x58000>; - reg-names =3D "llcc_base", "llcc_broadcast_base"; + reg =3D <0 0x09200000 0 0x58000>, <0 0x09280000 0 0x58000>, + <0 0x09300000 0 0x58000>, <0 0x09380000 0 0x58000>, + <0 0x09400000 0 0x58000>, <0 0x09480000 0 0x58000>, + <0 0x09500000 0 0x58000>, <0 0x09580000 0 0x58000>, + <0 0x09600000 0 0x58000>; + reg-names =3D "llcc0_base", "llcc1_base", "llcc2_base", + "llcc3_base", "llcc4_base", "llcc5_base", + "llcc6_base", "llcc7_base", "llcc_broadcast_base"; interrupts =3D ; }; =20 --=20 2.25.1 From nobody Sun Sep 14 20:25:45 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6F183C7618B for ; Tue, 14 Mar 2023 08:06:21 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231149AbjCNIGU (ORCPT ); Tue, 14 Mar 2023 04:06:20 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:39368 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230496AbjCNIFr (ORCPT ); Tue, 14 Mar 2023 04:05:47 -0400 Received: from mail-pl1-x636.google.com (mail-pl1-x636.google.com [IPv6:2607:f8b0:4864:20::636]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 32FC669057 for ; Tue, 14 Mar 2023 01:05:35 -0700 (PDT) Received: by mail-pl1-x636.google.com with SMTP id h8so15692087plf.10 for ; Tue, 14 Mar 2023 01:05:35 -0700 (PDT) DKIM-Signature: v=1; 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Tue, 14 Mar 2023 01:05:34 -0700 (PDT) Received: from localhost.localdomain ([117.217.177.49]) by smtp.gmail.com with ESMTPSA id l8-20020a170902f68800b001994a0f3380sm1078022plg.265.2023.03.14.01.05.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 14 Mar 2023 01:05:34 -0700 (PDT) From: Manivannan Sadhasivam To: andersson@kernel.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, bp@alien8.de, tony.luck@intel.com Cc: konrad.dybcio@linaro.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, james.morse@arm.com, mchehab@kernel.org, rric@kernel.org, linux-edac@vger.kernel.org, quic_ppareek@quicinc.com, luca.weiss@fairphone.com, ahalaney@redhat.com, steev@kali.org, Manivannan Sadhasivam Subject: [PATCH v8 07/14] arm64: dts: qcom: sm8150: Fix the base addresses of LLCC banks Date: Tue, 14 Mar 2023 13:34:36 +0530 Message-Id: <20230314080443.64635-8-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230314080443.64635-1-manivannan.sadhasivam@linaro.org> References: <20230314080443.64635-1-manivannan.sadhasivam@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" The LLCC block has several banks each with a different base address and holes in between. So it is not a correct approach to cover these banks with a single offset/size. Instead, the individual bank's base address needs to be specified in devicetree with the exact size. Reported-by: Parikshit Pareek Signed-off-by: Manivannan Sadhasivam --- arch/arm64/boot/dts/qcom/sm8150.dtsi | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm8150.dtsi b/arch/arm64/boot/dts/qco= m/sm8150.dtsi index fd20096cfc6e..e316a4e4b5aa 100644 --- a/arch/arm64/boot/dts/qcom/sm8150.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8150.dtsi @@ -1772,8 +1772,11 @@ mmss_noc: interconnect@1740000 { =20 system-cache-controller@9200000 { compatible =3D "qcom,sm8150-llcc"; - reg =3D <0 0x09200000 0 0x200000>, <0 0x09600000 0 0x50000>; - reg-names =3D "llcc_base", "llcc_broadcast_base"; + reg =3D <0 0x09200000 0 0x50000>, <0 0x09280000 0 0x50000>, + <0 0x09300000 0 0x50000>, <0 0x09380000 0 0x50000>, + <0 0x09600000 0 0x50000>; + reg-names =3D "llcc0_base", "llcc1_base", "llcc2_base", + "llcc3_base", "llcc_broadcast_base"; interrupts =3D ; }; =20 --=20 2.25.1 From nobody Sun Sep 14 20:25:45 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9112DC6FD1C for ; Tue, 14 Mar 2023 08:06:23 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230427AbjCNIGW (ORCPT ); Tue, 14 Mar 2023 04:06:22 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:38876 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230505AbjCNIFs (ORCPT ); Tue, 14 Mar 2023 04:05:48 -0400 Received: from mail-pl1-x635.google.com (mail-pl1-x635.google.com [IPv6:2607:f8b0:4864:20::635]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id E247E72B1C for ; Tue, 14 Mar 2023 01:05:40 -0700 (PDT) Received: by mail-pl1-x635.google.com with SMTP id p20so15678492plw.13 for ; Tue, 14 Mar 2023 01:05:40 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1678781140; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=KbEuZ8x9epY4wczXQcJX335FU4iMuAmx2Igvv4w4MY4=; b=Blim+bsjx7tnv55ZAmyMK4xpeetRd1ob3PM+2hfLojx4GQETr1DfWSUnWWUKg6fUWB aV+mvGSKBiDPcJfzfudmySE5WvreMfMr82z5e83ZVzgXWikdTAKKJW+cb7M5UqPpNVTa Vv3zZYi3w9waz8r4TUZeklnpybTq8ynW6Hh4+KfKYnz+a26sKLrTAVRb0CIXEq7ekf9D ABuCuqgprYHWWBMfU+ru4yysX7E9KHCQFAyXKnQLl6DZaqBCcNY7XJkzOvCtUxBycs9J 2/t8NgTkaxzlCCvGG1gJ/xxL6R5UOxA/fZ3FwfRNLnATShINDVLM2B/DEXeFU6k7pU+5 +sYA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1678781140; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=KbEuZ8x9epY4wczXQcJX335FU4iMuAmx2Igvv4w4MY4=; b=YNATsElpY+OnpTRlnlvn4UTcZDlz1rjw8nC6G9ZZkJ0SspHhS8PI5Mo4SR7QR8l0sI pgC844vg2JPnACjDEfTcw+McvgUvXakQsn7KJyyal/fV0KQCFg4UOsfkZvhsWfVD+m7p V1jeh8j6Wyb0c1aXRR+oqqwUJTahH7vRWZO40cRVFvBS6AiuaDjLv6yNn3SAjZLU/iM7 wwgsLN4PdeYckt6FseYGejSisxZHCc8Oxw4EqZVYF+3Jv5tpA9NmfVv7xVjNziwJt3Le gUfexsNkitzbxi8v0vX32UUs9SK+0M270xl1iSP6aOTAvuh0fhDwPpNKUXUQ+tWMTdXx DwAw== X-Gm-Message-State: AO0yUKXN/z5YS/w5x1R1CILweNPJfButizbBB/yDKZWyn+hbAUTzoAKx dVjaXPFVnPzi0YefHflkr4No X-Google-Smtp-Source: AK7set/DOXIH1oI5YDQIcuXZ+wY4Pk/bm/WyjYGwuD9JQbSpO3V6BW9gePdkEHh82bqspSSNBbcBQA== X-Received: by 2002:a17:90a:19:b0:23a:ad68:25a7 with SMTP id 25-20020a17090a001900b0023aad6825a7mr29838033pja.2.1678781140382; Tue, 14 Mar 2023 01:05:40 -0700 (PDT) Received: from localhost.localdomain ([117.217.177.49]) by smtp.gmail.com with ESMTPSA id l8-20020a170902f68800b001994a0f3380sm1078022plg.265.2023.03.14.01.05.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 14 Mar 2023 01:05:39 -0700 (PDT) From: Manivannan Sadhasivam To: andersson@kernel.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, bp@alien8.de, tony.luck@intel.com Cc: konrad.dybcio@linaro.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, james.morse@arm.com, mchehab@kernel.org, rric@kernel.org, linux-edac@vger.kernel.org, quic_ppareek@quicinc.com, luca.weiss@fairphone.com, ahalaney@redhat.com, steev@kali.org, Manivannan Sadhasivam Subject: [PATCH v8 08/14] arm64: dts: qcom: sm8250: Fix the base addresses of LLCC banks Date: Tue, 14 Mar 2023 13:34:37 +0530 Message-Id: <20230314080443.64635-9-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230314080443.64635-1-manivannan.sadhasivam@linaro.org> References: <20230314080443.64635-1-manivannan.sadhasivam@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" The LLCC block has several banks each with a different base address and holes in between. So it is not a correct approach to cover these banks with a single offset/size. Instead, the individual bank's base address needs to be specified in devicetree with the exact size. Reported-by: Parikshit Pareek Signed-off-by: Manivannan Sadhasivam --- arch/arm64/boot/dts/qcom/sm8250.dtsi | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm8250.dtsi b/arch/arm64/boot/dts/qco= m/sm8250.dtsi index 2f0e460acccd..a13cf98b1ac3 100644 --- a/arch/arm64/boot/dts/qcom/sm8250.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8250.dtsi @@ -3559,8 +3559,11 @@ usb_1_dwc3: usb@a600000 { =20 system-cache-controller@9200000 { compatible =3D "qcom,sm8250-llcc"; - reg =3D <0 0x09200000 0 0x1d0000>, <0 0x09600000 0 0x50000>; - reg-names =3D "llcc_base", "llcc_broadcast_base"; + reg =3D <0 0x09200000 0 0x50000>, <0 0x09280000 0 0x50000>, + <0 0x09300000 0 0x50000>, <0 0x09380000 0 0x50000>, + <0 0x09600000 0 0x50000>; + reg-names =3D "llcc0_base", "llcc1_base", "llcc2_base", + "llcc3_base", "llcc_broadcast_base"; }; =20 usb_2: usb@a8f8800 { --=20 2.25.1 From nobody Sun Sep 14 20:25:45 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 30372C6FD1C for ; Tue, 14 Mar 2023 08:06:26 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231164AbjCNIGZ (ORCPT ); Tue, 14 Mar 2023 04:06:25 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:38524 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230443AbjCNIFw (ORCPT ); Tue, 14 Mar 2023 04:05:52 -0400 Received: from mail-pl1-x62b.google.com (mail-pl1-x62b.google.com [IPv6:2607:f8b0:4864:20::62b]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 3C70A87DB2 for ; Tue, 14 Mar 2023 01:05:46 -0700 (PDT) Received: by mail-pl1-x62b.google.com with SMTP id k2so7829942pll.8 for ; Tue, 14 Mar 2023 01:05:46 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1678781146; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=WM/W3mGHWee04PiGhWaePDSEFLq+5Xz9JBoWs5RSs+4=; b=RDGwems7PyJZDZ29pYgfkme1i95dPUInFnXwzopbD6Em5qAza9fIY+En5MtKlgSpqG YEPMHWlaC2/G41YoL0usMUjvOqq6fkjWNI2RQgNUSoJ8ZfjSU3PQicRblMHRdBichWpX F3V6cYIEFrkj1FxBuPNHqp7ry3wbusvjYzSCqEJZbieoKqxWeyfuVvMAI0tNXSlv+lmJ EahXwYc/ksWZIJKinruI87wppf+TUFSw2IyyVpTBJBR1ED8VZh8ycFvca2pz01phKde0 xD8pFjaG4RgYhg3aupoOE+6jC1Dq4epW1Hyjzh1dH5/bF5+H5p4UWzBpA4HgQPTBrXiz 3+Vw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1678781146; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=WM/W3mGHWee04PiGhWaePDSEFLq+5Xz9JBoWs5RSs+4=; b=CTyPSGm+aQipB3q4I2pS0FyjdU7PgNsn4PnyQPu/tPjT8aP7/iwIFxuYRoRS9P+H3m d/mVKxBaD9nNHhxxw6FoyPC3WNjr4P8MAmjYZuHB4woXSgx9GhO6XJLpwgAcXWWv6apN l/7AuXa1iU4iMYcxeLwxK+9XlnxtGpaskGcZXapBcR8Ycz5PTk5maIAi1FHaW+CafpKN tFYz3Ig3dkIl2CJiIae1ky8zWCsT/Rz6I+kxe9ejHyOSFUIyi5lldoLBhWzrjfL8VSlA 6xTgIKQGeer6RAC/gXnP+zyXGdijrka7ST1diBdzlVi35syNZmVlS7UQzchPDX+zzgT6 QKzw== X-Gm-Message-State: AO0yUKX3cMtgaYVSzksO/zUEIrdJr6m8+uipDYHxp5f8eGfmJPdKcEo7 cQ6AjR+YTQioq184hCQCpJ3T X-Google-Smtp-Source: AK7set/EBRWn+iFCvwCLybzCKfHdXTnJNY/XzNdvpeEfeBdb0/V4NEbBLT9p7swb5llI6OB4biA5cg== X-Received: by 2002:a17:902:d502:b0:19d:16e4:ac0f with SMTP id b2-20020a170902d50200b0019d16e4ac0fmr46377415plg.5.1678781145728; Tue, 14 Mar 2023 01:05:45 -0700 (PDT) Received: from localhost.localdomain ([117.217.177.49]) by smtp.gmail.com with ESMTPSA id l8-20020a170902f68800b001994a0f3380sm1078022plg.265.2023.03.14.01.05.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 14 Mar 2023 01:05:44 -0700 (PDT) From: Manivannan Sadhasivam To: andersson@kernel.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, bp@alien8.de, tony.luck@intel.com Cc: konrad.dybcio@linaro.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, james.morse@arm.com, mchehab@kernel.org, rric@kernel.org, linux-edac@vger.kernel.org, quic_ppareek@quicinc.com, luca.weiss@fairphone.com, ahalaney@redhat.com, steev@kali.org, Manivannan Sadhasivam Subject: [PATCH v8 09/14] arm64: dts: qcom: sm8350: Fix the base addresses of LLCC banks Date: Tue, 14 Mar 2023 13:34:38 +0530 Message-Id: <20230314080443.64635-10-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230314080443.64635-1-manivannan.sadhasivam@linaro.org> References: <20230314080443.64635-1-manivannan.sadhasivam@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" The LLCC block has several banks each with a different base address and holes in between. So it is not a correct approach to cover these banks with a single offset/size. Instead, the individual bank's base address needs to be specified in devicetree with the exact size. Reported-by: Parikshit Pareek Signed-off-by: Manivannan Sadhasivam --- arch/arm64/boot/dts/qcom/sm8350.dtsi | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm8350.dtsi b/arch/arm64/boot/dts/qco= m/sm8350.dtsi index 1c97e28da6ad..3fefd8cbba6d 100644 --- a/arch/arm64/boot/dts/qcom/sm8350.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8350.dtsi @@ -2204,8 +2204,11 @@ gem_noc: interconnect@9100000 { =20 system-cache-controller@9200000 { compatible =3D "qcom,sm8350-llcc"; - reg =3D <0 0x09200000 0 0x1d0000>, <0 0x09600000 0 0x50000>; - reg-names =3D "llcc_base", "llcc_broadcast_base"; + reg =3D <0 0x09200000 0 0x58000>, <0 0x09280000 0 0x58000>, + <0 0x09300000 0 0x58000>, <0 0x09380000 0 0x58000>, + <0 0x09600000 0 0x58000>; + reg-names =3D "llcc0_base", "llcc1_base", "llcc2_base", + "llcc3_base", "llcc_broadcast_base"; }; =20 compute_noc: interconnect@a0c0000 { --=20 2.25.1 From nobody Sun Sep 14 20:25:45 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 62ECAC74A44 for ; Tue, 14 Mar 2023 08:06:36 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231185AbjCNIGf (ORCPT ); Tue, 14 Mar 2023 04:06:35 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:39082 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230406AbjCNIGB (ORCPT ); Tue, 14 Mar 2023 04:06:01 -0400 Received: from mail-pl1-x636.google.com (mail-pl1-x636.google.com [IPv6:2607:f8b0:4864:20::636]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id F1006848CC for ; Tue, 14 Mar 2023 01:05:51 -0700 (PDT) Received: by mail-pl1-x636.google.com with SMTP id ix20so9199438plb.3 for ; Tue, 14 Mar 2023 01:05:51 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1678781151; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=yqwK6TcGjAz04KGXLoszY4ospGxs4tGDAzQeGyANDbE=; b=nP/Tw2wixTXRLo4uciqirv8e2e05IGj3I3RKHIWEL/gCrS0deSj14T78ipg5nURkyt hZzdCjeuDl1uU7oXq3zjmsgUa70kRudHCDliEUnEFfwtMcuH3ScQw/ptFAghBUU5ElfP LqkHr6cIfMR1H6U3tKB0rJBY7f6+k+HkEKzZ53tD+Mw2fe7QUpqG7utRX80Byf7f1Yfd 4XaQUIwcFOXj8sEQ9E1O3TwuhfktGqaz2hOrvav1zxZdAK4eLDiAQBnOrK2QHUPxUbJ7 0qLNcBhn9NbhGBIUCPyWtDzR7xaBj71gdjEzxOTBUDXtIqEO3cI+5kHJYMEmxv/+oc3/ 9RwQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1678781151; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=yqwK6TcGjAz04KGXLoszY4ospGxs4tGDAzQeGyANDbE=; b=mEDoMYYWCBJc3MzztmyeyD0U0RO3Rnunn0eVRaveKxNlfC8DUNGcAfToJo4mXQBBg7 NzQ6EFm5Z4hQ2zzWhp/onuvdMmR5mJzfKyTlMHURw2HbkynFmFpgYMYmIOSGClZq/q8x KFVmUZuHt+/5X/IH8eppfv/Q+bkmqXyRF2vJQQDEhz2G2+/yPx1/lVI8xu97ETt8CzWF ImEKm41HSdGnKpLND6M/hq6Mwn9cXSv2lk86RUenjI0uUFvA35iWMk5TF/BWnTNqK+pH dSPHYdV+X+3avqxMaX8TERzE9brWEVKc6cAvv3ZGpcViIZwRBnalsR1hAkgN2JXNRN0+ S6dg== X-Gm-Message-State: AO0yUKWDUkx0JLZnyvfkh385Df4v6b9gu0OuQmX5IIlDl+UgpLPAgBqm +qw9yJjWWgF4tr9Ydb2OAPpF X-Google-Smtp-Source: AK7set+3jxjTVufu6gLNWUhkkyccG/7NWuiW2l/zYR0R7qUAePKN3BB2I3QBYStZpfSJloobYYi1Jw== X-Received: by 2002:a17:902:c412:b0:19c:be03:d18b with SMTP id k18-20020a170902c41200b0019cbe03d18bmr51755970plk.22.1678781151536; Tue, 14 Mar 2023 01:05:51 -0700 (PDT) Received: from localhost.localdomain ([117.217.177.49]) by smtp.gmail.com with ESMTPSA id l8-20020a170902f68800b001994a0f3380sm1078022plg.265.2023.03.14.01.05.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 14 Mar 2023 01:05:50 -0700 (PDT) From: Manivannan Sadhasivam To: andersson@kernel.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, bp@alien8.de, tony.luck@intel.com Cc: konrad.dybcio@linaro.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, james.morse@arm.com, mchehab@kernel.org, rric@kernel.org, linux-edac@vger.kernel.org, quic_ppareek@quicinc.com, luca.weiss@fairphone.com, ahalaney@redhat.com, steev@kali.org, Manivannan Sadhasivam Subject: [PATCH v8 10/14] arm64: dts: qcom: sm8450: Fix the base addresses of LLCC banks Date: Tue, 14 Mar 2023 13:34:39 +0530 Message-Id: <20230314080443.64635-11-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230314080443.64635-1-manivannan.sadhasivam@linaro.org> References: <20230314080443.64635-1-manivannan.sadhasivam@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" The LLCC block has several banks each with a different base address and holes in between. So it is not a correct approach to cover these banks with a single offset/size. Instead, the individual bank's base address needs to be specified in devicetree with the exact size. Reported-by: Parikshit Pareek Signed-off-by: Manivannan Sadhasivam --- arch/arm64/boot/dts/qcom/sm8450.dtsi | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm8450.dtsi b/arch/arm64/boot/dts/qco= m/sm8450.dtsi index 1a744a33bcf4..636dc6823d4c 100644 --- a/arch/arm64/boot/dts/qcom/sm8450.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8450.dtsi @@ -3981,8 +3981,11 @@ gem_noc: interconnect@19100000 { =20 system-cache-controller@19200000 { compatible =3D "qcom,sm8450-llcc"; - reg =3D <0 0x19200000 0 0x580000>, <0 0x19a00000 0 0x80000>; - reg-names =3D "llcc_base", "llcc_broadcast_base"; + reg =3D <0 0x19200000 0 0x80000>, <0 0x19600000 0 0x80000>, + <0 0x19300000 0 0x80000>, <0 0x19700000 0 0x80000>, + <0 0x19a00000 0 0x80000>; + reg-names =3D "llcc0_base", "llcc1_base", "llcc2_base", + "llcc3_base", "llcc_broadcast_base"; interrupts =3D ; }; =20 --=20 2.25.1 From nobody Sun Sep 14 20:25:45 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1C14BC74A44 for ; Tue, 14 Mar 2023 08:07:02 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230503AbjCNIHA (ORCPT ); Tue, 14 Mar 2023 04:07:00 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:38884 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230423AbjCNIGT (ORCPT ); Tue, 14 Mar 2023 04:06:19 -0400 Received: from mail-pj1-x102e.google.com (mail-pj1-x102e.google.com [IPv6:2607:f8b0:4864:20::102e]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id D931397FF5 for ; Tue, 14 Mar 2023 01:05:57 -0700 (PDT) Received: by mail-pj1-x102e.google.com with SMTP id l9-20020a17090a3f0900b0023d32684e7fso625884pjc.1 for ; Tue, 14 Mar 2023 01:05:57 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1678781157; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=sggevdgcbKkipnWP4TBoy7JyP1Clj0YxXKdQjrw2BUc=; b=n5ShiHu8TkifJ0rpTG3JyQ6+qX/9SlTcOKdiiRJo/l6aDmDiBrYXy1HcKwqr7467jj oEXtF/BwJ27I+1JMUNMVG66bwuQQwdnQx5qfFmOW/QBIUk26+ohXYo2xo96qW/heofsd El6IBaTR2yEu+ge99Ysh36mUSo7WAKF4wLgzThC9+uKTGaCjkshefW7pC28U8qj32lr0 cf6RoTkIRqYduRW7JGM9Bkr5GTUZ7D2CMmHsylcX9uCKA9Cg5BpFjZiAtLejSDqr/2m0 u4MOGQHHdsx9uzIIeSnV82eN0d9vpvKy61lG8/2X+Jnw7ZmEYW5PI34Tc6soqaT4fZmI PnEg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1678781157; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=sggevdgcbKkipnWP4TBoy7JyP1Clj0YxXKdQjrw2BUc=; b=rd1nAhp045Bk/Wsuj2lvGKodilyrWS4Urqq9xMrbuHn4foF21a/f4tvcbIJbdfv+gs olw0AvKG+zkwuOvAO2/PqDb4zznMr5Zv+YrqDYrFf3+7FKUThJ3RvNh4DugS+eq/RzUA weGh/p3Tgjf+ZNKohWljL53UmAAHlIl90/W5G84tGhjjbX2MGagDXPglT707HyfApb3l Ypv/5zfIzlmyuFZcWw8FElIGuIalHL3dksHwVCDrNAr7I9UzhYsNObSU12h7okL/jKvp 4BxhnRotxzZyyn4zkRiH6hTnDOFRiLb8E9TOo6wmUJHoJfG7zkLJ7OFcV3bwoGNr3dmb iAMQ== X-Gm-Message-State: AO0yUKVQgaIdTPiQN4UGU6w1yN6vUNlAiM7NLqPQYpDiYCWT/GpQYsbG 3NpRTpyLZbpSOIe4I7JrLllo X-Google-Smtp-Source: AK7set91E81Z5ue0s+hViGYIWmltBDyOFXxkdskzB+J3ofRfV5NNi52ZEZ0p16JswB08mvE13xUctQ== X-Received: by 2002:a17:903:24f:b0:19c:c8c8:b545 with SMTP id j15-20020a170903024f00b0019cc8c8b545mr40241222plh.50.1678781157396; Tue, 14 Mar 2023 01:05:57 -0700 (PDT) Received: from localhost.localdomain ([117.217.177.49]) by smtp.gmail.com with ESMTPSA id l8-20020a170902f68800b001994a0f3380sm1078022plg.265.2023.03.14.01.05.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 14 Mar 2023 01:05:56 -0700 (PDT) From: Manivannan Sadhasivam To: andersson@kernel.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, bp@alien8.de, tony.luck@intel.com Cc: konrad.dybcio@linaro.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, james.morse@arm.com, mchehab@kernel.org, rric@kernel.org, linux-edac@vger.kernel.org, quic_ppareek@quicinc.com, luca.weiss@fairphone.com, ahalaney@redhat.com, steev@kali.org, Manivannan Sadhasivam Subject: [PATCH v8 11/14] arm64: dts: qcom: sm6350: Fix the base addresses of LLCC banks Date: Tue, 14 Mar 2023 13:34:40 +0530 Message-Id: <20230314080443.64635-12-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230314080443.64635-1-manivannan.sadhasivam@linaro.org> References: <20230314080443.64635-1-manivannan.sadhasivam@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" The LLCC block has several banks each with a different base address and holes in between. So it is not a correct approach to cover these banks with a single offset/size. Instead, the individual bank's base address needs to be specified in devicetree with the exact size. On SM6350, there is only one LLCC bank available. So let's just pass that as "llcc0_base". Reported-by: Parikshit Pareek Tested-by: Luca Weiss Signed-off-by: Manivannan Sadhasivam --- arch/arm64/boot/dts/qcom/sm6350.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sm6350.dtsi b/arch/arm64/boot/dts/qco= m/sm6350.dtsi index 1e1d366c92c1..63e55579e9c4 100644 --- a/arch/arm64/boot/dts/qcom/sm6350.dtsi +++ b/arch/arm64/boot/dts/qcom/sm6350.dtsi @@ -1348,7 +1348,7 @@ dc_noc: interconnect@9160000 { system-cache-controller@9200000 { compatible =3D "qcom,sm6350-llcc"; reg =3D <0 0x09200000 0 0x50000>, <0 0x09600000 0 0x50000>; - reg-names =3D "llcc_base", "llcc_broadcast_base"; + reg-names =3D "llcc0_base", "llcc_broadcast_base"; }; =20 gem_noc: interconnect@9680000 { --=20 2.25.1 From nobody Sun Sep 14 20:25:45 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9956CC7618B for ; Tue, 14 Mar 2023 08:07:11 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231179AbjCNIHK (ORCPT ); Tue, 14 Mar 2023 04:07:10 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:38654 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229667AbjCNIGa (ORCPT ); Tue, 14 Mar 2023 04:06:30 -0400 Received: from mail-pj1-x102e.google.com (mail-pj1-x102e.google.com [IPv6:2607:f8b0:4864:20::102e]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 1F11A78C8D for ; Tue, 14 Mar 2023 01:06:03 -0700 (PDT) Received: by mail-pj1-x102e.google.com with SMTP id fy10-20020a17090b020a00b0023b4bcf0727so6838644pjb.0 for ; Tue, 14 Mar 2023 01:06:03 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1678781162; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=nUusDRy45tnE3HpdbouewJfbkC176V5vp9gS5W4zqOI=; b=G7ErtDNx9DqmYbhi5XSdo2JXgMqH1l30/Yo4ALoFCbLxI4NjJj0p2JlB7adkQ+xJDy Yi73c7srD8V7F5Fb4k3f/GM8e2ewU11ronsqm8ebNuIEJ6MTJgHNvV/zG6q5g44U1QsL P/UltiMdSMly3dPOBgD2Vo6pDu43nCU/+qZqLXaHASVScfP89D+JEl288i1EXs+QeYeV XfVW7Y2ImUxGBZgJjc4tV2GDh4I7eWHcOJmEoXk79zDykPCtQHrmPna6xzqT8CI+EzhM mPymaXdGV31N9tXsWjEzkXqZXzkP6X/u5QbG0SgA5xBG2GtYpCmEMW5keQTZQr5R0fOf ewlg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1678781162; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=nUusDRy45tnE3HpdbouewJfbkC176V5vp9gS5W4zqOI=; b=VHzIiphBtQUOIM1yKwhjlhHhsHe6c/fxUruV+z42hhTuPtweat7DCasR+gNsrlO++T igRofgQT8DdCrhB1SGEzhjFwxJ4ffKN3v7nJypKeYU+z8PgoS04LptyeLivLbhItPnj6 dwN6Qlmid7OVPNyk3myPtMR9qrKze8nA2ipPf3bYn+bq1P6Z9LGI31T2yE/C5Gouomtb 3gu4aFCKQKrkJVCqlqp83cQunC6+wqM4HNV9Ut+j4wTJ02xmiubelIKh7mWuDvyZo6GC +J1Y4gp1cUYXTRVvmyNcaVsV2jG5e04LIEHZEPM8eLn/ZvOGH1vxMIf3eSnG1QvwiwMs zezw== X-Gm-Message-State: AO0yUKVrBRC2dajOjkwBM4e6bdO7BDxxSFMPw6lAS/4ltye1RbuaNhWJ pSUkixlji5Fr+G/JBPCrQiov X-Google-Smtp-Source: AK7set+DvJvERhRXAen9Wga1FWOth9NupZNrKge9u37DCFL4ARDuXWsjiRZkxh2qcCgZIihrw3uqrA== X-Received: by 2002:a17:90a:fc87:b0:23d:a2a:3ae4 with SMTP id ci7-20020a17090afc8700b0023d0a2a3ae4mr5946081pjb.44.1678781162561; Tue, 14 Mar 2023 01:06:02 -0700 (PDT) Received: from localhost.localdomain ([117.217.177.49]) by smtp.gmail.com with ESMTPSA id l8-20020a170902f68800b001994a0f3380sm1078022plg.265.2023.03.14.01.05.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 14 Mar 2023 01:06:01 -0700 (PDT) From: Manivannan Sadhasivam To: andersson@kernel.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, bp@alien8.de, tony.luck@intel.com Cc: konrad.dybcio@linaro.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, james.morse@arm.com, mchehab@kernel.org, rric@kernel.org, linux-edac@vger.kernel.org, quic_ppareek@quicinc.com, luca.weiss@fairphone.com, ahalaney@redhat.com, steev@kali.org, Manivannan Sadhasivam Subject: [PATCH v8 12/14] qcom: llcc/edac: Fix the base address used for accessing LLCC banks Date: Tue, 14 Mar 2023 13:34:41 +0530 Message-Id: <20230314080443.64635-13-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230314080443.64635-1-manivannan.sadhasivam@linaro.org> References: <20230314080443.64635-1-manivannan.sadhasivam@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" The Qualcomm LLCC/EDAC drivers were using a fixed register stride for accessing the (Control and Status Registers) CSRs of each LLCC bank. This stride only works for some SoCs like SDM845 for which driver support was initially added. But the later SoCs use different register stride that vary between the banks with holes in-between. So it is not possible to use a single register stride for accessing the CSRs of each bank. By doing so could result in a crash. For fixing this issue, let's obtain the base address of each LLCC bank from devicetree and get rid of the fixed stride. This also means, there is no need to rely on reg-names property and the base addresses can be obtained using the index. First index is LLCC bank 0 and last index is LLCC broadcast. If the SoC supports more than one bank, then those need to be defined in devicetree for index from 1..N-1. Reported-by: Parikshit Pareek Tested-by: Luca Weiss Tested-by: Steev Klimaszewski # Thinkpad X13s Tested-by: Andrew Halaney # sa8540p-ride Reviewed-by: Borislav Petkov (AMD) Signed-off-by: Manivannan Sadhasivam --- drivers/edac/qcom_edac.c | 14 +++--- drivers/soc/qcom/llcc-qcom.c | 72 +++++++++++++++++------------- include/linux/soc/qcom/llcc-qcom.h | 6 +-- 3 files changed, 48 insertions(+), 44 deletions(-) diff --git a/drivers/edac/qcom_edac.c b/drivers/edac/qcom_edac.c index 3256254c3722..1d3cc1930a74 100644 --- a/drivers/edac/qcom_edac.c +++ b/drivers/edac/qcom_edac.c @@ -213,7 +213,7 @@ dump_syn_reg_values(struct llcc_drv_data *drv, u32 bank= , int err_type) =20 for (i =3D 0; i < reg_data.reg_cnt; i++) { synd_reg =3D reg_data.synd_reg + (i * 4); - ret =3D regmap_read(drv->regmap, drv->offsets[bank] + synd_reg, + ret =3D regmap_read(drv->regmaps[bank], synd_reg, &synd_val); if (ret) goto clear; @@ -222,8 +222,7 @@ dump_syn_reg_values(struct llcc_drv_data *drv, u32 bank= , int err_type) reg_data.name, i, synd_val); } =20 - ret =3D regmap_read(drv->regmap, - drv->offsets[bank] + reg_data.count_status_reg, + ret =3D regmap_read(drv->regmaps[bank], reg_data.count_status_reg, &err_cnt); if (ret) goto clear; @@ -233,8 +232,7 @@ dump_syn_reg_values(struct llcc_drv_data *drv, u32 bank= , int err_type) edac_printk(KERN_CRIT, EDAC_LLCC, "%s: Error count: 0x%4x\n", reg_data.name, err_cnt); =20 - ret =3D regmap_read(drv->regmap, - drv->offsets[bank] + reg_data.ways_status_reg, + ret =3D regmap_read(drv->regmaps[bank], reg_data.ways_status_reg, &err_ways); if (ret) goto clear; @@ -296,8 +294,7 @@ llcc_ecc_irq_handler(int irq, void *edev_ctl) =20 /* Iterate over the banks and look for Tag RAM or Data RAM errors */ for (i =3D 0; i < drv->num_banks; i++) { - ret =3D regmap_read(drv->regmap, - drv->offsets[i] + DRP_INTERRUPT_STATUS, + ret =3D regmap_read(drv->regmaps[i], DRP_INTERRUPT_STATUS, &drp_error); =20 if (!ret && (drp_error & SB_ECC_ERROR)) { @@ -312,8 +309,7 @@ llcc_ecc_irq_handler(int irq, void *edev_ctl) if (!ret) irq_rc =3D IRQ_HANDLED; =20 - ret =3D regmap_read(drv->regmap, - drv->offsets[i] + TRP_INTERRUPT_0_STATUS, + ret =3D regmap_read(drv->regmaps[i], TRP_INTERRUPT_0_STATUS, &trp_error); =20 if (!ret && (trp_error & SB_ECC_ERROR)) { diff --git a/drivers/soc/qcom/llcc-qcom.c b/drivers/soc/qcom/llcc-qcom.c index 23ce2f78c4ed..72f3f2a9aaa0 100644 --- a/drivers/soc/qcom/llcc-qcom.c +++ b/drivers/soc/qcom/llcc-qcom.c @@ -62,8 +62,6 @@ #define LLCC_TRP_WRSC_CACHEABLE_EN 0x21f2c #define LLCC_TRP_ALGO_CFG8 0x21f30 =20 -#define BANK_OFFSET_STRIDE 0x80000 - #define LLCC_VERSION_2_0_0_0 0x02000000 #define LLCC_VERSION_2_1_0_0 0x02010000 #define LLCC_VERSION_4_1_0_0 0x04010000 @@ -898,8 +896,8 @@ static int qcom_llcc_remove(struct platform_device *pde= v) return 0; } =20 -static struct regmap *qcom_llcc_init_mmio(struct platform_device *pdev, - const char *name) +static struct regmap *qcom_llcc_init_mmio(struct platform_device *pdev, u8= index, + const char *name) { void __iomem *base; struct regmap_config llcc_regmap_config =3D { @@ -909,7 +907,7 @@ static struct regmap *qcom_llcc_init_mmio(struct platfo= rm_device *pdev, .fast_io =3D true, }; =20 - base =3D devm_platform_ioremap_resource_byname(pdev, name); + base =3D devm_platform_ioremap_resource(pdev, index); if (IS_ERR(base)) return ERR_CAST(base); =20 @@ -927,6 +925,7 @@ static int qcom_llcc_probe(struct platform_device *pdev) const struct llcc_slice_config *llcc_cfg; u32 sz; u32 version; + struct regmap *regmap; =20 drv_data =3D devm_kzalloc(dev, sizeof(*drv_data), GFP_KERNEL); if (!drv_data) { @@ -934,21 +933,51 @@ static int qcom_llcc_probe(struct platform_device *pd= ev) goto err; } =20 - drv_data->regmap =3D qcom_llcc_init_mmio(pdev, "llcc_base"); - if (IS_ERR(drv_data->regmap)) { - ret =3D PTR_ERR(drv_data->regmap); + /* Initialize the first LLCC bank regmap */ + regmap =3D qcom_llcc_init_mmio(pdev, 0, "llcc0_base"); + if (IS_ERR(regmap)) { + ret =3D PTR_ERR(regmap); goto err; } =20 - drv_data->bcast_regmap =3D - qcom_llcc_init_mmio(pdev, "llcc_broadcast_base"); + cfg =3D of_device_get_match_data(&pdev->dev); + + ret =3D regmap_read(regmap, cfg->reg_offset[LLCC_COMMON_STATUS0], &num_ba= nks); + if (ret) + goto err; + + num_banks &=3D LLCC_LB_CNT_MASK; + num_banks >>=3D LLCC_LB_CNT_SHIFT; + drv_data->num_banks =3D num_banks; + + drv_data->regmaps =3D devm_kcalloc(dev, num_banks, sizeof(*drv_data->regm= aps), GFP_KERNEL); + if (!drv_data->regmaps) { + ret =3D -ENOMEM; + goto err; + } + + drv_data->regmaps[0] =3D regmap; + + /* Initialize rest of LLCC bank regmaps */ + for (i =3D 1; i < num_banks; i++) { + char *base =3D kasprintf(GFP_KERNEL, "llcc%d_base", i); + + drv_data->regmaps[i] =3D qcom_llcc_init_mmio(pdev, i, base); + if (IS_ERR(drv_data->regmaps[i])) { + ret =3D PTR_ERR(drv_data->regmaps[i]); + kfree(base); + goto err; + } + + kfree(base); + } + + drv_data->bcast_regmap =3D qcom_llcc_init_mmio(pdev, i, "llcc_broadcast_b= ase"); if (IS_ERR(drv_data->bcast_regmap)) { ret =3D PTR_ERR(drv_data->bcast_regmap); goto err; } =20 - cfg =3D of_device_get_match_data(&pdev->dev); - /* Extract version of the IP */ ret =3D regmap_read(drv_data->bcast_regmap, cfg->reg_offset[LLCC_COMMON_H= W_INFO], &version); @@ -957,15 +986,6 @@ static int qcom_llcc_probe(struct platform_device *pde= v) =20 drv_data->version =3D version; =20 - ret =3D regmap_read(drv_data->regmap, cfg->reg_offset[LLCC_COMMON_STATUS0= ], - &num_banks); - if (ret) - goto err; - - num_banks &=3D LLCC_LB_CNT_MASK; - num_banks >>=3D LLCC_LB_CNT_SHIFT; - drv_data->num_banks =3D num_banks; - llcc_cfg =3D cfg->sct_data; sz =3D cfg->size; =20 @@ -973,16 +993,6 @@ static int qcom_llcc_probe(struct platform_device *pde= v) if (llcc_cfg[i].slice_id > drv_data->max_slices) drv_data->max_slices =3D llcc_cfg[i].slice_id; =20 - drv_data->offsets =3D devm_kcalloc(dev, num_banks, sizeof(u32), - GFP_KERNEL); - if (!drv_data->offsets) { - ret =3D -ENOMEM; - goto err; - } - - for (i =3D 0; i < num_banks; i++) - drv_data->offsets[i] =3D i * BANK_OFFSET_STRIDE; - drv_data->bitmap =3D devm_bitmap_zalloc(dev, drv_data->max_slices, GFP_KERNEL); if (!drv_data->bitmap) { diff --git a/include/linux/soc/qcom/llcc-qcom.h b/include/linux/soc/qcom/ll= cc-qcom.h index ad1fd718169d..423220e66026 100644 --- a/include/linux/soc/qcom/llcc-qcom.h +++ b/include/linux/soc/qcom/llcc-qcom.h @@ -120,7 +120,7 @@ struct llcc_edac_reg_offset { =20 /** * struct llcc_drv_data - Data associated with the llcc driver - * @regmap: regmap associated with the llcc device + * @regmaps: regmaps associated with the llcc device * @bcast_regmap: regmap associated with llcc broadcast offset * @cfg: pointer to the data structure for slice configuration * @edac_reg_offset: Offset of the LLCC EDAC registers @@ -129,12 +129,11 @@ struct llcc_edac_reg_offset { * @max_slices: max slices as read from device tree * @num_banks: Number of llcc banks * @bitmap: Bit map to track the active slice ids - * @offsets: Pointer to the bank offsets array * @ecc_irq: interrupt for llcc cache error detection and reporting * @version: Indicates the LLCC version */ struct llcc_drv_data { - struct regmap *regmap; + struct regmap **regmaps; struct regmap *bcast_regmap; const struct llcc_slice_config *cfg; const struct llcc_edac_reg_offset *edac_reg_offset; @@ -143,7 +142,6 @@ struct llcc_drv_data { u32 max_slices; u32 num_banks; unsigned long *bitmap; - u32 *offsets; int ecc_irq; u32 version; }; --=20 2.25.1 From nobody Sun Sep 14 20:25:45 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id EDDF3C6FD1F for ; Tue, 14 Mar 2023 08:07:30 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230398AbjCNIH3 (ORCPT ); Tue, 14 Mar 2023 04:07:29 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:39316 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230435AbjCNIGt (ORCPT ); Tue, 14 Mar 2023 04:06:49 -0400 Received: from mail-pj1-x1032.google.com (mail-pj1-x1032.google.com [IPv6:2607:f8b0:4864:20::1032]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 4386D984D1 for ; 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charset="utf-8" Not all Qcom platforms support IRQ mode for ECC handling. For those platforms, the current EDAC driver will not be probed due to missing ECC IRQ in devicetree. So add support for polling mode so that the EDAC driver can be used on all Qcom platforms supporting LLCC. The polling delay of 5000ms is chosen based on Qcom downstream/vendor driver. Reported-by: Luca Weiss Tested-by: Luca Weiss Tested-by: Steev Klimaszewski # Thinkpad X13s Tested-by: Andrew Halaney # sa8540p-ride Reviewed-by: Borislav Petkov (AMD) Signed-off-by: Manivannan Sadhasivam --- drivers/edac/qcom_edac.c | 50 +++++++++++++++++++++--------------- drivers/soc/qcom/llcc-qcom.c | 13 +++++----- 2 files changed, 35 insertions(+), 28 deletions(-) diff --git a/drivers/edac/qcom_edac.c b/drivers/edac/qcom_edac.c index 1d3cc1930a74..265e0fb39bc7 100644 --- a/drivers/edac/qcom_edac.c +++ b/drivers/edac/qcom_edac.c @@ -76,6 +76,8 @@ #define DRP0_INTERRUPT_ENABLE BIT(6) #define SB_DB_DRP_INTERRUPT_ENABLE 0x3 =20 +#define ECC_POLL_MSEC 5000 + enum { LLCC_DRAM_CE =3D 0, LLCC_DRAM_UE, @@ -283,8 +285,7 @@ dump_syn_reg(struct edac_device_ctl_info *edev_ctl, int= err_type, u32 bank) return ret; } =20 -static irqreturn_t -llcc_ecc_irq_handler(int irq, void *edev_ctl) +static irqreturn_t llcc_ecc_irq_handler(int irq, void *edev_ctl) { struct edac_device_ctl_info *edac_dev_ctl =3D edev_ctl; struct llcc_drv_data *drv =3D edac_dev_ctl->dev->platform_data; @@ -328,6 +329,11 @@ llcc_ecc_irq_handler(int irq, void *edev_ctl) return irq_rc; } =20 +static void llcc_ecc_check(struct edac_device_ctl_info *edev_ctl) +{ + llcc_ecc_irq_handler(0, edev_ctl); +} + static int qcom_llcc_edac_probe(struct platform_device *pdev) { struct llcc_drv_data *llcc_driv_data =3D pdev->dev.platform_data; @@ -355,29 +361,31 @@ static int qcom_llcc_edac_probe(struct platform_devic= e *pdev) edev_ctl->ctl_name =3D "llcc"; edev_ctl->panic_on_ue =3D LLCC_ERP_PANIC_ON_UE; =20 - rc =3D edac_device_add_device(edev_ctl); - if (rc) - goto out_mem; - - platform_set_drvdata(pdev, edev_ctl); - - /* Request for ecc irq */ + /* Check if LLCC driver has passed ECC IRQ */ ecc_irq =3D llcc_driv_data->ecc_irq; - if (ecc_irq < 0) { - rc =3D -ENODEV; - goto out_dev; - } - rc =3D devm_request_irq(dev, ecc_irq, llcc_ecc_irq_handler, + if (ecc_irq > 0) { + /* Use interrupt mode if IRQ is available */ + rc =3D devm_request_irq(dev, ecc_irq, llcc_ecc_irq_handler, IRQF_TRIGGER_HIGH, "llcc_ecc", edev_ctl); - if (rc) - goto out_dev; + if (!rc) { + edac_op_state =3D EDAC_OPSTATE_INT; + goto irq_done; + } + } =20 - return rc; + /* Fall back to polling mode otherwise */ + edev_ctl->poll_msec =3D ECC_POLL_MSEC; + edev_ctl->edac_check =3D llcc_ecc_check; + edac_op_state =3D EDAC_OPSTATE_POLL; =20 -out_dev: - edac_device_del_device(edev_ctl->dev); -out_mem: - edac_device_free_ctl_info(edev_ctl); +irq_done: + rc =3D edac_device_add_device(edev_ctl); + if (rc) { + edac_device_free_ctl_info(edev_ctl); + return rc; + } + + platform_set_drvdata(pdev, edev_ctl); =20 return rc; } diff --git a/drivers/soc/qcom/llcc-qcom.c b/drivers/soc/qcom/llcc-qcom.c index 72f3f2a9aaa0..7b7c5a38bac6 100644 --- a/drivers/soc/qcom/llcc-qcom.c +++ b/drivers/soc/qcom/llcc-qcom.c @@ -1011,13 +1011,12 @@ static int qcom_llcc_probe(struct platform_device *= pdev) goto err; =20 drv_data->ecc_irq =3D platform_get_irq_optional(pdev, 0); - if (drv_data->ecc_irq >=3D 0) { - llcc_edac =3D platform_device_register_data(&pdev->dev, - "qcom_llcc_edac", -1, drv_data, - sizeof(*drv_data)); - if (IS_ERR(llcc_edac)) - dev_err(dev, "Failed to register llcc edac driver\n"); - } + + llcc_edac =3D platform_device_register_data(&pdev->dev, + "qcom_llcc_edac", -1, drv_data, + sizeof(*drv_data)); + if (IS_ERR(llcc_edac)) + dev_err(dev, "Failed to register llcc edac driver\n"); =20 return 0; err: --=20 2.25.1 From nobody Sun Sep 14 20:25:45 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id BDF34C6FD1C for ; Tue, 14 Mar 2023 08:07:41 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230371AbjCNIHk (ORCPT ); Tue, 14 Mar 2023 04:07:40 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:39032 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230510AbjCNIHI (ORCPT ); Tue, 14 Mar 2023 04:07:08 -0400 Received: from mail-pj1-x1029.google.com (mail-pj1-x1029.google.com [IPv6:2607:f8b0:4864:20::1029]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id BE0CA984FB for ; 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charset="utf-8" The platforms based on SDM845 SoC locks the access to EDAC registers in the bootloader. So probing the EDAC driver will result in a crash. Hence, disable the creation of EDAC platform device on all SDM845 devices. The issue has been observed on Lenovo Yoga C630 and DB845c. While at it, also sort the members of `struct qcom_llcc_config` to avoid any holes in-between. Cc: # 5.10 Reported-by: Steev Klimaszewski Signed-off-by: Manivannan Sadhasivam --- drivers/soc/qcom/llcc-qcom.c | 24 +++++++++++++++++------- 1 file changed, 17 insertions(+), 7 deletions(-) diff --git a/drivers/soc/qcom/llcc-qcom.c b/drivers/soc/qcom/llcc-qcom.c index 7b7c5a38bac6..a5140f19f200 100644 --- a/drivers/soc/qcom/llcc-qcom.c +++ b/drivers/soc/qcom/llcc-qcom.c @@ -120,10 +120,11 @@ struct llcc_slice_config { =20 struct qcom_llcc_config { const struct llcc_slice_config *sct_data; - int size; - bool need_llcc_cfg; const u32 *reg_offset; const struct llcc_edac_reg_offset *edac_reg_offset; + int size; + bool need_llcc_cfg; + bool no_edac; }; =20 enum llcc_reg_offset { @@ -452,6 +453,7 @@ static const struct qcom_llcc_config sdm845_cfg =3D { .need_llcc_cfg =3D false, .reg_offset =3D llcc_v1_reg_offset, .edac_reg_offset =3D &llcc_v1_edac_reg_offset, + .no_edac =3D true, }; =20 static const struct qcom_llcc_config sm6350_cfg =3D { @@ -1012,11 +1014,19 @@ static int qcom_llcc_probe(struct platform_device *= pdev) =20 drv_data->ecc_irq =3D platform_get_irq_optional(pdev, 0); =20 - llcc_edac =3D platform_device_register_data(&pdev->dev, - "qcom_llcc_edac", -1, drv_data, - sizeof(*drv_data)); - if (IS_ERR(llcc_edac)) - dev_err(dev, "Failed to register llcc edac driver\n"); + /* + * On some platforms, the access to EDAC registers will be locked by + * the bootloader. So probing the EDAC driver will result in a crash. + * Hence, disable the creation of EDAC platform device for the + * problematic platforms. + */ + if (!cfg->no_edac) { + llcc_edac =3D platform_device_register_data(&pdev->dev, + "qcom_llcc_edac", -1, drv_data, + sizeof(*drv_data)); + if (IS_ERR(llcc_edac)) + dev_err(dev, "Failed to register llcc edac driver\n"); + } =20 return 0; err: --=20 2.25.1