From nobody Wed Feb 11 16:13:48 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id C2FD9C61DA4 for ; Mon, 13 Mar 2023 13:58:10 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230077AbjCMN6J convert rfc822-to-8bit (ORCPT ); Mon, 13 Mar 2023 09:58:09 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:39820 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229885AbjCMN6E (ORCPT ); Mon, 13 Mar 2023 09:58:04 -0400 Received: from fd01.gateway.ufhost.com (fd01.gateway.ufhost.com [61.152.239.71]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id EE27165A9; Mon, 13 Mar 2023 06:57:56 -0700 (PDT) Received: from EXMBX166.cuchost.com (unknown [175.102.18.54]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client CN "EXMBX166", Issuer "EXMBX166" (not verified)) by fd01.gateway.ufhost.com (Postfix) with ESMTP id B47D924DFE2; Mon, 13 Mar 2023 21:57:45 +0800 (CST) Received: from EXMBX068.cuchost.com (172.16.6.68) by EXMBX166.cuchost.com (172.16.6.76) with Microsoft SMTP Server (TLS) id 15.0.1497.42; Mon, 13 Mar 2023 21:57:45 +0800 Received: from ubuntu.localdomain (202.190.105.77) by EXMBX068.cuchost.com (172.16.6.68) with Microsoft SMTP Server (TLS) id 15.0.1497.42; Mon, 13 Mar 2023 21:57:34 +0800 From: Jia Jie Ho To: Herbert Xu , "David S . Miller" , Rob Herring , Krzysztof Kozlowski , Emil Renner Berthing , Conor Dooley CC: , , , Subject: [PATCH v3 1/4] dt-bindings: crypto: Add StarFive crypto module Date: Mon, 13 Mar 2023 21:56:43 +0800 Message-ID: <20230313135646.2077707-2-jiajie.ho@starfivetech.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230313135646.2077707-1-jiajie.ho@starfivetech.com> References: <20230313135646.2077707-1-jiajie.ho@starfivetech.com> MIME-Version: 1.0 X-Originating-IP: [202.190.105.77] X-ClientProxiedBy: EXCAS064.cuchost.com (172.16.6.24) To EXMBX068.cuchost.com (172.16.6.68) X-YovoleRuleAgent: yovoleflag Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add documentation to describe StarFive cryptographic engine. Co-developed-by: Huan Feng Signed-off-by: Huan Feng Signed-off-by: Jia Jie Ho Reviewed-by: Rob Herring --- .../crypto/starfive,jh7110-crypto.yaml | 70 +++++++++++++++++++ 1 file changed, 70 insertions(+) create mode 100644 Documentation/devicetree/bindings/crypto/starfive,jh711= 0-crypto.yaml diff --git a/Documentation/devicetree/bindings/crypto/starfive,jh7110-crypt= o.yaml b/Documentation/devicetree/bindings/crypto/starfive,jh7110-crypto.ya= ml new file mode 100644 index 000000000000..71a2876bd6e4 --- /dev/null +++ b/Documentation/devicetree/bindings/crypto/starfive,jh7110-crypto.yaml @@ -0,0 +1,70 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/crypto/starfive,jh7110-crypto.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: StarFive Cryptographic Module + +maintainers: + - Jia Jie Ho + - William Qiu + +properties: + compatible: + const: starfive,jh7110-crypto + + reg: + maxItems: 1 + + clocks: + items: + - description: Hardware reference clock + - description: AHB reference clock + + clock-names: + items: + - const: hclk + - const: ahb + + interrupts: + maxItems: 1 + + resets: + maxItems: 1 + + dmas: + items: + - description: TX DMA channel + - description: RX DMA channel + + dma-names: + items: + - const: tx + - const: rx + +required: + - compatible + - reg + - clocks + - clock-names + - resets + - dmas + - dma-names + +additionalProperties: false + +examples: + - | + crypto: crypto@16000000 { + compatible =3D "starfive,jh7110-crypto"; + reg =3D <0x16000000 0x4000>; + clocks =3D <&clk 15>, <&clk 16>; + clock-names =3D "hclk", "ahb"; + interrupts =3D <28>; + resets =3D <&reset 3>; + dmas =3D <&dma 1 2>, + <&dma 0 2>; + dma-names =3D "tx", "rx"; + }; +... --=20 2.25.1 From nobody Wed Feb 11 16:13:48 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 77E50C61DA4 for ; Mon, 13 Mar 2023 13:58:15 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230309AbjCMN6N convert rfc822-to-8bit (ORCPT ); Mon, 13 Mar 2023 09:58:13 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:39838 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229757AbjCMN6E (ORCPT ); Mon, 13 Mar 2023 09:58:04 -0400 Received: from fd01.gateway.ufhost.com (fd01.gateway.ufhost.com [61.152.239.71]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id EE44C6A6C; Mon, 13 Mar 2023 06:57:56 -0700 (PDT) Received: from EXMBX165.cuchost.com (unknown [175.102.18.54]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client CN "EXMBX165", Issuer "EXMBX165" (not verified)) by fd01.gateway.ufhost.com (Postfix) with ESMTP id 2694124DB8C; Mon, 13 Mar 2023 21:57:55 +0800 (CST) Received: from EXMBX068.cuchost.com (172.16.6.68) by EXMBX165.cuchost.com (172.16.6.75) with Microsoft SMTP Server (TLS) id 15.0.1497.42; Mon, 13 Mar 2023 21:57:55 +0800 Received: from ubuntu.localdomain (202.190.105.77) by EXMBX068.cuchost.com (172.16.6.68) with Microsoft SMTP Server (TLS) id 15.0.1497.42; Mon, 13 Mar 2023 21:57:45 +0800 From: Jia Jie Ho To: Herbert Xu , "David S . Miller" , Rob Herring , Krzysztof Kozlowski , Emil Renner Berthing , Conor Dooley CC: , , , Subject: [PATCH v3 2/4] crypto: starfive - Add crypto engine support Date: Mon, 13 Mar 2023 21:56:44 +0800 Message-ID: <20230313135646.2077707-3-jiajie.ho@starfivetech.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230313135646.2077707-1-jiajie.ho@starfivetech.com> References: <20230313135646.2077707-1-jiajie.ho@starfivetech.com> MIME-Version: 1.0 X-Originating-IP: [202.190.105.77] X-ClientProxiedBy: EXCAS064.cuchost.com (172.16.6.24) To EXMBX068.cuchost.com (172.16.6.68) X-YovoleRuleAgent: yovoleflag Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Adding device probe and DMA init for StarFive cryptographic module. Co-developed-by: Huan Feng Signed-off-by: Huan Feng Signed-off-by: Jia Jie Ho --- MAINTAINERS | 7 + drivers/crypto/Kconfig | 1 + drivers/crypto/Makefile | 1 + drivers/crypto/starfive/Kconfig | 17 +++ drivers/crypto/starfive/Makefile | 4 + drivers/crypto/starfive/jh7110-cryp.c | 202 ++++++++++++++++++++++++++ drivers/crypto/starfive/jh7110-cryp.h | 67 +++++++++ 7 files changed, 299 insertions(+) create mode 100644 drivers/crypto/starfive/Kconfig create mode 100644 drivers/crypto/starfive/Makefile create mode 100644 drivers/crypto/starfive/jh7110-cryp.c create mode 100644 drivers/crypto/starfive/jh7110-cryp.h diff --git a/MAINTAINERS b/MAINTAINERS index 65140500d9f8..a6f7677db4db 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -19609,6 +19609,13 @@ F: Documentation/devicetree/bindings/clock/starfiv= e* F: drivers/clk/starfive/ F: include/dt-bindings/clock/starfive* =20 +STARFIVE CRYPTO DRIVER +M: Jia Jie Ho +M: William Qiu +S: Supported +F: Documentation/devicetree/bindings/crypto/starfive* +F: drivers/crypto/starfive/ + STARFIVE PINCTRL DRIVER M: Emil Renner Berthing M: Jianlong Huang diff --git a/drivers/crypto/Kconfig b/drivers/crypto/Kconfig index 55e75fbb658e..64b94376601c 100644 --- a/drivers/crypto/Kconfig +++ b/drivers/crypto/Kconfig @@ -817,5 +817,6 @@ config CRYPTO_DEV_SA2UL =20 source "drivers/crypto/keembay/Kconfig" source "drivers/crypto/aspeed/Kconfig" +source "drivers/crypto/starfive/Kconfig" =20 endif # CRYPTO_HW diff --git a/drivers/crypto/Makefile b/drivers/crypto/Makefile index 116de173a66c..212931c84412 100644 --- a/drivers/crypto/Makefile +++ b/drivers/crypto/Makefile @@ -53,3 +53,4 @@ obj-y +=3D xilinx/ obj-y +=3D hisilicon/ obj-$(CONFIG_CRYPTO_DEV_AMLOGIC_GXL) +=3D amlogic/ obj-y +=3D keembay/ +obj-y +=3D starfive/ diff --git a/drivers/crypto/starfive/Kconfig b/drivers/crypto/starfive/Kcon= fig new file mode 100644 index 000000000000..73f39b6bc09f --- /dev/null +++ b/drivers/crypto/starfive/Kconfig @@ -0,0 +1,17 @@ +# +# StarFive crypto drivers configuration +# + +config CRYPTO_DEV_JH7110 + tristate "StarFive JH7110 cryptographic engine driver" + depends on SOC_STARFIVE + select CRYPTO_ENGINE + select ARM_AMBA + select DMADEVICES + select AMBA_PL08X + help + Support for StarFive JH7110 crypto hardware acceleration engine. + This module provides acceleration for public key algo, + skciphers, AEAD and hash functions. + + If you choose 'M' here, this module will be called starfive-crypto. diff --git a/drivers/crypto/starfive/Makefile b/drivers/crypto/starfive/Mak= efile new file mode 100644 index 000000000000..071a4872fb5f --- /dev/null +++ b/drivers/crypto/starfive/Makefile @@ -0,0 +1,4 @@ +# SPDX-License-Identifier: GPL-2.0 + +obj-$(CONFIG_CRYPTO_DEV_JH7110) +=3D jh7110-crypto.o +starfive-crypto-objs :=3D jh7110-cryp.o diff --git a/drivers/crypto/starfive/jh7110-cryp.c b/drivers/crypto/starfiv= e/jh7110-cryp.c new file mode 100644 index 000000000000..abd500f3c1f3 --- /dev/null +++ b/drivers/crypto/starfive/jh7110-cryp.c @@ -0,0 +1,202 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Cryptographic API. + * + * Support for StarFive hardware cryptographic engine. + * Copyright (c) 2022 StarFive Technology + * + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "jh7110-cryp.h" + +#define DRIVER_NAME "starfive-crypto" + +struct starfive_dev_list { + struct list_head dev_list; + spinlock_t lock; /* protect dev_list */ +}; + +static struct starfive_dev_list dev_list =3D { + .dev_list =3D LIST_HEAD_INIT(dev_list.dev_list), + .lock =3D __SPIN_LOCK_UNLOCKED(dev_list.lock), +}; + +struct starfive_cryp_dev *starfive_cryp_find_dev(struct starfive_cryp_ctx = *ctx) +{ + struct starfive_cryp_dev *cryp =3D NULL, *tmp; + + spin_lock_bh(&dev_list.lock); + if (!ctx->cryp) { + list_for_each_entry(tmp, &dev_list.dev_list, list) { + cryp =3D tmp; + break; + } + ctx->cryp =3D cryp; + } else { + cryp =3D ctx->cryp; + } + + spin_unlock_bh(&dev_list.lock); + + return cryp; +} + +static int starfive_dma_init(struct starfive_cryp_dev *cryp) +{ + dma_cap_mask_t mask; + + cryp->tx =3D NULL; + cryp->rx =3D NULL; + + dma_cap_zero(mask); + dma_cap_set(DMA_SLAVE, mask); + + cryp->tx =3D dma_request_chan(cryp->dev, "tx"); + if (IS_ERR(cryp->tx)) + return dev_err_probe(cryp->dev, PTR_ERR(cryp->tx), + "Error requesting tx dma channel.\n"); + + cryp->rx =3D dma_request_chan(cryp->dev, "rx"); + if (IS_ERR(cryp->rx)) { + dma_release_channel(cryp->tx); + return dev_err_probe(cryp->dev, PTR_ERR(cryp->rx), + "Error requesting rx dma channel.\n"); + } + + init_completion(&cryp->tx_comp); + init_completion(&cryp->rx_comp); + + return 0; +} + +static void starfive_dma_cleanup(struct starfive_cryp_dev *cryp) +{ + dma_release_channel(cryp->tx); + dma_release_channel(cryp->rx); +} + +static int starfive_cryp_probe(struct platform_device *pdev) +{ + struct starfive_cryp_dev *cryp; + struct resource *res; + int ret; + + cryp =3D devm_kzalloc(&pdev->dev, sizeof(*cryp), GFP_KERNEL); + if (!cryp) + return -ENOMEM; + + platform_set_drvdata(pdev, cryp); + cryp->dev =3D &pdev->dev; + + cryp->base =3D devm_platform_get_and_ioremap_resource(pdev, 0, &res); + if (IS_ERR(cryp->base)) + return dev_err_probe(&pdev->dev, PTR_ERR(cryp->base), + "Error remapping memory for platform device\n"); + + cryp->phys_base =3D res->start; + cryp->dma_maxburst =3D 32; + + cryp->hclk =3D devm_clk_get(&pdev->dev, "hclk"); + if (IS_ERR(cryp->hclk)) + return dev_err_probe(&pdev->dev, PTR_ERR(cryp->hclk), + "Error getting hardware reference clock\n"); + + cryp->ahb =3D devm_clk_get(&pdev->dev, "ahb"); + if (IS_ERR(cryp->ahb)) + return dev_err_probe(&pdev->dev, PTR_ERR(cryp->ahb), + "Error getting ahb reference clock\n"); + + cryp->rst =3D devm_reset_control_get_shared(cryp->dev, NULL); + if (IS_ERR(cryp->rst)) + return dev_err_probe(&pdev->dev, PTR_ERR(cryp->rst), + "Error getting hardware reset line\n"); + + clk_prepare_enable(cryp->hclk); + clk_prepare_enable(cryp->ahb); + reset_control_deassert(cryp->rst); + + spin_lock(&dev_list.lock); + list_add(&cryp->list, &dev_list.dev_list); + spin_unlock(&dev_list.lock); + + ret =3D starfive_dma_init(cryp); + if (ret) + goto err_dma_init; + + /* Initialize crypto engine */ + cryp->engine =3D crypto_engine_alloc_init(&pdev->dev, 1); + if (!cryp->engine) { + ret =3D -ENOMEM; + goto err_engine; + } + + ret =3D crypto_engine_start(cryp->engine); + if (ret) + goto err_engine_start; + + return 0; + +err_engine_start: + crypto_engine_exit(cryp->engine); +err_engine: + starfive_dma_cleanup(cryp); +err_dma_init: + spin_lock(&dev_list.lock); + list_del(&cryp->list); + spin_unlock(&dev_list.lock); + + return ret; +} + +static int starfive_cryp_remove(struct platform_device *pdev) +{ + struct starfive_cryp_dev *cryp =3D platform_get_drvdata(pdev); + + if (!cryp) + return -ENODEV; + + crypto_engine_stop(cryp->engine); + crypto_engine_exit(cryp->engine); + + starfive_dma_cleanup(cryp); + + spin_lock(&dev_list.lock); + list_del(&cryp->list); + spin_unlock(&dev_list.lock); + + clk_disable_unprepare(cryp->hclk); + clk_disable_unprepare(cryp->ahb); + reset_control_assert(cryp->rst); + + return 0; +} + +static const struct of_device_id starfive_dt_ids[] __maybe_unused =3D { + { .compatible =3D "starfive,jh7110-crypto", .data =3D NULL}, + {}, +}; +MODULE_DEVICE_TABLE(of, starfive_dt_ids); + +static struct platform_driver starfive_cryp_driver =3D { + .probe =3D starfive_cryp_probe, + .remove =3D starfive_cryp_remove, + .driver =3D { + .name =3D DRIVER_NAME, + .of_match_table =3D starfive_dt_ids, + }, +}; + +module_platform_driver(starfive_cryp_driver); + +MODULE_LICENSE("GPL"); +MODULE_DESCRIPTION("StarFive Cryptographic Module"); diff --git a/drivers/crypto/starfive/jh7110-cryp.h b/drivers/crypto/starfiv= e/jh7110-cryp.h new file mode 100644 index 000000000000..2ac87ed3fb03 --- /dev/null +++ b/drivers/crypto/starfive/jh7110-cryp.h @@ -0,0 +1,67 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef __STARFIVE_STR_H__ +#define __STARFIVE_STR_H__ + +#include +#include +#include + +#include + +#define STARFIVE_ALG_CR_OFFSET 0x0 +#define STARFIVE_ALG_FIFO_OFFSET 0x4 +#define STARFIVE_IE_MASK_OFFSET 0x8 +#define STARFIVE_IE_FLAG_OFFSET 0xc +#define STARFIVE_DMA_IN_LEN_OFFSET 0x10 +#define STARFIVE_DMA_OUT_LEN_OFFSET 0x14 + +#define STARFIVE_MSG_BUFFER_SIZE SZ_16K + +union starfive_alg_cr { + u32 v; + struct { + u32 start :1; + u32 aes_dma_en :1; + u32 rsvd_0 :1; + u32 hash_dma_en :1; + u32 alg_done :1; + u32 rsvd_1 :3; + u32 clear :1; + u32 rsvd_2 :23; + }; +}; + +struct starfive_cryp_ctx { + struct crypto_engine_ctx enginectx; + struct starfive_cryp_dev *cryp; + + u8 *buffer; +}; + +struct starfive_cryp_dev { + struct list_head list; + struct device *dev; + + struct clk *hclk; + struct clk *ahb; + struct reset_control *rst; + + void __iomem *base; + phys_addr_t phys_base; + + u32 dma_maxburst; + struct dma_chan *tx; + struct dma_chan *rx; + struct dma_slave_config cfg_in; + struct dma_slave_config cfg_out; + struct completion tx_comp; + struct completion rx_comp; + + struct crypto_engine *engine; + + union starfive_alg_cr alg_cr; +}; + +struct starfive_cryp_dev *starfive_cryp_find_dev(struct starfive_cryp_ctx = *ctx); + +#endif --=20 2.25.1 From nobody Wed Feb 11 16:13:48 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id D5B04C6FD19 for ; Mon, 13 Mar 2023 13:58:30 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230086AbjCMN62 convert rfc822-to-8bit (ORCPT ); Mon, 13 Mar 2023 09:58:28 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:41354 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230422AbjCMN6X (ORCPT ); Mon, 13 Mar 2023 09:58:23 -0400 Received: from ex01.ufhost.com (ex01.ufhost.com [61.152.239.75]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 44E8C12BDB; Mon, 13 Mar 2023 06:58:03 -0700 (PDT) Received: from EXMBX166.cuchost.com (unknown [175.102.18.54]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client CN "EXMBX166", Issuer "EXMBX166" (not verified)) by ex01.ufhost.com (Postfix) with ESMTP id 3914224E17F; Mon, 13 Mar 2023 21:58:02 +0800 (CST) Received: from EXMBX068.cuchost.com (172.16.6.68) by EXMBX166.cuchost.com (172.16.6.76) with Microsoft SMTP Server (TLS) id 15.0.1497.42; Mon, 13 Mar 2023 21:58:02 +0800 Received: from ubuntu.localdomain (202.190.105.77) by EXMBX068.cuchost.com (172.16.6.68) with Microsoft SMTP Server (TLS) id 15.0.1497.42; Mon, 13 Mar 2023 21:57:55 +0800 From: Jia Jie Ho To: Herbert Xu , "David S . Miller" , Rob Herring , Krzysztof Kozlowski , Emil Renner Berthing , Conor Dooley CC: , , , Subject: [PATCH v3 3/4] riscv: dts: starfive: Add crypto and DMA node for VisionFive 2 Date: Mon, 13 Mar 2023 21:56:45 +0800 Message-ID: <20230313135646.2077707-4-jiajie.ho@starfivetech.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230313135646.2077707-1-jiajie.ho@starfivetech.com> References: <20230313135646.2077707-1-jiajie.ho@starfivetech.com> MIME-Version: 1.0 X-Originating-IP: [202.190.105.77] X-ClientProxiedBy: EXCAS064.cuchost.com (172.16.6.24) To EXMBX068.cuchost.com (172.16.6.68) X-YovoleRuleAgent: yovoleflag Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add StarFive cryptographic module and dedicated DMA controller node to VisionFive 2 SoCs. Co-developed-by: Huan Feng Signed-off-by: Huan Feng Signed-off-by: Jia Jie Ho Acked-by: Palmer Dabbelt --- arch/riscv/boot/dts/starfive/jh7110.dtsi | 28 ++++++++++++++++++++++++ 1 file changed, 28 insertions(+) diff --git a/arch/riscv/boot/dts/starfive/jh7110.dtsi b/arch/riscv/boot/dts= /starfive/jh7110.dtsi index 4ac159d79d66..591abe57ec31 100644 --- a/arch/riscv/boot/dts/starfive/jh7110.dtsi +++ b/arch/riscv/boot/dts/starfive/jh7110.dtsi @@ -455,5 +455,33 @@ uart5: serial@12020000 { reg-shift =3D <2>; status =3D "disabled"; }; + + sdma: dma@16008000 { + compatible =3D "arm,pl080", "arm,primecell"; + arm,primecell-periphid =3D <0x00041080>; + reg =3D <0x0 0x16008000 0x0 0x4000>; + interrupts =3D <29>; + clocks =3D <&stgcrg JH7110_STGCLK_SEC_HCLK>, + <&stgcrg JH7110_STGCLK_SEC_MISCAHB>; + clock-names =3D "hclk", "apb_pclk"; + resets =3D <&stgcrg JH7110_STGRST_SEC_TOP_HRESETN>; + lli-bus-interface-ahb1; + mem-bus-interface-ahb1; + memcpy-burst-size =3D <256>; + memcpy-bus-width =3D <32>; + #dma-cells =3D <2>; + }; + + crypto: crypto@16000000 { + compatible =3D "starfive,jh7110-crypto"; + reg =3D <0x0 0x16000000 0x0 0x4000>; + clocks =3D <&stgcrg JH7110_STGCLK_SEC_HCLK>, + <&stgcrg JH7110_STGCLK_SEC_MISCAHB>; + clock-names =3D "hclk", "ahb"; + interrupts =3D <28>; + resets =3D <&stgcrg JH7110_STGRST_SEC_TOP_HRESETN>; + dmas =3D <&sdma 1 2>, <&sdma 0 2>; + dma-names =3D "tx", "rx"; + }; }; }; --=20 2.25.1 From nobody Wed Feb 11 16:13:48 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0576CC6FD1C for ; Mon, 13 Mar 2023 13:58:53 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231281AbjCMN6u convert rfc822-to-8bit (ORCPT ); Mon, 13 Mar 2023 09:58:50 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:41576 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231297AbjCMN6g (ORCPT ); Mon, 13 Mar 2023 09:58:36 -0400 Received: from ex01.ufhost.com (ex01.ufhost.com [61.152.239.75]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 4902D14203; Mon, 13 Mar 2023 06:58:20 -0700 (PDT) Received: from EXMBX165.cuchost.com (unknown [175.102.18.54]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client CN "EXMBX165", Issuer "EXMBX165" (not verified)) by ex01.ufhost.com (Postfix) with ESMTP id C2E5B24E195; Mon, 13 Mar 2023 21:58:17 +0800 (CST) Received: from EXMBX068.cuchost.com (172.16.6.68) by EXMBX165.cuchost.com (172.16.6.75) with Microsoft SMTP Server (TLS) id 15.0.1497.42; Mon, 13 Mar 2023 21:58:17 +0800 Received: from ubuntu.localdomain (202.190.105.77) by EXMBX068.cuchost.com (172.16.6.68) with Microsoft SMTP Server (TLS) id 15.0.1497.42; Mon, 13 Mar 2023 21:58:02 +0800 From: Jia Jie Ho To: Herbert Xu , "David S . Miller" , Rob Herring , Krzysztof Kozlowski , Emil Renner Berthing , Conor Dooley CC: , , , Subject: [PATCH v3 4/4] crypto: starfive - Add hash and HMAC support Date: Mon, 13 Mar 2023 21:56:46 +0800 Message-ID: <20230313135646.2077707-5-jiajie.ho@starfivetech.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230313135646.2077707-1-jiajie.ho@starfivetech.com> References: <20230313135646.2077707-1-jiajie.ho@starfivetech.com> MIME-Version: 1.0 X-Originating-IP: [202.190.105.77] X-ClientProxiedBy: EXCAS064.cuchost.com (172.16.6.24) To EXMBX068.cuchost.com (172.16.6.68) X-YovoleRuleAgent: yovoleflag Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Adding hash/HMAC support for SHA-2 and SM3 to StarFive cryptographic module. Co-developed-by: Huan Feng Signed-off-by: Huan Feng Signed-off-by: Jia Jie Ho --- drivers/crypto/starfive/Kconfig | 4 + drivers/crypto/starfive/Makefile | 2 +- drivers/crypto/starfive/jh7110-cryp.c | 35 + drivers/crypto/starfive/jh7110-cryp.h | 69 +- drivers/crypto/starfive/jh7110-hash.c | 1041 +++++++++++++++++++++++++ 5 files changed, 1147 insertions(+), 4 deletions(-) create mode 100644 drivers/crypto/starfive/jh7110-hash.c diff --git a/drivers/crypto/starfive/Kconfig b/drivers/crypto/starfive/Kcon= fig index 73f39b6bc09f..cde485910f88 100644 --- a/drivers/crypto/starfive/Kconfig +++ b/drivers/crypto/starfive/Kconfig @@ -6,6 +6,10 @@ config CRYPTO_DEV_JH7110 tristate "StarFive JH7110 cryptographic engine driver" depends on SOC_STARFIVE select CRYPTO_ENGINE + select CRYPTO_HMAC + select CRYPTO_SHA256 + select CRYPTO_SHA512 + select CRYPTO_SM3_GENERIC select ARM_AMBA select DMADEVICES select AMBA_PL08X diff --git a/drivers/crypto/starfive/Makefile b/drivers/crypto/starfive/Mak= efile index 071a4872fb5f..2af49062e36d 100644 --- a/drivers/crypto/starfive/Makefile +++ b/drivers/crypto/starfive/Makefile @@ -1,4 +1,4 @@ # SPDX-License-Identifier: GPL-2.0 =20 obj-$(CONFIG_CRYPTO_DEV_JH7110) +=3D jh7110-crypto.o -starfive-crypto-objs :=3D jh7110-cryp.o +jh7110-crypto-objs :=3D jh7110-cryp.o jh7110-hash.o diff --git a/drivers/crypto/starfive/jh7110-cryp.c b/drivers/crypto/starfiv= e/jh7110-cryp.c index abd500f3c1f3..94c99aab308f 100644 --- a/drivers/crypto/starfive/jh7110-cryp.c +++ b/drivers/crypto/starfive/jh7110-cryp.c @@ -85,10 +85,25 @@ static void starfive_dma_cleanup(struct starfive_cryp_d= ev *cryp) dma_release_channel(cryp->rx); } =20 +static irqreturn_t starfive_cryp_irq(int irq, void *priv) +{ + u32 status; + struct starfive_cryp_dev *cryp =3D (struct starfive_cryp_dev *)priv; + + status =3D readl(cryp->base + STARFIVE_IE_FLAG_OFFSET); + if (status & STARFIVE_IE_FLAG_HASH_DONE) { + writel(STARFIVE_IE_MASK_HASH_DONE, cryp->base + STARFIVE_IE_MASK_OFFSET); + complete(&cryp->hash_done); + } + + return IRQ_HANDLED; +} + static int starfive_cryp_probe(struct platform_device *pdev) { struct starfive_cryp_dev *cryp; struct resource *res; + int irq; int ret; =20 cryp =3D devm_kzalloc(&pdev->dev, sizeof(*cryp), GFP_KERNEL); @@ -121,6 +136,18 @@ static int starfive_cryp_probe(struct platform_device = *pdev) return dev_err_probe(&pdev->dev, PTR_ERR(cryp->rst), "Error getting hardware reset line\n"); =20 + init_completion(&cryp->hash_done); + + irq =3D platform_get_irq(pdev, 0); + if (irq < 0) + return irq; + + ret =3D devm_request_irq(&pdev->dev, irq, starfive_cryp_irq, 0, pdev->nam= e, + (void *)cryp); + if (ret) + return dev_err_probe(&pdev->dev, irq, + "Failed to register interrupt handler\n"); + clk_prepare_enable(cryp->hclk); clk_prepare_enable(cryp->ahb); reset_control_deassert(cryp->rst); @@ -144,8 +171,14 @@ static int starfive_cryp_probe(struct platform_device = *pdev) if (ret) goto err_engine_start; =20 + ret =3D starfive_hash_register_algs(); + if (ret) + goto err_algs_hash; + return 0; =20 +err_algs_hash: + crypto_engine_stop(cryp->engine); err_engine_start: crypto_engine_exit(cryp->engine); err_engine: @@ -165,6 +198,8 @@ static int starfive_cryp_remove(struct platform_device = *pdev) if (!cryp) return -ENODEV; =20 + starfive_hash_unregister_algs(); + crypto_engine_stop(cryp->engine); crypto_engine_exit(cryp->engine); =20 diff --git a/drivers/crypto/starfive/jh7110-cryp.h b/drivers/crypto/starfiv= e/jh7110-cryp.h index 2ac87ed3fb03..28cc73308031 100644 --- a/drivers/crypto/starfive/jh7110-cryp.h +++ b/drivers/crypto/starfive/jh7110-cryp.h @@ -7,6 +7,8 @@ #include =20 #include +#include +#include =20 #define STARFIVE_ALG_CR_OFFSET 0x0 #define STARFIVE_ALG_FIFO_OFFSET 0x4 @@ -15,7 +17,44 @@ #define STARFIVE_DMA_IN_LEN_OFFSET 0x10 #define STARFIVE_DMA_OUT_LEN_OFFSET 0x14 =20 +#define STARFIVE_IE_MASK_HASH_DONE BIT(2) +#define STARFIVE_IE_FLAG_HASH_DONE BIT(2) + #define STARFIVE_MSG_BUFFER_SIZE SZ_16K +#define MAX_KEY_SIZE SHA512_BLOCK_SIZE + +union starfive_hash_csr { + u32 v; + struct { + u32 start :1; + u32 reset :1; + u32 ie :1; + u32 firstb :1; +#define STARFIVE_HASH_SM3 0x0 +#define STARFIVE_HASH_SHA224 0x3 +#define STARFIVE_HASH_SHA256 0x4 +#define STARFIVE_HASH_SHA384 0x5 +#define STARFIVE_HASH_SHA512 0x6 +#define STARFIVE_HASH_MODE_MASK 0x7 + u32 mode :3; + u32 rsvd_1 :1; + u32 final :1; + u32 rsvd_2 :2; +#define STARFIVE_HASH_HMAC_FLAGS 0x800 + u32 hmac :1; + u32 rsvd_3 :1; +#define STARFIVE_HASH_KEY_DONE BIT(13) + u32 key_done :1; + u32 key_flag :1; +#define STARFIVE_HASH_HMAC_DONE BIT(15) + u32 hmac_done :1; +#define STARFIVE_HASH_BUSY BIT(16) + u32 busy :1; + u32 hashdone :1; + u32 rsvd_4 :14; + }; +}; + =20 union starfive_alg_cr { u32 v; @@ -34,14 +73,17 @@ union starfive_alg_cr { struct starfive_cryp_ctx { struct crypto_engine_ctx enginectx; struct starfive_cryp_dev *cryp; + struct starfive_cryp_request_ctx *rctx; =20 - u8 *buffer; + unsigned int hash_mode; + u8 key[MAX_KEY_SIZE]; + int keylen; + struct crypto_ahash *ahash_fbk; }; =20 struct starfive_cryp_dev { struct list_head list; struct device *dev; - struct clk *hclk; struct clk *ahb; struct reset_control *rst; @@ -56,12 +98,33 @@ struct starfive_cryp_dev { struct dma_slave_config cfg_out; struct completion tx_comp; struct completion rx_comp; - + struct completion hash_done; struct crypto_engine *engine; =20 union starfive_alg_cr alg_cr; }; =20 +struct starfive_cryp_request_ctx { + union { + struct ahash_request *hreq; + } req; + union { + union starfive_hash_csr hash; + } csr; + + struct scatterlist *in_sg; + struct scatterlist in_sgl; + struct ahash_request ahash_fbk_req; + size_t total; + unsigned int blksize; + unsigned int digsize; + unsigned long in_sg_len; + bool sgs_copied; +}; + struct starfive_cryp_dev *starfive_cryp_find_dev(struct starfive_cryp_ctx = *ctx); =20 +int starfive_hash_register_algs(void); +void starfive_hash_unregister_algs(void); + #endif diff --git a/drivers/crypto/starfive/jh7110-hash.c b/drivers/crypto/starfiv= e/jh7110-hash.c new file mode 100644 index 000000000000..39570f517ccc --- /dev/null +++ b/drivers/crypto/starfive/jh7110-hash.c @@ -0,0 +1,1041 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Hash function and HMAC support for StarFive driver + * + * Copyright (c) 2022 StarFive Technology + * + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include + +#include "jh7110-cryp.h" + +#define STARFIVE_HASH_REGS_OFFSET 0x300 +#define STARFIVE_HASH_SHACSR (STARFIVE_HASH_REGS_OFFSET + 0x0) +#define STARFIVE_HASH_SHAWDR (STARFIVE_HASH_REGS_OFFSET + 0x4) +#define STARFIVE_HASH_SHARDR (STARFIVE_HASH_REGS_OFFSET + 0x8) +#define STARFIVE_HASH_SHAWSR (STARFIVE_HASH_REGS_OFFSET + 0xC) +#define STARFIVE_HASH_SHAWLEN3 (STARFIVE_HASH_REGS_OFFSET + 0x10) +#define STARFIVE_HASH_SHAWLEN2 (STARFIVE_HASH_REGS_OFFSET + 0x14) +#define STARFIVE_HASH_SHAWLEN1 (STARFIVE_HASH_REGS_OFFSET + 0x18) +#define STARFIVE_HASH_SHAWLEN0 (STARFIVE_HASH_REGS_OFFSET + 0x1C) +#define STARFIVE_HASH_SHAWKR (STARFIVE_HASH_REGS_OFFSET + 0x20) +#define STARFIVE_HASH_SHAWKLEN (STARFIVE_HASH_REGS_OFFSET + 0x24) + +#define STARFIVE_HASH_BUFLEN SHA512_BLOCK_SIZE + +static inline int starfive_hash_wait_busy(struct starfive_cryp_ctx *ctx) +{ + struct starfive_cryp_dev *cryp =3D ctx->cryp; + u32 status; + + return readl_relaxed_poll_timeout(cryp->base + STARFIVE_HASH_SHACSR, stat= us, + !(status & STARFIVE_HASH_BUSY), 10, 100000); +} + +static inline int starfive_hash_wait_key_done(struct starfive_cryp_ctx *ct= x) +{ + struct starfive_cryp_dev *cryp =3D ctx->cryp; + u32 status; + + return readl_relaxed_poll_timeout(cryp->base + STARFIVE_HASH_SHACSR, stat= us, + (status & STARFIVE_HASH_KEY_DONE), 10, 100000); +} + +static void starfive_hash_start(struct starfive_cryp_ctx *ctx) +{ + struct starfive_cryp_request_ctx *rctx =3D ctx->rctx; + struct starfive_cryp_dev *cryp =3D ctx->cryp; + + rctx->csr.hash.v =3D readl(cryp->base + STARFIVE_HASH_SHACSR); + rctx->csr.hash.firstb =3D 0; + rctx->csr.hash.final =3D 1; + + writel(rctx->csr.hash.v, cryp->base + STARFIVE_HASH_SHACSR); +} + +static int starfive_hash_hmac_key(struct starfive_cryp_ctx *ctx) +{ + struct starfive_cryp_request_ctx *rctx =3D ctx->rctx; + struct starfive_cryp_dev *cryp =3D ctx->cryp; + int klen =3D ctx->keylen, loop; + unsigned int *key =3D (unsigned int *)ctx->key; + unsigned char *cl; + + writel(ctx->keylen, cryp->base + STARFIVE_HASH_SHAWKLEN); + + rctx->csr.hash.hmac =3D !!(ctx->hash_mode & STARFIVE_HASH_HMAC_FLAGS); + rctx->csr.hash.key_flag =3D 1; + + writel(rctx->csr.hash.v, cryp->base + STARFIVE_HASH_SHACSR); + + for (loop =3D 0; loop < klen / sizeof(unsigned int); loop++, key++) + writel(*key, cryp->base + STARFIVE_HASH_SHAWKR); + + if (klen & 0x3) { + cl =3D (unsigned char *)key; + for (loop =3D 0; loop < (klen & 0x3); loop++, cl++) + writeb(*cl, cryp->base + STARFIVE_HASH_SHAWKR); + } + + if (starfive_hash_wait_key_done(ctx)) + return dev_err_probe(cryp->dev, -ETIMEDOUT, "starfive_hash_wait_key_done= error\n"); + + return 0; +} + +static void starfive_hash_dma_callback(void *param) +{ + struct starfive_cryp_dev *cryp =3D param; + + complete(&cryp->tx_comp); +} + +static int starfive_hash_xmit_dma(struct starfive_cryp_ctx *ctx) +{ + struct starfive_cryp_request_ctx *rctx =3D ctx->rctx; + struct starfive_cryp_dev *cryp =3D ctx->cryp; + struct dma_async_tx_descriptor *in_desc; + dma_cookie_t cookie; + union starfive_alg_cr alg_cr; + int total_len; + int ret; + + if (!rctx->total) + return 0; + + writel(rctx->total, cryp->base + STARFIVE_DMA_IN_LEN_OFFSET); + + total_len =3D rctx->total; + total_len =3D (total_len & 0x3) ? (((total_len >> 2) + 1) << 2) : total_l= en; + sg_dma_len(rctx->in_sg) =3D total_len; + + alg_cr.v =3D 0; + alg_cr.start =3D 1; + alg_cr.hash_dma_en =3D 1; + + writel(alg_cr.v, cryp->base + STARFIVE_ALG_CR_OFFSET); + + ret =3D dma_map_sg(cryp->dev, rctx->in_sg, rctx->in_sg_len, DMA_TO_DEVICE= ); + if (!ret) + return dev_err_probe(cryp->dev, -EINVAL, "dma_map_sg() error\n"); + + cryp->cfg_in.direction =3D DMA_MEM_TO_DEV; + cryp->cfg_in.src_addr_width =3D DMA_SLAVE_BUSWIDTH_4_BYTES; + cryp->cfg_in.dst_addr_width =3D DMA_SLAVE_BUSWIDTH_4_BYTES; + cryp->cfg_in.src_maxburst =3D cryp->dma_maxburst; + cryp->cfg_in.dst_maxburst =3D cryp->dma_maxburst; + cryp->cfg_in.dst_addr =3D cryp->phys_base + STARFIVE_ALG_FIFO_OFFSET; + + dmaengine_slave_config(cryp->tx, &cryp->cfg_in); + + in_desc =3D dmaengine_prep_slave_sg(cryp->tx, rctx->in_sg, + rctx->in_sg_len, DMA_MEM_TO_DEV, + DMA_PREP_INTERRUPT | DMA_CTRL_ACK); + + if (!in_desc) + return -EINVAL; + + reinit_completion(&cryp->tx_comp); + + in_desc->callback =3D starfive_hash_dma_callback; + in_desc->callback_param =3D cryp; + + cookie =3D dmaengine_submit(in_desc); + dma_async_issue_pending(cryp->tx); + + if (!wait_for_completion_timeout(&cryp->tx_comp, + msecs_to_jiffies(10000))) { + dev_err(cryp->dev, "wait_for_completion_timeout error, cookie =3D %x\n", + dma_async_is_tx_complete(cryp->rx, cookie, + NULL, NULL)); + } + + dma_unmap_sg(cryp->dev, rctx->in_sg, rctx->in_sg_len, DMA_TO_DEVICE); + + alg_cr.v =3D 0; + alg_cr.clear =3D 1; + + writel(alg_cr.v, cryp->base + STARFIVE_ALG_CR_OFFSET); + + return 0; +} + +static int starfive_hash_xmit(struct starfive_cryp_ctx *ctx) +{ + struct starfive_cryp_request_ctx *rctx =3D ctx->rctx; + struct starfive_cryp_dev *cryp =3D ctx->cryp; + int ret; + + rctx->csr.hash.v =3D 0; + rctx->csr.hash.reset =3D 1; + writel(rctx->csr.hash.v, cryp->base + STARFIVE_HASH_SHACSR); + + if (starfive_hash_wait_busy(ctx)) + return dev_err_probe(cryp->dev, -ETIMEDOUT, "Error resetting engine.\n"); + + rctx->csr.hash.v =3D 0; + rctx->csr.hash.mode =3D ctx->hash_mode & STARFIVE_HASH_MODE_MASK; + rctx->csr.hash.ie =3D 1; + + if (ctx->hash_mode & STARFIVE_HASH_HMAC_FLAGS) { + ret =3D starfive_hash_hmac_key(ctx); + if (ret) + return ret; + } else { + rctx->csr.hash.start =3D 1; + rctx->csr.hash.firstb =3D 1; + writel(rctx->csr.hash.v, cryp->base + STARFIVE_HASH_SHACSR); + } + + ret =3D starfive_hash_xmit_dma(ctx); + if (ret) + return ret; + + reinit_completion(&cryp->hash_done); + writel(~STARFIVE_IE_MASK_HASH_DONE, cryp->base + STARFIVE_IE_MASK_OFFSET); + + starfive_hash_start(ctx); + + if (!wait_for_completion_timeout(&cryp->hash_done, usecs_to_jiffies(1000)= )) + return dev_err_probe(cryp->dev, -ETIMEDOUT, "Timeout waiting for hash do= ne\n"); + + return 0; +} + +static int starfive_hash_copy_hash(struct ahash_request *req) +{ + struct starfive_cryp_request_ctx *rctx =3D ahash_request_ctx(req); + struct starfive_cryp_ctx *ctx =3D crypto_ahash_ctx(crypto_ahash_reqtfm(re= q)); + int count, *data; + int mlen; + + if (!req->result) + return 0; + + mlen =3D rctx->digsize / sizeof(u32); + data =3D (u32 *)req->result; + + for (count =3D 0; count < mlen; count++) + data[count] =3D readl(ctx->cryp->base + STARFIVE_HASH_SHARDR); + + return 0; +} + +static void starfive_hash_finish_req(struct ahash_request *req, int err) +{ + struct starfive_cryp_ctx *ctx =3D crypto_ahash_ctx(crypto_ahash_reqtfm(re= q)); + struct starfive_cryp_dev *cryp =3D ctx->cryp; + struct starfive_cryp_request_ctx *rctx =3D ahash_request_ctx(req); + + if (!err) + err =3D starfive_hash_copy_hash(req); + + if (rctx->sgs_copied) { + void *buf_in; + int pages, len; + + buf_in =3D sg_virt(&rctx->in_sgl); + len =3D ALIGN(rctx->total, rctx->blksize); + pages =3D len ? get_order(len) : 1; + free_pages((unsigned long)buf_in, pages); + } + + crypto_finalize_hash_request(cryp->engine, req, err); +} + +static int starfive_hash_check_aligned(struct scatterlist *sg, size_t tota= l, size_t align) +{ + int len =3D 0; + + if (!total) + return 0; + + if (!IS_ALIGNED(total, align)) + return -EINVAL; + + while (sg) { + if (!IS_ALIGNED(sg->offset, sizeof(u32))) + return -EINVAL; + + if (!IS_ALIGNED(sg->length, align)) + return -EINVAL; + + len +=3D sg->length; + sg =3D sg_next(sg); + } + + if (len !=3D total) + return -EINVAL; + + return 0; +} + +static int starfive_hash_check_io_aligned(struct starfive_cryp_request_ctx= *rctx) +{ + return starfive_hash_check_aligned(rctx->in_sg, rctx->total, rctx->blksiz= e); +} + +static void sg_copy_buf(void *buf, struct scatterlist *sg, + unsigned int start, unsigned int nbytes, int out) +{ + struct scatter_walk walk; + + if (!nbytes) + return; + + scatterwalk_start(&walk, sg); + scatterwalk_advance(&walk, start); + scatterwalk_copychunks(buf, &walk, nbytes, out); + scatterwalk_done(&walk, out, 0); +} + +static int starfive_hash_copy_sgs(struct starfive_cryp_request_ctx *rctx) +{ + void *buf_in; + int pages, total_in; + + if (!starfive_hash_check_io_aligned(rctx)) { + rctx->sgs_copied =3D 0; + return 0; + } + + total_in =3D ALIGN(rctx->total, rctx->blksize); + pages =3D total_in ? get_order(total_in) : 1; + buf_in =3D (void *)__get_free_pages(GFP_ATOMIC, pages); + if (!buf_in) { + rctx->sgs_copied =3D 0; + return -EFAULT; + } + + sg_copy_buf(buf_in, rctx->in_sg, 0, rctx->total, 0); + sg_init_one(&rctx->in_sgl, buf_in, total_in); + + rctx->in_sg =3D &rctx->in_sgl; + rctx->in_sg_len =3D 1; + rctx->sgs_copied =3D 1; + + return 0; +} + +static int starfive_hash_prepare_req(struct crypto_engine *engine, void *a= req) +{ + struct ahash_request *req =3D container_of(areq, struct ahash_request, + base); + struct starfive_cryp_ctx *ctx =3D crypto_ahash_ctx(crypto_ahash_reqtfm(re= q)); + struct starfive_cryp_dev *cryp =3D ctx->cryp; + struct starfive_cryp_request_ctx *rctx =3D ahash_request_ctx(req); + + if (!cryp) + return -ENODEV; + + rctx->req.hreq =3D req; + + return starfive_hash_copy_sgs(rctx); +} + +static int starfive_hash_one_request(struct crypto_engine *engine, void *a= req) +{ + struct ahash_request *req =3D container_of(areq, struct ahash_request, + base); + struct starfive_cryp_ctx *ctx =3D crypto_ahash_ctx(crypto_ahash_reqtfm(re= q)); + struct starfive_cryp_dev *cryp =3D ctx->cryp; + int err; + + if (!cryp) + return -ENODEV; + + err =3D starfive_hash_xmit(ctx); + if (err) + return err; + + starfive_hash_finish_req(req, err); + + return 0; +} + +static int starfive_hash_init(struct ahash_request *req) +{ + struct crypto_ahash *tfm =3D crypto_ahash_reqtfm(req); + struct starfive_cryp_request_ctx *rctx =3D ahash_request_ctx(req); + struct starfive_cryp_ctx *ctx =3D crypto_ahash_ctx(tfm); + + ahash_request_set_tfm(&rctx->ahash_fbk_req, ctx->ahash_fbk); + rctx->ahash_fbk_req.base.flags =3D req->base.flags + & CRYPTO_TFM_REQ_MAY_SLEEP; + + return crypto_ahash_init(&rctx->ahash_fbk_req); +} + +static int starfive_hash_update(struct ahash_request *req) +{ + struct starfive_cryp_request_ctx *rctx =3D ahash_request_ctx(req); + struct crypto_ahash *tfm =3D crypto_ahash_reqtfm(req); + struct starfive_cryp_ctx *ctx =3D crypto_ahash_ctx(tfm); + + ahash_request_set_tfm(&rctx->ahash_fbk_req, ctx->ahash_fbk); + rctx->ahash_fbk_req.base.flags =3D req->base.flags + & CRYPTO_TFM_REQ_MAY_SLEEP; + rctx->ahash_fbk_req.nbytes =3D req->nbytes; + rctx->ahash_fbk_req.src =3D req->src; + + return crypto_ahash_update(&rctx->ahash_fbk_req); +} + +static int starfive_hash_final(struct ahash_request *req) +{ + struct starfive_cryp_request_ctx *rctx =3D ahash_request_ctx(req); + struct crypto_ahash *tfm =3D crypto_ahash_reqtfm(req); + struct starfive_cryp_ctx *ctx =3D crypto_ahash_ctx(tfm); + + ahash_request_set_tfm(&rctx->ahash_fbk_req, ctx->ahash_fbk); + rctx->ahash_fbk_req.base.flags =3D req->base.flags + & CRYPTO_TFM_REQ_MAY_SLEEP; + rctx->ahash_fbk_req.result =3D req->result; + + return crypto_ahash_final(&rctx->ahash_fbk_req); +} + +static int starfive_hash_finup(struct ahash_request *req) +{ + struct starfive_cryp_request_ctx *rctx =3D ahash_request_ctx(req); + struct crypto_ahash *tfm =3D crypto_ahash_reqtfm(req); + struct starfive_cryp_ctx *ctx =3D crypto_ahash_ctx(tfm); + + ahash_request_set_tfm(&rctx->ahash_fbk_req, ctx->ahash_fbk); + rctx->ahash_fbk_req.base.flags =3D req->base.flags + & CRYPTO_TFM_REQ_MAY_SLEEP; + rctx->ahash_fbk_req.nbytes =3D req->nbytes; + rctx->ahash_fbk_req.src =3D req->src; + rctx->ahash_fbk_req.result =3D req->result; + + return crypto_ahash_finup(&rctx->ahash_fbk_req); +} + +static int starfive_hash_digest(struct ahash_request *req) +{ + struct crypto_ahash *tfm =3D crypto_ahash_reqtfm(req); + struct starfive_cryp_ctx *ctx =3D crypto_ahash_ctx(tfm); + struct starfive_cryp_request_ctx *rctx =3D ahash_request_ctx(req); + struct starfive_cryp_dev *cryp =3D ctx->cryp; + + memset(rctx, 0, sizeof(struct starfive_cryp_request_ctx)); + + rctx->req.hreq =3D req; + rctx->total =3D req->nbytes; + rctx->in_sg =3D req->src; + rctx->blksize =3D crypto_tfm_alg_blocksize(crypto_ahash_tfm(tfm)); + rctx->digsize =3D crypto_ahash_digestsize(tfm); + rctx->in_sg_len =3D sg_nents_for_len(rctx->in_sg, rctx->total); + ctx->rctx =3D rctx; + + return crypto_transfer_hash_request_to_engine(cryp->engine, req); +} + +static int starfive_hash_export(struct ahash_request *req, void *out) +{ + struct starfive_cryp_request_ctx *rctx =3D ahash_request_ctx(req); + struct crypto_ahash *tfm =3D crypto_ahash_reqtfm(req); + struct starfive_cryp_ctx *ctx =3D crypto_ahash_ctx(tfm); + + ahash_request_set_tfm(&rctx->ahash_fbk_req, ctx->ahash_fbk); + rctx->ahash_fbk_req.base.flags =3D req->base.flags + & CRYPTO_TFM_REQ_MAY_SLEEP; + + return crypto_ahash_export(&rctx->ahash_fbk_req, out); +} + +static int starfive_hash_import(struct ahash_request *req, const void *in) +{ + struct starfive_cryp_request_ctx *rctx =3D ahash_request_ctx(req); + struct crypto_ahash *tfm =3D crypto_ahash_reqtfm(req); + struct starfive_cryp_ctx *ctx =3D crypto_ahash_ctx(tfm); + + ahash_request_set_tfm(&rctx->ahash_fbk_req, ctx->ahash_fbk); + rctx->ahash_fbk_req.base.flags =3D req->base.flags + & CRYPTO_TFM_REQ_MAY_SLEEP; + + return crypto_ahash_import(&rctx->ahash_fbk_req, in); +} + +static int starfive_hash_cra_init_algs(struct crypto_tfm *tfm, + const char *algs_hmac_name, + unsigned int mode, + const char *alg_name) +{ + struct starfive_cryp_ctx *ctx =3D crypto_tfm_ctx(tfm); + struct crypto_ahash *ahash =3D __crypto_ahash_cast(tfm); + + ctx->cryp =3D starfive_cryp_find_dev(ctx); + + if (!ctx->cryp) + return -ENODEV; + + ctx->ahash_fbk =3D crypto_alloc_ahash(alg_name, 0, + CRYPTO_ALG_NEED_FALLBACK); + + if (IS_ERR(ctx->ahash_fbk)) + return dev_err_probe(ctx->cryp->dev, PTR_ERR(ctx->ahash_fbk), + "starfive_hash: Could not load fallback driver.\n"); + + crypto_hash_alg_common(ahash)->statesize =3D crypto_ahash_statesize(ctx->= ahash_fbk); + crypto_ahash_set_reqsize(ahash, sizeof(struct starfive_cryp_request_ctx) + + crypto_ahash_reqsize(ctx->ahash_fbk)); + + ctx->keylen =3D 0; + ctx->hash_mode =3D mode; + + if (algs_hmac_name) + ctx->hash_mode |=3D STARFIVE_HASH_HMAC_FLAGS; + + ctx->enginectx.op.do_one_request =3D starfive_hash_one_request; + ctx->enginectx.op.prepare_request =3D starfive_hash_prepare_req; + ctx->enginectx.op.unprepare_request =3D NULL; + + return 0; +} + +static void starfive_hash_cra_exit(struct crypto_tfm *tfm) +{ + struct starfive_cryp_ctx *ctx =3D crypto_tfm_ctx(tfm); + + crypto_free_ahash(ctx->ahash_fbk); + + ctx->ahash_fbk =3D NULL; + ctx->enginectx.op.do_one_request =3D NULL; + ctx->enginectx.op.prepare_request =3D NULL; + ctx->enginectx.op.unprepare_request =3D NULL; +} + +static int starfive_hash_long_setkey(struct starfive_cryp_ctx *ctx, + const u8 *key, unsigned int keylen, + const char *alg_name) +{ + struct crypto_wait wait; + struct ahash_request *req; + struct scatterlist sg; + struct crypto_ahash *ahash_tfm; + u8 *buf; + int ret; + + ahash_tfm =3D crypto_alloc_ahash(alg_name, 0, 0); + if (IS_ERR(ahash_tfm)) + return PTR_ERR(ahash_tfm); + + req =3D ahash_request_alloc(ahash_tfm, GFP_KERNEL); + if (!req) { + ret =3D -ENOMEM; + goto err_free_ahash; + } + + crypto_init_wait(&wait); + ahash_request_set_callback(req, CRYPTO_TFM_REQ_MAY_BACKLOG, + crypto_req_done, &wait); + crypto_ahash_clear_flags(ahash_tfm, ~0); + + buf =3D kzalloc(keylen + STARFIVE_HASH_BUFLEN, GFP_KERNEL); + if (!buf) { + ret =3D -ENOMEM; + goto err_free_req; + } + + memcpy(buf, key, keylen); + sg_init_one(&sg, buf, keylen); + ahash_request_set_crypt(req, &sg, ctx->key, keylen); + + ret =3D crypto_wait_req(crypto_ahash_digest(req), &wait); + + kfree(buf); +err_free_req: + ahash_request_free(req); +err_free_ahash: + crypto_free_ahash(ahash_tfm); + return ret; +} + +static int starfive_hash224_setkey(struct crypto_ahash *tfm, + const u8 *key, unsigned int keylen) +{ + struct starfive_cryp_ctx *ctx =3D crypto_ahash_ctx(tfm); + unsigned int digestsize =3D crypto_ahash_digestsize(tfm); + unsigned int blocksize; + int ret =3D 0; + + blocksize =3D crypto_tfm_alg_blocksize(crypto_ahash_tfm(tfm)); + crypto_ahash_setkey(ctx->ahash_fbk, key, keylen); + + if (keylen <=3D blocksize) { + memcpy(ctx->key, key, keylen); + ctx->keylen =3D keylen; + } else { + ctx->keylen =3D digestsize; + ret =3D starfive_hash_long_setkey(ctx, key, keylen, "starfive-sha224"); + } + + return ret; +} + +static int starfive_hash256_setkey(struct crypto_ahash *tfm, + const u8 *key, unsigned int keylen) +{ + struct starfive_cryp_ctx *ctx =3D crypto_ahash_ctx(tfm); + unsigned int digestsize =3D crypto_ahash_digestsize(tfm); + unsigned int blocksize; + int ret =3D 0; + + blocksize =3D crypto_tfm_alg_blocksize(crypto_ahash_tfm(tfm)); + crypto_ahash_setkey(ctx->ahash_fbk, key, keylen); + + if (keylen <=3D blocksize) { + memcpy(ctx->key, key, keylen); + ctx->keylen =3D keylen; + } else { + ctx->keylen =3D digestsize; + ret =3D starfive_hash_long_setkey(ctx, key, keylen, "starfive-sha256"); + } + + return ret; +} + +static int starfive_hash384_setkey(struct crypto_ahash *tfm, + const u8 *key, unsigned int keylen) +{ + struct starfive_cryp_ctx *ctx =3D crypto_ahash_ctx(tfm); + unsigned int digestsize =3D crypto_ahash_digestsize(tfm); + unsigned int blocksize; + int ret =3D 0; + + blocksize =3D crypto_tfm_alg_blocksize(crypto_ahash_tfm(tfm)); + crypto_ahash_setkey(ctx->ahash_fbk, key, keylen); + + if (keylen <=3D blocksize) { + memcpy(ctx->key, key, keylen); + ctx->keylen =3D keylen; + } else { + ctx->keylen =3D digestsize; + ret =3D starfive_hash_long_setkey(ctx, key, keylen, "starfive-sha384"); + } + + return ret; +} + +static int starfive_hash512_setkey(struct crypto_ahash *tfm, + const u8 *key, unsigned int keylen) +{ + struct starfive_cryp_ctx *ctx =3D crypto_ahash_ctx(tfm); + unsigned int digestsize =3D crypto_ahash_digestsize(tfm); + unsigned int blocksize; + int ret =3D 0; + + blocksize =3D crypto_tfm_alg_blocksize(crypto_ahash_tfm(tfm)); + crypto_ahash_setkey(ctx->ahash_fbk, key, keylen); + + if (keylen <=3D blocksize) { + memcpy(ctx->key, key, keylen); + ctx->keylen =3D keylen; + } else { + ctx->keylen =3D digestsize; + ret =3D starfive_hash_long_setkey(ctx, key, keylen, "starfive-sha512"); + } + + return ret; +} + +static int starfive_sm3_setkey(struct crypto_ahash *tfm, + const u8 *key, unsigned int keylen) +{ + struct starfive_cryp_ctx *ctx =3D crypto_ahash_ctx(tfm); + unsigned int digestsize =3D crypto_ahash_digestsize(tfm); + unsigned int blocksize; + int ret =3D 0; + + blocksize =3D crypto_tfm_alg_blocksize(crypto_ahash_tfm(tfm)); + crypto_ahash_setkey(ctx->ahash_fbk, key, keylen); + + if (keylen <=3D blocksize) { + memcpy(ctx->key, key, keylen); + ctx->keylen =3D keylen; + } else { + ctx->keylen =3D digestsize; + ret =3D starfive_hash_long_setkey(ctx, key, keylen, "starfive-sm3"); + } + + return ret; +} + +static int starfive_hash_cra_sha224_init(struct crypto_tfm *tfm) +{ + return starfive_hash_cra_init_algs(tfm, NULL, + STARFIVE_HASH_SHA224, + "sha224-generic"); +} + +static int starfive_hash_cra_sha256_init(struct crypto_tfm *tfm) +{ + return starfive_hash_cra_init_algs(tfm, NULL, + STARFIVE_HASH_SHA256, + "sha256-generic"); +} + +static int starfive_hash_cra_sha384_init(struct crypto_tfm *tfm) +{ + return starfive_hash_cra_init_algs(tfm, NULL, + STARFIVE_HASH_SHA384, + "sha384-generic"); +} + +static int starfive_hash_cra_sha512_init(struct crypto_tfm *tfm) +{ + return starfive_hash_cra_init_algs(tfm, NULL, + STARFIVE_HASH_SHA512, + "sha512-generic"); +} + +static int starfive_hash_cra_sm3_init(struct crypto_tfm *tfm) +{ + return starfive_hash_cra_init_algs(tfm, NULL, + STARFIVE_HASH_SM3, + "sm3-generic"); +} + +static int starfive_hash_cra_hmac_sha224_init(struct crypto_tfm *tfm) +{ + return starfive_hash_cra_init_algs(tfm, "sha224", + STARFIVE_HASH_SHA224, + "hmac(sha224-generic)"); +} + +static int starfive_hash_cra_hmac_sha256_init(struct crypto_tfm *tfm) +{ + return starfive_hash_cra_init_algs(tfm, "sha256", + STARFIVE_HASH_SHA256, + "hmac(sha256-generic)"); +} + +static int starfive_hash_cra_hmac_sha384_init(struct crypto_tfm *tfm) +{ + return starfive_hash_cra_init_algs(tfm, "sha384", + STARFIVE_HASH_SHA384, + "hmac(sha384-generic)"); +} + +static int starfive_hash_cra_hmac_sha512_init(struct crypto_tfm *tfm) +{ + return starfive_hash_cra_init_algs(tfm, "sha512", + STARFIVE_HASH_SHA512, + "hmac(sha512-generic)"); +} + +static int starfive_hash_cra_hmac_sm3_init(struct crypto_tfm *tfm) +{ + return starfive_hash_cra_init_algs(tfm, "sm3", + STARFIVE_HASH_SM3, + "hmac(sm3-generic)"); +} + +static struct ahash_alg algs_sha2_sm3[] =3D { +{ + .init =3D starfive_hash_init, + .update =3D starfive_hash_update, + .final =3D starfive_hash_final, + .finup =3D starfive_hash_finup, + .digest =3D starfive_hash_digest, + .export =3D starfive_hash_export, + .import =3D starfive_hash_import, + .halg =3D { + .digestsize =3D SHA224_DIGEST_SIZE, + .statesize =3D sizeof(struct sha256_state), + .base =3D { + .cra_name =3D "sha224", + .cra_driver_name =3D "starfive-sha224", + .cra_priority =3D 200, + .cra_flags =3D CRYPTO_ALG_ASYNC | + CRYPTO_ALG_TYPE_AHASH | + CRYPTO_ALG_NEED_FALLBACK, + .cra_blocksize =3D SHA224_BLOCK_SIZE, + .cra_ctxsize =3D sizeof(struct starfive_cryp_ctx), + .cra_alignmask =3D 3, + .cra_init =3D starfive_hash_cra_sha224_init, + .cra_exit =3D starfive_hash_cra_exit, + .cra_module =3D THIS_MODULE, + } + } +}, +{ + .init =3D starfive_hash_init, + .update =3D starfive_hash_update, + .final =3D starfive_hash_final, + .finup =3D starfive_hash_finup, + .digest =3D starfive_hash_digest, + .export =3D starfive_hash_export, + .import =3D starfive_hash_import, + .setkey =3D starfive_hash224_setkey, + .halg =3D { + .digestsize =3D SHA224_DIGEST_SIZE, + .statesize =3D sizeof(struct sha256_state), + .base =3D { + .cra_name =3D "hmac(sha224)", + .cra_driver_name =3D "starfive-hmac-sha224", + .cra_priority =3D 200, + .cra_flags =3D CRYPTO_ALG_ASYNC | + CRYPTO_ALG_TYPE_AHASH | + CRYPTO_ALG_NEED_FALLBACK, + .cra_blocksize =3D SHA224_BLOCK_SIZE, + .cra_ctxsize =3D sizeof(struct starfive_cryp_ctx), + .cra_alignmask =3D 3, + .cra_init =3D starfive_hash_cra_hmac_sha224_init, + .cra_exit =3D starfive_hash_cra_exit, + .cra_module =3D THIS_MODULE, + } + } +}, +{ + .init =3D starfive_hash_init, + .update =3D starfive_hash_update, + .final =3D starfive_hash_final, + .finup =3D starfive_hash_finup, + .digest =3D starfive_hash_digest, + .export =3D starfive_hash_export, + .import =3D starfive_hash_import, + .halg =3D { + .digestsize =3D SHA256_DIGEST_SIZE, + .statesize =3D sizeof(struct sha256_state), + .base =3D { + .cra_name =3D "sha256", + .cra_driver_name =3D "starfive-sha256", + .cra_priority =3D 200, + .cra_flags =3D CRYPTO_ALG_ASYNC | + CRYPTO_ALG_TYPE_AHASH | + CRYPTO_ALG_NEED_FALLBACK, + .cra_blocksize =3D SHA256_BLOCK_SIZE, + .cra_ctxsize =3D sizeof(struct starfive_cryp_ctx), + .cra_alignmask =3D 3, + .cra_init =3D starfive_hash_cra_sha256_init, + .cra_exit =3D starfive_hash_cra_exit, + .cra_module =3D THIS_MODULE, + } + } +}, +{ + .init =3D starfive_hash_init, + .update =3D starfive_hash_update, + .final =3D starfive_hash_final, + .finup =3D starfive_hash_finup, + .digest =3D starfive_hash_digest, + .export =3D starfive_hash_export, + .import =3D starfive_hash_import, + .setkey =3D starfive_hash256_setkey, + .halg =3D { + .digestsize =3D SHA256_DIGEST_SIZE, + .statesize =3D sizeof(struct sha256_state), + .base =3D { + .cra_name =3D "hmac(sha256)", + .cra_driver_name =3D "starfive-hmac-sha256", + .cra_priority =3D 200, + .cra_flags =3D CRYPTO_ALG_ASYNC | + CRYPTO_ALG_TYPE_AHASH | + CRYPTO_ALG_NEED_FALLBACK, + .cra_blocksize =3D SHA256_BLOCK_SIZE, + .cra_ctxsize =3D sizeof(struct starfive_cryp_ctx), + .cra_alignmask =3D 3, + .cra_init =3D starfive_hash_cra_hmac_sha256_init, + .cra_exit =3D starfive_hash_cra_exit, + .cra_module =3D THIS_MODULE, + } + } +}, +{ + .init =3D starfive_hash_init, + .update =3D starfive_hash_update, + .final =3D starfive_hash_final, + .finup =3D starfive_hash_finup, + .digest =3D starfive_hash_digest, + .export =3D starfive_hash_export, + .import =3D starfive_hash_import, + .halg =3D { + .digestsize =3D SHA384_DIGEST_SIZE, + .statesize =3D sizeof(struct sha512_state), + .base =3D { + .cra_name =3D "sha384", + .cra_driver_name =3D "starfive-sha384", + .cra_priority =3D 200, + .cra_flags =3D CRYPTO_ALG_ASYNC | + CRYPTO_ALG_TYPE_AHASH | + CRYPTO_ALG_NEED_FALLBACK, + .cra_blocksize =3D SHA384_BLOCK_SIZE, + .cra_ctxsize =3D sizeof(struct starfive_cryp_ctx), + .cra_alignmask =3D 3, + .cra_init =3D starfive_hash_cra_sha384_init, + .cra_exit =3D starfive_hash_cra_exit, + .cra_module =3D THIS_MODULE, + } + } +}, +{ + .init =3D starfive_hash_init, + .update =3D starfive_hash_update, + .final =3D starfive_hash_final, + .finup =3D starfive_hash_finup, + .digest =3D starfive_hash_digest, + .setkey =3D starfive_hash384_setkey, + .export =3D starfive_hash_export, + .import =3D starfive_hash_import, + .halg =3D { + .digestsize =3D SHA384_DIGEST_SIZE, + .statesize =3D sizeof(struct sha512_state), + .base =3D { + .cra_name =3D "hmac(sha384)", + .cra_driver_name =3D "starfive-hmac-sha384", + .cra_priority =3D 200, + .cra_flags =3D CRYPTO_ALG_ASYNC | + CRYPTO_ALG_TYPE_AHASH | + CRYPTO_ALG_NEED_FALLBACK, + .cra_blocksize =3D SHA384_BLOCK_SIZE, + .cra_ctxsize =3D sizeof(struct starfive_cryp_ctx), + .cra_alignmask =3D 3, + .cra_init =3D starfive_hash_cra_hmac_sha384_init, + .cra_exit =3D starfive_hash_cra_exit, + .cra_module =3D THIS_MODULE, + } + } +}, +{ + .init =3D starfive_hash_init, + .update =3D starfive_hash_update, + .final =3D starfive_hash_final, + .finup =3D starfive_hash_finup, + .digest =3D starfive_hash_digest, + .export =3D starfive_hash_export, + .import =3D starfive_hash_import, + .halg =3D { + .digestsize =3D SHA512_DIGEST_SIZE, + .statesize =3D sizeof(struct sha512_state), + .base =3D { + .cra_name =3D "sha512", + .cra_driver_name =3D "starfive-sha512", + .cra_priority =3D 200, + .cra_flags =3D CRYPTO_ALG_ASYNC | + CRYPTO_ALG_TYPE_AHASH, + .cra_blocksize =3D SHA512_BLOCK_SIZE, + .cra_ctxsize =3D sizeof(struct starfive_cryp_ctx), + .cra_alignmask =3D 3, + .cra_init =3D starfive_hash_cra_sha512_init, + .cra_exit =3D starfive_hash_cra_exit, + .cra_module =3D THIS_MODULE, + } + } +}, +{ + .init =3D starfive_hash_init, + .update =3D starfive_hash_update, + .final =3D starfive_hash_final, + .finup =3D starfive_hash_finup, + .digest =3D starfive_hash_digest, + .setkey =3D starfive_hash512_setkey, + .export =3D starfive_hash_export, + .import =3D starfive_hash_import, + .halg =3D { + .digestsize =3D SHA512_DIGEST_SIZE, + .statesize =3D sizeof(struct sha512_state), + .base =3D { + .cra_name =3D "hmac(sha512)", + .cra_driver_name =3D "starfive-hmac-sha512", + .cra_priority =3D 200, + .cra_flags =3D CRYPTO_ALG_ASYNC | + CRYPTO_ALG_TYPE_AHASH | + CRYPTO_ALG_NEED_FALLBACK, + .cra_blocksize =3D SHA512_BLOCK_SIZE, + .cra_ctxsize =3D sizeof(struct starfive_cryp_ctx), + .cra_alignmask =3D 3, + .cra_init =3D starfive_hash_cra_hmac_sha512_init, + .cra_exit =3D starfive_hash_cra_exit, + .cra_module =3D THIS_MODULE, + } + } +}, +{ + .init =3D starfive_hash_init, + .update =3D starfive_hash_update, + .final =3D starfive_hash_final, + .finup =3D starfive_hash_finup, + .digest =3D starfive_hash_digest, + .export =3D starfive_hash_export, + .import =3D starfive_hash_import, + .halg =3D { + .digestsize =3D SM3_DIGEST_SIZE, + .statesize =3D sizeof(struct sm3_state), + .base =3D { + .cra_name =3D "sm3", + .cra_driver_name =3D "starfive-sm3", + .cra_priority =3D 200, + .cra_flags =3D CRYPTO_ALG_ASYNC | + CRYPTO_ALG_TYPE_AHASH | + CRYPTO_ALG_NEED_FALLBACK, + .cra_blocksize =3D SM3_BLOCK_SIZE, + .cra_ctxsize =3D sizeof(struct starfive_cryp_ctx), + .cra_alignmask =3D 3, + .cra_init =3D starfive_hash_cra_sm3_init, + .cra_exit =3D starfive_hash_cra_exit, + .cra_module =3D THIS_MODULE, + } + } +}, +{ + .init =3D starfive_hash_init, + .update =3D starfive_hash_update, + .final =3D starfive_hash_final, + .finup =3D starfive_hash_finup, + .digest =3D starfive_hash_digest, + .setkey =3D starfive_sm3_setkey, + .export =3D starfive_hash_export, + .import =3D starfive_hash_import, + .halg =3D { + .digestsize =3D SM3_DIGEST_SIZE, + .statesize =3D sizeof(struct sm3_state), + .base =3D { + .cra_name =3D "hmac(sm3)", + .cra_driver_name =3D "starfive-hmac-sm3", + .cra_priority =3D 200, + .cra_flags =3D CRYPTO_ALG_ASYNC | + CRYPTO_ALG_TYPE_AHASH | + CRYPTO_ALG_NEED_FALLBACK, + .cra_blocksize =3D SM3_BLOCK_SIZE, + .cra_ctxsize =3D sizeof(struct starfive_cryp_ctx), + .cra_alignmask =3D 3, + .cra_init =3D starfive_hash_cra_hmac_sm3_init, + .cra_exit =3D starfive_hash_cra_exit, + .cra_module =3D THIS_MODULE, + } + } +}, +}; + +int starfive_hash_register_algs(void) +{ + int ret =3D 0; + + ret =3D crypto_register_ahashes(algs_sha2_sm3, ARRAY_SIZE(algs_sha2_sm3)); + + return ret; +} + +void starfive_hash_unregister_algs(void) +{ + crypto_unregister_ahashes(algs_sha2_sm3, ARRAY_SIZE(algs_sha2_sm3)); +} --=20 2.25.1