From nobody Wed Feb 11 17:24:27 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 46AD6C6FD19 for ; Mon, 13 Mar 2023 07:14:29 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229968AbjCMHO1 (ORCPT ); Mon, 13 Mar 2023 03:14:27 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:55406 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229919AbjCMHOS (ORCPT ); Mon, 13 Mar 2023 03:14:18 -0400 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 0E8CC135; Mon, 13 Mar 2023 00:14:15 -0700 (PDT) Received: from pps.filterd (m0279870.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 32D6lMfd026416; Mon, 13 Mar 2023 07:13:48 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding; s=qcppdkim1; bh=arWtPEA0bcJXqwG62AWlaCRZSxo1cNJCkmPGoarEGKM=; b=MgCqYDAbWCz+WOxBkDEghkmo3XPaFljZ1kFuoT6Sx51bG2vu0nw0GxEkKcaIt39pJtsH foxJL2gDnjZ3AXPmVJZ1zeXp2BiZBS4bMdYoSdKYU9o1r47JTpvef1JHqaHYscQ52xxI NNRJbDOvdyFoa+FXQQagcU3qkOZnSOHRY1f9S76MWmdwdzHeRxCDaub6qwh92Cx34txk 0FLBqjnGQHheLj6CsWsd2ZHRQWWk174Fe4Yl5CTUmSiYH8XaIG3V6POTOOwOcCtKEceH yhed6mV5aUUV1wdnW5sMW6I5DViEXGcU4tb+XDCfeyVoOhlFQdbVw9CiSd1oIiV9BIgB jw== Received: from apblrppmta01.qualcomm.com (blr-bdr-fw-01_GlobalNAT_AllZones-Outside.qualcomm.com [103.229.18.19]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 3p8hr2m0f0-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Mon, 13 Mar 2023 07:13:47 +0000 Received: from pps.filterd (APBLRPPMTA01.qualcomm.com [127.0.0.1]) by APBLRPPMTA01.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTP id 32D7Dils032123; Mon, 13 Mar 2023 07:13:44 GMT Received: from pps.reinject (localhost [127.0.0.1]) by APBLRPPMTA01.qualcomm.com (PPS) with ESMTP id 3p8jqkkykb-1; Mon, 13 Mar 2023 07:13:44 +0000 Received: from APBLRPPMTA01.qualcomm.com (APBLRPPMTA01.qualcomm.com [127.0.0.1]) by pps.reinject (8.17.1.5/8.17.1.5) with ESMTP id 32D7DiRs032114; Mon, 13 Mar 2023 07:13:44 GMT Received: from kbajaj-linux.qualcomm.com (kbajaj-linux.qualcomm.com [10.214.66.129]) by APBLRPPMTA01.qualcomm.com (PPS) with ESMTP id 32D7DiSv032113; Mon, 13 Mar 2023 07:13:44 +0000 Received: from kbajaj-linux.qualcomm.com (localhost [127.0.0.1]) by kbajaj-linux.qualcomm.com (Postfix) with ESMTP id A384FD8; Mon, 13 Mar 2023 12:43:43 +0530 (IST) From: Komal Bajaj To: Rob Herring , Bjorn Andersson , Konrad Dybcio , Abel Vesa , Rishabh Bhatnagar , Prakash Ranjan , Krzysztof Kozlowski , Andy Gross Cc: Komal Bajaj , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org Subject: [PATCH 1/5] soc: qcom: llcc: Refactor llcc driver to support multiple configuration Date: Mon, 13 Mar 2023 12:43:21 +0530 Message-Id: <20230313071325.21605-2-quic_kbajaj@quicinc.com> X-Mailer: git-send-email 2.39.1 In-Reply-To: <20230313071325.21605-1-quic_kbajaj@quicinc.com> References: <20230313071325.21605-1-quic_kbajaj@quicinc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-QCInternal: smtphost X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: 9WYrD_pm8AlTCFZlDNk2o9LvuOp6fs8T X-Proofpoint-GUID: 9WYrD_pm8AlTCFZlDNk2o9LvuOp6fs8T X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.254,Aquarius:18.0.942,Hydra:6.0.573,FMLib:17.11.170.22 definitions=2023-03-12_10,2023-03-10_01,2023-02-09_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 mlxscore=0 phishscore=0 adultscore=0 priorityscore=1501 clxscore=1015 impostorscore=0 spamscore=0 bulkscore=0 suspectscore=0 mlxlogscore=999 malwarescore=0 lowpriorityscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2212070000 definitions=main-2303130058 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Refactor driver to support multiple configuration for llcc on a target. Signed-off-by: Komal Bajaj --- drivers/soc/qcom/llcc-qcom.c | 191 ++++++++++++++++++++--------------- 1 file changed, 112 insertions(+), 79 deletions(-) diff --git a/drivers/soc/qcom/llcc-qcom.c b/drivers/soc/qcom/llcc-qcom.c index 23ce2f78c4ed..00699a0c047e 100644 --- a/drivers/soc/qcom/llcc-qcom.c +++ b/drivers/soc/qcom/llcc-qcom.c @@ -416,92 +416,125 @@ static const u32 llcc_v2_1_reg_offset[] =3D { [LLCC_COMMON_STATUS0] =3D 0x0003400c, }; =20 -static const struct qcom_llcc_config sc7180_cfg =3D { - .sct_data =3D sc7180_data, - .size =3D ARRAY_SIZE(sc7180_data), - .need_llcc_cfg =3D true, - .reg_offset =3D llcc_v1_reg_offset, - .edac_reg_offset =3D &llcc_v1_edac_reg_offset, +static const struct qcom_llcc_config sc7180_cfg[] =3D { + { + .sct_data =3D sc7180_data, + .size =3D ARRAY_SIZE(sc7180_data), + .need_llcc_cfg =3D true, + .reg_offset =3D llcc_v1_reg_offset, + .edac_reg_offset =3D &llcc_v1_edac_reg_offset, + }, + { }, }; =20 -static const struct qcom_llcc_config sc7280_cfg =3D { - .sct_data =3D sc7280_data, - .size =3D ARRAY_SIZE(sc7280_data), - .need_llcc_cfg =3D true, - .reg_offset =3D llcc_v1_reg_offset, - .edac_reg_offset =3D &llcc_v1_edac_reg_offset, +static const struct qcom_llcc_config sc7280_cfg[] =3D { + { + .sct_data =3D sc7280_data, + .size =3D ARRAY_SIZE(sc7280_data), + .need_llcc_cfg =3D true, + .reg_offset =3D llcc_v1_reg_offset, + .edac_reg_offset =3D &llcc_v1_edac_reg_offset, + }, + { }, }; =20 -static const struct qcom_llcc_config sc8180x_cfg =3D { - .sct_data =3D sc8180x_data, - .size =3D ARRAY_SIZE(sc8180x_data), - .need_llcc_cfg =3D true, - .reg_offset =3D llcc_v1_reg_offset, - .edac_reg_offset =3D &llcc_v1_edac_reg_offset, +static const struct qcom_llcc_config sc8180x_cfg[] =3D { + { + .sct_data =3D sc8180x_data, + .size =3D ARRAY_SIZE(sc8180x_data), + .need_llcc_cfg =3D true, + .reg_offset =3D llcc_v1_reg_offset, + .edac_reg_offset =3D &llcc_v1_edac_reg_offset, + }, + { }, }; =20 -static const struct qcom_llcc_config sc8280xp_cfg =3D { - .sct_data =3D sc8280xp_data, - .size =3D ARRAY_SIZE(sc8280xp_data), - .need_llcc_cfg =3D true, - .reg_offset =3D llcc_v1_reg_offset, - .edac_reg_offset =3D &llcc_v1_edac_reg_offset, +static const struct qcom_llcc_config sc8280xp_cfg[] =3D { + { + .sct_data =3D sc8280xp_data, + .size =3D ARRAY_SIZE(sc8280xp_data), + .need_llcc_cfg =3D true, + .reg_offset =3D llcc_v1_reg_offset, + .edac_reg_offset =3D &llcc_v1_edac_reg_offset, + }, + { }, }; =20 -static const struct qcom_llcc_config sdm845_cfg =3D { - .sct_data =3D sdm845_data, - .size =3D ARRAY_SIZE(sdm845_data), - .need_llcc_cfg =3D false, - .reg_offset =3D llcc_v1_reg_offset, - .edac_reg_offset =3D &llcc_v1_edac_reg_offset, +static const struct qcom_llcc_config sdm845_cfg[] =3D { + { + .sct_data =3D sdm845_data, + .size =3D ARRAY_SIZE(sdm845_data), + .need_llcc_cfg =3D false, + .reg_offset =3D llcc_v1_reg_offset, + .edac_reg_offset =3D &llcc_v1_edac_reg_offset, + }, + { }, }; =20 -static const struct qcom_llcc_config sm6350_cfg =3D { - .sct_data =3D sm6350_data, - .size =3D ARRAY_SIZE(sm6350_data), - .need_llcc_cfg =3D true, - .reg_offset =3D llcc_v1_reg_offset, - .edac_reg_offset =3D &llcc_v1_edac_reg_offset, +static const struct qcom_llcc_config sm6350_cfg[] =3D { + { + .sct_data =3D sm6350_data, + .size =3D ARRAY_SIZE(sm6350_data), + .need_llcc_cfg =3D true, + .reg_offset =3D llcc_v1_reg_offset, + .edac_reg_offset =3D &llcc_v1_edac_reg_offset, + }, + { }, }; =20 -static const struct qcom_llcc_config sm8150_cfg =3D { - .sct_data =3D sm8150_data, - .size =3D ARRAY_SIZE(sm8150_data), - .need_llcc_cfg =3D true, - .reg_offset =3D llcc_v1_reg_offset, - .edac_reg_offset =3D &llcc_v1_edac_reg_offset, +static const struct qcom_llcc_config sm8150_cfg[] =3D { + { + .sct_data =3D sm8150_data, + .size =3D ARRAY_SIZE(sm8150_data), + .need_llcc_cfg =3D true, + .reg_offset =3D llcc_v1_reg_offset, + .edac_reg_offset =3D &llcc_v1_edac_reg_offset, + }, + { }, }; =20 -static const struct qcom_llcc_config sm8250_cfg =3D { - .sct_data =3D sm8250_data, - .size =3D ARRAY_SIZE(sm8250_data), - .need_llcc_cfg =3D true, - .reg_offset =3D llcc_v1_reg_offset, - .edac_reg_offset =3D &llcc_v1_edac_reg_offset, +static const struct qcom_llcc_config sm8250_cfg[] =3D { + { + .sct_data =3D sm8250_data, + .size =3D ARRAY_SIZE(sm8250_data), + .need_llcc_cfg =3D true, + .reg_offset =3D llcc_v1_reg_offset, + .edac_reg_offset =3D &llcc_v1_edac_reg_offset, + }, + { }, }; =20 -static const struct qcom_llcc_config sm8350_cfg =3D { - .sct_data =3D sm8350_data, - .size =3D ARRAY_SIZE(sm8350_data), - .need_llcc_cfg =3D true, - .reg_offset =3D llcc_v1_reg_offset, - .edac_reg_offset =3D &llcc_v1_edac_reg_offset, +static const struct qcom_llcc_config sm8350_cfg[] =3D { + { + .sct_data =3D sm8350_data, + .size =3D ARRAY_SIZE(sm8350_data), + .need_llcc_cfg =3D true, + .reg_offset =3D llcc_v1_reg_offset, + .edac_reg_offset =3D &llcc_v1_edac_reg_offset, + }, + { }, }; =20 -static const struct qcom_llcc_config sm8450_cfg =3D { - .sct_data =3D sm8450_data, - .size =3D ARRAY_SIZE(sm8450_data), - .need_llcc_cfg =3D true, - .reg_offset =3D llcc_v2_1_reg_offset, - .edac_reg_offset =3D &llcc_v2_1_edac_reg_offset, +static const struct qcom_llcc_config sm8450_cfg[] =3D { + { + .sct_data =3D sm8450_data, + .size =3D ARRAY_SIZE(sm8450_data), + .need_llcc_cfg =3D true, + .reg_offset =3D llcc_v2_1_reg_offset, + .edac_reg_offset =3D &llcc_v2_1_edac_reg_offset, + }, + { }, }; =20 -static const struct qcom_llcc_config sm8550_cfg =3D { - .sct_data =3D sm8550_data, - .size =3D ARRAY_SIZE(sm8550_data), - .need_llcc_cfg =3D true, - .reg_offset =3D llcc_v2_1_reg_offset, - .edac_reg_offset =3D &llcc_v2_1_edac_reg_offset, +static const struct qcom_llcc_config sm8550_cfg[] =3D { + { + .sct_data =3D sm8550_data, + .size =3D ARRAY_SIZE(sm8550_data), + .need_llcc_cfg =3D true, + .reg_offset =3D llcc_v2_1_reg_offset, + .edac_reg_offset =3D &llcc_v2_1_edac_reg_offset, + }, + { }, }; =20 static struct llcc_drv_data *drv_data =3D (void *) -EPROBE_DEFER; @@ -966,8 +999,8 @@ static int qcom_llcc_probe(struct platform_device *pdev) num_banks >>=3D LLCC_LB_CNT_SHIFT; drv_data->num_banks =3D num_banks; =20 - llcc_cfg =3D cfg->sct_data; - sz =3D cfg->size; + llcc_cfg =3D cfg[0].sct_data; + sz =3D cfg[0].size; =20 for (i =3D 0; i < sz; i++) if (llcc_cfg[i].slice_id > drv_data->max_slices) @@ -1016,17 +1049,17 @@ static int qcom_llcc_probe(struct platform_device *= pdev) } =20 static const struct of_device_id qcom_llcc_of_match[] =3D { - { .compatible =3D "qcom,sc7180-llcc", .data =3D &sc7180_cfg }, - { .compatible =3D "qcom,sc7280-llcc", .data =3D &sc7280_cfg }, - { .compatible =3D "qcom,sc8180x-llcc", .data =3D &sc8180x_cfg }, - { .compatible =3D "qcom,sc8280xp-llcc", .data =3D &sc8280xp_cfg }, - { .compatible =3D "qcom,sdm845-llcc", .data =3D &sdm845_cfg }, - { .compatible =3D "qcom,sm6350-llcc", .data =3D &sm6350_cfg }, - { .compatible =3D "qcom,sm8150-llcc", .data =3D &sm8150_cfg }, - { .compatible =3D "qcom,sm8250-llcc", .data =3D &sm8250_cfg }, - { .compatible =3D "qcom,sm8350-llcc", .data =3D &sm8350_cfg }, - { .compatible =3D "qcom,sm8450-llcc", .data =3D &sm8450_cfg }, - { .compatible =3D "qcom,sm8550-llcc", .data =3D &sm8550_cfg }, + { .compatible =3D "qcom,sc7180-llcc", .data =3D sc7180_cfg }, + { .compatible =3D "qcom,sc7280-llcc", .data =3D sc7280_cfg }, + { .compatible =3D "qcom,sc8180x-llcc", .data =3D sc8180x_cfg }, + { .compatible =3D "qcom,sc8280xp-llcc", .data =3D sc8280xp_cfg }, + { .compatible =3D "qcom,sdm845-llcc", .data =3D sdm845_cfg }, + { .compatible =3D "qcom,sm6350-llcc", .data =3D sm6350_cfg }, + { .compatible =3D "qcom,sm8150-llcc", .data =3D sm8150_cfg }, + { .compatible =3D "qcom,sm8250-llcc", .data =3D sm8250_cfg }, + { .compatible =3D "qcom,sm8350-llcc", .data =3D sm8350_cfg }, + { .compatible =3D "qcom,sm8450-llcc", .data =3D sm8450_cfg }, + { .compatible =3D "qcom,sm8550-llcc", .data =3D sm8550_cfg }, { } }; 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charset="utf-8" Add description for additional nodes needed to support mulitple channel DDR configurations in LLCC. Signed-off-by: Komal Bajaj --- Documentation/devicetree/bindings/arm/msm/qcom,llcc.yaml | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/msm/qcom,llcc.yaml b/Doc= umentation/devicetree/bindings/arm/msm/qcom,llcc.yaml index 38efcad56dbd..9a4a76caf490 100644 --- a/Documentation/devicetree/bindings/arm/msm/qcom,llcc.yaml +++ b/Documentation/devicetree/bindings/arm/msm/qcom,llcc.yaml @@ -37,15 +37,24 @@ properties: items: - description: LLCC base register region - description: LLCC broadcast base register region + - description: Feature register to decide which LLCC configuration + to use, this is optional =20 reg-names: items: - const: llcc_base - const: llcc_broadcast_base + - const: multi_channel_register =20 interrupts: maxItems: 1 =20 + multi-ch-bit-off: + items: + - description: Specifies the offset in bits into the multi_channel_r= egister + and the number of bits used to decide which LLCC conf= iguration + to use + required: - compatible - reg --=20 2.39.1 From nobody Wed Feb 11 17:24:27 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id A42CBC6FD19 for ; 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charset="utf-8" Add LLCC compatible for QDU1000/QRU1000 SoCs. Signed-off-by: Komal Bajaj --- Documentation/devicetree/bindings/arm/msm/qcom,llcc.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/arm/msm/qcom,llcc.yaml b/Doc= umentation/devicetree/bindings/arm/msm/qcom,llcc.yaml index 9a4a76caf490..afb1b84907e0 100644 --- a/Documentation/devicetree/bindings/arm/msm/qcom,llcc.yaml +++ b/Documentation/devicetree/bindings/arm/msm/qcom,llcc.yaml @@ -32,6 +32,7 @@ properties: - qcom,sm8350-llcc - qcom,sm8450-llcc - qcom,sm8550-llcc + - qcom,qdu1000-llcc =20 reg: items: --=20 2.39.1 From nobody Wed Feb 11 17:24:27 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id E5EBDC61DA4 for ; Mon, 13 Mar 2023 07:14:59 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229842AbjCMHO6 (ORCPT ); Mon, 13 Mar 2023 03:14:58 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:55570 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230017AbjCMHOd (ORCPT ); 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charset="utf-8" Add LLCC support for multi channel DDR configurations based off of a feature register. Signed-off-by: Komal Bajaj --- drivers/soc/qcom/llcc-qcom.c | 56 ++++++++++++++++++++++++++++-- include/linux/soc/qcom/llcc-qcom.h | 2 ++ 2 files changed, 55 insertions(+), 3 deletions(-) diff --git a/drivers/soc/qcom/llcc-qcom.c b/drivers/soc/qcom/llcc-qcom.c index 00699a0c047e..696f1f46dd61 100644 --- a/drivers/soc/qcom/llcc-qcom.c +++ b/drivers/soc/qcom/llcc-qcom.c @@ -17,6 +17,7 @@ #include #include #include +#include #include =20 #define ACTIVATE BIT(0) @@ -924,6 +925,40 @@ static int qcom_llcc_cfg_program(struct platform_devic= e *pdev, return ret; } =20 +static int qcom_llcc_get_cfg_index(struct platform_device *pdev, u32 *cfg_= index) +{ + struct device *dev =3D &pdev->dev; + struct resource *ch_res =3D NULL; + + u32 ch_reg_sz; + u32 ch_reg_off; + u32 val; + int ret =3D 0; + + ch_res =3D platform_get_resource_byname(pdev, IORESOURCE_MEM, "multi_chan= nel_register"); + if (ch_res) { + if (of_property_read_u32(dev->of_node, "multi-ch-bit-off", &ch_reg_off))= { + dev_err(&pdev->dev, + "Couldn't get offset for multi channel feature register\n"); + return -ENODEV; + } + if (of_property_read_u32_index(dev->of_node, "multi-ch-bit-off", 1, &ch_= reg_sz)) { + dev_err(&pdev->dev, + "Couldn't get size of multi channel feature register\n"); + return -ENODEV; + } + + if (qcom_scm_io_readl(ch_res->start, &val)) { + dev_err(&pdev->dev, "Couldn't access multi channel feature register\n"); + ret =3D -EINVAL; + } + *cfg_index =3D (val >> ch_reg_off) & ((1 << ch_reg_sz) - 1); + } else + *cfg_index =3D 0; + + return ret; +} + static int qcom_llcc_remove(struct platform_device *pdev) { /* Set the global pointer to a error code to avoid referencing it */ @@ -956,10 +991,13 @@ static int qcom_llcc_probe(struct platform_device *pd= ev) struct device *dev =3D &pdev->dev; int ret, i; struct platform_device *llcc_edac; - const struct qcom_llcc_config *cfg; + const struct qcom_llcc_config *cfg, *entry; const struct llcc_slice_config *llcc_cfg; + u32 sz; + u32 cfg_index; u32 version; + u32 no_of_entries =3D 0; =20 drv_data =3D devm_kzalloc(dev, sizeof(*drv_data), GFP_KERNEL); if (!drv_data) { @@ -999,8 +1037,20 @@ static int qcom_llcc_probe(struct platform_device *pd= ev) num_banks >>=3D LLCC_LB_CNT_SHIFT; drv_data->num_banks =3D num_banks; =20 - llcc_cfg =3D cfg[0].sct_data; - sz =3D cfg[0].size; + ret =3D qcom_llcc_get_cfg_index(pdev, &cfg_index); + if (ret) + goto err; + + for (entry =3D cfg; entry->sct_data; entry++, no_of_entries++) + ; + if (cfg_index >=3D no_of_entries) { + ret =3D -EINVAL; + goto err; + } + + drv_data->cfg_index =3D cfg_index; + llcc_cfg =3D cfg[cfg_index].sct_data; + sz =3D cfg[cfg_index].size; =20 for (i =3D 0; i < sz; i++) if (llcc_cfg[i].slice_id > drv_data->max_slices) diff --git a/include/linux/soc/qcom/llcc-qcom.h b/include/linux/soc/qcom/ll= cc-qcom.h index ad1fd718169d..225891a02f5d 100644 --- a/include/linux/soc/qcom/llcc-qcom.h +++ b/include/linux/soc/qcom/llcc-qcom.h @@ -125,6 +125,7 @@ struct llcc_edac_reg_offset { * @cfg: pointer to the data structure for slice configuration * @edac_reg_offset: Offset of the LLCC EDAC registers * @lock: mutex associated with each slice + * @cfg_index: index of config table if multiple configs present for a tar= get * @cfg_size: size of the config data table * @max_slices: max slices as read from device tree * @num_banks: Number of llcc banks @@ -139,6 +140,7 @@ struct llcc_drv_data { const struct llcc_slice_config *cfg; const struct llcc_edac_reg_offset *edac_reg_offset; struct mutex lock; + u32 cfg_index; u32 cfg_size; u32 max_slices; u32 num_banks; --=20 2.39.1 From nobody Wed Feb 11 17:24:27 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id C33EDC61DA4 for ; Mon, 13 Mar 2023 07:14:54 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230048AbjCMHOq (ORCPT ); Mon, 13 Mar 2023 03:14:46 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:55986 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229988AbjCMHO2 (ORCPT ); Mon, 13 Mar 2023 03:14:28 -0400 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id D386134F7D; Mon, 13 Mar 2023 00:14:21 -0700 (PDT) Received: from pps.filterd (m0279867.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 32D4k1cr003214; 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Mon, 13 Mar 2023 07:13:52 GMT Received: from pps.reinject (localhost [127.0.0.1]) by APBLRPPMTA01.qualcomm.com (PPS) with ESMTP id 3p8jqkkymb-1; Mon, 13 Mar 2023 07:13:52 +0000 Received: from APBLRPPMTA01.qualcomm.com (APBLRPPMTA01.qualcomm.com [127.0.0.1]) by pps.reinject (8.17.1.5/8.17.1.5) with ESMTP id 32D7DqiI032184; Mon, 13 Mar 2023 07:13:52 GMT Received: from kbajaj-linux.qualcomm.com (kbajaj-linux.qualcomm.com [10.214.66.129]) by APBLRPPMTA01.qualcomm.com (PPS) with ESMTP id 32D7DpWk032183; Mon, 13 Mar 2023 07:13:52 +0000 Received: from kbajaj-linux.qualcomm.com (localhost [127.0.0.1]) by kbajaj-linux.qualcomm.com (Postfix) with ESMTP id 1AE17D8; Mon, 13 Mar 2023 12:43:51 +0530 (IST) From: Komal Bajaj To: Rob Herring , Bjorn Andersson , Konrad Dybcio , Abel Vesa , Rishabh Bhatnagar , Prakash Ranjan , Krzysztof Kozlowski , Andy Gross Cc: Komal Bajaj , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org Subject: [PATCH 5/5] soc: qcom: llcc: Add QDU1000 and QRU1000 LLCC support Date: Mon, 13 Mar 2023 12:43:25 +0530 Message-Id: <20230313071325.21605-6-quic_kbajaj@quicinc.com> X-Mailer: git-send-email 2.39.1 In-Reply-To: <20230313071325.21605-1-quic_kbajaj@quicinc.com> References: <20230313071325.21605-1-quic_kbajaj@quicinc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-QCInternal: smtphost X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: HXhlDz34mRU-r-llx61NRfpGSnW4Aygm X-Proofpoint-GUID: HXhlDz34mRU-r-llx61NRfpGSnW4Aygm X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.254,Aquarius:18.0.942,Hydra:6.0.573,FMLib:17.11.170.22 definitions=2023-03-12_10,2023-03-10_01,2023-02-09_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 bulkscore=0 malwarescore=0 spamscore=0 impostorscore=0 mlxlogscore=999 clxscore=1015 priorityscore=1501 mlxscore=0 phishscore=0 adultscore=0 lowpriorityscore=0 suspectscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2212070000 definitions=main-2303130058 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add LLCC configuration data for QDU1000 and QRU1000 SoCs and updating macro name for LLCC_DRE to LLCC_ECC as per the latest specification. Signed-off-by: Komal Bajaj --- drivers/soc/qcom/llcc-qcom.c | 65 +++++++++++++++++++++++++++++- include/linux/soc/qcom/llcc-qcom.h | 2 +- 2 files changed, 65 insertions(+), 2 deletions(-) diff --git a/drivers/soc/qcom/llcc-qcom.c b/drivers/soc/qcom/llcc-qcom.c index 696f1f46dd61..c2c05fcf1f7b 100644 --- a/drivers/soc/qcom/llcc-qcom.c +++ b/drivers/soc/qcom/llcc-qcom.c @@ -188,7 +188,7 @@ static const struct llcc_slice_config sc8280xp_data[] = =3D { { LLCC_MMUHWT, 13, 1024, 1, 1, 0xfff, 0x0, 0, 0, 0, 0, 1, 0 }, { LLCC_DISP, 16, 6144, 1, 1, 0xfff, 0x0, 0, 0, 0, 1, 0, 0 }, { LLCC_AUDHW, 22, 2048, 1, 1, 0xfff, 0x0, 0, 0, 0, 1, 0, 0 }, - { LLCC_DRE, 26, 1024, 1, 1, 0xfff, 0x0, 0, 0, 0, 1, 0, 0 }, + { LLCC_ECC, 26, 1024, 1, 1, 0xfff, 0x0, 0, 0, 0, 1, 0, 0 }, { LLCC_CVP, 28, 512, 3, 1, 0xfff, 0x0, 0, 0, 0, 1, 0, 0 }, { LLCC_APTCM, 30, 1024, 3, 1, 0x0, 0x1, 1, 0, 0, 1, 0, 0 }, { LLCC_WRCACHE, 31, 1024, 1, 1, 0xfff, 0x0, 0, 0, 0, 0, 1, 0 }, @@ -351,6 +351,36 @@ static const struct llcc_slice_config sm8550_data[] = =3D { {LLCC_VIDVSP, 28, 256, 4, 1, 0xFFFFFF, 0x0, 0, 0, 0, 0, 0, 0, 0, 0, = 0, 0, 0, 0, 0, 0, 0, }, }; =20 +static const struct llcc_slice_config qdu1000_data_2ch[] =3D { + {LLCC_MDMHPGRW, 7, 512, 1, 1, 0xFFF, 0x0, 0, 0, 0, 1, 0, 0, 0 }, + {LLCC_MODHW, 9, 256, 1, 1, 0xFFF, 0x0, 0, 0, 0, 1, 0, 0, 0 }, + {LLCC_MDMPNG, 21, 256, 0, 1, 0x3, 0x0, 0, 0, 0, 1, 0, 0, 0 }, + {LLCC_ECC, 26, 512, 3, 1, 0xFFC, 0x0, 0, 0, 0, 0, 1, 0, 0 }, + {LLCC_MODPE, 29, 256, 1, 1, 0xFFF, 0x0, 0, 0, 0, 1, 0, 0, 0 }, + {LLCC_APTCM, 30, 256, 3, 1, 0x0, 0xC, 1, 0, 0, 1, 0, 0, 0 }, + {LLCC_WRCACHE, 31, 128, 1, 1, 0x3, 0x0, 0, 0, 0, 0, 1, 0, 0 }, +}; + +static const struct llcc_slice_config qdu1000_data_4ch[] =3D { + {LLCC_MDMHPGRW, 7, 1024, 1, 1, 0xFFF, 0x0, 0, 0, 0, 1, 0, 0, 0 }, + {LLCC_MODHW, 9, 512, 1, 1, 0xFFF, 0x0, 0, 0, 0, 1, 0, 0, 0 }, + {LLCC_MDMPNG, 21, 512, 0, 1, 0x3, 0x0, 0, 0, 0, 1, 0, 0, 0 }, + {LLCC_ECC, 26, 1024, 3, 1, 0xFFC, 0x0, 0, 0, 0, 0, 1, 0, 0 }, + {LLCC_MODPE, 29, 512, 1, 1, 0xFFF, 0x0, 0, 0, 0, 1, 0, 0, 0 }, + {LLCC_APTCM, 30, 512, 3, 1, 0x0, 0xC, 1, 0, 0, 1, 0, 0, 0 }, + {LLCC_WRCACHE, 31, 256, 1, 1, 0x3, 0x0, 0, 0, 0, 0, 1, 0, 0 }, +}; + +static const struct llcc_slice_config qdu1000_data_8ch[] =3D { + {LLCC_MDMHPGRW, 7, 2048, 1, 1, 0xFFF, 0x0, 0, 0, 0, 1, 0, 0, 0 }, + {LLCC_MODHW, 9, 1024, 1, 1, 0xFFF, 0x0, 0, 0, 0, 1, 0, 0, 0 }, + {LLCC_MDMPNG, 21, 1024, 0, 1, 0x3, 0x0, 0, 0, 0, 1, 0, 0, 0 }, + {LLCC_ECC, 26, 2048, 3, 1, 0xFFC, 0x0, 0, 0, 0, 0, 1, 0, 0 }, + {LLCC_MODPE, 29, 1024, 1, 1, 0xFFF, 0x0, 0, 0, 0, 1, 0, 0, 0 }, + {LLCC_APTCM, 30, 1024, 3, 1, 0x0, 0xC, 1, 0, 0, 1, 0, 0, 0 }, + {LLCC_WRCACHE, 31, 512, 1, 1, 0x3, 0x0, 0, 0, 0, 0, 1, 0, 0 }, +}; + static const struct llcc_edac_reg_offset llcc_v1_edac_reg_offset =3D { .trp_ecc_error_status0 =3D 0x20344, .trp_ecc_error_status1 =3D 0x20348, @@ -538,6 +568,38 @@ static const struct qcom_llcc_config sm8550_cfg[] =3D { { }, }; =20 +static const struct qcom_llcc_config qdu1000_cfg[] =3D { + { + .sct_data =3D qdu1000_data_8ch, + .size =3D ARRAY_SIZE(qdu1000_data_8ch), + .need_llcc_cfg =3D true, + .reg_offset =3D llcc_v2_1_reg_offset, + .edac_reg_offset =3D &llcc_v2_1_edac_reg_offset, + }, + { + .sct_data =3D qdu1000_data_4ch, + .size =3D ARRAY_SIZE(qdu1000_data_4ch), + .need_llcc_cfg =3D true, + .reg_offset =3D llcc_v2_1_reg_offset, + .edac_reg_offset =3D &llcc_v2_1_edac_reg_offset, + }, + { + .sct_data =3D qdu1000_data_4ch, + .size =3D ARRAY_SIZE(qdu1000_data_4ch), + .need_llcc_cfg =3D true, + .reg_offset =3D llcc_v2_1_reg_offset, + .edac_reg_offset =3D &llcc_v2_1_edac_reg_offset, + }, + { + .sct_data =3D qdu1000_data_2ch, + .size =3D ARRAY_SIZE(qdu1000_data_2ch), + .need_llcc_cfg =3D true, + .reg_offset =3D llcc_v2_1_reg_offset, + .edac_reg_offset =3D &llcc_v2_1_edac_reg_offset, + }, + { }, +}; + static struct llcc_drv_data *drv_data =3D (void *) -EPROBE_DEFER; =20 /** @@ -1110,6 +1172,7 @@ static const struct of_device_id qcom_llcc_of_match[]= =3D { { .compatible =3D "qcom,sm8350-llcc", .data =3D sm8350_cfg }, { .compatible =3D "qcom,sm8450-llcc", .data =3D sm8450_cfg }, { .compatible =3D "qcom,sm8550-llcc", .data =3D sm8550_cfg }, + { .compatible =3D "qcom,qdu1000-llcc", .data =3D qdu1000_cfg}, { } }; MODULE_DEVICE_TABLE(of, qcom_llcc_of_match); diff --git a/include/linux/soc/qcom/llcc-qcom.h b/include/linux/soc/qcom/ll= cc-qcom.h index 225891a02f5d..150b2836c8b9 100644 --- a/include/linux/soc/qcom/llcc-qcom.h +++ b/include/linux/soc/qcom/llcc-qcom.h @@ -30,7 +30,7 @@ #define LLCC_NPU 23 #define LLCC_WLHW 24 #define LLCC_PIMEM 25 -#define LLCC_DRE 26 +#define LLCC_ECC 26 #define LLCC_CVP 28 #define LLCC_MODPE 29 #define LLCC_APTCM 30 --=20 2.39.1