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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 12 Mar 2023 00:45:08.5796 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 066bc509-0af3-455d-defd-08db229307a0 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT053.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS7PR12MB6071 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Document the compatible for AMD Pensando Elba SoC boards. Signed-off-by: Brad Larson Reviewed-by: Rob Herring Reported-by: kernel test robot --- .../devicetree/bindings/arm/amd,pensando.yaml | 26 +++++++++++++++++++ 1 file changed, 26 insertions(+) create mode 100644 Documentation/devicetree/bindings/arm/amd,pensando.yaml diff --git a/Documentation/devicetree/bindings/arm/amd,pensando.yaml b/Docu= mentation/devicetree/bindings/arm/amd,pensando.yaml new file mode 100644 index 000000000000..e5c2591834a8 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/amd,pensando.yaml @@ -0,0 +1,26 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/amd,pensando.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: AMD Pensando SoC Platforms + +maintainers: + - Brad Larson + +properties: + $nodename: + const: "/" + compatible: + oneOf: + + - description: Boards with Pensando Elba SoC + items: + - enum: + - amd,pensando-elba-ortano + - const: amd,pensando-elba + +additionalProperties: true + +... --=20 2.17.1 From nobody Wed Feb 11 17:20:54 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id E3C96C7618A for ; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 12 Mar 2023 00:45:18.7414 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: fa615764-cb66-4861-d3ca-08db22930db1 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT054.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN0PR12MB6199 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" AMD Pensando Elba ARM 64-bit SoC is integrated with this IP and explicitly controls byte-lane enables. Signed-off-by: Brad Larson Reported-by: kernel test robot --- v11 changes: - Remove resets description and reset-names - Add descriptions for amd,pensando-elba-sd4hc reg items v10 changes: - Move reset-names property definition next to existing resets prop - Move allOf to the bottom and set resets/reset-names required only for pen= sando - Fix reg maxItems for existing, must be 1 v9 changes: - Add reset-names and resets properties - Add if/then on property amd,pensando-elba-sd4hc to set reg property values for minItems and maxItems --- .../devicetree/bindings/mmc/cdns,sdhci.yaml | 28 ++++++++++++++++--- 1 file changed, 24 insertions(+), 4 deletions(-) diff --git a/Documentation/devicetree/bindings/mmc/cdns,sdhci.yaml b/Docume= ntation/devicetree/bindings/mmc/cdns,sdhci.yaml index adacd0535c14..3c511c02e8a6 100644 --- a/Documentation/devicetree/bindings/mmc/cdns,sdhci.yaml +++ b/Documentation/devicetree/bindings/mmc/cdns,sdhci.yaml @@ -9,19 +9,18 @@ title: Cadence SD/SDIO/eMMC Host Controller (SD4HC) maintainers: - Masahiro Yamada =20 -allOf: - - $ref: mmc-controller.yaml - properties: compatible: items: - enum: + - amd,pensando-elba-sd4hc - microchip,mpfs-sd4hc - socionext,uniphier-sd4hc - const: cdns,sd4hc =20 reg: - maxItems: 1 + minItems: 1 + maxItems: 2 =20 interrupts: maxItems: 1 @@ -120,6 +119,27 @@ required: - interrupts - clocks =20 +allOf: + - $ref: mmc-controller.yaml + - if: + properties: + compatible: + contains: + const: amd,pensando-elba-sd4hc + then: + properties: + reg: + items: + - description: Host controller registers + - description: Elba byte-lane enable register for writes + required: + - resets + else: + properties: + resets: false + reg: + maxItems: 1 + unevaluatedProperties: false =20 examples: --=20 2.17.1 From nobody Wed Feb 11 17:20:54 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3FEC2C7618A for ; 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Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C Received: from SATLEXMB04.amd.com (165.204.84.17) by DM6NAM11FT030.mail.protection.outlook.com (10.13.172.146) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.6178.22 via Frontend Transport; Sun, 12 Mar 2023 00:45:27 +0000 Received: from platform-dev1.pensando.io (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.34; Sat, 11 Mar 2023 18:45:24 -0600 From: Brad Larson To: CC: , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , Subject: [PATCH v11 03/15] dt-bindings: spi: cdns: Add compatible for AMD Pensando Elba SoC Date: Sat, 11 Mar 2023 16:44:33 -0800 Message-ID: <20230312004445.15913-4-blarson@amd.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230312004445.15913-1-blarson@amd.com> References: <20230312004445.15913-1-blarson@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DM6NAM11FT030:EE_|SA3PR12MB7832:EE_ X-MS-Office365-Filtering-Correlation-Id: a4fc0ee2-d8a1-4df6-e7dc-08db22931317 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 12 Mar 2023 00:45:27.8146 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: a4fc0ee2-d8a1-4df6-e7dc-08db22931317 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT030.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SA3PR12MB7832 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Document the cadence qspi controller compatible for AMD Pensando Elba SoC boards. The Elba qspi fifo size is 1024. Signed-off-by: Brad Larson Reported-by: kernel test robot Reviewed-by: Krzysztof Kozlowski --- v11 changes: - Removed redundant if/then for amd,pensando-elba-qspi v10 changes: - Fix cdns,fifo-depth, only amd,pensando-elba-qspi is 1024 bytes v9 changes: - Add 1024 to cdns,fifo-depth property to resolve dtbs_check error --- .../bindings/spi/cdns,qspi-nor.yaml | 19 +++++++++++++++++-- 1 file changed, 17 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/spi/cdns,qspi-nor.yaml b/Doc= umentation/devicetree/bindings/spi/cdns,qspi-nor.yaml index 5c01db128be0..6e67de9da293 100644 --- a/Documentation/devicetree/bindings/spi/cdns,qspi-nor.yaml +++ b/Documentation/devicetree/bindings/spi/cdns,qspi-nor.yaml @@ -20,11 +20,28 @@ allOf: required: - power-domains =20 + - if: + properties: + compatible: + contains: + const: amd,pensando-elba-qspi + then: + properties: + cdns,fifo-depth: + enum: [ 128, 256, 1024 ] + default: 1024 + else: + properties: + cdns,fifo-depth: + enum: [ 128, 256 ] + default: 128 + properties: compatible: oneOf: - items: - enum: + - amd,pensando-elba-qspi - ti,k2g-qspi - ti,am654-ospi - intel,lgm-qspi @@ -48,8 +65,6 @@ properties: description: Size of the data FIFO in words. $ref: /schemas/types.yaml#/definitions/uint32 - enum: [ 128, 256 ] - default: 128 =20 cdns,fifo-width: $ref: /schemas/types.yaml#/definitions/uint32 --=20 2.17.1 From nobody Wed Feb 11 17:20:54 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id C46A0C74A5B for ; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 12 Mar 2023 00:45:35.5538 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 4eef2146-42f8-443d-cfb7-08db229317b4 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT022.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CY8PR12MB7196 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The AMD Pensando Elba SoC has integrated the DW APB SPI Controller Signed-off-by: Brad Larson Reviewed-by: Krzysztof Kozlowski Reported-by: kernel test robot Reviewed-by: Serge Semin --- v10 changes: - Move definition of amd,pensando-elba-syscon into properties with a better description - Add amd,pensando-elba-syscon: false for non elba designs v9 changes: - Define property amd,pensando-elba-syscon - Move compatible amd,pensando-elba-spi ahead of baikal,bt1-ssi --- .../bindings/spi/snps,dw-apb-ssi.yaml | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.yaml b/D= ocumentation/devicetree/bindings/spi/snps,dw-apb-ssi.yaml index a132b5fc56e0..2383d6497b1e 100644 --- a/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.yaml +++ b/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.yaml @@ -37,6 +37,17 @@ allOf: else: required: - interrupts + - if: + properties: + compatible: + contains: + const: amd,pensando-elba-spi + then: + required: + - amd,pensando-elba-syscon + else: + properties: + amd,pensando-elba-syscon: false =20 properties: compatible: @@ -63,6 +74,8 @@ properties: const: intel,keembay-ssi - description: Intel Thunder Bay SPI Controller const: intel,thunderbay-ssi + - description: AMD Pensando Elba SoC SPI Controller + const: amd,pensando-elba-spi - description: Baikal-T1 SPI Controller const: baikal,bt1-ssi - description: Baikal-T1 System Boot SPI Controller @@ -136,6 +149,12 @@ properties: of the designware controller, and the upper limit is also subject to controller configuration. =20 + amd,pensando-elba-syscon: + $ref: /schemas/types.yaml#/definitions/phandle-array + description: | + Block address to control SPI chip-selects. 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Sun, 12 Mar 2023 00:45:46 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 165.204.84.17) smtp.mailfrom=amd.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=amd.com; Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C Received: from SATLEXMB04.amd.com (165.204.84.17) by DM6NAM11FT014.mail.protection.outlook.com (10.13.173.132) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.6178.24 via Frontend Transport; Sun, 12 Mar 2023 00:45:46 +0000 Received: from platform-dev1.pensando.io (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.34; Sat, 11 Mar 2023 18:45:42 -0600 From: Brad Larson To: CC: , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , Subject: [PATCH v11 05/15] dt-bindings: soc: amd: amd,pensando-elba-ctrl: Add Pensando SoC Controller Date: Sat, 11 Mar 2023 16:44:35 -0800 Message-ID: <20230312004445.15913-6-blarson@amd.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230312004445.15913-1-blarson@amd.com> References: <20230312004445.15913-1-blarson@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DM6NAM11FT014:EE_|SJ0PR12MB5664:EE_ X-MS-Office365-Filtering-Correlation-Id: 1b892207-3379-423f-a68c-08db22931e06 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 12 Mar 2023 00:45:46.1408 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 1b892207-3379-423f-a68c-08db22931e06 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT014.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SJ0PR12MB5664 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Support the AMD Pensando Elba SoC Controller which is a SPI connected device providing a miscellaneous set of essential board control/status registers. This device is present in all Pensando SoC based designs. Signed-off-by: Brad Larson Reported-by: kernel test robot Reviewed-by: Krzysztof Kozlowski --- v11 changes: - Fixed the compatible which should have stayed as 'amd,pensando-elba-ctrl', the commit message, and the filename - Reference spi-peripheral-props - Delete spi-max-frequency=20 - Remove num-cs from example v10 changes: - Property renamed to amd,pensando-ctrl - Driver is renamed and moved to soc/drivers/amd affecting binding - Delete cs property, driver handles device node creation from parent num-cs fixing schema reg error in a different way v9 changes: - Instead of four nodes, one per chip-select, a single node is used with reset-cells in the parent. - No MFD API is used anymore in the driver so it made sense to move this to drivers/spi. - This driver is common for all Pensando SoC based designs so changed the name to pensando-sr.c to not make it Elba SoC specific. - Added property cs for the chip-select number which is used by the driver to create /dev/pensr0. --- .../soc/amd/amd,pensando-elba-ctrl.yaml | 58 +++++++++++++++++++ 1 file changed, 58 insertions(+) create mode 100644 Documentation/devicetree/bindings/soc/amd/amd,pensando-= elba-ctrl.yaml diff --git a/Documentation/devicetree/bindings/soc/amd/amd,pensando-elba-ct= rl.yaml b/Documentation/devicetree/bindings/soc/amd/amd,pensando-elba-ctrl.= yaml new file mode 100644 index 000000000000..f1d3ed4f519b --- /dev/null +++ b/Documentation/devicetree/bindings/soc/amd/amd,pensando-elba-ctrl.yaml @@ -0,0 +1,58 @@ +# SPDX-License-Identifier: (GPL-2.0-only or BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/soc/amd/amd,pensando-elba-ctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: AMD Pensando Elba SoC Controller + +description: + The AMD Pensando Elba SoC Controller is a SPI connected device with esse= ntial + control/status registers accessed on chip select 0. This device is pres= ent + in all Pensando SoC based designs. + +maintainers: + - Brad Larson + +properties: + compatible: + enum: + - amd,pensando-elba-ctrl + + reg: + maxItems: 1 + + '#reset-cells': + const: 1 + + interrupts: + maxItems: 1 + +required: + - compatible + - '#reset-cells' + +allOf: + - $ref: /schemas/spi/spi-peripheral-props.yaml# + +unevaluatedProperties: false + +examples: + - | + #include + + spi { + #address-cells =3D <1>; + #size-cells =3D <0>; + + system-controller@0 { + compatible =3D "amd,pensando-elba-ctrl"; + reg =3D <0>; + spi-max-frequency =3D <12000000>; + interrupt-parent =3D <&porta>; + interrupts =3D <0 IRQ_TYPE_LEVEL_LOW>; + #reset-cells =3D <1>; + }; + }; + +... --=20 2.17.1 From nobody Wed Feb 11 17:20:54 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 41108C7618D for ; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 12 Mar 2023 00:45:55.0900 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 83cd7601-2a07-4a1a-cd64-08db22932359 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT110.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SA1PR12MB8698 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add entry for AMD PENSANDO maintainer and files Signed-off-by: Brad Larson Reported-by: kernel test robot --- MAINTAINERS | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index 8d5bc223f305..5e39def215c9 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -1875,6 +1875,15 @@ N: allwinner N: sun[x456789]i N: sun[25]0i =20 +ARM/AMD PENSANDO ARM64 ARCHITECTURE +M: Brad Larson +L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) +S: Supported +F: Documentation/devicetree/bindings/*/amd,pensando* +F: Documentation/devicetree/bindings/soc/amd/amd,pensando* +F: arch/arm64/boot/dts/amd/elba* +F: drivers/soc/amd/ + ARM/Amlogic Meson SoC CLOCK FRAMEWORK M: Neil Armstrong M: Jerome Brunet --=20 2.17.1 From nobody Wed Feb 11 17:20:54 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id A1365C74A5B for ; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 12 Mar 2023 00:46:00.8167 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 1b7b532b-0554-4ea2-a10f-08db229326c3 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT021.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SN7PR12MB6768 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add ARCH_PENSANDO configuration option for AMD Pensando SoC based platforms. Signed-off-by: Brad Larson Reported-by: kernel test robot --- arch/arm64/Kconfig.platforms | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/arch/arm64/Kconfig.platforms b/arch/arm64/Kconfig.platforms index 89a0b13b058d..3510daaabe27 100644 --- a/arch/arm64/Kconfig.platforms +++ b/arch/arm64/Kconfig.platforms @@ -236,6 +236,18 @@ config ARCH_NPCM General support for NPCM8xx BMC (Arbel). Nuvoton NPCM8xx BMC based on the Cortex A35. =20 +config ARCH_PENSANDO + bool "AMD Pensando Platforms" + help + This enables support for the ARMv8 based AMD Pensando SoC + family to include the Elba SoC. + + AMD Pensando SoCs support a range of Distributed Services + Cards in PCIe format installed into servers. The Elba + SoC includes 16 A-72 CPU cores, 144 programmable P4 + cores for a minimal latency/jitter datapath, and network + interfaces up to 200 Gb/s. + config ARCH_QCOM bool "Qualcomm Platforms" select GPIOLIB --=20 2.17.1 From nobody Wed Feb 11 17:20:54 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 173D0C74A4B for ; Sun, 12 Mar 2023 00:47:03 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229814AbjCLArC (ORCPT ); Sat, 11 Mar 2023 19:47:02 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:39586 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229756AbjCLAq7 (ORCPT ); Sat, 11 Mar 2023 19:46:59 -0500 Received: from NAM11-CO1-obe.outbound.protection.outlook.com (mail-co1nam11on2080.outbound.protection.outlook.com [40.107.220.80]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 9ED663CE02; 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Sun, 12 Mar 2023 00:46:09 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 165.204.84.17) smtp.mailfrom=amd.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=amd.com; Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C Received: from SATLEXMB04.amd.com (165.204.84.17) by DM6NAM11FT029.mail.protection.outlook.com (10.13.173.23) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.6178.22 via Frontend Transport; Sun, 12 Mar 2023 00:46:08 +0000 Received: from platform-dev1.pensando.io (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.34; Sat, 11 Mar 2023 18:46:05 -0600 From: Brad Larson To: CC: , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , Subject: [PATCH v11 08/15] arm64: dts: Add AMD Pensando Elba SoC support Date: Sat, 11 Mar 2023 16:44:38 -0800 Message-ID: <20230312004445.15913-9-blarson@amd.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230312004445.15913-1-blarson@amd.com> References: <20230312004445.15913-1-blarson@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DM6NAM11FT029:EE_|IA1PR12MB8261:EE_ X-MS-Office365-Filtering-Correlation-Id: c08f16d6-b926-4acc-551a-08db22932b8f X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 12 Mar 2023 00:46:08.8626 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: c08f16d6-b926-4acc-551a-08db22932b8f X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT029.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: IA1PR12MB8261 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add AMD Pensando common and Elba SoC specific device nodes Signed-off-by: Brad Larson Reported-by: kernel test robot --- v11 changes: - Delete reset-names - Fix spi0 compatible to be specific 'amd,pensando-elba-ctrl' v9 changes: - Single node for spi0 system-controller and squash the reset-controller child into parent --- arch/arm64/boot/dts/amd/Makefile | 1 + arch/arm64/boot/dts/amd/elba-16core.dtsi | 189 +++++++++++++++++ arch/arm64/boot/dts/amd/elba-asic-common.dtsi | 80 ++++++++ arch/arm64/boot/dts/amd/elba-asic.dts | 28 +++ arch/arm64/boot/dts/amd/elba-flash-parts.dtsi | 106 ++++++++++ arch/arm64/boot/dts/amd/elba.dtsi | 192 ++++++++++++++++++ 6 files changed, 596 insertions(+) create mode 100644 arch/arm64/boot/dts/amd/elba-16core.dtsi create mode 100644 arch/arm64/boot/dts/amd/elba-asic-common.dtsi create mode 100644 arch/arm64/boot/dts/amd/elba-asic.dts create mode 100644 arch/arm64/boot/dts/amd/elba-flash-parts.dtsi create mode 100644 arch/arm64/boot/dts/amd/elba.dtsi diff --git a/arch/arm64/boot/dts/amd/Makefile b/arch/arm64/boot/dts/amd/Mak= efile index 68103a8b0ef5..8502cc2afbc5 100644 --- a/arch/arm64/boot/dts/amd/Makefile +++ b/arch/arm64/boot/dts/amd/Makefile @@ -1,2 +1,3 @@ # SPDX-License-Identifier: GPL-2.0 +dtb-$(CONFIG_ARCH_PENSANDO) +=3D elba-asic.dtb dtb-$(CONFIG_ARCH_SEATTLE) +=3D amd-overdrive-rev-b0.dtb amd-overdrive-rev= -b1.dtb diff --git a/arch/arm64/boot/dts/amd/elba-16core.dtsi b/arch/arm64/boot/dts= /amd/elba-16core.dtsi new file mode 100644 index 000000000000..37aadd442db8 --- /dev/null +++ b/arch/arm64/boot/dts/amd/elba-16core.dtsi @@ -0,0 +1,189 @@ +// SPDX-License-Identifier: (GPL-2.0-only or BSD-2-Clause) +/* + * Copyright 2020-2022 Advanced Micro Devices, Inc. + */ + +/ { + cpus { + #address-cells =3D <2>; + #size-cells =3D <0>; + + cpu-map { + cluster0 { + core0 { cpu =3D <&cpu0>; }; + core1 { cpu =3D <&cpu1>; }; + core2 { cpu =3D <&cpu2>; }; + core3 { cpu =3D <&cpu3>; }; + }; + + cluster1 { + core0 { cpu =3D <&cpu4>; }; + core1 { cpu =3D <&cpu5>; }; + core2 { cpu =3D <&cpu6>; }; + core3 { cpu =3D <&cpu7>; }; + }; + + cluster2 { + core0 { cpu =3D <&cpu8>; }; + core1 { cpu =3D <&cpu9>; }; + core2 { cpu =3D <&cpu10>; }; + core3 { cpu =3D <&cpu11>; }; + }; + + cluster3 { + core0 { cpu =3D <&cpu12>; }; + core1 { cpu =3D <&cpu13>; }; + core2 { cpu =3D <&cpu14>; }; + core3 { cpu =3D <&cpu15>; }; + }; + }; + + /* CLUSTER 0 */ + cpu0: cpu@0 { + device_type =3D "cpu"; + compatible =3D "arm,cortex-a72"; + reg =3D <0 0x0>; + next-level-cache =3D <&l2_0>; + enable-method =3D "psci"; + }; + + cpu1: cpu@1 { + device_type =3D "cpu"; + compatible =3D "arm,cortex-a72"; + reg =3D <0 0x1>; + next-level-cache =3D <&l2_0>; + enable-method =3D "psci"; + }; + + cpu2: cpu@2 { + device_type =3D "cpu"; + compatible =3D "arm,cortex-a72"; + reg =3D <0 0x2>; + next-level-cache =3D <&l2_0>; + enable-method =3D "psci"; + }; + + cpu3: cpu@3 { + device_type =3D "cpu"; + compatible =3D "arm,cortex-a72"; + reg =3D <0 0x3>; + next-level-cache =3D <&l2_0>; + enable-method =3D "psci"; + }; + + l2_0: l2-cache0 { + compatible =3D "cache"; + }; + + /* CLUSTER 1 */ + cpu4: cpu@100 { + device_type =3D "cpu"; + compatible =3D "arm,cortex-a72"; + reg =3D <0 0x100>; + next-level-cache =3D <&l2_1>; + enable-method =3D "psci"; + }; + + cpu5: cpu@101 { + device_type =3D "cpu"; + compatible =3D "arm,cortex-a72"; + reg =3D <0 0x101>; + next-level-cache =3D <&l2_1>; + enable-method =3D "psci"; + }; + + cpu6: cpu@102 { + device_type =3D "cpu"; + compatible =3D "arm,cortex-a72"; + reg =3D <0 0x102>; + next-level-cache =3D <&l2_1>; + enable-method =3D "psci"; + }; + + cpu7: cpu@103 { + device_type =3D "cpu"; + compatible =3D "arm,cortex-a72"; + reg =3D <0 0x103>; + next-level-cache =3D <&l2_1>; + enable-method =3D "psci"; + }; + + l2_1: l2-cache1 { + compatible =3D "cache"; + }; + + /* CLUSTER 2 */ + cpu8: cpu@200 { + device_type =3D "cpu"; + compatible =3D "arm,cortex-a72"; + reg =3D <0 0x200>; + next-level-cache =3D <&l2_2>; + enable-method =3D "psci"; + }; + + cpu9: cpu@201 { + device_type =3D "cpu"; + compatible =3D "arm,cortex-a72"; + reg =3D <0 0x201>; + next-level-cache =3D <&l2_2>; + enable-method =3D "psci"; + }; + + cpu10: cpu@202 { + device_type =3D "cpu"; + compatible =3D "arm,cortex-a72"; + reg =3D <0 0x202>; + next-level-cache =3D <&l2_2>; + enable-method =3D "psci"; + }; + + cpu11: cpu@203 { + device_type =3D "cpu"; + compatible =3D "arm,cortex-a72"; + reg =3D <0 0x203>; + next-level-cache =3D <&l2_2>; + enable-method =3D "psci"; + }; + + l2_2: l2-cache2 { + compatible =3D "cache"; + }; + + /* CLUSTER 3 */ + cpu12: cpu@300 { + device_type =3D "cpu"; + compatible =3D "arm,cortex-a72"; + reg =3D <0 0x300>; + next-level-cache =3D <&l2_3>; + enable-method =3D "psci"; + }; + + cpu13: cpu@301 { + device_type =3D "cpu"; + compatible =3D "arm,cortex-a72"; + reg =3D <0 0x301>; + next-level-cache =3D <&l2_3>; + enable-method =3D "psci"; + }; + + cpu14: cpu@302 { + device_type =3D "cpu"; + compatible =3D "arm,cortex-a72"; + reg =3D <0 0x302>; + next-level-cache =3D <&l2_3>; + enable-method =3D "psci"; + }; + + cpu15: cpu@303 { + device_type =3D "cpu"; + compatible =3D "arm,cortex-a72"; + reg =3D <0 0x303>; + next-level-cache =3D <&l2_3>; + enable-method =3D "psci"; + }; + + l2_3: l2-cache3 { + compatible =3D "cache"; + }; + }; +}; diff --git a/arch/arm64/boot/dts/amd/elba-asic-common.dtsi b/arch/arm64/boo= t/dts/amd/elba-asic-common.dtsi new file mode 100644 index 000000000000..1a615788f54e --- /dev/null +++ b/arch/arm64/boot/dts/amd/elba-asic-common.dtsi @@ -0,0 +1,80 @@ +// SPDX-License-Identifier: (GPL-2.0-only or BSD-2-Clause) +/* + * Copyright 2020-2022 Advanced Micro Devices, Inc. + */ + +&ahb_clk { + clock-frequency =3D <400000000>; +}; + +&emmc_clk { + clock-frequency =3D <200000000>; +}; + +&flash_clk { + clock-frequency =3D <400000000>; +}; + +&ref_clk { + clock-frequency =3D <156250000>; +}; + +&qspi { + status =3D "okay"; + + flash0: flash@0 { + compatible =3D "jedec,spi-nor"; + reg =3D <0>; + spi-max-frequency =3D <40000000>; + spi-rx-bus-width =3D <2>; + m25p,fast-read; + cdns,read-delay =3D <0>; + cdns,tshsl-ns =3D <0>; + cdns,tsd2d-ns =3D <0>; + cdns,tchsh-ns =3D <0>; + cdns,tslch-ns =3D <0>; + }; +}; + +&gpio0 { + status =3D "okay"; +}; + +&emmc { + bus-width =3D <8>; + cap-mmc-hw-reset; + resets =3D <&rstc 0>; + status =3D "okay"; +}; + +&wdt0 { + status =3D "okay"; +}; + +&i2c0 { + clock-frequency =3D <100000>; + status =3D "okay"; + + rtc@51 { + compatible =3D "nxp,pcf85263"; + reg =3D <0x51>; + }; +}; + +&spi0 { + #address-cells =3D <1>; + #size-cells =3D <0>; + num-cs =3D <4>; + cs-gpios =3D <0>, <0>, <&porta 1 GPIO_ACTIVE_LOW>, + <&porta 7 GPIO_ACTIVE_LOW>; + status =3D "okay"; + + rstc: system-controller@0 { + compatible =3D "amd,pensando-elba-ctrl"; + reg =3D <0>; + spi-max-frequency =3D <12000000>; + interrupt-parent =3D <&porta>; + interrupts =3D <0 IRQ_TYPE_LEVEL_LOW>; + #reset-cells =3D <1>; + }; +}; diff --git a/arch/arm64/boot/dts/amd/elba-asic.dts b/arch/arm64/boot/dts/am= d/elba-asic.dts new file mode 100644 index 000000000000..c3f4da2f7449 --- /dev/null +++ b/arch/arm64/boot/dts/amd/elba-asic.dts @@ -0,0 +1,28 @@ +// SPDX-License-Identifier: (GPL-2.0-only or BSD-2-Clause) +/* + * Device Tree file for AMD Pensando Elba Board. + * + * Copyright 2020-2022 Advanced Micro Devices, Inc. + */ + +/dts-v1/; + +#include "elba.dtsi" +#include "elba-16core.dtsi" +#include "elba-asic-common.dtsi" +#include "elba-flash-parts.dtsi" + +/ { + model =3D "AMD Pensando Elba Board"; + compatible =3D "amd,pensando-elba-ortano", "amd,pensando-elba"; + + aliases { + serial0 =3D &uart0; + spi0 =3D &spi0; + spi1 =3D &qspi; + }; + + chosen { + stdout-path =3D "serial0:115200n8"; + }; +}; diff --git a/arch/arm64/boot/dts/amd/elba-flash-parts.dtsi b/arch/arm64/boo= t/dts/amd/elba-flash-parts.dtsi new file mode 100644 index 000000000000..734893fef2c3 --- /dev/null +++ b/arch/arm64/boot/dts/amd/elba-flash-parts.dtsi @@ -0,0 +1,106 @@ +// SPDX-License-Identifier: (GPL-2.0-only or BSD-2-Clause) +/* + * Copyright 2020-2022 Advanced Micro Devices, Inc. + */ + +&flash0 { + partitions { + compatible =3D "fixed-partitions"; + #address-cells =3D <1>; + #size-cells =3D <1>; + partition@0 { + label =3D "flash"; + reg =3D <0x10000 0xfff0000>; + }; + + partition@f0000 { + label =3D "golduenv"; + reg =3D <0xf0000 0x10000>; + }; + + partition@100000 { + label =3D "boot0"; + reg =3D <0x100000 0x80000>; + }; + + partition@180000 { + label =3D "golduboot"; + reg =3D <0x180000 0x200000>; + }; + + partition@380000 { + label =3D "brdcfg0"; + reg =3D <0x380000 0x10000>; + }; + + partition@390000 { + label =3D "brdcfg1"; + reg =3D <0x390000 0x10000>; + }; + + partition@400000 { + label =3D "goldfw"; + reg =3D <0x400000 0x3c00000>; + }; + + partition@4010000 { + label =3D "fwmap"; + reg =3D <0x4010000 0x20000>; + }; + + partition@4030000 { + label =3D "fwsel"; + reg =3D <0x4030000 0x20000>; + }; + + partition@4090000 { + label =3D "bootlog"; + reg =3D <0x4090000 0x20000>; + }; + + partition@40b0000 { + label =3D "panicbuf"; + reg =3D <0x40b0000 0x20000>; + }; + + partition@40d0000 { + label =3D "uservars"; + reg =3D <0x40d0000 0x20000>; + }; + + partition@4200000 { + label =3D "uboota"; + reg =3D <0x4200000 0x400000>; + }; + + partition@4600000 { + label =3D "ubootb"; + reg =3D <0x4600000 0x400000>; + }; + + partition@4a00000 { + label =3D "mainfwa"; + reg =3D <0x4a00000 0x1000000>; + }; + + partition@5a00000 { + label =3D "mainfwb"; + reg =3D <0x5a00000 0x1000000>; + }; + + partition@6a00000 { + label =3D "diaguboot"; + reg =3D <0x6a00000 0x400000>; + }; + + partition@8000000 { + label =3D "diagfw"; + reg =3D <0x8000000 0x7fe0000>; + }; + + partition@ffe0000 { + label =3D "ubootenv"; + reg =3D <0xffe0000 0x10000>; + }; + }; +}; diff --git a/arch/arm64/boot/dts/amd/elba.dtsi b/arch/arm64/boot/dts/amd/el= ba.dtsi new file mode 100644 index 000000000000..285d776aa67b --- /dev/null +++ b/arch/arm64/boot/dts/amd/elba.dtsi @@ -0,0 +1,192 @@ +// SPDX-License-Identifier: (GPL-2.0-only or BSD-2-Clause) +/* + * Copyright 2020-2022 Advanced Micro Devices, Inc. + */ + +#include +#include "dt-bindings/interrupt-controller/arm-gic.h" + +/ { + model =3D "Elba ASIC Board"; + compatible =3D "amd,pensando-elba"; + interrupt-parent =3D <&gic>; + #address-cells =3D <2>; + #size-cells =3D <2>; + + dma-coherent; + + ahb_clk: oscillator0 { + compatible =3D "fixed-clock"; + #clock-cells =3D <0>; + }; + + emmc_clk: oscillator2 { + compatible =3D "fixed-clock"; + #clock-cells =3D <0>; + }; + + flash_clk: oscillator3 { + compatible =3D "fixed-clock"; + #clock-cells =3D <0>; + }; + + ref_clk: oscillator4 { + compatible =3D "fixed-clock"; + #clock-cells =3D <0>; + }; + + psci { + compatible =3D "arm,psci-0.2"; + method =3D "smc"; + }; + + timer { + compatible =3D "arm,armv8-timer"; + interrupts =3D , + , + , + ; + }; + + pmu { + compatible =3D "arm,cortex-a72-pmu"; + interrupts =3D ; + }; + + soc: soc { + compatible =3D "simple-bus"; + #address-cells =3D <2>; + #size-cells =3D <2>; + ranges; + + i2c0: i2c@400 { + compatible =3D "snps,designware-i2c"; + reg =3D <0x0 0x400 0x0 0x100>; + clocks =3D <&ahb_clk>; + #address-cells =3D <1>; + #size-cells =3D <0>; + i2c-sda-hold-time-ns =3D <480>; + snps,sda-timeout-ms =3D <750>; + interrupts =3D ; + status =3D "disabled"; + }; + + wdt0: watchdog@1400 { + compatible =3D "snps,dw-wdt"; + reg =3D <0x0 0x1400 0x0 0x100>; + clocks =3D <&ahb_clk>; + interrupts =3D ; + status =3D "disabled"; + }; + + qspi: spi@2400 { + compatible =3D "amd,pensando-elba-qspi", "cdns,qspi-nor"; + reg =3D <0x0 0x2400 0x0 0x400>, + <0x0 0x7fff0000 0x0 0x1000>; + #address-cells =3D <1>; + #size-cells =3D <0>; + interrupts =3D ; + clocks =3D <&flash_clk>; + cdns,fifo-depth =3D <1024>; + cdns,fifo-width =3D <4>; + cdns,trigger-address =3D <0x7fff0000>; + status =3D "disabled"; + }; + + spi0: spi@2800 { + compatible =3D "amd,pensando-elba-spi"; + reg =3D <0x0 0x2800 0x0 0x100>; + #address-cells =3D <1>; + #size-cells =3D <0>; + amd,pensando-elba-syscon =3D <&syscon>; + clocks =3D <&ahb_clk>; + interrupts =3D ; + num-cs =3D <2>; + status =3D "disabled"; + }; + + gpio0: gpio@4000 { + compatible =3D "snps,dw-apb-gpio"; + reg =3D <0x0 0x4000 0x0 0x78>; + #address-cells =3D <1>; + #size-cells =3D <0>; + status =3D "disabled"; + + porta: gpio-port@0 { + compatible =3D "snps,dw-apb-gpio-port"; + reg =3D <0>; + gpio-controller; + #gpio-cells =3D <2>; + ngpios =3D <8>; + interrupts =3D ; + interrupt-controller; + interrupt-parent =3D <&gic>; + #interrupt-cells =3D <2>; + }; + + portb: gpio-port@1 { + compatible =3D "snps,dw-apb-gpio-port"; + reg =3D <1>; + gpio-controller; + #gpio-cells =3D <2>; + ngpios =3D <8>; + }; + }; + + uart0: serial@4800 { + compatible =3D "ns16550a"; + reg =3D <0x0 0x4800 0x0 0x100>; + clocks =3D <&ref_clk>; + interrupts =3D ; + reg-shift =3D <2>; + reg-io-width =3D <4>; + }; + + gic: interrupt-controller@800000 { + compatible =3D "arm,gic-v3"; + reg =3D <0x0 0x800000 0x0 0x200000>, /* GICD */ + <0x0 0xa00000 0x0 0x200000>, /* GICR */ + <0x0 0x60000000 0x0 0x2000>, /* GICC */ + <0x0 0x60010000 0x0 0x1000>, /* GICH */ + <0x0 0x60020000 0x0 0x2000>; /* GICV */ + #address-cells =3D <2>; + #size-cells =3D <2>; + #interrupt-cells =3D <3>; + ranges; + interrupt-controller; + interrupts =3D ; + + /* + * Elba specific pre-ITS is enabled using the + * existing property socionext,synquacer-pre-its + */ + gic_its: msi-controller@820000 { + compatible =3D "arm,gic-v3-its"; + reg =3D <0x0 0x820000 0x0 0x10000>; + msi-controller; + #msi-cells =3D <1>; + socionext,synquacer-pre-its =3D + <0xc00000 0x1000000>; + }; + }; + + emmc: mmc@30440000 { + compatible =3D "amd,pensando-elba-sd4hc", "cdns,sd4hc"; + reg =3D <0x0 0x30440000 0x0 0x10000>, + <0x0 0x30480044 0x0 0x4>; /* byte-lane ctrl */ + clocks =3D <&emmc_clk>; + interrupts =3D ; + cdns,phy-input-delay-sd-highspeed =3D <0x4>; + cdns,phy-input-delay-legacy =3D <0x4>; + cdns,phy-input-delay-sd-uhs-sdr50 =3D <0x6>; + cdns,phy-input-delay-sd-uhs-ddr50 =3D <0x16>; + mmc-ddr-1_8v; + status =3D "disabled"; + }; + + syscon: syscon@307c0000 { + compatible =3D "amd,pensando-elba-syscon", "syscon"; + reg =3D <0x0 0x307c0000 0x0 0x3000>; + }; + }; +}; --=20 2.17.1 From nobody Wed Feb 11 17:20:54 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id F0352C7618A for ; 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Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C Received: from SATLEXMB04.amd.com (165.204.84.17) by DM6NAM11FT029.mail.protection.outlook.com (10.13.173.23) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.6178.22 via Frontend Transport; Sun, 12 Mar 2023 00:46:17 +0000 Received: from platform-dev1.pensando.io (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.34; Sat, 11 Mar 2023 18:46:13 -0600 From: Brad Larson To: CC: , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , Subject: [PATCH v11 09/15] spi: cadence-quadspi: Add compatible for AMD Pensando Elba SoC Date: Sat, 11 Mar 2023 16:44:39 -0800 Message-ID: <20230312004445.15913-10-blarson@amd.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230312004445.15913-1-blarson@amd.com> References: <20230312004445.15913-1-blarson@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DM6NAM11FT029:EE_|SA1PR12MB6920:EE_ X-MS-Office365-Filtering-Correlation-Id: 3b2bde4f-5c07-4c96-5fb6-08db229330e5 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 12 Mar 2023 00:46:17.7995 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 3b2bde4f-5c07-4c96-5fb6-08db229330e5 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT029.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SA1PR12MB6920 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The AMD Pensando Elba SoC has the Cadence QSPI controller integrated. The quirk CQSPI_NEEDS_APB_AHB_HAZARD_WAR is added and if enabled a dummy readback from the controller is performed to ensure synchronization. Signed-off-by: Brad Larson Reported-by: kernel test robot --- v9 changes: - Rebase to linux-next 6.2.0-rc1 --- drivers/spi/spi-cadence-quadspi.c | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/drivers/spi/spi-cadence-quadspi.c b/drivers/spi/spi-cadence-qu= adspi.c index 64b6a460d739..ad82d2ab3442 100644 --- a/drivers/spi/spi-cadence-quadspi.c +++ b/drivers/spi/spi-cadence-quadspi.c @@ -40,6 +40,7 @@ #define CQSPI_SUPPORT_EXTERNAL_DMA BIT(2) #define CQSPI_NO_SUPPORT_WR_COMPLETION BIT(3) #define CQSPI_SLOW_SRAM BIT(4) +#define CQSPI_NEEDS_APB_AHB_HAZARD_WAR BIT(5) =20 /* Capabilities */ #define CQSPI_SUPPORTS_OCTAL BIT(0) @@ -90,6 +91,7 @@ struct cqspi_st { u32 pd_dev_id; bool wr_completion; bool slow_sram; + bool apb_ahb_hazard; }; =20 struct cqspi_driver_platdata { @@ -1004,6 +1006,13 @@ static int cqspi_indirect_write_execute(struct cqspi= _flash_pdata *f_pdata, if (cqspi->wr_delay) ndelay(cqspi->wr_delay); =20 + /* + * If a hazard exists between the APB and AHB interfaces, perform a + * dummy readback from the controller to ensure synchronization. + */ + if (cqspi->apb_ahb_hazard) + readl(reg_base + CQSPI_REG_INDIRECTWR); + while (remaining > 0) { size_t write_words, mod_bytes; =20 @@ -1734,6 +1743,8 @@ static int cqspi_probe(struct platform_device *pdev) cqspi->wr_completion =3D false; if (ddata->quirks & CQSPI_SLOW_SRAM) cqspi->slow_sram =3D true; + if (ddata->quirks & CQSPI_NEEDS_APB_AHB_HAZARD_WAR) + cqspi->apb_ahb_hazard =3D true; =20 if (of_device_is_compatible(pdev->dev.of_node, "xlnx,versal-ospi-1.0")) @@ -1859,6 +1870,10 @@ static const struct cqspi_driver_platdata versal_osp= i =3D { .get_dma_status =3D cqspi_get_versal_dma_status, }; =20 +static const struct cqspi_driver_platdata pensando_cdns_qspi =3D { + .quirks =3D CQSPI_NEEDS_APB_AHB_HAZARD_WAR | CQSPI_DISABLE_DAC_MODE, +}; + static const struct of_device_id cqspi_dt_ids[] =3D { { .compatible =3D "cdns,qspi-nor", @@ -1884,6 +1899,10 @@ static const struct of_device_id cqspi_dt_ids[] =3D { .compatible =3D "intel,socfpga-qspi", .data =3D &socfpga_qspi, }, + { + .compatible =3D "amd,pensando-elba-qspi", + .data =3D &pensando_cdns_qspi, + }, { /* end of table */ } }; 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Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C Received: from SATLEXMB04.amd.com (165.204.84.17) by DM6NAM11FT062.mail.protection.outlook.com (10.13.173.40) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.6178.24 via Frontend Transport; Sun, 12 Mar 2023 00:46:26 +0000 Received: from platform-dev1.pensando.io (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.34; Sat, 11 Mar 2023 18:46:22 -0600 From: Brad Larson To: CC: , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , Subject: [PATCH v11 10/15] spi: dw: Add support for AMD Pensando Elba SoC Date: Sat, 11 Mar 2023 16:44:40 -0800 Message-ID: <20230312004445.15913-11-blarson@amd.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230312004445.15913-1-blarson@amd.com> References: <20230312004445.15913-1-blarson@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DM6NAM11FT062:EE_|IA0PR12MB7628:EE_ X-MS-Office365-Filtering-Correlation-Id: 44549a0f-6b68-47a2-0aa7-08db22933643 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 12 Mar 2023 00:46:26.7863 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 44549a0f-6b68-47a2-0aa7-08db22933643 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT062.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: IA0PR12MB7628 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The AMD Pensando Elba SoC includes a DW apb_ssi v4 controller with device specific chip-select control. The Elba SoC provides four chip-selects where the native DW IP supports two chip-selects. The Elba DW_SPI instance has two native CS signals that are always overridden. Signed-off-by: Brad Larson Reported-by: kernel test robot Reviewed-by: Serge Semin --- v11 changes: - Simplify dw_spi_elb_init by using syscon_regmap_lookup_by_phandle() v10 changes: - Delete struct dw_spi_elba, use regmap directly in priv v9 changes: - Add use of macros GENMASK() and BIT() - Change ELBA_SPICS_SHIFT() to ELBA_SPICS_OFFSET() --- drivers/spi/spi-dw-mmio.c | 57 +++++++++++++++++++++++++++++++++++++++ 1 file changed, 57 insertions(+) diff --git a/drivers/spi/spi-dw-mmio.c b/drivers/spi/spi-dw-mmio.c index 26c40ea6dd12..5851ecc6e1e9 100644 --- a/drivers/spi/spi-dw-mmio.c +++ b/drivers/spi/spi-dw-mmio.c @@ -53,6 +53,20 @@ struct dw_spi_mscc { void __iomem *spi_mst; /* Not sparx5 */ }; =20 +/* + * Elba SoC does not use ssi, pin override is used for cs 0,1 and + * gpios for cs 2,3 as defined in the device tree. + * + * cs: | 1 0 + * bit: |---3-------2-------1-------0 + * | cs1 cs1_ovr cs0 cs0_ovr + */ +#define ELBA_SPICS_REG 0x2468 +#define ELBA_SPICS_OFFSET(cs) ((cs) << 1) +#define ELBA_SPICS_MASK(cs) (GENMASK(1, 0) << ELBA_SPICS_OFFSET(cs)) +#define ELBA_SPICS_SET(cs, val) \ + ((((val) << 1) | BIT(0)) << ELBA_SPICS_OFFSET(cs)) + /* * The Designware SPI controller (referred to as master in the documentati= on) * automatically deasserts chip select when the tx fifo is empty. The chip @@ -237,6 +251,48 @@ static int dw_spi_canaan_k210_init(struct platform_dev= ice *pdev, return 0; } =20 +static void dw_spi_elba_override_cs(struct regmap *syscon, int cs, int ena= ble) +{ + regmap_update_bits(syscon, ELBA_SPICS_REG, ELBA_SPICS_MASK(cs), + ELBA_SPICS_SET(cs, enable)); +} + +static void dw_spi_elba_set_cs(struct spi_device *spi, bool enable) +{ + struct dw_spi *dws =3D spi_master_get_devdata(spi->master); + struct dw_spi_mmio *dwsmmio =3D container_of(dws, struct dw_spi_mmio, dws= ); + struct regmap *syscon =3D dwsmmio->priv; + u8 cs; + + cs =3D spi->chip_select; + if (cs < 2) + dw_spi_elba_override_cs(syscon, spi->chip_select, enable); + + /* + * The DW SPI controller needs a native CS bit selected to start + * the serial engine. + */ + spi->chip_select =3D 0; + dw_spi_set_cs(spi, enable); + spi->chip_select =3D cs; +} + +static int dw_spi_elba_init(struct platform_device *pdev, + struct dw_spi_mmio *dwsmmio) +{ + struct regmap *syscon; + + syscon =3D syscon_regmap_lookup_by_phandle(dev_of_node(&pdev->dev), + "amd,pensando-elba-syscon"); + if (IS_ERR(syscon)) + return dev_err_probe(&pdev->dev, PTR_ERR(syscon), + "syscon regmap lookup failed\n"); + dwsmmio->priv =3D syscon; + dwsmmio->dws.set_cs =3D dw_spi_elba_set_cs; + + return 0; +} + static int dw_spi_mmio_probe(struct platform_device *pdev) { int (*init_func)(struct platform_device *pdev, @@ -352,6 +408,7 @@ static const struct of_device_id dw_spi_mmio_of_match[]= =3D { { .compatible =3D "intel,thunderbay-ssi", .data =3D dw_spi_intel_init}, { .compatible =3D "microchip,sparx5-spi", dw_spi_mscc_sparx5_init}, { .compatible =3D "canaan,k210-spi", dw_spi_canaan_k210_init}, + { .compatible =3D "amd,pensando-elba-spi", .data =3D dw_spi_elba_init}, { /* end of table */} }; MODULE_DEVICE_TABLE(of, dw_spi_mmio_of_match); --=20 2.17.1 From nobody Wed Feb 11 17:20:54 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id DF7DFC74A4B for ; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 12 Mar 2023 00:46:32.4259 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 69d53063-4179-4c28-cf97-08db2293399a X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT070.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM4PR12MB5747 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" SoCs with device specific Cadence implementation, such as setting byte-enables before the write, need to override writel(). Add a callback where the default is writel() for all existing chips. Signed-off-by: Brad Larson Acked-by: Adrian Hunter Reported-by: kernel test robot --- v10 changes: - The 1st patch adding private writel() is unchanged. The 2nd patch is spl= it into two patches to provide for device specific init in one patch with no effect on existing designs. Then add the pensando support into the next = patch. Then the 4th patch is mmc hardware reset support which is unchanged. v9 changes: - No change to this patch but as some patches are deleted and this is a respin the three successive patches to sdhci-cadence.c are patches 12, 13, and 14 which do the following: 1. Add ability for Cadence specific design to have priv writel(). 2. Add Elba SoC support that requires its own priv writel() for byte-lane control . 3. Add support for mmc hardware reset. --- drivers/mmc/host/sdhci-cadence.c | 18 +++++++++++++----- 1 file changed, 13 insertions(+), 5 deletions(-) diff --git a/drivers/mmc/host/sdhci-cadence.c b/drivers/mmc/host/sdhci-cade= nce.c index 6f2de54a5987..708d4297f241 100644 --- a/drivers/mmc/host/sdhci-cadence.c +++ b/drivers/mmc/host/sdhci-cadence.c @@ -67,6 +67,7 @@ struct sdhci_cdns_phy_param { struct sdhci_cdns_priv { void __iomem *hrs_addr; bool enhanced_strobe; + void (*priv_writel)(struct sdhci_cdns_priv *priv, u32 val, void __iomem *= reg); unsigned int nr_phy_params; struct sdhci_cdns_phy_param phy_params[]; }; @@ -90,6 +91,12 @@ static const struct sdhci_cdns_phy_cfg sdhci_cdns_phy_cf= gs[] =3D { { "cdns,phy-dll-delay-strobe", SDHCI_CDNS_PHY_DLY_STROBE, }, }; =20 +static inline void cdns_writel(struct sdhci_cdns_priv *priv, u32 val, + void __iomem *reg) +{ + writel(val, reg); +} + static int sdhci_cdns_write_phy_reg(struct sdhci_cdns_priv *priv, u8 addr, u8 data) { @@ -104,17 +111,17 @@ static int sdhci_cdns_write_phy_reg(struct sdhci_cdns= _priv *priv, =20 tmp =3D FIELD_PREP(SDHCI_CDNS_HRS04_WDATA, data) | FIELD_PREP(SDHCI_CDNS_HRS04_ADDR, addr); - writel(tmp, reg); + priv->priv_writel(priv, tmp, reg); =20 tmp |=3D SDHCI_CDNS_HRS04_WR; - writel(tmp, reg); + priv->priv_writel(priv, tmp, reg); =20 ret =3D readl_poll_timeout(reg, tmp, tmp & SDHCI_CDNS_HRS04_ACK, 0, 10); if (ret) return ret; =20 tmp &=3D ~SDHCI_CDNS_HRS04_WR; - writel(tmp, reg); + priv->priv_writel(priv, tmp, reg); =20 ret =3D readl_poll_timeout(reg, tmp, !(tmp & SDHCI_CDNS_HRS04_ACK), 0, 10); @@ -191,7 +198,7 @@ static void sdhci_cdns_set_emmc_mode(struct sdhci_cdns_= priv *priv, u32 mode) tmp =3D readl(priv->hrs_addr + SDHCI_CDNS_HRS06); tmp &=3D ~SDHCI_CDNS_HRS06_MODE; tmp |=3D FIELD_PREP(SDHCI_CDNS_HRS06_MODE, mode); - writel(tmp, priv->hrs_addr + SDHCI_CDNS_HRS06); + priv->priv_writel(priv, tmp, priv->hrs_addr + SDHCI_CDNS_HRS06); } =20 static u32 sdhci_cdns_get_emmc_mode(struct sdhci_cdns_priv *priv) @@ -223,7 +230,7 @@ static int sdhci_cdns_set_tune_val(struct sdhci_host *h= ost, unsigned int val) */ for (i =3D 0; i < 2; i++) { tmp |=3D SDHCI_CDNS_HRS06_TUNE_UP; - writel(tmp, reg); + priv->priv_writel(priv, tmp, reg); =20 ret =3D readl_poll_timeout(reg, tmp, !(tmp & SDHCI_CDNS_HRS06_TUNE_UP), @@ -386,6 +393,7 @@ static int sdhci_cdns_probe(struct platform_device *pde= v) priv->nr_phy_params =3D nr_phy_params; priv->hrs_addr =3D host->ioaddr; priv->enhanced_strobe =3D false; + priv->priv_writel =3D cdns_writel; host->ioaddr +=3D SDHCI_CDNS_SRS_BASE; host->mmc_host_ops.hs400_enhanced_strobe =3D sdhci_cdns_hs400_enhanced_strobe; --=20 2.17.1 From nobody Wed Feb 11 17:20:54 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id AFC04C7618A for ; Sun, 12 Mar 2023 00:48:26 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229862AbjCLAsY (ORCPT ); Sat, 11 Mar 2023 19:48:24 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:42970 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229712AbjCLAsV (ORCPT ); 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Sat, 11 Mar 2023 18:46:40 -0600 From: Brad Larson To: CC: , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , Subject: [PATCH v11 12/15] mmc: sdhci-cadence: Support device specific init during probe Date: Sat, 11 Mar 2023 16:44:42 -0800 Message-ID: <20230312004445.15913-13-blarson@amd.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230312004445.15913-1-blarson@amd.com> References: <20230312004445.15913-1-blarson@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DM6NAM11FT072:EE_|MN2PR12MB4407:EE_ X-MS-Office365-Filtering-Correlation-Id: d0b8c91b-7d22-4020-61ee-08db22934052 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: hbssGhvUc5vU4hzozr49hgNmhKxcw9/JcgoHCstWwlck1aUutjYhOQjG/YQfXvI+hxSUDifJN3xPm2Upk9xqW33wYAx2U0dBSsT4t1rVaoGeWivaM92KLYo/OuCSxGrb5v6Ih86jXRX0c2N1AtoorDsCNd8+tJpRPKanQtb1IpCY7C4FZ6Lzi4sz0UdLA2K+be86ZjzB85tIq0MgPmnDVetLCnIO7ruEIm4TGLvYABdjAU07z0PSmX7aH7yioJkwCYgO1+5vvPxxvNVfFrShgecbFyY14EIaxVCQkMj+HCIj6SYnL0cOKjXfmrC9te+IJGJ8FdkHPk8aZdqnNU9L/0W7USAGIhw+EHWcOHO3FSLXA7c/NhphfMgwojfMiFfkmnZsC6td/3a1XwJ0DYcvHjUkiE070v0ZnOxE+YXHWOnp9RJdfuD49iIBhXA0KZ5dU+xFpZreoLGsOF6lniKOl5yuHySZe3f2WuyCqWcM2nNYiHzFs+LRG5NxCNtqX7uNxWRNe220xDrXHGWMr+sqYrH11kkGpML5QgnHyICJciR9tgpfUCH9QDIsW2Rzd6YiTqq0cuwcNJ4RbRcYoBSRNMrB92d1wPJcSOvVXyh9YjJcXG1+aTzUoehC2gy44TSot4EhN/1f7s6VFgg2h2I/fhiKb3J+sO9iQ8/33InAAh2+T58BpRIpYS8+lDz/Bbi0h0UPOjSzFPwWyBPELFQXDdvnSo91dGLKK/byv4HQQCU= X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230025)(4636009)(39860400002)(136003)(376002)(346002)(396003)(451199018)(46966006)(36840700001)(40470700004)(356005)(82310400005)(36756003)(36860700001)(81166007)(82740400003)(40480700001)(40460700003)(4326008)(6916009)(70586007)(70206006)(8676002)(41300700001)(54906003)(478600001)(8936002)(316002)(7416002)(7406005)(2906002)(5660300002)(47076005)(336012)(2616005)(426003)(83380400001)(26005)(16526019)(186003)(1076003)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 12 Mar 2023 00:46:43.6953 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: d0b8c91b-7d22-4020-61ee-08db22934052 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT072.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN2PR12MB4407 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Move struct sdhci_pltfm_data under new struct sdhci_cdns_drv_data. Add an init() into sdhci_cdns_drv_data for platform specific device initialization in the device probe which is not used for existing devices. Signed-off-by: Brad Larson Acked-by: Adrian Hunter Reported-by: kernel test robot --- v10 changes: - New patch to provide for platform specific init() with no change to existing designs. --- drivers/mmc/host/sdhci-cadence.c | 32 +++++++++++++++++++++++--------- 1 file changed, 23 insertions(+), 9 deletions(-) diff --git a/drivers/mmc/host/sdhci-cadence.c b/drivers/mmc/host/sdhci-cade= nce.c index 708d4297f241..c528a25f48b8 100644 --- a/drivers/mmc/host/sdhci-cadence.c +++ b/drivers/mmc/host/sdhci-cadence.c @@ -77,6 +77,11 @@ struct sdhci_cdns_phy_cfg { u8 addr; }; =20 +struct sdhci_cdns_drv_data { + int (*init)(struct platform_device *pdev); + const struct sdhci_pltfm_data pltfm_data; +}; + static const struct sdhci_cdns_phy_cfg sdhci_cdns_phy_cfgs[] =3D { { "cdns,phy-input-delay-sd-highspeed", SDHCI_CDNS_PHY_DLY_SD_HS, }, { "cdns,phy-input-delay-legacy", SDHCI_CDNS_PHY_DLY_SD_DEFAULT, }, @@ -325,13 +330,17 @@ static const struct sdhci_ops sdhci_cdns_ops =3D { .set_uhs_signaling =3D sdhci_cdns_set_uhs_signaling, }; =20 -static const struct sdhci_pltfm_data sdhci_cdns_uniphier_pltfm_data =3D { - .ops =3D &sdhci_cdns_ops, - .quirks2 =3D SDHCI_QUIRK2_PRESET_VALUE_BROKEN, +static const struct sdhci_cdns_drv_data sdhci_cdns_uniphier_drv_data =3D { + .pltfm_data =3D { + .ops =3D &sdhci_cdns_ops, + .quirks2 =3D SDHCI_QUIRK2_PRESET_VALUE_BROKEN, + }, }; =20 -static const struct sdhci_pltfm_data sdhci_cdns_pltfm_data =3D { - .ops =3D &sdhci_cdns_ops, +static const struct sdhci_cdns_drv_data sdhci_cdns_drv_data =3D { + .pltfm_data =3D { + .ops =3D &sdhci_cdns_ops, + }, }; =20 static void sdhci_cdns_hs400_enhanced_strobe(struct mmc_host *mmc, @@ -357,7 +366,7 @@ static void sdhci_cdns_hs400_enhanced_strobe(struct mmc= _host *mmc, static int sdhci_cdns_probe(struct platform_device *pdev) { struct sdhci_host *host; - const struct sdhci_pltfm_data *data; + const struct sdhci_cdns_drv_data *data; struct sdhci_pltfm_host *pltfm_host; struct sdhci_cdns_priv *priv; struct clk *clk; @@ -376,10 +385,10 @@ static int sdhci_cdns_probe(struct platform_device *p= dev) =20 data =3D of_device_get_match_data(dev); if (!data) - data =3D &sdhci_cdns_pltfm_data; + data =3D &sdhci_cdns_drv_data; =20 nr_phy_params =3D sdhci_cdns_phy_param_count(dev->of_node); - host =3D sdhci_pltfm_init(pdev, data, + host =3D sdhci_pltfm_init(pdev, &data->pltfm_data, struct_size(priv, phy_params, nr_phy_params)); if (IS_ERR(host)) { ret =3D PTR_ERR(host); @@ -397,6 +406,11 @@ static int sdhci_cdns_probe(struct platform_device *pd= ev) host->ioaddr +=3D SDHCI_CDNS_SRS_BASE; host->mmc_host_ops.hs400_enhanced_strobe =3D sdhci_cdns_hs400_enhanced_strobe; + if (data->init) { + ret =3D data->init(pdev); + if (ret) + goto free; + } sdhci_enable_v4_mode(host); __sdhci_read_caps(host, &version, NULL, NULL); =20 @@ -461,7 +475,7 @@ static const struct dev_pm_ops sdhci_cdns_pm_ops =3D { static const struct of_device_id sdhci_cdns_match[] =3D { { .compatible =3D "socionext,uniphier-sd4hc", - .data =3D &sdhci_cdns_uniphier_pltfm_data, + .data =3D &sdhci_cdns_uniphier_drv_data, }, { .compatible =3D "cdns,sd4hc" }, { /* sentinel */ } --=20 2.17.1 From nobody Wed Feb 11 17:20:54 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6A679C74A44 for ; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 12 Mar 2023 00:47:08.0776 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: b3fa9872-e447-4905-d0c9-08db22934eda X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT018.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH3PR12MB7546 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add support for AMD Pensando Elba SoC which explicitly controls byte-lane enables on writes. Select MMC_SDHCI_IO_ACCESSORS for MMC_SDHCI_CADENCE which allows Elba SoC sdhci_elba_ops to overwrite the SDHCI IO memory accessors Signed-off-by: Brad Larson Acked-by: Adrian Hunter Reported-by: kernel test robot --- v11 changes: - Remove elba-drv_init() call to platform_get_resource() since that check is done inside devm_platform_ioremap_resource() - Move spin_lock_init() before error check - Remove extra parentheses v10 changes: - Add Elba specific support into this 3rd patch. This builds on the private writel() enabled in patch 1 followed by platform specific init() in patch= 2. - Specify when first used the reason for the spinlock use to order byte-ena= ble prior to write data. --- drivers/mmc/host/Kconfig | 1 + drivers/mmc/host/sdhci-cadence.c | 96 ++++++++++++++++++++++++++++++++ 2 files changed, 97 insertions(+) diff --git a/drivers/mmc/host/Kconfig b/drivers/mmc/host/Kconfig index 4745fe217ade..9f793892123c 100644 --- a/drivers/mmc/host/Kconfig +++ b/drivers/mmc/host/Kconfig @@ -255,6 +255,7 @@ config MMC_SDHCI_CADENCE tristate "SDHCI support for the Cadence SD/SDIO/eMMC controller" depends on MMC_SDHCI_PLTFM depends on OF + select MMC_SDHCI_IO_ACCESSORS help This selects the Cadence SD/SDIO/eMMC driver. =20 diff --git a/drivers/mmc/host/sdhci-cadence.c b/drivers/mmc/host/sdhci-cade= nce.c index c528a25f48b8..c0024d1e69a8 100644 --- a/drivers/mmc/host/sdhci-cadence.c +++ b/drivers/mmc/host/sdhci-cadence.c @@ -66,6 +66,8 @@ struct sdhci_cdns_phy_param { =20 struct sdhci_cdns_priv { void __iomem *hrs_addr; + void __iomem *ctl_addr; /* write control */ + spinlock_t wrlock; /* write lock */ bool enhanced_strobe; void (*priv_writel)(struct sdhci_cdns_priv *priv, u32 val, void __iomem *= reg); unsigned int nr_phy_params; @@ -321,6 +323,89 @@ static void sdhci_cdns_set_uhs_signaling(struct sdhci_= host *host, sdhci_set_uhs_signaling(host, timing); } =20 +/* Elba control register bits [6:3] are byte-lane enables */ +#define ELBA_BYTE_ENABLE_MASK(x) ((x) << 3) + +/* + * The Pensando Elba SoC explicitly controls byte-lane enabling on writes + * which includes writes to the HRS registers. The write lock (wrlock) + * is used to ensure byte-lane enable, using write control (ctl_addr), + * occurs before the data write. + */ +static void elba_priv_writel(struct sdhci_cdns_priv *priv, u32 val, + void __iomem *reg) +{ + unsigned long flags; + + spin_lock_irqsave(&priv->wrlock, flags); + writel(ELBA_BYTE_ENABLE_MASK(0xf), priv->ctl_addr); + writel(val, reg); + spin_unlock_irqrestore(&priv->wrlock, flags); +} + +static void elba_write_l(struct sdhci_host *host, u32 val, int reg) +{ + elba_priv_writel(sdhci_cdns_priv(host), val, host->ioaddr + reg); +} + +static void elba_write_w(struct sdhci_host *host, u16 val, int reg) +{ + struct sdhci_cdns_priv *priv =3D sdhci_cdns_priv(host); + u32 byte_enables; + unsigned long flags; + + byte_enables =3D GENMASK(1, 0) << (reg & 0x3); + spin_lock_irqsave(&priv->wrlock, flags); + writel(ELBA_BYTE_ENABLE_MASK(byte_enables), priv->ctl_addr); + writew(val, host->ioaddr + reg); + spin_unlock_irqrestore(&priv->wrlock, flags); +} + +static void elba_write_b(struct sdhci_host *host, u8 val, int reg) +{ + struct sdhci_cdns_priv *priv =3D sdhci_cdns_priv(host); + u32 byte_enables; + unsigned long flags; + + byte_enables =3D BIT(0) << (reg & 0x3); + spin_lock_irqsave(&priv->wrlock, flags); + writel(ELBA_BYTE_ENABLE_MASK(byte_enables), priv->ctl_addr); + writeb(val, host->ioaddr + reg); + spin_unlock_irqrestore(&priv->wrlock, flags); +} + +static const struct sdhci_ops sdhci_elba_ops =3D { + .write_l =3D elba_write_l, + .write_w =3D elba_write_w, + .write_b =3D elba_write_b, + .set_clock =3D sdhci_set_clock, + .get_timeout_clock =3D sdhci_cdns_get_timeout_clock, + .set_bus_width =3D sdhci_set_bus_width, + .reset =3D sdhci_reset, + .set_uhs_signaling =3D sdhci_cdns_set_uhs_signaling, +}; + +static int elba_drv_init(struct platform_device *pdev) +{ + struct sdhci_host *host =3D platform_get_drvdata(pdev); + struct sdhci_cdns_priv *priv =3D sdhci_cdns_priv(host); + void __iomem *ioaddr; + + host->mmc->caps |=3D MMC_CAP_1_8V_DDR | MMC_CAP_8_BIT_DATA; + spin_lock_init(&priv->wrlock); + + /* Byte-lane control register */ + ioaddr =3D devm_platform_ioremap_resource(pdev, 1); + if (IS_ERR(ioaddr)) + return PTR_ERR(ioaddr); + + priv->ctl_addr =3D ioaddr; + priv->priv_writel =3D elba_priv_writel; + writel(ELBA_BYTE_ENABLE_MASK(0xf), priv->ctl_addr); + + return 0; +} + static const struct sdhci_ops sdhci_cdns_ops =3D { .set_clock =3D sdhci_set_clock, .get_timeout_clock =3D sdhci_cdns_get_timeout_clock, @@ -337,6 +422,13 @@ static const struct sdhci_cdns_drv_data sdhci_cdns_uni= phier_drv_data =3D { }, }; =20 +static const struct sdhci_cdns_drv_data sdhci_elba_drv_data =3D { + .init =3D elba_drv_init, + .pltfm_data =3D { + .ops =3D &sdhci_elba_ops, + }, +}; + static const struct sdhci_cdns_drv_data sdhci_cdns_drv_data =3D { .pltfm_data =3D { .ops =3D &sdhci_cdns_ops, @@ -477,6 +569,10 @@ static const struct of_device_id sdhci_cdns_match[] = =3D { .compatible =3D "socionext,uniphier-sd4hc", .data =3D &sdhci_cdns_uniphier_drv_data, }, + { + .compatible =3D "amd,pensando-elba-sd4hc", + .data =3D &sdhci_elba_drv_data, + }, { .compatible =3D "cdns,sd4hc" }, { /* sentinel */ } }; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 12 Mar 2023 00:47:16.4067 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: e984df04-d42f-4443-bc58-08db229353d1 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT060.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM6PR12MB4332 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add support for mmc hardware reset using a reset-controller that would need to be enabled in the device tree with a supporting driver. The default is disabled for all existing designs. Signed-off-by: Brad Larson Acked-by: Adrian Hunter Reported-by: kernel test robot --- v9 changes: - Previously patch 17/17 - Changed delay after reset_control_assert() from 9 to 3 usec - Renamed sdhci_mmc_hw_reset() to sdhci_cdns_mmc_hw_reset() --- drivers/mmc/host/sdhci-cadence.c | 27 +++++++++++++++++++++++++++ 1 file changed, 27 insertions(+) diff --git a/drivers/mmc/host/sdhci-cadence.c b/drivers/mmc/host/sdhci-cade= nce.c index c0024d1e69a8..0d8db1a54729 100644 --- a/drivers/mmc/host/sdhci-cadence.c +++ b/drivers/mmc/host/sdhci-cadence.c @@ -12,6 +12,7 @@ #include #include #include +#include =20 #include "sdhci-pltfm.h" =20 @@ -70,6 +71,7 @@ struct sdhci_cdns_priv { spinlock_t wrlock; /* write lock */ bool enhanced_strobe; void (*priv_writel)(struct sdhci_cdns_priv *priv, u32 val, void __iomem *= reg); + struct reset_control *rst_hw; unsigned int nr_phy_params; struct sdhci_cdns_phy_param phy_params[]; }; @@ -455,6 +457,22 @@ static void sdhci_cdns_hs400_enhanced_strobe(struct mm= c_host *mmc, SDHCI_CDNS_HRS06_MODE_MMC_HS400); } =20 +static void sdhci_cdns_mmc_hw_reset(struct mmc_host *mmc) +{ + struct sdhci_host *host =3D mmc_priv(mmc); + struct sdhci_cdns_priv *priv =3D sdhci_cdns_priv(host); + + dev_dbg(mmc_dev(host->mmc), "emmc hardware reset\n"); + + reset_control_assert(priv->rst_hw); + /* For eMMC, minimum is 1us but give it 3us for good measure */ + udelay(3); + + reset_control_deassert(priv->rst_hw); + /* For eMMC, minimum is 200us but give it 300us for good measure */ + usleep_range(300, 1000); +} + static int sdhci_cdns_probe(struct platform_device *pdev) { struct sdhci_host *host; @@ -518,6 +536,15 @@ static int sdhci_cdns_probe(struct platform_device *pd= ev) if (ret) goto free; =20 + if (host->mmc->caps & MMC_CAP_HW_RESET) { + priv->rst_hw =3D devm_reset_control_get_optional_exclusive(dev, NULL); + if (IS_ERR(priv->rst_hw)) + return dev_err_probe(mmc_dev(host->mmc), PTR_ERR(priv->rst_hw), + "reset controller error\n"); + if (priv->rst_hw) + host->mmc_host_ops.card_hw_reset =3D sdhci_cdns_mmc_hw_reset; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 12 Mar 2023 00:47:25.2897 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 8af844c2-152f-4bde-cb95-08db2293591a X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT080.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH0PR12MB5235 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The Pensando SoC controller is a SPI connected companion device that is present in all Pensando SoC board designs. The essential board management registers are accessed on chip select 0 with board mgmt IO support accessed using additional chip selects. Signed-off-by: Brad Larson Reported-by: kernel test robot --- v11 changes: - Fix the compatible to be specific 'amd,pensando-elba-ctrl' - Cast arguments flagged with a gcc-12.1.0 warning: Reported-by: kernel test robot Link: https://lore.kernel.org/oe-kbuild-all/202303061526.I8VPcR1M-lkp@intel= .com/ v10 changes: - Different driver implementation specific to this Pensando controller devi= ce. - Moved to soc/amd directory under new name based on guidance. This driver= is of no use to any design other than all Pensando SoC based cards. - Removed use of builtin_driver, can be built as a module. v9 changes: - Previously patch 14/17 - After the change to the device tree node and squashing reset-cells into the parent simplified this to not use any MFD API and move it to drivers/spi/pensando-sr.c. - Change the naming to remove elba since this driver is common for all Pensando SoC designs . - Default yes SPI_PENSANDO_SR for ARCH_PENSANDO --- drivers/soc/Kconfig | 1 + drivers/soc/Makefile | 1 + drivers/soc/amd/Kconfig | 16 ++ drivers/soc/amd/Makefile | 2 + drivers/soc/amd/pensando-ctrl.c | 378 +++++++++++++++++++++++++ include/uapi/linux/amd-pensando-ctrl.h | 30 ++ 6 files changed, 428 insertions(+) create mode 100644 drivers/soc/amd/Kconfig create mode 100644 drivers/soc/amd/Makefile create mode 100644 drivers/soc/amd/pensando-ctrl.c create mode 100644 include/uapi/linux/amd-pensando-ctrl.h diff --git a/drivers/soc/Kconfig b/drivers/soc/Kconfig index 4e176280113a..9e023f74e47c 100644 --- a/drivers/soc/Kconfig +++ b/drivers/soc/Kconfig @@ -2,6 +2,7 @@ menu "SOC (System On Chip) specific Drivers" =20 source "drivers/soc/actions/Kconfig" +source "drivers/soc/amd/Kconfig" source "drivers/soc/amlogic/Kconfig" source "drivers/soc/apple/Kconfig" source "drivers/soc/aspeed/Kconfig" diff --git a/drivers/soc/Makefile b/drivers/soc/Makefile index 3b0f9fb3b5c8..8914530f2721 100644 --- a/drivers/soc/Makefile +++ b/drivers/soc/Makefile @@ -4,6 +4,7 @@ # =20 obj-$(CONFIG_ARCH_ACTIONS) +=3D actions/ +obj-y +=3D amd/ obj-y +=3D apple/ obj-y +=3D aspeed/ obj-$(CONFIG_ARCH_AT91) +=3D atmel/ diff --git a/drivers/soc/amd/Kconfig b/drivers/soc/amd/Kconfig new file mode 100644 index 000000000000..9fc03de49f11 --- /dev/null +++ b/drivers/soc/amd/Kconfig @@ -0,0 +1,16 @@ +# SPDX-License-Identifier: GPL-2.0-only +menu "AMD Pensando SoC drivers" + +config AMD_PENSANDO_CTRL + tristate "AMD Pensando SoC Controller" + depends on SPI_MASTER=3Dy + depends on (ARCH_PENSANDO && OF) || COMPILE_TEST + default y if ARCH_PENSANDO + select REGMAP_SPI + select MFD_SYSCON + help + Enables AMD Pensando SoC controller device support. This is a SPI + attached companion device in all Pensando SoC board designs which + provides essential board control/status registers and management IO + support. +endmenu diff --git a/drivers/soc/amd/Makefile b/drivers/soc/amd/Makefile new file mode 100644 index 000000000000..a2de0424f68d --- /dev/null +++ b/drivers/soc/amd/Makefile @@ -0,0 +1,2 @@ +# SPDX-License-Identifier: GPL-2.0-only +obj-$(CONFIG_AMD_PENSANDO_CTRL) +=3D pensando-ctrl.o diff --git a/drivers/soc/amd/pensando-ctrl.c b/drivers/soc/amd/pensando-ctr= l.c new file mode 100644 index 000000000000..4f1b2b1f5092 --- /dev/null +++ b/drivers/soc/amd/pensando-ctrl.c @@ -0,0 +1,378 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * AMD Pensando SoC Controller + * + * Userspace interface and reset driver support for SPI connected Pensando= SoC + * controller device. This device is present in all Pensando SoC designs = and + * contains board control/status regsiters and management IO support. + * + * Copyright 2023 Advanced Micro Devices, Inc. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +struct penctrl_device { + struct spi_device *spi_dev; + struct reset_controller_dev rcdev; +}; + +static DEFINE_MUTEX(spi_lock); +static dev_t penctrl_devt; +static struct penctrl_device *penctrl; +static struct class *penctrl_class; + +static long +penctrl_ioctl(struct file *filp, unsigned int cmd, unsigned long arg) +{ + struct spi_transfer t[2] =3D { 0 }; + struct penctrl_device *penctrl; + struct penctrl_spi_xfer *msg; + struct spi_device *spi_dev; + unsigned int num_msgs; + struct spi_message m; + u8 tx_buf[PENCTRL_MAX_MSG_LEN]; + u8 rx_buf[PENCTRL_MAX_MSG_LEN]; + u32 size; + int ret; + + /* Check for a valid command */ + if (_IOC_TYPE(cmd) !=3D PENCTRL_IOC_MAGIC) + return -ENOTTY; + + if (_IOC_NR(cmd) > PENCTRL_IOC_MAXNR) + return -ENOTTY; + + if (_IOC_DIR(cmd) & _IOC_READ) + ret =3D !access_ok((void __user *)arg, _IOC_SIZE(cmd)); + else if (_IOC_DIR(cmd) & _IOC_WRITE) + ret =3D !access_ok((void __user *)arg, _IOC_SIZE(cmd)); + + if (ret) + return -EFAULT; + + /* Get a reference to the SPI device */ + penctrl =3D filp->private_data; + if (!penctrl) + return -ESHUTDOWN; + + spi_dev =3D spi_dev_get(penctrl->spi_dev); + if (!spi_dev) + return -ESHUTDOWN; + + /* Verify and prepare spi message */ + size =3D _IOC_SIZE(cmd); + if ((size % sizeof(struct penctrl_spi_xfer)) !=3D 0) { + ret =3D -EINVAL; + goto done; + } + num_msgs =3D size / sizeof(struct penctrl_spi_xfer); + if (num_msgs =3D=3D 0) { + ret =3D -EINVAL; + goto done; + } + msg =3D memdup_user((struct penctrl_spi_xfer __user *)arg, size); + if (!msg) { + ret =3D PTR_ERR(msg); + goto done; + } + if (msg->len > PENCTRL_MAX_MSG_LEN) { + ret =3D -EINVAL; + goto done; + } + + t[0].tx_buf =3D tx_buf; + t[0].len =3D msg->len; + if (copy_from_user((void *)tx_buf, (void __user *)msg->tx_buf, msg->len))= { + ret =3D -EFAULT; + goto done; + } + if (num_msgs > 1) { + msg++; + if (msg->len > PENCTRL_MAX_MSG_LEN) { + ret =3D -EINVAL; + goto done; + } + t[1].rx_buf =3D rx_buf; + t[1].len =3D msg->len; + } + spi_message_init_with_transfers(&m, t, num_msgs); + + /* Perform the transfer */ + mutex_lock(&spi_lock); + ret =3D spi_sync(spi_dev, &m); + mutex_unlock(&spi_lock); + + if (ret || (num_msgs =3D=3D 1)) + goto done; + + if (copy_to_user((void __user *)msg->rx_buf, (void *)rx_buf, msg->len)) + ret =3D -EFAULT; + +done: + spi_dev_put(spi_dev); + return ret; +} + +static int penctrl_open(struct inode *inode, struct file *filp) +{ + struct spi_device *spi_dev; + u8 current_cs; + + if (!penctrl) + return -ENODEV; + + filp->private_data =3D penctrl; + current_cs =3D iminor(inode); + spi_dev =3D penctrl->spi_dev; + spi_dev->chip_select =3D current_cs; + spi_dev->cs_gpiod =3D spi_dev->controller->cs_gpiods[current_cs]; + spi_setup(spi_dev); + stream_open(inode, filp); + + return 0; +} + +static int penctrl_release(struct inode *inode, struct file *filp) +{ + filp->private_data =3D NULL; + return 0; +} + +static const struct file_operations penctrl_fops =3D { + .owner =3D THIS_MODULE, + .unlocked_ioctl =3D penctrl_ioctl, + .open =3D penctrl_open, + .release =3D penctrl_release, + .llseek =3D no_llseek, +}; + +static int penctrl_regs_read(struct penctrl_device *penctrl, u32 reg, u32 = *val) +{ + struct spi_device *spi_dev =3D penctrl->spi_dev; + struct spi_transfer t[2] =3D { 0 }; + struct spi_message m; + u8 txbuf[3]; + u8 rxbuf[1]; + int ret; + + txbuf[0] =3D PENCTRL_SPI_CMD_REGRD; + txbuf[1] =3D reg; + txbuf[2] =3D 0x0; + t[0].tx_buf =3D txbuf; + t[0].len =3D 3; + + rxbuf[0] =3D 0x0; + t[1].rx_buf =3D rxbuf; + t[1].len =3D 1; + + spi_message_init_with_transfers(&m, t, ARRAY_SIZE(t)); + ret =3D spi_sync(spi_dev, &m); + if (ret =3D=3D 0) + *val =3D rxbuf[0]; + + return ret; +} + +static int penctrl_regs_write(struct penctrl_device *penctrl, u32 reg, u32= val) +{ + struct spi_device *spi_dev =3D penctrl->spi_dev; + struct spi_transfer t[1] =3D { 0 }; + struct spi_message m; + u8 txbuf[4]; + int ret; + + txbuf[0] =3D PENCTRL_SPI_CMD_REGWR; + txbuf[1] =3D reg; + txbuf[2] =3D val; + txbuf[3] =3D 0; + + t[0].tx_buf =3D txbuf; + t[0].len =3D 4; + spi_message_init_with_transfers(&m, t, ARRAY_SIZE(t)); + ret =3D spi_sync(spi_dev, &m); + return ret; +} + +static int penctrl_reset_assert(struct reset_controller_dev *rcdev, + unsigned long id) +{ + struct penctrl_device *penctrl =3D + container_of(rcdev, struct penctrl_device, rcdev); + struct spi_device *spi_dev =3D penctrl->spi_dev; + unsigned int val; + int ret; + + mutex_lock(&spi_lock); + spi_dev->chip_select =3D 0; + spi_dev->cs_gpiod =3D spi_dev->controller->cs_gpiods[0]; + spi_setup(spi_dev); + ret =3D penctrl_regs_read(penctrl, PENCTRL_REG_CTRL0, &val); + if (ret) { + dev_err(&spi_dev->dev, "error reading ctrl0 reg\n"); + goto done; + } + + val |=3D BIT(6); + ret =3D penctrl_regs_write(penctrl, PENCTRL_REG_CTRL0, val); + if (ret) + dev_err(&spi_dev->dev, "error writing ctrl0 reg\n"); + +done: + mutex_unlock(&spi_lock); + return ret; +} + +static int penctrl_reset_deassert(struct reset_controller_dev *rcdev, + unsigned long id) +{ + struct penctrl_device *penctrl =3D + container_of(rcdev, struct penctrl_device, rcdev); + struct spi_device *spi_dev =3D penctrl->spi_dev; + unsigned int val; + int ret; + + mutex_lock(&spi_lock); + spi_dev->chip_select =3D 0; + spi_dev->cs_gpiod =3D spi_dev->controller->cs_gpiods[0]; + spi_setup(spi_dev); + ret =3D penctrl_regs_read(penctrl, PENCTRL_REG_CTRL0, &val); + if (ret) { + dev_err(&spi_dev->dev, "error reading ctrl0 reg\n"); + goto done; + } + + val &=3D ~BIT(6); + ret =3D penctrl_regs_write(penctrl, PENCTRL_REG_CTRL0, val); + if (ret) + dev_err(&spi_dev->dev, "error writing ctrl0 reg\n"); + +done: + mutex_unlock(&spi_lock); + return ret; +} + +static const struct reset_control_ops penctrl_reset_ops =3D { + .assert =3D penctrl_reset_assert, + .deassert =3D penctrl_reset_deassert, +}; + +static int penctrl_spi_probe(struct spi_device *spi_dev) +{ + struct device_node *np; + struct device *dev; + struct cdev *cdev; + u32 num_cs; + int ret; + u32 cs; + + np =3D spi_dev->dev.parent->of_node; + ret =3D of_property_read_u32(np, "num-cs", &num_cs); + if (ret) + return dev_err_probe(&spi_dev->dev, ret, + "number of chip-selects not defined"); + + ret =3D alloc_chrdev_region(&penctrl_devt, 0, num_cs, "penctrl"); + if (ret) + return dev_err_probe(&spi_dev->dev, ret, + "failed to alloc chrdev region\n"); + + penctrl_class =3D class_create(THIS_MODULE, "penctrl"); + if (IS_ERR(penctrl_class)) { + unregister_chrdev(MAJOR(penctrl_devt), "penctrl"); + return dev_err_probe(&spi_dev->dev, PTR_ERR(penctrl_class), + "failed to create class\n"); + } + + cdev =3D cdev_alloc(); + if (!cdev) { + dev_err(&spi_dev->dev, "allocation of cdev failed"); + ret =3D -ENOMEM; + goto cdev_failed; + } + cdev->owner =3D THIS_MODULE; + cdev_init(cdev, &penctrl_fops); + + ret =3D cdev_add(cdev, penctrl_devt, num_cs); + if (ret) { + dev_err(&spi_dev->dev, "register of cdev failed"); + goto cdev_delete; + } + + /* Allocate driver data */ + penctrl =3D kzalloc(sizeof(*penctrl), GFP_KERNEL); + if (!penctrl) { + ret =3D -ENOMEM; + dev_err(&spi_dev->dev, "allocate driver data failed"); + goto cdev_delete; + } + + penctrl->spi_dev =3D spi_dev; + mutex_init(&spi_lock); + + /* Create a device for each chip select */ + for (cs =3D 0; cs < num_cs; cs++) { + dev =3D device_create(penctrl_class, + &spi_dev->dev, + MKDEV(MAJOR(penctrl_devt), cs), + penctrl, + "penctrl0.%d", + cs); + if (IS_ERR(dev)) { + ret =3D IS_ERR(dev); + dev_err(&spi_dev->dev, "error creating device\n"); + goto cdev_delete; + } + dev_dbg(&spi_dev->dev, "created device major %u, minor %d\n", + MAJOR(penctrl_devt), cs); + } + + spi_set_drvdata(spi_dev, penctrl); + + /* Register emmc hardware reset */ + penctrl->rcdev.nr_resets =3D 1; + penctrl->rcdev.owner =3D THIS_MODULE; + penctrl->rcdev.dev =3D &spi_dev->dev; + penctrl->rcdev.ops =3D &penctrl_reset_ops; + penctrl->rcdev.of_node =3D spi_dev->dev.of_node; + ret =3D reset_controller_register(&penctrl->rcdev); + if (ret) + return dev_err_probe(&spi_dev->dev, ret, + "failed to register reset controller\n"); + return ret; + +cdev_delete: + cdev_del(cdev); +cdev_failed: + device_destroy(penctrl_class, penctrl_devt); + return ret; +} + +static const struct of_device_id penctrl_dt_match[] =3D { + { .compatible =3D "amd,pensando-elba-ctrl" }, + { /* sentinel */ } +}; + +static struct spi_driver penctrl_spi_driver =3D { + .probe =3D penctrl_spi_probe, + .driver =3D { + .name =3D "pensando-ctrl", + .of_match_table =3D penctrl_dt_match, + }, +}; +module_spi_driver(penctrl_spi_driver); + +MODULE_AUTHOR("Brad Larson "); +MODULE_DESCRIPTION("AMD Pensando SoC Controller via SPI"); +MODULE_LICENSE("GPL"); diff --git a/include/uapi/linux/amd-pensando-ctrl.h b/include/uapi/linux/am= d-pensando-ctrl.h new file mode 100644 index 000000000000..0a6caf3b764c --- /dev/null +++ b/include/uapi/linux/amd-pensando-ctrl.h @@ -0,0 +1,30 @@ +/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */ +/* + * Userspace interface for /dev/penctrl + * + * This file can be used by applications that need to communicate + * with the AMD Pensando SoC controller device via the ioctl interface. + */ +#ifndef _UAPI_LINUX_AMD_PENSANDO_CTRL_H +#define _UAPI_LINUX_AMD_PENSANDO_CTRL_H + +#include +#include + +#define PENCTRL_SPI_CMD_REGRD 0x0b +#define PENCTRL_SPI_CMD_REGWR 0x02 +#define PENCTRL_IOC_MAGIC 'k' +#define PENCTRL_IOC_MAXNR 0 +#define PENCTRL_MAX_MSG_LEN 16 +#define PENCTRL_MAX_REG 0xff +#define PENCTRL_REG_CTRL0 0x10 + +struct penctrl_spi_xfer { + __u64 tx_buf; + __u64 rx_buf; + __u32 len; + __u32 speed_hz; + __u64 compat; +}; + +#endif /* _UAPI_LINUX_AMD_PENSANDO_CTRL_H */ --=20 2.17.1