From nobody Sat Apr 11 20:22:29 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 80714C6FD1C for ; Fri, 10 Mar 2023 10:37:05 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230167AbjCJKgy (ORCPT ); Fri, 10 Mar 2023 05:36:54 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:59672 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229768AbjCJKg3 (ORCPT ); Fri, 10 Mar 2023 05:36:29 -0500 Received: from lelv0142.ext.ti.com (lelv0142.ext.ti.com [198.47.23.249]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id F3C61111B28; Fri, 10 Mar 2023 02:36:06 -0800 (PST) Received: from fllv0034.itg.ti.com ([10.64.40.246]) by lelv0142.ext.ti.com (8.15.2/8.15.2) with ESMTP id 32AAZC3E112570; Fri, 10 Mar 2023 04:35:12 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1678444512; bh=zecu4Dkj1NP+2bK5nhx0QaP/I0pwX+MjJTmA50/nH+o=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=x2bAdcAVYN8qmLuQ8R3ix3AzXpa7PzvJ6prbrNiau2FB9IIzSN+p2IbDq8p16vCiH 7km6BHOz0W9RZIoCsYkAV4oSTohMRHgAPsH/srP5wpX4KEMFH0LQ7sjE2Y4X15WwaE 41ObNMg1fvX0KwF7eOHkbgaizOdA+KBiSZ+u5MgY= Received: from DFLE107.ent.ti.com (dfle107.ent.ti.com [10.64.6.28]) by fllv0034.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 32AAZCMA075920 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Fri, 10 Mar 2023 04:35:12 -0600 Received: from DFLE100.ent.ti.com (10.64.6.21) by DFLE107.ent.ti.com (10.64.6.28) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.16; Fri, 10 Mar 2023 04:35:11 -0600 Received: from fllv0040.itg.ti.com (10.64.41.20) by DFLE100.ent.ti.com (10.64.6.21) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.16 via Frontend Transport; Fri, 10 Mar 2023 04:35:11 -0600 Received: from uda0492258.dhcp.ti.com (ileaxei01-snat.itg.ti.com [10.180.69.5]) by fllv0040.itg.ti.com (8.15.2/8.15.2) with ESMTP id 32AAZ4Pg088652; Fri, 10 Mar 2023 04:35:08 -0600 From: Siddharth Vadapalli To: , , , , , CC: , , , , Subject: [PATCH v2 1/2] arm64: dts: ti: k3-j721e: Add CPSW9G nodes Date: Fri, 10 Mar 2023 16:05:03 +0530 Message-ID: <20230310103504.731845-2-s-vadapalli@ti.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230310103504.731845-1-s-vadapalli@ti.com> References: <20230310103504.731845-1-s-vadapalli@ti.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" TI's J721E SoC has a 9 port Ethernet Switch instance with 8 external ports and 1 host port, referred to as CPSW9G. Add device-tree nodes for CPSW9G and disable it by default. Device-tree overlays will be used to enable it. Signed-off-by: Siddharth Vadapalli --- arch/arm64/boot/dts/ti/k3-j721e-main.dtsi | 107 ++++++++++++++++++++++ arch/arm64/boot/dts/ti/k3-j721e.dtsi | 1 + 2 files changed, 108 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi b/arch/arm64/boot/dt= s/ti/k3-j721e-main.dtsi index c935622f0102..1ac7a47fc437 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi @@ -61,6 +61,13 @@ serdes_ln_ctrl: mux-controller@4080 { , ; }; =20 + cpsw0_phy_gmii_sel: phy@4044 { + compatible =3D "ti,j721e-cpsw9g-phy-gmii-sel"; + ti,qsgmii-main-ports =3D <2>, <2>; + reg =3D <0x4044 0x20>; + #phy-cells =3D <1>; + }; + usb_serdes_mux: mux-controller@4000 { compatible =3D "mmio-mux"; #mux-control-cells =3D <1>; @@ -404,6 +411,106 @@ cpts@310d0000 { }; }; =20 + cpsw0: ethernet@c000000 { + compatible =3D "ti,j721e-cpswxg-nuss"; + #address-cells =3D <2>; + #size-cells =3D <2>; + reg =3D <0x0 0xc000000 0x0 0x200000>; + reg-names =3D "cpsw_nuss"; + ranges =3D <0x0 0x0 0x0 0x0c000000 0x0 0x200000>; + clocks =3D <&k3_clks 19 89>; + clock-names =3D "fck"; + power-domains =3D <&k3_pds 19 TI_SCI_PD_EXCLUSIVE>; + + dmas =3D <&main_udmap 0xca00>, + <&main_udmap 0xca01>, + <&main_udmap 0xca02>, + <&main_udmap 0xca03>, + <&main_udmap 0xca04>, + <&main_udmap 0xca05>, + <&main_udmap 0xca06>, + <&main_udmap 0xca07>, + <&main_udmap 0x4a00>; + dma-names =3D "tx0", "tx1", "tx2", "tx3", + "tx4", "tx5", "tx6", "tx7", + "rx"; + + status =3D "disabled"; + + ethernet-ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + cpsw0_port1: port@1 { + reg =3D <1>; + ti,mac-only; + label =3D "port1"; + }; + + cpsw0_port2: port@2 { + reg =3D <2>; + ti,mac-only; + label =3D "port2"; + }; + + cpsw0_port3: port@3 { + reg =3D <3>; + ti,mac-only; + label =3D "port3"; + }; + + cpsw0_port4: port@4 { + reg =3D <4>; + ti,mac-only; + label =3D "port4"; + }; + + cpsw0_port5: port@5 { + reg =3D <5>; + ti,mac-only; + label =3D "port5"; + }; + + cpsw0_port6: port@6 { + reg =3D <6>; + ti,mac-only; + label =3D "port6"; + }; + + cpsw0_port7: port@7 { + reg =3D <7>; + ti,mac-only; + label =3D "port7"; + }; + + cpsw0_port8: port@8 { + reg =3D <8>; + ti,mac-only; + label =3D "port8"; + }; + }; + + cpsw9g_mdio: mdio@f00 { + compatible =3D "ti,cpsw-mdio","ti,davinci_mdio"; + reg =3D <0x0 0xf00 0x0 0x100>; + #address-cells =3D <1>; + #size-cells =3D <0>; + clocks =3D <&k3_clks 19 89>; + clock-names =3D "fck"; + bus_freq =3D <1000000>; + }; + + cpts@3d000 { + compatible =3D "ti,j721e-cpts"; + reg =3D <0x0 0x3d000 0x0 0x400>; + clocks =3D <&k3_clks 19 16>; + clock-names =3D "cpts"; + interrupts-extended =3D <&gic500 GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names =3D "cpts"; + ti,cpts-ext-ts-inputs =3D <4>; + ti,cpts-periodic-outputs =3D <2>; + }; + }; + main_crypto: crypto@4e00000 { compatible =3D "ti,j721e-sa2ul"; reg =3D <0x0 0x4e00000 0x0 0x1200>; diff --git a/arch/arm64/boot/dts/ti/k3-j721e.dtsi b/arch/arm64/boot/dts/ti/= k3-j721e.dtsi index 6975cae644d9..ddbaa06e21bd 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j721e.dtsi @@ -135,6 +135,7 @@ cbass_main: bus@100000 { <0x00 0x06000000 0x00 0x06000000 0x00 0x00400000>, /* USBSS0 */ <0x00 0x06400000 0x00 0x06400000 0x00 0x00400000>, /* USBSS1 */ <0x00 0x01000000 0x00 0x01000000 0x00 0x0af02400>, /* Most peripherals= */ + <0x00 0x0c000000 0x00 0x0c000000 0x00 0x0d000000>, /* CPSW9G */ <0x00 0x30000000 0x00 0x30000000 0x00 0x0c400000>, /* MAIN NAVSS */ <0x00 0x0d000000 0x00 0x0d000000 0x00 0x01800000>, /* PCIe Core*/ <0x00 0x0e000000 0x00 0x0e000000 0x00 0x01800000>, /* PCIe Core*/ --=20 2.25.1 From nobody Sat Apr 11 20:22:29 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id B03E4C74A44 for ; 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Fri, 10 Mar 2023 04:35:15 -0600 Received: from DLEE114.ent.ti.com (157.170.170.25) by DLEE103.ent.ti.com (157.170.170.33) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.16; Fri, 10 Mar 2023 04:35:14 -0600 Received: from fllv0040.itg.ti.com (10.64.41.20) by DLEE114.ent.ti.com (157.170.170.25) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.16 via Frontend Transport; Fri, 10 Mar 2023 04:35:15 -0600 Received: from uda0492258.dhcp.ti.com (ileaxei01-snat.itg.ti.com [10.180.69.5]) by fllv0040.itg.ti.com (8.15.2/8.15.2) with ESMTP id 32AAZ4Ph088652; Fri, 10 Mar 2023 04:35:12 -0600 From: Siddharth Vadapalli To: , , , , , CC: , , , , Subject: [PATCH v2 2/2] arm64: dts: ti: k3-j721e: Add overlay to enable CPSW9G ports in QSGMII mode Date: Fri, 10 Mar 2023 16:05:04 +0530 Message-ID: <20230310103504.731845-3-s-vadapalli@ti.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230310103504.731845-1-s-vadapalli@ti.com> References: <20230310103504.731845-1-s-vadapalli@ti.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" The J7 Quad Port Add-On Ethernet Card for J721E Common-Proc-Board supports QSGMII mode. Use the overlay to configure CPSW9G ports in QSGMII mode. Add support to reset the PHY from kernel by using gpio-hog and gpio-reset. Add aliases for CPSW9G ports to enable kernel to fetch MAC addresses directly from U-Boot. Signed-off-by: Siddharth Vadapalli --- arch/arm64/boot/dts/ti/Makefile | 4 + .../dts/ti/k3-j721e-quad-port-eth-exp.dtso | 148 ++++++++++++++++++ 2 files changed, 152 insertions(+) create mode 100644 arch/arm64/boot/dts/ti/k3-j721e-quad-port-eth-exp.dtso diff --git a/arch/arm64/boot/dts/ti/Makefile b/arch/arm64/boot/dts/ti/Makef= ile index 6acd12409d59..167bcd9b09b7 100644 --- a/arch/arm64/boot/dts/ti/Makefile +++ b/arch/arm64/boot/dts/ti/Makefile @@ -45,3 +45,7 @@ dtb-$(CONFIG_ARCH_K3) +=3D k3-j784s4-evm.dtb =20 # Enable support for device-tree overlays DTC_FLAGS_k3-am6548-iot2050-advanced-m2 +=3D -@ +DTC_FLAGS_k3-j721e-common-proc-board +=3D -@ + +# Device-tree overlays +dtb-$(CONFIG_ARCH_K3) +=3D k3-j721e-quad-port-eth-exp.dtbo diff --git a/arch/arm64/boot/dts/ti/k3-j721e-quad-port-eth-exp.dtso b/arch/= arm64/boot/dts/ti/k3-j721e-quad-port-eth-exp.dtso new file mode 100644 index 000000000000..d7977d16c921 --- /dev/null +++ b/arch/arm64/boot/dts/ti/k3-j721e-quad-port-eth-exp.dtso @@ -0,0 +1,148 @@ +// SPDX-License-Identifier: GPL-2.0 +/** + * DT Overlay for CPSW9G in QSGMII mode using J7 Quad Port ETH EXP Add-On = Ethernet Card with + * J721E board. + * + * Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/ + */ + +/dts-v1/; +/plugin/; + +#include +#include +#include +#include +#include + +/ { + fragment@102 { + target-path =3D "/"; + __overlay__ { + aliases { + ethernet1 =3D "/bus@100000/ethernet@c000000/ethernet-ports/port@1"; + ethernet2 =3D "/bus@100000/ethernet@c000000/ethernet-ports/port@2"; + ethernet3 =3D "/bus@100000/ethernet@c000000/ethernet-ports/port@3"; + ethernet4 =3D "/bus@100000/ethernet@c000000/ethernet-ports/port@4"; + }; + }; + }; +}; + +&cpsw0 { + status =3D "okay"; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&mdio0_pins_default>; +}; + +&cpsw0_port1 { + phy-handle =3D <&cpsw9g_phy0>; + phy-mode =3D "qsgmii"; + mac-address =3D [00 00 00 00 00 00]; + phys =3D <&cpsw0_phy_gmii_sel 1>; +}; + +&cpsw0_port2 { + phy-handle =3D <&cpsw9g_phy1>; + phy-mode =3D "qsgmii"; + mac-address =3D [00 00 00 00 00 00]; + phys =3D <&cpsw0_phy_gmii_sel 2>; +}; + +&cpsw0_port3 { + phy-handle =3D <&cpsw9g_phy2>; + phy-mode =3D "qsgmii"; + mac-address =3D [00 00 00 00 00 00]; + phys =3D <&cpsw0_phy_gmii_sel 3>; +}; + +&cpsw0_port4 { + phy-handle =3D <&cpsw9g_phy3>; + phy-mode =3D "qsgmii"; + mac-address =3D [00 00 00 00 00 00]; + phys =3D <&cpsw0_phy_gmii_sel 4>; +}; + +&cpsw0_port5 { + status =3D "disabled"; +}; + +&cpsw0_port6 { + status =3D "disabled"; +}; + +&cpsw0_port7 { + status =3D "disabled"; +}; + +&cpsw0_port8 { + status =3D "disabled"; +}; + +&cpsw9g_mdio { + reset-gpios =3D <&exp2 17 GPIO_ACTIVE_LOW>; + reset-post-delay-us =3D <120000>; + #address-cells =3D <1>; + #size-cells =3D <0>; + + cpsw9g_phy0: ethernet-phy@17 { + reg =3D <17>; + }; + cpsw9g_phy1: ethernet-phy@16 { + reg =3D <16>; + }; + cpsw9g_phy2: ethernet-phy@18 { + reg =3D <18>; + }; + cpsw9g_phy3: ethernet-phy@19 { + reg =3D <19>; + }; +}; + +&exp2 { + qsgmii-line-hog { + gpio-hog; + gpios =3D <16 GPIO_ACTIVE_HIGH>; + output-low; + line-name =3D "qsgmii-pwrdn-line"; + }; +}; + +&main_pmx0 { + mdio0_pins_default: mdio0-pins-default { + pinctrl-single,pins =3D < + J721E_IOPAD(0x1bc, PIN_OUTPUT, 0) /* (V24) MDIO0_MDC */ + J721E_IOPAD(0x1b8, PIN_INPUT, 0) /* (V26) MDIO0_MDIO */ + >; + }; +}; + +&serdes_ln_ctrl { + idle-states =3D , , + , , + , , + , , + , , + , ; +}; + +&serdes_wiz0 { + status =3D "okay"; +}; + +&serdes0 { + status =3D "okay"; + + assigned-clocks =3D <&serdes0 CDNS_SIERRA_PLL_CMNLC>, <&serdes0 CDNS_SIER= RA_PLL_CMNLC1>; + assigned-clock-parents =3D <&wiz0_pll1_refclk>, <&wiz0_pll1_refclk>; + #address-cells =3D <1>; + #size-cells =3D <0>; + + serdes0_qsgmii_link: phy@1 { + reg =3D <1>; + cdns,num-lanes =3D <1>; + #phy-cells =3D <0>; + cdns,phy-type =3D ; + resets =3D <&serdes_wiz0 2>; + }; +}; --=20 2.25.1