From nobody Wed Sep 10 05:41:31 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7BF37C6FD19 for ; Wed, 8 Mar 2023 23:38:38 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230076AbjCHXig (ORCPT ); Wed, 8 Mar 2023 18:38:36 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:37270 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229891AbjCHXi1 (ORCPT ); Wed, 8 Mar 2023 18:38:27 -0500 Received: from mail-oa1-x31.google.com (mail-oa1-x31.google.com [IPv6:2001:4860:4864:20::31]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id F08A554CBF for ; Wed, 8 Mar 2023 15:38:25 -0800 (PST) Received: by mail-oa1-x31.google.com with SMTP id 586e51a60fabf-176d1a112bfso552425fac.5 for ; Wed, 08 Mar 2023 15:38:25 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1678318705; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=uJnVP86v80cE19P+pF4Y6ZPg1z52ptg2NHYCv/S3Tvs=; b=BuQWA5ZBBgtF0cM2MPdV6GoZdjhlbq7bInCPFh7dUmCH8qXz21Any7rCTd4RtTnZrZ +/FSoZ+ADeQEBPdIiiDNC5z3WszOLoATv05XbvlMg6YZHC87w/j5dSjE31s/WY7jFnNV UOGDkhxTHOJBlNec4dDO5kqngzyV18cq78OvekxCsdJFzpadxWgoW10QmTjmvJ6QtY3w yIfsWQXzihe60eNVRnU70ImysdTbjtGlihxLAuuZ58CSITGoDG0LUNEeqCA1+WMss9Ot cSMj3v6I3nkvco9lI3uYaPpUORJz7KHvjTCcwRXQ+BfO6SpDaS5rqPWerNCxG2aayIWy wJ0A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1678318705; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=uJnVP86v80cE19P+pF4Y6ZPg1z52ptg2NHYCv/S3Tvs=; b=A9aokC2wyz+yEDuF0oC2G+qdMKGKGQgIJcDiR4bBYoNE8eBgzGyINJ1xeBeDN0IM3w CD5nodJ1cdXvOgOADkkXJwWjgcgG+3XKkf8Pwzi0WPppJ5K7sCVfOs0kjAGB8Pig1u3E /X4udNX1yNoU8qELo14Uw4EZMgvL5Bj32VDp2TydE+tTPdALbeiF4VM+p9qto37uPFmL Bmyo0w/Ji8P8+2r6OgyCUF9fYj3wz2kcs9nBjbhbZogeY30vMMxIXj1Gs6CvFxPfPzHc N++bg46Ug8V0cI7pTBtD/khc+UN1dL+0HAhC9dhG2/rVdDwH6KfES0+YmyqxZMWUnlOa HgLQ== X-Gm-Message-State: AO0yUKXNB77G9ldzDc2iWk5cUuWlHORPAuGp8tX+x/OumdRMuhEiHrma dLscLgBf2Hxlkh/Laa43ezT75g== X-Google-Smtp-Source: AK7set9ZbuWP9DuATT4yEuGAADPyzGBQZ4BihOLgSjpwiz9NxVFYJNvWYIGSR4vMf1RR4+WAwozzYg== X-Received: by 2002:a05:6871:708:b0:176:2486:16fb with SMTP id f8-20020a056871070800b00176248616fbmr14787743oap.7.1678318705262; Wed, 08 Mar 2023 15:38:25 -0800 (PST) Received: from localhost ([136.49.140.41]) by smtp.gmail.com with ESMTPSA id dy39-20020a056870c7a700b001763897690csm6807207oab.1.2023.03.08.15.38.24 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 08 Mar 2023 15:38:24 -0800 (PST) From: Sam Protsenko To: Krzysztof Kozlowski , Rob Herring , Sylwester Nawrocki Cc: Marek Szyprowski , Tomasz Figa , Chanwoo Choi , Chanho Park , David Virag , Alim Akhtar , Michael Turquette , Stephen Boyd , linux-samsung-soc@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH 1/7] dt-bindings: clock: exynos850: Add power-domains property Date: Wed, 8 Mar 2023 17:38:16 -0600 Message-Id: <20230308233822.31180-2-semen.protsenko@linaro.org> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230308233822.31180-1-semen.protsenko@linaro.org> References: <20230308233822.31180-1-semen.protsenko@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Document power-domains property in Exynos850 clock controller. Signed-off-by: Sam Protsenko --- .../devicetree/bindings/clock/samsung,exynos850-clock.yaml | 3 +++ 1 file changed, 3 insertions(+) diff --git a/Documentation/devicetree/bindings/clock/samsung,exynos850-cloc= k.yaml b/Documentation/devicetree/bindings/clock/samsung,exynos850-clock.ya= ml index 8aa87b8c1b33..cc1e9173b272 100644 --- a/Documentation/devicetree/bindings/clock/samsung,exynos850-clock.yaml +++ b/Documentation/devicetree/bindings/clock/samsung,exynos850-clock.yaml @@ -54,6 +54,9 @@ properties: "#clock-cells": const: 1 =20 + power-domains: + maxItems: 1 + reg: maxItems: 1 =20 --=20 2.39.2 From nobody Wed Sep 10 05:41:31 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id ECA86C678D5 for ; Wed, 8 Mar 2023 23:38:42 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229603AbjCHXil (ORCPT ); Wed, 8 Mar 2023 18:38:41 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:37392 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230101AbjCHXi2 (ORCPT ); Wed, 8 Mar 2023 18:38:28 -0500 Received: from mail-ot1-x329.google.com (mail-ot1-x329.google.com [IPv6:2607:f8b0:4864:20::329]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 4AC6557D09 for ; Wed, 8 Mar 2023 15:38:27 -0800 (PST) Received: by mail-ot1-x329.google.com with SMTP id g73-20020a9d12cf000000b006943a7df072so123836otg.11 for ; Wed, 08 Mar 2023 15:38:27 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1678318706; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=c1aCfh++R75HCn6rV29gUz4FnrRGANFpdhcsqijAx/o=; b=wcTZjull7l8jDiPC59APixfrJy4MzvcItSe+rO/P7rkBtJoa3ywzaJv46Y/KgyTUax qzYWrVXLlM4b14dlgS2xci/lFbCiD3O7xwA/RRt7tvx435mRv1BaCLTUHVU1TcUX/ZxW R+0hLvOs3ntoFIeUr4YvifDPZgc5G85dLm8X6/d2EgtWB36YJMeJVLk4w1Prk0ZqeTPJ WwWxiiigVozkcncmyAsGCChDIrqkU3mxVRt+qJUI60lKGffD+G2RtdF+3FC4ugKsjo3S JeCn7mBRV3Jo4u0C8U4siURtbIU2otXgX1YVQzukY1zVr1ddwsQdTC6xa4PNIkRVlu4D 43TA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1678318706; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=c1aCfh++R75HCn6rV29gUz4FnrRGANFpdhcsqijAx/o=; b=xVWb7Ewp8HYMNqJcTCOkMNVQdRFSl9X0VGuWlzkDAtYi5OIklIjoiAcBMIo6MxTqLj YBCR4sV+ONH9HCLYUbYTznyL0bTQfPCioEcICh3i4tvsolJmtqxQQoVgn6XNYxGVxMjg M7OZVajC69NsPgTEzUj39FYHHnf/0E76bfRaTi1X+fRyYEQSpm5OF8RCIy0YVfWe00iC cFZLY0es83kWVtSKAm6r2XwOn7y+EsI7d9pSdEwc2pcQ0ZnhVeBkrhLimKJlQEd375hZ IhNUmDy7HKkqpxs4EI5q/COMUqdBReefPEsJqN8a2Cgfjq2adOIogUyaB4wLY+uLVnJj POGQ== X-Gm-Message-State: AO0yUKW/97QN1W4rpYQl3YT7oblpe1skgLCrAzXgMjV54oxhv5BOzT2w svTn7Twbt6rEw6Kl5bXsUjOKyQ== X-Google-Smtp-Source: AK7set86T3Ma2Mao5rC+bFw/kxkZzZq2DqDx+Iag9iINHHJah+WzhFV01lHKVAqMkmHZY45R4VkleA== X-Received: by 2002:a9d:3e03:0:b0:690:ee9d:f47 with SMTP id a3-20020a9d3e03000000b00690ee9d0f47mr8122115otd.1.1678318706541; Wed, 08 Mar 2023 15:38:26 -0800 (PST) Received: from localhost ([136.49.140.41]) by smtp.gmail.com with ESMTPSA id y12-20020a9d714c000000b006864b5f4650sm7159351otj.46.2023.03.08.15.38.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 08 Mar 2023 15:38:26 -0800 (PST) From: Sam Protsenko To: Krzysztof Kozlowski , Rob Herring , Sylwester Nawrocki Cc: Marek Szyprowski , Tomasz Figa , Chanwoo Choi , Chanho Park , David Virag , Alim Akhtar , Michael Turquette , Stephen Boyd , linux-samsung-soc@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH 2/7] dt-bindings: clock: exynos850: Add tzpc property Date: Wed, 8 Mar 2023 17:38:17 -0600 Message-Id: <20230308233822.31180-3-semen.protsenko@linaro.org> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230308233822.31180-1-semen.protsenko@linaro.org> References: <20230308233822.31180-1-semen.protsenko@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Exynos850 requires extra TZPC handling to keep CMU registers non-secure (accessible from the kernel) after PM resume. It's done using a specific SMC call to the EL3 monitor. Describe "samsung,tzpc" property for Exynos850 clock controller which allows one to specify the SMC call address for PD capable CMUs. Signed-off-by: Sam Protsenko --- .../bindings/clock/samsung,exynos850-clock.yaml | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/Documentation/devicetree/bindings/clock/samsung,exynos850-cloc= k.yaml b/Documentation/devicetree/bindings/clock/samsung,exynos850-clock.ya= ml index cc1e9173b272..5098dce5caf6 100644 --- a/Documentation/devicetree/bindings/clock/samsung,exynos850-clock.yaml +++ b/Documentation/devicetree/bindings/clock/samsung,exynos850-clock.yaml @@ -60,6 +60,16 @@ properties: reg: maxItems: 1 =20 + samsung,tzpc: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + The register address in corresponding Trust Zone Protection Control = block + for setting the CMU registers access to non-secure. If provided, it'= ll be + used for issuing SMC calls to EL3 monitor during CMU's PM suspend and + resume operations, ensuring CMU registers are unprotected after waki= ng up. + + This property is optional. + allOf: - if: properties: --=20 2.39.2 From nobody Wed Sep 10 05:41:31 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id B8B7DC64EC4 for ; Wed, 8 Mar 2023 23:38:47 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229970AbjCHXip (ORCPT ); Wed, 8 Mar 2023 18:38:45 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:37392 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230153AbjCHXib (ORCPT ); Wed, 8 Mar 2023 18:38:31 -0500 Received: from mail-ot1-x32e.google.com (mail-ot1-x32e.google.com [IPv6:2607:f8b0:4864:20::32e]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 822DF5B5FA for ; Wed, 8 Mar 2023 15:38:28 -0800 (PST) Received: by mail-ot1-x32e.google.com with SMTP id g6-20020a056830308600b0068d4b30536aso129328ots.9 for ; Wed, 08 Mar 2023 15:38:28 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1678318708; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=woOYONkToPVHYWga31WFD9txV73HBu+FiarlM+DWulI=; b=lRsJ3IRNiUqFgrEUYgPttSw5MR8Z9Yh9RHQ9H58mztAYJYPUN5XZ/t1Gl2eOU02Dkp LytKW3GxqUFuDM4Hh3yKiGDtDsUEavCb5iIJD8/eOHWJB9G/G9spgqsfLbNfO6n0uAfW nveUzUqxgvsRb4KEU+Ty/ovknkLWziy0xmkick+JMXWmd5AWRPVZP9IT8XeYd/iyW7n+ sKhnlMom+Py8EVkMaE9B1ZhUGQoxL6N508ImCb5NGuhwcIUB02YFijIpsmVjxhDWbRca IdU0ZHAjfaRx92tPGYUzOcterNKUIkIbS8DPVhp3IBtHjvZBsSEf7NTTVNEq8eorD68U OBlA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1678318708; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=woOYONkToPVHYWga31WFD9txV73HBu+FiarlM+DWulI=; b=Ygo0fJSt0qHzDyooAp1vfg7n0t7jNgpWTbor1vI+iUmp9lw9XFwqCA5NgnEB+Pm2st pghjp/ZLWVvB/SNrzzuEvxY+WmNPmYU9sxD+CwDEFtcodyNKQ7Bawlp766nfitRLVtMa 93HJHbO+CjI7uotR1qFjmGayrHpIm2pflZrEtwHaoQEkw8yTxgo4unHdcWKvXRcXf6cm OkzNmG2CeCi0SdKg2n75Zt4y3/8wv58qqXooLYBuIn11bJdzHcKFhES6jAm/ybbR0XUV hx3MCHpqTPeRNhZsGZdkYDqYtItFYjZSzG5zsAYnLjtcfQQPPIP1+G52vObPnZHc3aHf MAKQ== X-Gm-Message-State: AO0yUKUDQRJ3pNZtSzFN2EBGS+AY83PZPJLc4lncHy34s7O80nq7mHEG vepDP5O4UPMW4l6If7YEolFGpw== X-Google-Smtp-Source: AK7set/sBQMg+Sa7FJqtY3KmdnHRg0UVZJhWENSlY8qIYW07sgauEXFUt9pV/Pb7xM+ywbZPG/xINQ== X-Received: by 2002:a05:6830:1614:b0:693:c9f9:64ab with SMTP id g20-20020a056830161400b00693c9f964abmr9781546otr.3.1678318707846; Wed, 08 Mar 2023 15:38:27 -0800 (PST) Received: from localhost ([136.49.140.41]) by smtp.gmail.com with ESMTPSA id x2-20020a9d6282000000b00690eeb8b436sm6899431otk.65.2023.03.08.15.38.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 08 Mar 2023 15:38:27 -0800 (PST) From: Sam Protsenko To: Krzysztof Kozlowski , Rob Herring , Sylwester Nawrocki Cc: Marek Szyprowski , Tomasz Figa , Chanwoo Choi , Chanho Park , David Virag , Alim Akhtar , Michael Turquette , Stephen Boyd , linux-samsung-soc@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH 3/7] clk: samsung: Implement PM SMC calls for ARM64 Exynos SoCs Date: Wed, 8 Mar 2023 17:38:18 -0600 Message-Id: <20230308233822.31180-4-semen.protsenko@linaro.org> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230308233822.31180-1-semen.protsenko@linaro.org> References: <20230308233822.31180-1-semen.protsenko@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Exynos850 requires extra TZPC handling to keep CMU registers non-secure (accessible from the kernel) after PM resume. It's done using a specific SMC call to the EL3 monitor. Implement corresponding SMC calls in suspend and resume functions. Perform those calls when the parent (bus) clock is running to avoid SMC freezes. The "samsung,tzpc" property is used to specify the TZPC register address for those calls (for each particular domain). If that property is not provided, SMC calls won't be performed, thus keeping the compatibility with CMUs and platforms where that SMC functionality is not needed. Signed-off-by: Sam Protsenko --- drivers/clk/samsung/clk-exynos-arm64.c | 39 ++++++++++++++++++++++++-- 1 file changed, 37 insertions(+), 2 deletions(-) diff --git a/drivers/clk/samsung/clk-exynos-arm64.c b/drivers/clk/samsung/c= lk-exynos-arm64.c index 7d8937caf22a..57e9bee7ec4d 100644 --- a/drivers/clk/samsung/clk-exynos-arm64.c +++ b/drivers/clk/samsung/clk-exynos-arm64.c @@ -8,6 +8,8 @@ * This file contains shared functions used by some arm64 Exynos SoCs, * such as Exynos7885 or Exynos850 to register and init CMUs. */ + +#include #include #include #include @@ -24,6 +26,12 @@ #define GATE_OFF_START 0x2000 #define GATE_OFF_END 0x2fff =20 +/* Power control SMC command and its parameters */ +#define SMC_CMD_PREPARE_PD_ONOFF 0x82000410 +#define EXYNOS_PD_RUNTIME_PM 2 +#define EXYNOS_GET_IN_PD_DOWN 0 +#define EXYNOS_WAKEUP_PD_DOWN 1 + struct exynos_arm64_cmu_data { struct samsung_clk_reg_dump *clk_save; unsigned int nr_clk_save; @@ -34,6 +42,7 @@ struct exynos_arm64_cmu_data { struct clk **pclks; int nr_pclks; =20 + unsigned int tzpc_addr; /* address for PM SMC calls */ struct samsung_clk_provider *ctx; }; =20 @@ -149,6 +158,22 @@ static int __init exynos_arm64_cmu_prepare_pm(struct d= evice *dev, return 0; } =20 +static int exynos_arm64_pm_smc(struct device *dev, bool on) +{ + struct exynos_arm64_cmu_data *data =3D dev_get_drvdata(dev); + struct arm_smccc_res res; + unsigned int pm_arg; + + if (!data->tzpc_addr) + return 0; + + pm_arg =3D on ? EXYNOS_WAKEUP_PD_DOWN : EXYNOS_GET_IN_PD_DOWN; + arm_smccc_smc(SMC_CMD_PREPARE_PD_ONOFF, pm_arg, data->tzpc_addr, + EXYNOS_PD_RUNTIME_PM, 0, 0, 0, 0, &res); + + return res.a0; +} + /** * exynos_arm64_register_cmu - Register specified Exynos CMU domain * @dev: Device object; may be NULL if this function is not being @@ -207,6 +232,8 @@ int __init exynos_arm64_register_cmu_pm(struct platform= _device *pdev, if (!data) return -ENOMEM; =20 + of_property_read_u32(np, "samsung,tzpc", (u32 *)&data->tzpc_addr); + platform_set_drvdata(pdev, data); =20 ret =3D exynos_arm64_cmu_prepare_pm(dev, cmu); @@ -251,7 +278,7 @@ int __init exynos_arm64_register_cmu_pm(struct platform= _device *pdev, int exynos_arm64_cmu_suspend(struct device *dev) { struct exynos_arm64_cmu_data *data =3D dev_get_drvdata(dev); - int i; + int i, ret; =20 samsung_clk_save(data->ctx->reg_base, data->clk_save, data->nr_clk_save); @@ -263,6 +290,10 @@ int exynos_arm64_cmu_suspend(struct device *dev) samsung_clk_restore(data->ctx->reg_base, data->clk_suspend, data->nr_clk_suspend); =20 + ret =3D exynos_arm64_pm_smc(dev, false); + if (ret) + return ret; + for (i =3D 0; i < data->nr_pclks; i++) clk_disable_unprepare(data->pclks[i]); =20 @@ -274,13 +305,17 @@ int exynos_arm64_cmu_suspend(struct device *dev) int exynos_arm64_cmu_resume(struct device *dev) { struct exynos_arm64_cmu_data *data =3D dev_get_drvdata(dev); - int i; + int i, ret; =20 clk_prepare_enable(data->clk); =20 for (i =3D 0; i < data->nr_pclks; i++) clk_prepare_enable(data->pclks[i]); =20 + ret =3D exynos_arm64_pm_smc(dev, true); + if (ret) + return ret; + samsung_clk_restore(data->ctx->reg_base, data->clk_save, data->nr_clk_save); =20 --=20 2.39.2 From nobody Wed Sep 10 05:41:31 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id B21EEC64EC4 for ; Wed, 8 Mar 2023 23:38:51 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230297AbjCHXit (ORCPT ); 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Wed, 08 Mar 2023 15:38:28 -0800 (PST) From: Sam Protsenko To: Krzysztof Kozlowski , Rob Herring , Sylwester Nawrocki Cc: Marek Szyprowski , Tomasz Figa , Chanwoo Choi , Chanho Park , David Virag , Alim Akhtar , Michael Turquette , Stephen Boyd , linux-samsung-soc@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH 4/7] clk: samsung: exynos850: Make PMU_ALIVE_PCLK critical Date: Wed, 8 Mar 2023 17:38:19 -0600 Message-Id: <20230308233822.31180-5-semen.protsenko@linaro.org> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230308233822.31180-1-semen.protsenko@linaro.org> References: <20230308233822.31180-1-semen.protsenko@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" PMU_ALIVE_PCLK is needed for PMU registers access, and it must be always running, as not only the kernel accesses PMU registers. Make it critical to ensure that. Signed-off-by: Sam Protsenko --- drivers/clk/samsung/clk-exynos850.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/clk/samsung/clk-exynos850.c b/drivers/clk/samsung/clk-= exynos850.c index 6ab5fa8c2ef3..98b23af7324d 100644 --- a/drivers/clk/samsung/clk-exynos850.c +++ b/drivers/clk/samsung/clk-exynos850.c @@ -612,7 +612,7 @@ static const struct samsung_gate_clock apm_gate_clks[] = __initconst =3D { CLK_CON_GAT_GOUT_APM_APBIF_GPIO_ALIVE_PCLK, 21, CLK_IGNORE_UNUSED, 0), GATE(CLK_GOUT_PMU_ALIVE_PCLK, "gout_pmu_alive_pclk", "dout_apm_bus", - CLK_CON_GAT_GOUT_APM_APBIF_PMU_ALIVE_PCLK, 21, 0, 0), + CLK_CON_GAT_GOUT_APM_APBIF_PMU_ALIVE_PCLK, 21, CLK_IS_CRITICAL, 0), GATE(CLK_GOUT_SYSREG_APM_PCLK, "gout_sysreg_apm_pclk", "dout_apm_bus", CLK_CON_GAT_GOUT_APM_SYSREG_APM_PCLK, 21, 0, 0), }; --=20 2.39.2 From nobody Wed Sep 10 05:41:31 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id D881CC678D5 for ; Wed, 8 Mar 2023 23:38:54 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230304AbjCHXix (ORCPT ); Wed, 8 Mar 2023 18:38:53 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:37690 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230203AbjCHXid (ORCPT ); Wed, 8 Mar 2023 18:38:33 -0500 Received: from mail-oi1-x22d.google.com (mail-oi1-x22d.google.com [IPv6:2607:f8b0:4864:20::22d]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id DE5C7580E0 for ; Wed, 8 Mar 2023 15:38:30 -0800 (PST) Received: by mail-oi1-x22d.google.com with SMTP id be16so416011oib.0 for ; Wed, 08 Mar 2023 15:38:30 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1678318710; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=OhdSRqJaGfztHCYkWeNpp02lhvYbsG6+3kQCkkXc7Pc=; b=myK0jC+/mCPv7bj4QZjfKujIW7s5qz4C4CX+hrTsKV0Ed2EcuIjpHKLR2ZVa2Q0lKT 1WDrcUgQmd+9rr7lZg1UzoTZmzQcwMIxwVhjJBlWSkAz5YDruoqRks2ox9oJfMkZ2AR/ x0xYrt0Al4un/UhGeMGmiYZsHgSW9N1rCq75w7c6ENYcw4ldbAfM2HQCHzp7aSGKKiST jXDhQF+NMIxHO7JbBkl48Q42o5abcxJd6C2TGlUPdirgIJTZgQw5RxmdwLR+pv9TkQah 3O/NFu1H/IH2BpSFtvvc2RLQfV7gXiE0mHh3nlgSFKVEgTqPul36zZvyYEBsPEX+uvKX XQFw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1678318710; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=OhdSRqJaGfztHCYkWeNpp02lhvYbsG6+3kQCkkXc7Pc=; b=DEeWCK6XmBAunDciA0wtDZX2sGQlLqFEu+Gbaec8eK7D5KqWMX3Z9nhjDRW13SAlJ/ KwHNzy3qfHZF2xxUBLdfKVvPWu8XvWo85TtkHRoQXkMAyNc6opz5rNr5/bcyRauO204W GIsDJeKzIiSFZMf1wg3h79uPSYlXoXejiUx71FXYdxgHMg4LZdDLIdhMwKBxEMHURhbL 7kElusSf/kLOAmTc2GRalMvMUO7Q1ttaBHs9iAU7nkP3wW5PISsz7xOLKXtz2ODGFRFU xzuk/8zRGJ43Iuap3Rlylr0aYI8pPTgRUAqmuyqvOHOpzlImX5ABewmmw3HtiAtm7w4X ldcQ== X-Gm-Message-State: AO0yUKVKDe4Mw8UTgK0fAoxXRyMH3WfJTpVS529VYTCVX4IM06jQW2lj QV23f/C3OniU1JdyN/xD67xcfzNFpGWbPfVzqxpsBw== X-Google-Smtp-Source: AK7set/5z392BFVptFZBGokctJdIkZ9WCLRF4yHopeCLA19ESHC4RJaazlSVqK2iAy92qLm8tsbZXA== X-Received: by 2002:a05:6808:188:b0:384:232:2a4f with SMTP id w8-20020a056808018800b0038402322a4fmr7731504oic.4.1678318710527; Wed, 08 Mar 2023 15:38:30 -0800 (PST) Received: from localhost ([136.49.140.41]) by smtp.gmail.com with ESMTPSA id f8-20020a9d2c08000000b00690dc5d9b9esm7021525otb.6.2023.03.08.15.38.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 08 Mar 2023 15:38:30 -0800 (PST) From: Sam Protsenko To: Krzysztof Kozlowski , Rob Herring , Sylwester Nawrocki Cc: Marek Szyprowski , Tomasz Figa , Chanwoo Choi , Chanho Park , David Virag , Alim Akhtar , Michael Turquette , Stephen Boyd , linux-samsung-soc@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH 5/7] clk: samsung: exynos850: Add suspend state for all CMUs Date: Wed, 8 Mar 2023 17:38:20 -0600 Message-Id: <20230308233822.31180-6-semen.protsenko@linaro.org> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230308233822.31180-1-semen.protsenko@linaro.org> References: <20230308233822.31180-1-semen.protsenko@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Before entering suspend, some clocks must be set to some specific configuration. For example, top-level MUX clocks in each CMU should be switched to OSCCLK input, etc. This is needed by the firmware to properly perform system suspend operation. Provide the suspend state for mentioned clocks using 'suspend_regs' feature. This patch was inspired by commit a766065279e2 ("clk: samsung: exynos5433: Add suspend state for TOP, CPIF & PERIC CMUs"). Signed-off-by: Sam Protsenko --- drivers/clk/samsung/clk-exynos850.c | 92 +++++++++++++++++++++++++++++ 1 file changed, 92 insertions(+) diff --git a/drivers/clk/samsung/clk-exynos850.c b/drivers/clk/samsung/clk-= exynos850.c index 98b23af7324d..5664d17bae83 100644 --- a/drivers/clk/samsung/clk-exynos850.c +++ b/drivers/clk/samsung/clk-exynos850.c @@ -186,6 +186,12 @@ static const unsigned long top_clk_regs[] __initconst = =3D { CLK_CON_GAT_GATE_CLKCMU_PERI_UART, }; =20 +static const struct samsung_clk_reg_dump top_suspend_regs[] =3D { + { PLL_CON0_PLL_MMC, 0 }, + { PLL_CON0_PLL_SHARED0, 0 }, + { PLL_CON0_PLL_SHARED1, 0 }, +}; + /* * Do not provide PLL tables to core PLLs, as MANUAL_PLL_CTRL bit is not s= et * for those PLLs by default, so set_rate operation would fail. @@ -489,6 +495,8 @@ static const struct samsung_cmu_info top_cmu_info __ini= tconst =3D { .nr_clk_ids =3D TOP_NR_CLK, .clk_regs =3D top_clk_regs, .nr_clk_regs =3D ARRAY_SIZE(top_clk_regs), + .suspend_regs =3D top_suspend_regs, + .nr_suspend_regs =3D ARRAY_SIZE(top_suspend_regs), }; =20 static void __init exynos850_cmu_top_init(struct device_node *np) @@ -547,6 +555,13 @@ static const unsigned long apm_clk_regs[] __initconst = =3D { CLK_CON_GAT_GOUT_APM_SYSREG_APM_PCLK, }; =20 +static const struct samsung_clk_reg_dump apm_suspend_regs[] =3D { + { PLL_CON0_MUX_CLKCMU_APM_BUS_USER, 0 }, + { PLL_CON0_MUX_CLK_RCO_APM_I3C_USER, 0 }, + { PLL_CON0_MUX_CLK_RCO_APM_USER, 0 }, + { PLL_CON0_MUX_DLL_USER, 0 }, +}; + /* List of parent clocks for Muxes in CMU_APM */ PNAME(mout_apm_bus_user_p) =3D { "oscclk_rco_apm", "dout_clkcmu_apm_bus" }; PNAME(mout_rco_apm_i3c_user_p) =3D { "oscclk_rco_apm", "clk_rco_i3c_pmic" = }; @@ -629,6 +644,8 @@ static const struct samsung_cmu_info apm_cmu_info __ini= tconst =3D { .nr_clk_ids =3D APM_NR_CLK, .clk_regs =3D apm_clk_regs, .nr_clk_regs =3D ARRAY_SIZE(apm_clk_regs), + .suspend_regs =3D apm_suspend_regs, + .nr_suspend_regs =3D ARRAY_SIZE(apm_suspend_regs), .clk_name =3D "dout_clkcmu_apm_bus", }; =20 @@ -746,6 +763,12 @@ static const unsigned long aud_clk_regs[] __initconst = =3D { CLK_CON_GAT_GOUT_AUD_WDT_PCLK, }; =20 +static const struct samsung_clk_reg_dump aud_suspend_regs[] =3D { + { PLL_CON0_PLL_AUD, 0 }, + { PLL_CON0_MUX_CLKCMU_AUD_CPU_USER, 0 }, + { PLL_CON0_MUX_TICK_USB_USER, 0 }, +}; + /* List of parent clocks for Muxes in CMU_AUD */ PNAME(mout_aud_pll_p) =3D { "oscclk", "fout_aud_pll" }; PNAME(mout_aud_cpu_user_p) =3D { "oscclk", "dout_aud" }; @@ -912,6 +935,8 @@ static const struct samsung_cmu_info aud_cmu_info __ini= tconst =3D { .nr_clk_ids =3D AUD_NR_CLK, .clk_regs =3D aud_clk_regs, .nr_clk_regs =3D ARRAY_SIZE(aud_clk_regs), + .suspend_regs =3D aud_suspend_regs, + .nr_suspend_regs =3D ARRAY_SIZE(aud_suspend_regs), .clk_name =3D "dout_aud", }; =20 @@ -950,6 +975,12 @@ static const unsigned long cmgp_clk_regs[] __initconst= =3D { CLK_CON_GAT_GOUT_CMGP_USI_CMGP1_PCLK, }; =20 +static const struct samsung_clk_reg_dump cmgp_suspend_regs[] =3D { + { CLK_CON_MUX_CLK_CMGP_ADC, 0 }, + { CLK_CON_MUX_MUX_CLK_CMGP_USI_CMGP0, 0 }, + { CLK_CON_MUX_MUX_CLK_CMGP_USI_CMGP1, 0 }, +}; + /* List of parent clocks for Muxes in CMU_CMGP */ PNAME(mout_cmgp_usi0_p) =3D { "clk_rco_cmgp", "gout_clkcmu_cmgp_bus" }; PNAME(mout_cmgp_usi1_p) =3D { "clk_rco_cmgp", "gout_clkcmu_cmgp_bus" }; @@ -1015,6 +1046,8 @@ static const struct samsung_cmu_info cmgp_cmu_info __= initconst =3D { .nr_clk_ids =3D CMGP_NR_CLK, .clk_regs =3D cmgp_clk_regs, .nr_clk_regs =3D ARRAY_SIZE(cmgp_clk_regs), + .suspend_regs =3D cmgp_suspend_regs, + .nr_suspend_regs =3D ARRAY_SIZE(cmgp_suspend_regs), .clk_name =3D "gout_clkcmu_cmgp_bus", }; =20 @@ -1051,6 +1084,11 @@ static const unsigned long g3d_clk_regs[] __initcons= t =3D { CLK_CON_GAT_GOUT_G3D_SYSREG_PCLK, }; =20 +static const struct samsung_clk_reg_dump g3d_suspend_regs[] =3D { + { PLL_CON0_PLL_G3D, 0 }, + { PLL_CON0_MUX_CLKCMU_G3D_SWITCH_USER, 0 }, +}; + /* List of parent clocks for Muxes in CMU_G3D */ PNAME(mout_g3d_pll_p) =3D { "oscclk", "fout_g3d_pll" }; PNAME(mout_g3d_switch_user_p) =3D { "oscclk", "dout_g3d_switch" }; @@ -1111,6 +1149,8 @@ static const struct samsung_cmu_info g3d_cmu_info __i= nitconst =3D { .nr_clk_ids =3D G3D_NR_CLK, .clk_regs =3D g3d_clk_regs, .nr_clk_regs =3D ARRAY_SIZE(g3d_clk_regs), + .suspend_regs =3D g3d_suspend_regs, + .nr_suspend_regs =3D ARRAY_SIZE(g3d_suspend_regs), .clk_name =3D "dout_g3d_switch", }; =20 @@ -1153,6 +1193,13 @@ static const unsigned long hsi_clk_regs[] __initcons= t =3D { CLK_CON_GAT_GOUT_HSI_USB20DRD_TOP_BUS_CLK_EARLY, }; =20 +static const struct samsung_clk_reg_dump hsi_suspend_regs[] =3D { + { PLL_CON0_MUX_CLKCMU_HSI_BUS_USER, 0 }, + { PLL_CON0_MUX_CLKCMU_HSI_MMC_CARD_USER, 0 }, + { PLL_CON0_MUX_CLKCMU_HSI_USB20DRD_USER, 0 }, + { CLK_CON_MUX_MUX_CLK_HSI_RTC, 0 }, +}; + /* List of parent clocks for Muxes in CMU_HSI */ PNAME(mout_hsi_bus_user_p) =3D { "oscclk", "dout_hsi_bus" }; PNAME(mout_hsi_mmc_card_user_p) =3D { "oscclk", "dout_hsi_mmc_card" }; @@ -1213,6 +1260,8 @@ static const struct samsung_cmu_info hsi_cmu_info __i= nitconst =3D { .nr_clk_ids =3D HSI_NR_CLK, .clk_regs =3D hsi_clk_regs, .nr_clk_regs =3D ARRAY_SIZE(hsi_clk_regs), + .suspend_regs =3D hsi_suspend_regs, + .nr_suspend_regs =3D ARRAY_SIZE(hsi_suspend_regs), .clk_name =3D "dout_hsi_bus", }; =20 @@ -1268,6 +1317,13 @@ static const unsigned long is_clk_regs[] __initconst= =3D { CLK_CON_GAT_GOUT_IS_SYSREG_PCLK, }; =20 +static const struct samsung_clk_reg_dump is_suspend_regs[] =3D { + { PLL_CON0_MUX_CLKCMU_IS_BUS_USER, 0 }, + { PLL_CON0_MUX_CLKCMU_IS_GDC_USER, 0 }, + { PLL_CON0_MUX_CLKCMU_IS_ITP_USER, 0 }, + { PLL_CON0_MUX_CLKCMU_IS_VRA_USER, 0 }, +}; + /* List of parent clocks for Muxes in CMU_IS */ PNAME(mout_is_bus_user_p) =3D { "oscclk", "dout_is_bus" }; PNAME(mout_is_itp_user_p) =3D { "oscclk", "dout_is_itp" }; @@ -1345,6 +1401,8 @@ static const struct samsung_cmu_info is_cmu_info __in= itconst =3D { .nr_clk_ids =3D IS_NR_CLK, .clk_regs =3D is_clk_regs, .nr_clk_regs =3D ARRAY_SIZE(is_clk_regs), + .suspend_regs =3D is_suspend_regs, + .nr_suspend_regs =3D ARRAY_SIZE(is_suspend_regs), .clk_name =3D "dout_is_bus", }; =20 @@ -1384,6 +1442,13 @@ static const unsigned long mfcmscl_clk_regs[] __init= const =3D { CLK_CON_GAT_GOUT_MFCMSCL_SYSREG_PCLK, }; =20 +static const struct samsung_clk_reg_dump mfcmscl_suspend_regs[] =3D { + { PLL_CON0_MUX_CLKCMU_MFCMSCL_JPEG_USER, 0 }, + { PLL_CON0_MUX_CLKCMU_MFCMSCL_M2M_USER, 0 }, + { PLL_CON0_MUX_CLKCMU_MFCMSCL_MCSC_USER, 0 }, + { PLL_CON0_MUX_CLKCMU_MFCMSCL_MFC_USER, 0 }, +}; + /* List of parent clocks for Muxes in CMU_MFCMSCL */ PNAME(mout_mfcmscl_mfc_user_p) =3D { "oscclk", "dout_mfcmscl_mfc" }; PNAME(mout_mfcmscl_m2m_user_p) =3D { "oscclk", "dout_mfcmscl_m2m" }; @@ -1454,6 +1519,8 @@ static const struct samsung_cmu_info mfcmscl_cmu_info= __initconst =3D { .nr_clk_ids =3D MFCMSCL_NR_CLK, .clk_regs =3D mfcmscl_clk_regs, .nr_clk_regs =3D ARRAY_SIZE(mfcmscl_clk_regs), + .suspend_regs =3D mfcmscl_suspend_regs, + .nr_suspend_regs =3D ARRAY_SIZE(mfcmscl_suspend_regs), .clk_name =3D "dout_mfcmscl_mfc", }; =20 @@ -1532,6 +1599,13 @@ static const unsigned long peri_clk_regs[] __initcon= st =3D { CLK_CON_GAT_GOUT_PERI_WDT_1_PCLK, }; =20 +static const struct samsung_clk_reg_dump peri_suspend_regs[] =3D { + { PLL_CON0_MUX_CLKCMU_PERI_BUS_USER, 0 }, + { PLL_CON0_MUX_CLKCMU_PERI_HSI2C_USER, 0 }, + { PLL_CON0_MUX_CLKCMU_PERI_SPI_USER, 0 }, + { PLL_CON0_MUX_CLKCMU_PERI_UART_USER, 0 }, +}; + /* List of parent clocks for Muxes in CMU_PERI */ PNAME(mout_peri_bus_user_p) =3D { "oscclk", "dout_peri_bus" }; PNAME(mout_peri_uart_user_p) =3D { "oscclk", "dout_peri_uart" }; @@ -1629,6 +1703,8 @@ static const struct samsung_cmu_info peri_cmu_info __= initconst =3D { .nr_clk_ids =3D PERI_NR_CLK, .clk_regs =3D peri_clk_regs, .nr_clk_regs =3D ARRAY_SIZE(peri_clk_regs), + .suspend_regs =3D peri_suspend_regs, + .nr_suspend_regs =3D ARRAY_SIZE(peri_suspend_regs), .clk_name =3D "dout_peri_bus", }; =20 @@ -1676,6 +1752,14 @@ static const unsigned long core_clk_regs[] __initcon= st =3D { CLK_CON_GAT_GOUT_CORE_SYSREG_CORE_PCLK, }; =20 +static const struct samsung_clk_reg_dump core_suspend_regs[] =3D { + { PLL_CON0_MUX_CLKCMU_CORE_BUS_USER, 0 }, + { PLL_CON0_MUX_CLKCMU_CORE_CCI_USER, 0 }, + { PLL_CON0_MUX_CLKCMU_CORE_MMC_EMBD_USER, 0 }, + { PLL_CON0_MUX_CLKCMU_CORE_SSS_USER, 0 }, + { CLK_CON_MUX_MUX_CLK_CORE_GIC, 0x1 }, +}; + /* List of parent clocks for Muxes in CMU_CORE */ PNAME(mout_core_bus_user_p) =3D { "oscclk", "dout_core_bus" }; PNAME(mout_core_cci_user_p) =3D { "oscclk", "dout_core_cci" }; @@ -1736,6 +1820,8 @@ static const struct samsung_cmu_info core_cmu_info __= initconst =3D { .nr_clk_ids =3D CORE_NR_CLK, .clk_regs =3D core_clk_regs, .nr_clk_regs =3D ARRAY_SIZE(core_clk_regs), + .suspend_regs =3D core_suspend_regs, + .nr_suspend_regs =3D ARRAY_SIZE(core_suspend_regs), .clk_name =3D "dout_core_bus", }; =20 @@ -1766,6 +1852,10 @@ static const unsigned long dpu_clk_regs[] __initcons= t =3D { CLK_CON_GAT_GOUT_DPU_SYSREG_PCLK, }; =20 +static const struct samsung_clk_reg_dump dpu_suspend_regs[] =3D { + { PLL_CON0_MUX_CLKCMU_DPU_USER, 0 }, +}; + /* List of parent clocks for Muxes in CMU_DPU */ PNAME(mout_dpu_user_p) =3D { "oscclk", "dout_dpu" }; =20 @@ -1810,6 +1900,8 @@ static const struct samsung_cmu_info dpu_cmu_info __i= nitconst =3D { .nr_clk_ids =3D DPU_NR_CLK, .clk_regs =3D dpu_clk_regs, .nr_clk_regs =3D ARRAY_SIZE(dpu_clk_regs), + .suspend_regs =3D dpu_suspend_regs, + .nr_suspend_regs =3D ARRAY_SIZE(dpu_suspend_regs), .clk_name =3D "dout_dpu", }; =20 --=20 2.39.2 From nobody Wed Sep 10 05:41:31 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 245DFC64EC4 for ; Wed, 8 Mar 2023 23:39:02 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230311AbjCHXi6 (ORCPT ); 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Wed, 08 Mar 2023 15:38:31 -0800 (PST) From: Sam Protsenko To: Krzysztof Kozlowski , Rob Herring , Sylwester Nawrocki Cc: Marek Szyprowski , Tomasz Figa , Chanwoo Choi , Chanho Park , David Virag , Alim Akhtar , Michael Turquette , Stephen Boyd , linux-samsung-soc@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH 6/7] clk: samsung: exynos850: Enable PM support in clk-exynos850 Date: Wed, 8 Mar 2023 17:38:21 -0600 Message-Id: <20230308233822.31180-7-semen.protsenko@linaro.org> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230308233822.31180-1-semen.protsenko@linaro.org> References: <20230308233822.31180-1-semen.protsenko@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Some CMUs in Exynos850 SoC belong to power domains. In order to support "power-domains" property for such CMUs, use exynos_arm64_register_cmu_pm() API instead of exynos_arm64_register_cmu() in the probe function, and also provide PM ops for suspend/resume accordingly. Signed-off-by: Sam Protsenko --- drivers/clk/samsung/clk-exynos850.c | 18 ++++++++++-------- 1 file changed, 10 insertions(+), 8 deletions(-) diff --git a/drivers/clk/samsung/clk-exynos850.c b/drivers/clk/samsung/clk-= exynos850.c index 5664d17bae83..bbf0498dd0b0 100644 --- a/drivers/clk/samsung/clk-exynos850.c +++ b/drivers/clk/samsung/clk-exynos850.c @@ -9,8 +9,8 @@ #include #include #include -#include #include +#include =20 #include =20 @@ -1909,13 +1909,7 @@ static const struct samsung_cmu_info dpu_cmu_info __= initconst =3D { =20 static int __init exynos850_cmu_probe(struct platform_device *pdev) { - const struct samsung_cmu_info *info; - struct device *dev =3D &pdev->dev; - - info =3D of_device_get_match_data(dev); - exynos_arm64_register_cmu(dev, dev->of_node, info); - - return 0; + return exynos_arm64_register_cmu_pm(pdev, true); } =20 static const struct of_device_id exynos850_cmu_of_match[] =3D { @@ -1950,11 +1944,19 @@ static const struct of_device_id exynos850_cmu_of_m= atch[] =3D { }, }; =20 +static const struct dev_pm_ops exynos850_cmu_pm_ops =3D { + SET_RUNTIME_PM_OPS(exynos_arm64_cmu_suspend, exynos_arm64_cmu_resume, + NULL) + SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, + pm_runtime_force_resume) +}; + static struct platform_driver exynos850_cmu_driver __refdata =3D { .driver =3D { .name =3D "exynos850-cmu", .of_match_table =3D exynos850_cmu_of_match, .suppress_bind_attrs =3D true, + .pm =3D &exynos850_cmu_pm_ops, }, .probe =3D exynos850_cmu_probe, }; --=20 2.39.2 From nobody Wed Sep 10 05:41:31 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 91149C64EC4 for ; Wed, 8 Mar 2023 23:39:20 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230373AbjCHXjS (ORCPT ); Wed, 8 Mar 2023 18:39:18 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:38098 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230188AbjCHXii (ORCPT ); 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Wed, 08 Mar 2023 15:38:32 -0800 (PST) From: Sam Protsenko To: Krzysztof Kozlowski , Rob Herring , Sylwester Nawrocki Cc: Marek Szyprowski , Tomasz Figa , Chanwoo Choi , Chanho Park , David Virag , Alim Akhtar , Michael Turquette , Stephen Boyd , linux-samsung-soc@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH 7/7] arm64: dts: exynos: Remove clock from Exynos850 pmu_system_controller Date: Wed, 8 Mar 2023 17:38:22 -0600 Message-Id: <20230308233822.31180-8-semen.protsenko@linaro.org> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230308233822.31180-1-semen.protsenko@linaro.org> References: <20230308233822.31180-1-semen.protsenko@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" As described in the corresponding binding documentation for "samsung,exynos850-pmu", the "clocks" property should be used for specifying CLKOUT mux inputs. Therefore, the clock provided to exynos850 pmu_system_controller is incorrect and should be removed. Instead of making syscon regmap keep that clock running for PMU accesses, it should be made always running in the clock driver, because the kernel is not the only software accessing PMU registers on Exynos850 platform. Signed-off-by: Sam Protsenko --- arch/arm64/boot/dts/exynos/exynos850.dtsi | 1 - 1 file changed, 1 deletion(-) diff --git a/arch/arm64/boot/dts/exynos/exynos850.dtsi b/arch/arm64/boot/dt= s/exynos/exynos850.dtsi index d67e98120313..aa077008b3be 100644 --- a/arch/arm64/boot/dts/exynos/exynos850.dtsi +++ b/arch/arm64/boot/dts/exynos/exynos850.dtsi @@ -200,7 +200,6 @@ gic: interrupt-controller@12a01000 { pmu_system_controller: system-controller@11860000 { compatible =3D "samsung,exynos850-pmu", "syscon"; reg =3D <0x11860000 0x10000>; - clocks =3D <&cmu_apm CLK_GOUT_PMU_ALIVE_PCLK>; =20 reboot: syscon-reboot { compatible =3D "syscon-reboot"; --=20 2.39.2