From nobody Tue Sep 9 12:06:30 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 28224C742A7 for ; Wed, 8 Mar 2023 08:25:22 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230137AbjCHIZT (ORCPT ); Wed, 8 Mar 2023 03:25:19 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:46820 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230283AbjCHIYy (ORCPT ); Wed, 8 Mar 2023 03:24:54 -0500 Received: from mail-pj1-x102f.google.com (mail-pj1-x102f.google.com [IPv6:2607:f8b0:4864:20::102f]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id EB09C168A1 for ; Wed, 8 Mar 2023 00:24:36 -0800 (PST) Received: by mail-pj1-x102f.google.com with SMTP id qa18-20020a17090b4fd200b0023750b675f5so1501915pjb.3 for ; Wed, 08 Mar 2023 00:24:36 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1678263876; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=Hku7GI8fxnyC2ugXj0rjNviSGHzIDWLdfW64e83ph/U=; b=S2IrAmdHcm7bUgPqWiRffn0Hlsp2BqnYwJv4XBFQgfPcJI+vFmaDXjPCWfARaed2IH wIrPT0Fe/TNOMIF+Lb9G93gvD2TWYGJ4fKJXgRzUGfQtkyjg1wxeXNlDu28qFDtclfKo p+S/QhmEhYh8mUs11wPkrAqZl0FYgSZ5Y2MxAJPRx9g1XHCpKIvREMFt4rPbnQ2ObMas bo5mij/kUtqhHkVyYDGWNrseFO7SRy4jHVVyfMR6saiNOkS9WxxFYJyjl6Q3/ipIosB9 m6OhFbIvpb9Ya4NILIg1L/Vt7q4y7HhbMzAbkvxRiqtXVaz64VFovjXvvALw/Y2zkvv1 tzMw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1678263876; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Hku7GI8fxnyC2ugXj0rjNviSGHzIDWLdfW64e83ph/U=; b=2hgDLG6Mgmt3a1HIVajat1lyFtpRAA9/thwS9ryG/jRWwHUD6q/GIrcZR+KiH/uTM9 lsCszmXMvdcOVY9efojS/VjrynInSY+X8J9+7xSvgOOpR7zHLB5FvW00Tod7tdNl/Ru/ UcYq7o4u09MEhCHAHlAvs0qzOI6IlQyR2C3rlwuWw9fluIITb7iVwxF08KVlYM8TycZe fCFTAaYvlkKX/80Zpn/oVVAYZ4cHykVv5jC8IHAlKFu2TU0K6d0WM5Yo6YZJg+6pvDC4 xmfeuMCoEdzYZOUOl9o9XiTVw4Us5gxcXxJCZ9gLeFiKw44MJV/3kHMWobqCKWl/dFgF cZcA== X-Gm-Message-State: AO0yUKXEQP8M6/SsOrSHHW2tlLaCTdXmZZSIk1DPjbb27kAY2BCYEtHb yhpoMg2nrIDACGUYCE5UQ8ItE0/PY3WNDdWdzA== X-Google-Smtp-Source: AK7set+z2ohjLMrW/ySDf6/Oh+UEPC1wQb+tHc0FTJS9Kcx/n4N6wSZuXNOT6xuA5n5AkVTr9Gltmg== X-Received: by 2002:a17:902:b282:b0:19a:b151:bf68 with SMTP id u2-20020a170902b28200b0019ab151bf68mr17535437plr.38.1678263876361; Wed, 08 Mar 2023 00:24:36 -0800 (PST) Received: from localhost.localdomain ([59.97.52.140]) by smtp.gmail.com with ESMTPSA id s10-20020a170902ea0a00b0019aaab3f9d7sm9448086plg.113.2023.03.08.00.24.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 08 Mar 2023 00:24:36 -0800 (PST) From: Manivannan Sadhasivam To: andersson@kernel.org, lpieralisi@kernel.org, robh@kernel.org, kw@linux.com, krzysztof.kozlowski+dt@linaro.org, vkoul@kernel.org Cc: konrad.dybcio@linaro.org, bhelgaas@google.com, kishon@kernel.org, linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org, linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, Manivannan Sadhasivam , Krzysztof Kozlowski Subject: [PATCH v3 01/13] dt-bindings: PCI: qcom: Update maintainers entry Date: Wed, 8 Mar 2023 13:54:12 +0530 Message-Id: <20230308082424.140224-2-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230308082424.140224-1-manivannan.sadhasivam@linaro.org> References: <20230308082424.140224-1-manivannan.sadhasivam@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Stan is no longer working with MMSOL and expressed his interest to not continue maintaining Qcom PCIe driver. Since I took over the driver maintainership, I'm stepping in to maintain the binding also. Acked-by: Krzysztof Kozlowski Signed-off-by: Manivannan Sadhasivam --- Documentation/devicetree/bindings/pci/qcom,pcie.yaml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml b/Documen= tation/devicetree/bindings/pci/qcom,pcie.yaml index fb32c43dd12d..92eb273581f6 100644 --- a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml +++ b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml @@ -8,7 +8,7 @@ title: Qualcomm PCI express root complex =20 maintainers: - Bjorn Andersson - - Stanimir Varbanov + - Manivannan Sadhasivam =20 description: | Qualcomm PCIe root complex controller is based on the Synopsys DesignWare --=20 2.25.1 From nobody Tue Sep 9 12:06:30 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5312FC742A7 for ; Wed, 8 Mar 2023 08:25:31 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230147AbjCHIZ0 (ORCPT ); Wed, 8 Mar 2023 03:25:26 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:46860 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230301AbjCHIY4 (ORCPT ); Wed, 8 Mar 2023 03:24:56 -0500 Received: from mail-pl1-x636.google.com (mail-pl1-x636.google.com [IPv6:2607:f8b0:4864:20::636]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 4E25A8FBE7 for ; Wed, 8 Mar 2023 00:24:41 -0800 (PST) Received: by mail-pl1-x636.google.com with SMTP id y11so16986205plg.1 for ; Wed, 08 Mar 2023 00:24:41 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1678263881; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=WT/YBVNsPknrBjyIkGUY9UiL+2Gj/Zemk+zRmMN7Jkk=; b=IU1Ed86toqfeL/Oy5S9RLvgyjhKn4YpmAkbkjTUtlIYfyxwE6ss5nnj0A6aD5fihad 5YkLLWGCXIfYwDa6fLQxk3cHtvfit/giKXBtqIMZpOPlbTcWOVLPFxDj0xzeWoMasOma iVMEvW21hIS6FfgzrVtxi2kRHuAiOtEGHFbxOmoj4ltE7uWTJ0m4kApJme7X5j0NPIkb D/Rk+8qsklFZegDG8Os2SB3hNuI0zl2fERMn3Ja62fix/UnUKPeOZnopO4OUqfm/94/5 ewWodg5fB/p4yGvAfQoErsiv/UDPygj7R64RzhBJn5eRSKtuGp2tZLqcjUotGOPJxD9/ SGbA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1678263881; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=WT/YBVNsPknrBjyIkGUY9UiL+2Gj/Zemk+zRmMN7Jkk=; b=NSeIg46RwpUcvRDbApH0SQJZN7wWoVFwY96uSRCSZIxDBU7o7zNtunEFfvP2oWQqEh VAox7daV4KOqZRxE5dqV3H7nBBT1nSP+7jhfiqwnHpOECy8fMoGMIs2EDju82aWTXZln h2Hu7TqqYoYpjlhrNrHZMmEiOjZt5s8Wy8eMBvuaEaejBIl6a1yP+QSHCpfCKrFi3Gf3 FwEOs7NhTkKezqcJemIHhf4A4MlynjN99DnFjTMXFCli42twZ5Ax82EXMKGEB8C7Hsks UXQh+7ZJT6ONkjHfeYbzwj82zARVwEJ7lA/QQa3mbS5/FhD54tlqzc0tMeE9r2mmTzav P00g== X-Gm-Message-State: AO0yUKWKxHF4EtyvBKzoexcP+b71rN3GlmZKbxkCPj3cboqvDfEeI9Ov 3V01DIayka/o0EeSsKgAIk8b X-Google-Smtp-Source: AK7set/u3U2U32Lk//wFu6fAj0zNV+97AFPfKeYRbfUxhcrYTjxdj5ItKedSSAA8khsHfHl97oL8EA== X-Received: by 2002:a17:902:c948:b0:19c:dd49:9bf8 with SMTP id i8-20020a170902c94800b0019cdd499bf8mr21710306pla.28.1678263880800; Wed, 08 Mar 2023 00:24:40 -0800 (PST) Received: from localhost.localdomain ([59.97.52.140]) by smtp.gmail.com with ESMTPSA id s10-20020a170902ea0a00b0019aaab3f9d7sm9448086plg.113.2023.03.08.00.24.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 08 Mar 2023 00:24:40 -0800 (PST) From: Manivannan Sadhasivam To: andersson@kernel.org, lpieralisi@kernel.org, robh@kernel.org, kw@linux.com, krzysztof.kozlowski+dt@linaro.org, vkoul@kernel.org Cc: konrad.dybcio@linaro.org, bhelgaas@google.com, kishon@kernel.org, linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org, linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, Manivannan Sadhasivam Subject: [PATCH v3 02/13] dt-bindings: PCI: qcom: Add iommu-map properties Date: Wed, 8 Mar 2023 13:54:13 +0530 Message-Id: <20230308082424.140224-3-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230308082424.140224-1-manivannan.sadhasivam@linaro.org> References: <20230308082424.140224-1-manivannan.sadhasivam@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Most of the PCIe controllers require iommu support to function properly. So let's add the "iommu-map" property that specifies the SMMU SID of the PCIe devices to the binding. Signed-off-by: Manivannan Sadhasivam Reviewed-by: Rob Herring --- Documentation/devicetree/bindings/pci/qcom,pcie.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml b/Documen= tation/devicetree/bindings/pci/qcom,pcie.yaml index 92eb273581f6..55ee86facbc0 100644 --- a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml +++ b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml @@ -70,6 +70,8 @@ properties: =20 dma-coherent: true =20 + iommu-map: true + interconnects: maxItems: 2 =20 --=20 2.25.1 From nobody Tue Sep 9 12:06:30 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4FF42C678D5 for ; Wed, 8 Mar 2023 08:25:37 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230253AbjCHIZd (ORCPT ); Wed, 8 Mar 2023 03:25:33 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:39626 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230332AbjCHIY6 (ORCPT ); Wed, 8 Mar 2023 03:24:58 -0500 Received: from mail-pl1-x636.google.com (mail-pl1-x636.google.com [IPv6:2607:f8b0:4864:20::636]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id D109911E83 for ; Wed, 8 Mar 2023 00:24:45 -0800 (PST) Received: by mail-pl1-x636.google.com with SMTP id x11so12422999pln.12 for ; Wed, 08 Mar 2023 00:24:45 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1678263885; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=BWGkUKxc1+RShsSquL6TSNv4d+3ZNQVwM0OHF82Nolc=; b=nnv0TKxz1LQVhz72XMyVwhz2edQHF5C8K/gYRQygBo/yk+Dbv/xU+iD8tOrKpBybxo Th40/nZ5t3RuUuVaBM6w9/X487xPXQIMTOKM9TbKVKor+Z0RVV2eYg8W8PhlRGiSX/kh ddWdEZIFEpMwK++1pKPLAP1lGQcQYlhaYBvzvGWLWaFB70c6ZfKmR0GdchQKNjwHjGZc iN+14smx3G6dHXcmkw1THuLbzgflDB5QFz+VmZr10YyKqLAPt7GpI7XLw4ybBEWFJWv7 Hrj4r6bBgz9hKSJUOWbkNDVSPO/ri5RP9664q/ztWxL4fVHCC9ZgzTxmkwpwyZYGN4gi v6kg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1678263885; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=BWGkUKxc1+RShsSquL6TSNv4d+3ZNQVwM0OHF82Nolc=; b=fXEXR2/Ovv0+X2Olc1X+8VubzGjTVupaPeYf8fpVGzADEfZsRWTd4jSP6J3Mi78uEk HSYrCVJqFCazYhgCPXL86cYfDX5fBDK8oTTcYC3PHiTszQI2g6nRkuS7LnG4WJkTY00y 18IM1C3evZn67mMP3Qt/RluhfOfZdStMwEmystcD0UDvCpm32+ekSmx0cj8fdsZiCQBG 7Ta8WQ9uiFarsyxgTAl8nTWYocsrG6dMQfyUm6L8JZfuUnDfHqSG7kiTDGV9BI1scuFn j8gCHbQ6M9foPw1S1HvpnxkiQA9sjjVfbns82xlyp9i0oMg8HSXhQtmfPRIAQ0b8M49W TKAA== X-Gm-Message-State: AO0yUKXjNkxWU7SC9Un0JJX7jREYGAqE6COUmbEwv1cozouvelnZjWGb QSYtAnc4DwKM6QnXEUHr9bn0 X-Google-Smtp-Source: AK7set9hgLNXRCzM9+1cjNcg3cIBVdT4wUvKBQU14zJyGNk2N5NXDyJJWVjP3UoIVTQYzfWFhPYFbA== X-Received: by 2002:a17:902:cec6:b0:19d:1bc8:488a with SMTP id d6-20020a170902cec600b0019d1bc8488amr22220855plg.29.1678263885323; Wed, 08 Mar 2023 00:24:45 -0800 (PST) Received: from localhost.localdomain ([59.97.52.140]) by smtp.gmail.com with ESMTPSA id s10-20020a170902ea0a00b0019aaab3f9d7sm9448086plg.113.2023.03.08.00.24.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 08 Mar 2023 00:24:45 -0800 (PST) From: Manivannan Sadhasivam To: andersson@kernel.org, lpieralisi@kernel.org, robh@kernel.org, kw@linux.com, krzysztof.kozlowski+dt@linaro.org, vkoul@kernel.org Cc: konrad.dybcio@linaro.org, bhelgaas@google.com, kishon@kernel.org, linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org, linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, Manivannan Sadhasivam , Krzysztof Kozlowski Subject: [PATCH v3 03/13] dt-bindings: PCI: qcom: Add SDX55 SoC Date: Wed, 8 Mar 2023 13:54:14 +0530 Message-Id: <20230308082424.140224-4-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230308082424.140224-1-manivannan.sadhasivam@linaro.org> References: <20230308082424.140224-1-manivannan.sadhasivam@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add support for the PCIe controller on the Qcom SDX55 SoC to the binding. Reviewed-by: Krzysztof Kozlowski Signed-off-by: Manivannan Sadhasivam --- .../devicetree/bindings/pci/qcom,pcie.yaml | 28 +++++++++++++++++++ 1 file changed, 28 insertions(+) diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml b/Documen= tation/devicetree/bindings/pci/qcom,pcie.yaml index 55ee86facbc0..35ef56553603 100644 --- a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml +++ b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml @@ -33,6 +33,7 @@ properties: - qcom,pcie-sc8180x - qcom,pcie-sc8280xp - qcom,pcie-sdm845 + - qcom,pcie-sdx55 - qcom,pcie-sm8150 - qcom,pcie-sm8250 - qcom,pcie-sm8350 @@ -203,6 +204,7 @@ allOf: - qcom,pcie-sc7280 - qcom,pcie-sc8180x - qcom,pcie-sc8280xp + - qcom,pcie-sdx55 - qcom,pcie-sm8250 - qcom,pcie-sm8350 - qcom,pcie-sm8450-pcie0 @@ -671,6 +673,32 @@ allOf: items: - const: pci # PCIe core reset =20 + - if: + properties: + compatible: + contains: + enum: + - qcom,pcie-sdx55 + then: + properties: + clocks: + minItems: 7 + maxItems: 7 + clock-names: + items: + - const: pipe # PIPE clock + - const: aux # Auxiliary clock + - const: cfg # Configuration clock + - const: bus_master # Master AXI clock + - const: bus_slave # Slave AXI clock + - const: slave_q2a # Slave Q2A clock + - const: sleep # PCIe Sleep clock + resets: + maxItems: 1 + reset-names: + items: + - const: pci # PCIe core reset + - if: properties: compatible: --=20 2.25.1 From nobody Tue Sep 9 12:06:30 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2C3B6C742A7 for ; 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Wed, 08 Mar 2023 00:24:49 -0800 (PST) Received: from localhost.localdomain ([59.97.52.140]) by smtp.gmail.com with ESMTPSA id s10-20020a170902ea0a00b0019aaab3f9d7sm9448086plg.113.2023.03.08.00.24.45 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 08 Mar 2023 00:24:49 -0800 (PST) From: Manivannan Sadhasivam To: andersson@kernel.org, lpieralisi@kernel.org, robh@kernel.org, kw@linux.com, krzysztof.kozlowski+dt@linaro.org, vkoul@kernel.org Cc: konrad.dybcio@linaro.org, bhelgaas@google.com, kishon@kernel.org, linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org, linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, Manivannan Sadhasivam , Krzysztof Kozlowski Subject: [PATCH v3 04/13] dt-bindings: PCI: qcom-ep: Fix the unit address used in example Date: Wed, 8 Mar 2023 13:54:15 +0530 Message-Id: <20230308082424.140224-5-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230308082424.140224-1-manivannan.sadhasivam@linaro.org> References: <20230308082424.140224-1-manivannan.sadhasivam@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Unit address of PCIe EP node should be 0x1c00000 as it has to match the first address specified in the reg property. Fixes: 31c9ef002580 ("dt-bindings: PCI: Add Qualcomm PCIe Endpoint controll= er") Reviewed-by: Krzysztof Kozlowski Signed-off-by: Manivannan Sadhasivam --- Documentation/devicetree/bindings/pci/qcom,pcie-ep.yaml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie-ep.yaml b/Docu= mentation/devicetree/bindings/pci/qcom,pcie-ep.yaml index 89cfdee4b89f..b7f6fbaa0ba0 100644 --- a/Documentation/devicetree/bindings/pci/qcom,pcie-ep.yaml +++ b/Documentation/devicetree/bindings/pci/qcom,pcie-ep.yaml @@ -166,7 +166,7 @@ examples: #include #include #include - pcie_ep: pcie-ep@40000000 { + pcie_ep: pcie-ep@1c00000 { compatible =3D "qcom,sdx55-pcie-ep"; reg =3D <0x01c00000 0x3000>, <0x40000000 0xf1d>, --=20 2.25.1 From nobody Tue Sep 9 12:06:30 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 99857C74A44 for ; Wed, 8 Mar 2023 08:25:46 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230284AbjCHIZo (ORCPT ); Wed, 8 Mar 2023 03:25:44 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:46668 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230372AbjCHIZC (ORCPT ); Wed, 8 Mar 2023 03:25:02 -0500 Received: from mail-pj1-x1032.google.com (mail-pj1-x1032.google.com [IPv6:2607:f8b0:4864:20::1032]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id E2AEB29149 for ; Wed, 8 Mar 2023 00:24:54 -0800 (PST) Received: by mail-pj1-x1032.google.com with SMTP id y15-20020a17090aa40f00b00237ad8ee3a0so1203601pjp.2 for ; Wed, 08 Mar 2023 00:24:54 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1678263894; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=eLVjhutA2hfGCZ6M883YUXMDKjvpwcVnGmnnfjx/2V0=; b=JZgivbmib2JBc4xEDzQ8oGcl/APFNGx+KsS+9Iy+NNra0VL+pqjs5BekmHJLnHapBU mF/CtoU05zcIBbyqx9lV/bnpDmEhYCasDKiQZfhrqfsJ1ozTKk722NSnO9VIjaERI9ML 5SVmzIYLUzgHWOXJC1zO7SkCZ1iFirQsX8XBqHAH2+hD69mPjuWOMRklpXCTFrAUyhlG 4v/lRpTJ7EfXBR89BTlWyiUzLyeCUXX3ZGnW2t1Nct0NC671DJCdP0nPWt35tem6lB7v h7+zveBybLMYdfXoRzsmSWuHMppzfG2NjAC4Sa8uwEUUxJ/evsQLBJ+RJE1P6rPjFSpO g88Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1678263894; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=eLVjhutA2hfGCZ6M883YUXMDKjvpwcVnGmnnfjx/2V0=; b=tGOT3yhItnY76LS+PfD55sqSSiiCL6CwFbGMEtV0HoXErz+A281XHSfrj49C5j6VZ3 UKHqujH86ruQDZQr/ZHfLKDp5BtMCd0j55pzFyjRpEG54Zq3TVHNhck/G/ICiETWEdBv d3anMGMrwUYPUTLPr4SKqxD/F+0SJhkGepvuhKMCxXgf0Sgo8T7BE2hH8tkBBTfVuO4n anCLGwk9caxkuUQyxGZEkrx++6cVF1GokDFqyS+s2AVRXmdUctMtYCCNamox72xOFf4u xzoJoHF4oAQgMDkS3JEPaZAO52eacP9/Ndkumy0JHklxcbn4BHcUrk0QDgH5qpPZ2SX7 Ev+w== X-Gm-Message-State: AO0yUKW88E0K02ymeYgdqCe7rImV2gE9IrWzFimtLo+6pXyLk6wrZ3tC 8Bepfws26APY5NgSSDd+K+yI X-Google-Smtp-Source: AK7set91RovMZQ6AND4VBKAYwNmUQMvjbtMSJridqM/I4ZipYdc2rWKaVNf6WpTp6n1sdMvtcw9iLg== X-Received: by 2002:a17:902:d492:b0:19d:abd:bb7e with SMTP id c18-20020a170902d49200b0019d0abdbb7emr21509188plg.34.1678263894378; Wed, 08 Mar 2023 00:24:54 -0800 (PST) Received: from localhost.localdomain ([59.97.52.140]) by smtp.gmail.com with ESMTPSA id s10-20020a170902ea0a00b0019aaab3f9d7sm9448086plg.113.2023.03.08.00.24.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 08 Mar 2023 00:24:54 -0800 (PST) From: Manivannan Sadhasivam To: andersson@kernel.org, lpieralisi@kernel.org, robh@kernel.org, kw@linux.com, krzysztof.kozlowski+dt@linaro.org, vkoul@kernel.org Cc: konrad.dybcio@linaro.org, bhelgaas@google.com, kishon@kernel.org, linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org, linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, Manivannan Sadhasivam Subject: [PATCH v3 05/13] ARM: dts: qcom: sdx55: Fix the unit address of PCIe EP node Date: Wed, 8 Mar 2023 13:54:16 +0530 Message-Id: <20230308082424.140224-6-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230308082424.140224-1-manivannan.sadhasivam@linaro.org> References: <20230308082424.140224-1-manivannan.sadhasivam@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Unit address of PCIe EP node should be 0x1c00000 as it has to match the first address specified in the reg property. This also requires sorting the node in the ascending order. Fixes: e6b69813283f ("ARM: dts: qcom: sdx55: Add support for PCIe EP") Reviewed-by: Konrad Dybcio Signed-off-by: Manivannan Sadhasivam --- arch/arm/boot/dts/qcom-sdx55.dtsi | 78 +++++++++++++++---------------- 1 file changed, 39 insertions(+), 39 deletions(-) diff --git a/arch/arm/boot/dts/qcom-sdx55.dtsi b/arch/arm/boot/dts/qcom-sdx= 55.dtsi index df7303c5c843..7fa542249f1a 100644 --- a/arch/arm/boot/dts/qcom-sdx55.dtsi +++ b/arch/arm/boot/dts/qcom-sdx55.dtsi @@ -304,6 +304,45 @@ qpic_nand: nand-controller@1b30000 { status =3D "disabled"; }; =20 + pcie_ep: pcie-ep@1c00000 { + compatible =3D "qcom,sdx55-pcie-ep"; + reg =3D <0x01c00000 0x3000>, + <0x40000000 0xf1d>, + <0x40000f20 0xc8>, + <0x40001000 0x1000>, + <0x40200000 0x100000>, + <0x01c03000 0x3000>; + reg-names =3D "parf", "dbi", "elbi", "atu", "addr_space", + "mmio"; + + qcom,perst-regs =3D <&tcsr 0xb258 0xb270>; + + clocks =3D <&gcc GCC_PCIE_AUX_CLK>, + <&gcc GCC_PCIE_CFG_AHB_CLK>, + <&gcc GCC_PCIE_MSTR_AXI_CLK>, + <&gcc GCC_PCIE_SLV_AXI_CLK>, + <&gcc GCC_PCIE_SLV_Q2A_AXI_CLK>, + <&gcc GCC_PCIE_SLEEP_CLK>, + <&gcc GCC_PCIE_0_CLKREF_CLK>; + clock-names =3D "aux", "cfg", "bus_master", "bus_slave", + "slave_q2a", "sleep", "ref"; + + interrupts =3D , + ; + interrupt-names =3D "global", "doorbell"; + reset-gpios =3D <&tlmm 57 GPIO_ACTIVE_LOW>; + wake-gpios =3D <&tlmm 53 GPIO_ACTIVE_LOW>; + resets =3D <&gcc GCC_PCIE_BCR>; + reset-names =3D "core"; + power-domains =3D <&gcc PCIE_GDSC>; + phys =3D <&pcie0_lane>; + phy-names =3D "pciephy"; + max-link-speed =3D <3>; + num-lanes =3D <2>; + + status =3D "disabled"; + }; + pcie0_phy: phy@1c07000 { compatible =3D "qcom,sdx55-qmp-pcie-phy"; reg =3D <0x01c07000 0x1c4>; @@ -401,45 +440,6 @@ sdhc_1: mmc@8804000 { status =3D "disabled"; }; =20 - pcie_ep: pcie-ep@40000000 { - compatible =3D "qcom,sdx55-pcie-ep"; - reg =3D <0x01c00000 0x3000>, - <0x40000000 0xf1d>, - <0x40000f20 0xc8>, - <0x40001000 0x1000>, - <0x40200000 0x100000>, - <0x01c03000 0x3000>; - reg-names =3D "parf", "dbi", "elbi", "atu", "addr_space", - "mmio"; - - qcom,perst-regs =3D <&tcsr 0xb258 0xb270>; - - clocks =3D <&gcc GCC_PCIE_AUX_CLK>, - <&gcc GCC_PCIE_CFG_AHB_CLK>, - <&gcc GCC_PCIE_MSTR_AXI_CLK>, - <&gcc GCC_PCIE_SLV_AXI_CLK>, - <&gcc GCC_PCIE_SLV_Q2A_AXI_CLK>, - <&gcc GCC_PCIE_SLEEP_CLK>, - <&gcc GCC_PCIE_0_CLKREF_CLK>; - clock-names =3D "aux", "cfg", "bus_master", "bus_slave", - "slave_q2a", "sleep", "ref"; - - interrupts =3D , - ; - interrupt-names =3D "global", "doorbell"; - reset-gpios =3D <&tlmm 57 GPIO_ACTIVE_LOW>; - wake-gpios =3D <&tlmm 53 GPIO_ACTIVE_LOW>; - resets =3D <&gcc GCC_PCIE_BCR>; - reset-names =3D "core"; - power-domains =3D <&gcc PCIE_GDSC>; - phys =3D <&pcie0_lane>; - phy-names =3D "pciephy"; - max-link-speed =3D <3>; - num-lanes =3D <2>; - - status =3D "disabled"; - }; - remoteproc_mpss: remoteproc@4080000 { compatible =3D "qcom,sdx55-mpss-pas"; reg =3D <0x04080000 0x4040>; --=20 2.25.1 From nobody Tue Sep 9 12:06:30 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6256AC678D5 for ; Wed, 8 Mar 2023 08:25:52 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230045AbjCHIZv (ORCPT ); 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Wed, 08 Mar 2023 00:24:58 -0800 (PST) From: Manivannan Sadhasivam To: andersson@kernel.org, lpieralisi@kernel.org, robh@kernel.org, kw@linux.com, krzysztof.kozlowski+dt@linaro.org, vkoul@kernel.org Cc: konrad.dybcio@linaro.org, bhelgaas@google.com, kishon@kernel.org, linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org, linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, Manivannan Sadhasivam Subject: [PATCH v3 06/13] ARM: dts: qcom: sdx55: Rename pcie0_{phy/lane} to pcie_{phy/lane} Date: Wed, 8 Mar 2023 13:54:17 +0530 Message-Id: <20230308082424.140224-7-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230308082424.140224-1-manivannan.sadhasivam@linaro.org> References: <20230308082424.140224-1-manivannan.sadhasivam@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" There is only one PCIe PHY in this SoC, so there is no need to add an index to the suffix. This also matches the naming convention of the PCIe controller. Reviewed-by: Konrad Dybcio Signed-off-by: Manivannan Sadhasivam --- arch/arm/boot/dts/qcom-sdx55-telit-fn980-tlb.dts | 2 +- arch/arm/boot/dts/qcom-sdx55.dtsi | 6 +++--- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm/boot/dts/qcom-sdx55-telit-fn980-tlb.dts b/arch/arm/bo= ot/dts/qcom-sdx55-telit-fn980-tlb.dts index ad74ecc2a196..81f33eba39e5 100644 --- a/arch/arm/boot/dts/qcom-sdx55-telit-fn980-tlb.dts +++ b/arch/arm/boot/dts/qcom-sdx55-telit-fn980-tlb.dts @@ -242,7 +242,7 @@ &ipa { status =3D "okay"; }; =20 -&pcie0_phy { +&pcie_phy { status =3D "okay"; =20 vdda-phy-supply =3D <&vreg_l1e_bb_1p2>; diff --git a/arch/arm/boot/dts/qcom-sdx55.dtsi b/arch/arm/boot/dts/qcom-sdx= 55.dtsi index 7fa542249f1a..bd4edceaa1f4 100644 --- a/arch/arm/boot/dts/qcom-sdx55.dtsi +++ b/arch/arm/boot/dts/qcom-sdx55.dtsi @@ -335,7 +335,7 @@ pcie_ep: pcie-ep@1c00000 { resets =3D <&gcc GCC_PCIE_BCR>; reset-names =3D "core"; power-domains =3D <&gcc PCIE_GDSC>; - phys =3D <&pcie0_lane>; + phys =3D <&pcie_lane>; phy-names =3D "pciephy"; max-link-speed =3D <3>; num-lanes =3D <2>; @@ -343,7 +343,7 @@ pcie_ep: pcie-ep@1c00000 { status =3D "disabled"; }; =20 - pcie0_phy: phy@1c07000 { + pcie_phy: phy@1c07000 { compatible =3D "qcom,sdx55-qmp-pcie-phy"; reg =3D <0x01c07000 0x1c4>; #address-cells =3D <1>; @@ -363,7 +363,7 @@ pcie0_phy: phy@1c07000 { =20 status =3D "disabled"; =20 - pcie0_lane: lanes@1c06000 { + pcie_lane: lanes@1c06000 { reg =3D <0x01c06000 0x104>, /* tx0 */ <0x01c06200 0x328>, /* rx0 */ <0x01c07200 0x1e8>, /* pcs */ --=20 2.25.1 From nobody Tue Sep 9 12:06:30 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 90FDAC7618D for ; Wed, 8 Mar 2023 08:26:02 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230196AbjCHI0A (ORCPT ); Wed, 8 Mar 2023 03:26:00 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:44916 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229717AbjCHIZG (ORCPT ); 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Wed, 08 Mar 2023 00:25:02 -0800 (PST) From: Manivannan Sadhasivam To: andersson@kernel.org, lpieralisi@kernel.org, robh@kernel.org, kw@linux.com, krzysztof.kozlowski+dt@linaro.org, vkoul@kernel.org Cc: konrad.dybcio@linaro.org, bhelgaas@google.com, kishon@kernel.org, linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org, linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, Manivannan Sadhasivam Subject: [PATCH v3 07/13] ARM: dts: qcom: sdx55: Add support for PCIe RC controller Date: Wed, 8 Mar 2023 13:54:18 +0530 Message-Id: <20230308082424.140224-8-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230308082424.140224-1-manivannan.sadhasivam@linaro.org> References: <20230308082424.140224-1-manivannan.sadhasivam@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" The PCIe controller in SDX55 can act as the RC controller also. Let's add support for it. Reviewed-by: Konrad Dybcio Signed-off-by: Manivannan Sadhasivam --- arch/arm/boot/dts/qcom-sdx55.dtsi | 81 +++++++++++++++++++++++++++++++ 1 file changed, 81 insertions(+) diff --git a/arch/arm/boot/dts/qcom-sdx55.dtsi b/arch/arm/boot/dts/qcom-sdx= 55.dtsi index bd4edceaa1f4..9dabb94eafbc 100644 --- a/arch/arm/boot/dts/qcom-sdx55.dtsi +++ b/arch/arm/boot/dts/qcom-sdx55.dtsi @@ -304,6 +304,87 @@ qpic_nand: nand-controller@1b30000 { status =3D "disabled"; }; =20 + pcie_rc: pcie@1c00000 { + compatible =3D "qcom,pcie-sdx55"; + reg =3D <0x01c00000 0x3000>, + <0x40000000 0xf1d>, + <0x40000f20 0xc8>, + <0x40001000 0x1000>, + <0x40100000 0x100000>; + reg-names =3D "parf", + "dbi", + "elbi", + "atu", + "config"; + device_type =3D "pci"; + linux,pci-domain =3D <0>; + bus-range =3D <0x00 0xff>; + num-lanes =3D <1>; + + #address-cells =3D <3>; + #size-cells =3D <2>; + + ranges =3D <0x01000000 0x0 0x00000000 0x40200000 0x0 0x100000>, + <0x02000000 0x0 0x40300000 0x40300000 0x0 0x3fd00000>; + + interrupts =3D , + , + , + , + , + , + , + ; + interrupt-names =3D "msi", + "msi2", + "msi3", + "msi4", + "msi5", + "msi6", + "msi7", + "msi8"; + #interrupt-cells =3D <1>; + interrupt-map-mask =3D <0 0 0 0x7>; + interrupt-map =3D <0 0 0 1 &intc 0 0 0 141 IRQ_TYPE_LEVEL_HIGH>, /* int= _a */ + <0 0 0 2 &intc 0 0 0 142 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ + <0 0 0 3 &intc 0 0 0 143 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ + <0 0 0 4 &intc 0 0 0 144 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ + + clocks =3D <&gcc GCC_PCIE_PIPE_CLK>, + <&gcc GCC_PCIE_AUX_CLK>, + <&gcc GCC_PCIE_CFG_AHB_CLK>, + <&gcc GCC_PCIE_MSTR_AXI_CLK>, + <&gcc GCC_PCIE_SLV_AXI_CLK>, + <&gcc GCC_PCIE_SLV_Q2A_AXI_CLK>, + <&gcc GCC_PCIE_SLEEP_CLK>; + clock-names =3D "pipe", + "aux", + "cfg", + "bus_master", + "bus_slave", + "slave_q2a", + "sleep"; + + assigned-clocks =3D <&gcc GCC_PCIE_AUX_CLK>; + assigned-clock-rates =3D <19200000>; + + iommu-map =3D <0x0 &apps_smmu 0x0200 0x1>, + <0x100 &apps_smmu 0x0201 0x1>, + <0x200 &apps_smmu 0x0202 0x1>, + <0x300 &apps_smmu 0x0203 0x1>, + <0x400 &apps_smmu 0x0204 0x1>; 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charset="utf-8" To align with the rest of the devicetree files and the relative properties, let's list the values of properties such as {reg/clock/interrupt}-names vertically. Suggested-by: Konrad Dybcio Reviewed-by: Konrad Dybcio Signed-off-by: Manivannan Sadhasivam --- arch/arm/boot/dts/qcom-sdx55.dtsi | 23 ++++++++++++++++++----- 1 file changed, 18 insertions(+), 5 deletions(-) diff --git a/arch/arm/boot/dts/qcom-sdx55.dtsi b/arch/arm/boot/dts/qcom-sdx= 55.dtsi index 9dabb94eafbc..286fa92da428 100644 --- a/arch/arm/boot/dts/qcom-sdx55.dtsi +++ b/arch/arm/boot/dts/qcom-sdx55.dtsi @@ -393,7 +393,11 @@ pcie_ep: pcie-ep@1c00000 { <0x40001000 0x1000>, <0x40200000 0x100000>, <0x01c03000 0x3000>; - reg-names =3D "parf", "dbi", "elbi", "atu", "addr_space", + reg-names =3D "parf", + "dbi", + "elbi", + "atu", + "addr_space", "mmio"; =20 qcom,perst-regs =3D <&tcsr 0xb258 0xb270>; @@ -405,12 +409,18 @@ pcie_ep: pcie-ep@1c00000 { <&gcc GCC_PCIE_SLV_Q2A_AXI_CLK>, <&gcc GCC_PCIE_SLEEP_CLK>, <&gcc GCC_PCIE_0_CLKREF_CLK>; - clock-names =3D "aux", "cfg", "bus_master", "bus_slave", - "slave_q2a", "sleep", "ref"; + clock-names =3D "aux", + "cfg", + "bus_master", + "bus_slave", + "slave_q2a", + "sleep", + "ref"; =20 interrupts =3D , ; - interrupt-names =3D "global", "doorbell"; + interrupt-names =3D "global", + "doorbell"; reset-gpios =3D <&tlmm 57 GPIO_ACTIVE_LOW>; wake-gpios =3D <&tlmm 53 GPIO_ACTIVE_LOW>; resets =3D <&gcc GCC_PCIE_BCR>; @@ -434,7 +444,10 @@ pcie_phy: phy@1c07000 { <&gcc GCC_PCIE_CFG_AHB_CLK>, <&gcc GCC_PCIE_0_CLKREF_CLK>, <&gcc GCC_PCIE_RCHNG_PHY_CLK>; - clock-names =3D "aux", "cfg_ahb", "ref", "refgen"; + clock-names =3D "aux", + "cfg_ahb", + "ref", + "refgen"; =20 resets =3D <&gcc GCC_PCIE_PHY_BCR>; reset-names =3D "phy"; --=20 2.25.1 From nobody Tue Sep 9 12:06:30 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id A54B6C64EC4 for ; Wed, 8 Mar 2023 08:26:14 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230192AbjCHI0N (ORCPT ); Wed, 8 Mar 2023 03:26:13 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:39574 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230145AbjCHIZV (ORCPT ); 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Wed, 08 Mar 2023 00:25:11 -0800 (PST) From: Manivannan Sadhasivam To: andersson@kernel.org, lpieralisi@kernel.org, robh@kernel.org, kw@linux.com, krzysztof.kozlowski+dt@linaro.org, vkoul@kernel.org Cc: konrad.dybcio@linaro.org, bhelgaas@google.com, kishon@kernel.org, linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org, linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, Manivannan Sadhasivam Subject: [PATCH v3 09/13] ARM: dts: qcom: sdx55-t55: Enable PCIe RC support Date: Wed, 8 Mar 2023 13:54:20 +0530 Message-Id: <20230308082424.140224-10-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230308082424.140224-1-manivannan.sadhasivam@linaro.org> References: <20230308082424.140224-1-manivannan.sadhasivam@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Enable PCIe RC support on Thundercomm T55 board. Reviewed-by: Konrad Dybcio Signed-off-by: Manivannan Sadhasivam --- arch/arm/boot/dts/qcom-sdx55-t55.dts | 42 ++++++++++++++++++++++++++++ 1 file changed, 42 insertions(+) diff --git a/arch/arm/boot/dts/qcom-sdx55-t55.dts b/arch/arm/boot/dts/qcom-= sdx55-t55.dts index d5343bb0daee..5edc09af8e0d 100644 --- a/arch/arm/boot/dts/qcom-sdx55-t55.dts +++ b/arch/arm/boot/dts/qcom-sdx55-t55.dts @@ -242,6 +242,23 @@ &ipa { status =3D "okay"; }; =20 +&pcie_phy { + vdda-phy-supply =3D <&vreg_l1e_bb_1p2>; + vdda-pll-supply =3D <&vreg_l4e_bb_0p875>; + + status =3D "okay"; +}; + +&pcie_rc { + perst-gpios =3D <&tlmm 57 GPIO_ACTIVE_LOW>; + wake-gpios =3D <&tlmm 53 GPIO_ACTIVE_HIGH>; + + pinctrl-0 =3D <&pcie_default>; + pinctrl-names =3D "default"; + + status =3D "okay"; +}; + &qpic_bam { status =3D "okay"; }; @@ -265,6 +282,31 @@ &remoteproc_mpss { memory-region =3D <&mpss_adsp_mem>; }; =20 +&tlmm { + pcie_default: pcie-default-state { + clkreq-pins { + pins =3D "gpio56"; + function =3D "pcie_clkreq"; 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charset="utf-8" To align with rest of the devicetree files, let's move the "status" property down Suggested-by: Konrad Dybcio Reviewed-by: Konrad Dybcio Signed-off-by: Manivannan Sadhasivam --- arch/arm/boot/dts/qcom-sdx55-t55.dts | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) diff --git a/arch/arm/boot/dts/qcom-sdx55-t55.dts b/arch/arm/boot/dts/qcom-= sdx55-t55.dts index 5edc09af8e0d..51058b065279 100644 --- a/arch/arm/boot/dts/qcom-sdx55-t55.dts +++ b/arch/arm/boot/dts/qcom-sdx55-t55.dts @@ -278,8 +278,8 @@ nand@0 { }; =20 &remoteproc_mpss { - status =3D "okay"; memory-region =3D <&mpss_adsp_mem>; + status =3D "okay"; }; =20 &tlmm { @@ -308,16 +308,18 @@ wake-pins { }; =20 &usb_hsphy { - status =3D "okay"; vdda-pll-supply =3D <&vreg_l4e_bb_0p875>; vdda33-supply =3D <&vreg_l10e_3p1>; vdda18-supply =3D <&vreg_l5e_bb_1p7>; + + status =3D "okay"; }; =20 &usb_qmpphy { - status =3D "okay"; vdda-phy-supply =3D <&vreg_l4e_bb_0p875>; vdda-pll-supply =3D <&vreg_l1e_bb_1p2>; + + status =3D "okay"; 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Wed, 08 Mar 2023 00:25:21 -0800 (PST) Received: from localhost.localdomain ([59.97.52.140]) by smtp.gmail.com with ESMTPSA id s10-20020a170902ea0a00b0019aaab3f9d7sm9448086plg.113.2023.03.08.00.25.16 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 08 Mar 2023 00:25:21 -0800 (PST) From: Manivannan Sadhasivam To: andersson@kernel.org, lpieralisi@kernel.org, robh@kernel.org, kw@linux.com, krzysztof.kozlowski+dt@linaro.org, vkoul@kernel.org Cc: konrad.dybcio@linaro.org, bhelgaas@google.com, kishon@kernel.org, linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org, linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, Manivannan Sadhasivam Subject: [PATCH v3 11/13] phy: qcom-qmp-pcie: Split out EP related init sequence for SDX55 Date: Wed, 8 Mar 2023 13:54:22 +0530 Message-Id: <20230308082424.140224-12-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230308082424.140224-1-manivannan.sadhasivam@linaro.org> References: <20230308082424.140224-1-manivannan.sadhasivam@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" In preparation for adding RC support, let's split out the EP related init sequence so that the common sequence could be reused by RC as well. Signed-off-by: Manivannan Sadhasivam --- drivers/phy/qualcomm/phy-qcom-qmp-pcie.c | 42 ++++++++++++++++-------- 1 file changed, 28 insertions(+), 14 deletions(-) diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c b/drivers/phy/qualcom= m/phy-qcom-qmp-pcie.c index 5182aeac43ee..35328e998699 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c +++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c @@ -1130,10 +1130,25 @@ static const struct qmp_phy_init_tbl sm8250_qmp_gen= 3x2_pcie_pcs_misc_tbl[] =3D { }; =20 static const struct qmp_phy_init_tbl sdx55_qmp_pcie_serdes_tbl[] =3D { - QMP_PHY_INIT_CFG(QSERDES_V4_COM_BG_TIMER, 0x02), QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIAS_EN_CLKBUFLR_EN, 0x18), - QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYS_CLK_CTRL, 0x07), QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_IVCO, 0x0f), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x46), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_CFG, 0x04), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x02), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x12), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_HS_SWITCH_SEL, 0x00), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE0, 0x05), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE1, 0x04), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_MISC1, 0x88), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_MISC2, 0x03), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_MODE, 0x17), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_DC_LEVEL_CTRL, 0x0b), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_HSCLK_SEL, 0x22), +}; + +static const struct qmp_phy_init_tbl sdx55_qmp_pcie_ep_serdes_tbl[] =3D { + QMP_PHY_INIT_CFG(QSERDES_V4_COM_BG_TIMER, 0x02), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYS_CLK_CTRL, 0x07), QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x0a), QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE1, 0x0a), QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x19), @@ -1141,8 +1156,6 @@ static const struct qmp_phy_init_tbl sdx55_qmp_pcie_s= erdes_tbl[] =3D { QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x03), QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE1, 0x03), QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0x00), - QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x46), - QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_CFG, 0x04), QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x7f), QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x02), QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE1, 0xff), @@ -1154,21 +1167,11 @@ static const struct qmp_phy_init_tbl sdx55_qmp_pcie= _serdes_tbl[] =3D { QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTEGLOOP_GAIN1_MODE0, 0x01), QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTEGLOOP_GAIN0_MODE1, 0xfb), QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTEGLOOP_GAIN1_MODE1, 0x01), - QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x02), - QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x12), - QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_HS_SWITCH_SEL, 0x00), - QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE0, 0x05), - QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE1, 0x04), QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_CONFIG, 0x04), - QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_MISC1, 0x88), - QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_MISC2, 0x03), - QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_MODE, 0x17), - QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_DC_LEVEL_CTRL, 0x0b), QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0x56), QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1d), QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0x4b), QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x1f), - QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_HSCLK_SEL, 0x22), }; =20 static const struct qmp_phy_init_tbl sdx55_qmp_pcie_tx_tbl[] =3D { @@ -1220,6 +1223,9 @@ static const struct qmp_phy_init_tbl sdx55_qmp_pcie_p= cs_misc_tbl[] =3D { QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_PCIE_G4_RXEQEVAL_TIME, 0x13), QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_PCIE_G4_EQ_CONFIG2, 0x01), QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_PCIE_G4_EQ_CONFIG5, 0x02), +}; + +static const struct qmp_phy_init_tbl sdx55_qmp_pcie_ep_pcs_misc_tbl[] =3D { QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_LANE1_INSIG_SW_CTRL2, 0x00), QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_LANE1_INSIG_MX_CTRL2, 0x00), }; @@ -2301,6 +2307,14 @@ static const struct qmp_phy_cfg sdx55_qmp_pciephy_cf= g =3D { .pcs_misc =3D sdx55_qmp_pcie_pcs_misc_tbl, .pcs_misc_num =3D ARRAY_SIZE(sdx55_qmp_pcie_pcs_misc_tbl), }, + + .tbls_ep =3D &(const struct qmp_phy_cfg_tbls) { + .serdes =3D sdx55_qmp_pcie_ep_serdes_tbl, + .serdes_num =3D ARRAY_SIZE(sdx55_qmp_pcie_ep_serdes_tbl), + .pcs_misc =3D sdx55_qmp_pcie_ep_pcs_misc_tbl, + .pcs_misc_num =3D ARRAY_SIZE(sdx55_qmp_pcie_ep_pcs_misc_tbl), + }, + .clk_list =3D sdm845_pciephy_clk_l, .num_clks =3D ARRAY_SIZE(sdm845_pciephy_clk_l), .reset_list =3D sdm845_pciephy_reset_l, --=20 2.25.1 From nobody Tue Sep 9 12:06:30 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 24E21C742A7 for ; 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Wed, 08 Mar 2023 00:25:27 -0800 (PST) From: Manivannan Sadhasivam To: andersson@kernel.org, lpieralisi@kernel.org, robh@kernel.org, kw@linux.com, krzysztof.kozlowski+dt@linaro.org, vkoul@kernel.org Cc: konrad.dybcio@linaro.org, bhelgaas@google.com, kishon@kernel.org, linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org, linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, Manivannan Sadhasivam Subject: [PATCH v3 12/13] phy: qcom-qmp-pcie: Add RC init sequence for SDX55 Date: Wed, 8 Mar 2023 13:54:23 +0530 Message-Id: <20230308082424.140224-13-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230308082424.140224-1-manivannan.sadhasivam@linaro.org> References: <20230308082424.140224-1-manivannan.sadhasivam@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add PCIe RC init sequence making use of the common init sequence. The RC mode additionally requires REFCLK_DRV_DSBL bit to set during powerup and powerdown. Signed-off-by: Manivannan Sadhasivam --- drivers/phy/qualcomm/phy-qcom-qmp-pcie.c | 49 ++++++++++++++++++- .../qualcomm/phy-qcom-qmp-pcs-pcie-v4_20.h | 2 + 2 files changed, 50 insertions(+), 1 deletion(-) diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c b/drivers/phy/qualcom= m/phy-qcom-qmp-pcie.c index 35328e998699..d671748bc097 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c +++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c @@ -1146,6 +1146,41 @@ static const struct qmp_phy_init_tbl sdx55_qmp_pcie_= serdes_tbl[] =3D { QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_HSCLK_SEL, 0x22), }; =20 +static const struct qmp_phy_init_tbl sdx55_qmp_pcie_rc_serdes_tbl[] =3D { + QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_EN_CENTER, 0x01), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER1, 0x31), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER2, 0x01), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE0, 0xce), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE0, 0x0b), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE1, 0x97), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE1, 0x0c), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_ENABLE1, 0x90), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_EP_DIV_MODE0, 0x0a), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_EP_DIV_MODE1, 0x10), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x06), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE1, 0x06), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x16), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE1, 0x16), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x36), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE1, 0x36), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0x08), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x04), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x0d), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE1, 0x0a), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE1, 0x1a), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0xc3), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE1, 0xd0), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x05), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE1, 0x55), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE1, 0x55), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE1, 0x05), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_SELECT, 0x34), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xca), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xd8), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x20), +}; + static const struct qmp_phy_init_tbl sdx55_qmp_pcie_ep_serdes_tbl[] =3D { QMP_PHY_INIT_CFG(QSERDES_V4_COM_BG_TIMER, 0x02), QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYS_CLK_CTRL, 0x07), @@ -1225,6 +1260,11 @@ static const struct qmp_phy_init_tbl sdx55_qmp_pcie_= pcs_misc_tbl[] =3D { QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_PCIE_G4_EQ_CONFIG5, 0x02), }; =20 +static const struct qmp_phy_init_tbl sdx55_qmp_pcie_rc_pcs_misc_tbl[] =3D { + QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1), + QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_PCIE_OSC_DTCT_ACTIONS, 0x00), +}; + static const struct qmp_phy_init_tbl sdx55_qmp_pcie_ep_pcs_misc_tbl[] =3D { QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_LANE1_INSIG_SW_CTRL2, 0x00), QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_LANE1_INSIG_MX_CTRL2, 0x00), @@ -2308,6 +2348,13 @@ static const struct qmp_phy_cfg sdx55_qmp_pciephy_cf= g =3D { .pcs_misc_num =3D ARRAY_SIZE(sdx55_qmp_pcie_pcs_misc_tbl), }, =20 + .tbls_rc =3D &(const struct qmp_phy_cfg_tbls) { + .serdes =3D sdx55_qmp_pcie_rc_serdes_tbl, + .serdes_num =3D ARRAY_SIZE(sdx55_qmp_pcie_rc_serdes_tbl), + .pcs_misc =3D sdx55_qmp_pcie_rc_pcs_misc_tbl, + .pcs_misc_num =3D ARRAY_SIZE(sdx55_qmp_pcie_rc_pcs_misc_tbl), + }, + .tbls_ep =3D &(const struct qmp_phy_cfg_tbls) { .serdes =3D sdx55_qmp_pcie_ep_serdes_tbl, .serdes_num =3D ARRAY_SIZE(sdx55_qmp_pcie_ep_serdes_tbl), @@ -2323,7 +2370,7 @@ static const struct qmp_phy_cfg sdx55_qmp_pciephy_cfg= =3D { .num_vregs =3D ARRAY_SIZE(qmp_phy_vreg_l), .regs =3D pciephy_v4_regs_layout, =20 - .pwrdn_ctrl =3D SW_PWRDN, + .pwrdn_ctrl =3D SW_PWRDN | REFCLK_DRV_DSBL, .phy_status =3D PHYSTATUS_4_20, }; =20 diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcs-pcie-v4_20.h b/drivers/p= hy/qualcomm/phy-qcom-qmp-pcs-pcie-v4_20.h index af273602998e..ac872a9eff9a 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp-pcs-pcie-v4_20.h +++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcs-pcie-v4_20.h @@ -6,6 +6,8 @@ #ifndef QCOM_PHY_QMP_PCS_PCIE_V4_20_H_ #define QCOM_PHY_QMP_PCS_PCIE_V4_20_H_ =20 +#define QPHY_V4_20_PCS_PCIE_ENDPOINT_REFCLK_DRIVE 0x01c +#define QPHY_V4_20_PCS_PCIE_OSC_DTCT_ACTIONS 0x090 #define QPHY_V4_20_PCS_PCIE_EQ_CONFIG1 0x0a0 #define QPHY_V4_20_PCS_PCIE_G3_RXEQEVAL_TIME 0x0f0 #define QPHY_V4_20_PCS_PCIE_G4_RXEQEVAL_TIME 0x0f4 --=20 2.25.1 From nobody Tue Sep 9 12:06:30 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id E6B80C64EC4 for ; Wed, 8 Mar 2023 08:27:13 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230338AbjCHI1L (ORCPT ); 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Wed, 08 Mar 2023 00:25:33 -0800 (PST) From: Manivannan Sadhasivam To: andersson@kernel.org, lpieralisi@kernel.org, robh@kernel.org, kw@linux.com, krzysztof.kozlowski+dt@linaro.org, vkoul@kernel.org Cc: konrad.dybcio@linaro.org, bhelgaas@google.com, kishon@kernel.org, linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org, linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, Manivannan Sadhasivam Subject: [PATCH v3 13/13] PCI: qcom: Add support for SDX55 SoC Date: Wed, 8 Mar 2023 13:54:24 +0530 Message-Id: <20230308082424.140224-14-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230308082424.140224-1-manivannan.sadhasivam@linaro.org> References: <20230308082424.140224-1-manivannan.sadhasivam@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add support for SDX55 SoC reusing the 1.9.0 config. The PCIe controller is of version 1.10.0 but it is compatible with the 1.9.0 config. This SoC also requires "sleep" clock which is added as an optional clock in the driver, since it is not required on other SoCs. Signed-off-by: Manivannan Sadhasivam --- drivers/pci/controller/dwc/pcie-qcom.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controlle= r/dwc/pcie-qcom.c index a232b04af048..17dd26cbfd61 100644 --- a/drivers/pci/controller/dwc/pcie-qcom.c +++ b/drivers/pci/controller/dwc/pcie-qcom.c @@ -182,7 +182,7 @@ struct qcom_pcie_resources_2_3_3 { =20 /* 6 clocks typically, 7 for sm8250 */ struct qcom_pcie_resources_2_7_0 { - struct clk_bulk_data clks[12]; + struct clk_bulk_data clks[13]; int num_clks; struct regulator_bulk_data supplies[2]; struct reset_control *pci_reset; @@ -1208,6 +1208,7 @@ static int qcom_pcie_get_resources_2_7_0(struct qcom_= pcie *pcie) res->clks[idx++].id =3D "noc_aggr_4"; res->clks[idx++].id =3D "noc_aggr_south_sf"; res->clks[idx++].id =3D "cnoc_qx"; + res->clks[idx++].id =3D "sleep"; =20 num_opt_clks =3D idx - num_clks; res->num_clks =3D idx; @@ -1836,6 +1837,7 @@ static const struct of_device_id qcom_pcie_match[] = =3D { { .compatible =3D "qcom,pcie-sc8180x", .data =3D &cfg_1_9_0 }, { .compatible =3D "qcom,pcie-sc8280xp", .data =3D &cfg_1_9_0 }, { .compatible =3D "qcom,pcie-sdm845", .data =3D &cfg_2_7_0 }, + { .compatible =3D "qcom,pcie-sdx55", .data =3D &cfg_1_9_0 }, { .compatible =3D "qcom,pcie-sm8150", .data =3D &cfg_1_9_0 }, { .compatible =3D "qcom,pcie-sm8250", .data =3D &cfg_1_9_0 }, { .compatible =3D "qcom,pcie-sm8350", .data =3D &cfg_1_9_0 }, --=20 2.25.1