From nobody Wed Sep 10 05:46:15 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9B97DC678D5 for ; Wed, 8 Mar 2023 15:40:37 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230071AbjCHPkg (ORCPT ); Wed, 8 Mar 2023 10:40:36 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:32784 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232414AbjCHPkK (ORCPT ); Wed, 8 Mar 2023 10:40:10 -0500 Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 1BF91B8F16 for ; Wed, 8 Mar 2023 07:39:50 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1678289990; x=1709825990; h=from:date:subject:mime-version:content-transfer-encoding: message-id:references:in-reply-to:to:cc; bh=UFsc11qcv0An3YTgsx2jUXx1nEcHzBdMgxW2w6BVW+0=; b=MACEQGZmaVuwhCs7LR/uQarID42E+EPlwAMla0aSVcu3DH6MYc3Ehbmw yXpZm/xLQIUqUSp9TXgiMVx3/p3U7j2oawiOyRzuA1oTZY7Xoq4VlO9yT dJA/6cJ3m6A9HWWI9ovnfQHqsZE672GSYLnZdpy0IyIk9gH9BuXdpbeS6 uCWPzLJpH/cNoUhyDgUZOBnZx74s/LtIVPkTr/8dMtL2D2mR4vk30hXMu diVHnds+untvk1QMH96rlAs9B/K++bshEd3SZrPFdZ/6wN+hhkPSnjSQP mwdnCOMd55EnuLYEiWm1QM5jDM5wI6n3KuaZozbCmub7C6EDCjttHdu3o g==; X-IronPort-AV: E=McAfee;i="6500,9779,10642"; a="337703537" X-IronPort-AV: E=Sophos;i="5.98,244,1673942400"; d="scan'208";a="337703537" Received: from fmsmga002.fm.intel.com ([10.253.24.26]) by orsmga102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 08 Mar 2023 07:39:46 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10642"; a="787160246" X-IronPort-AV: E=Sophos;i="5.98,244,1673942400"; d="scan'208";a="787160246" Received: from lab-ah.igk.intel.com ([10.102.42.211]) by fmsmga002-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 08 Mar 2023 07:39:44 -0800 From: Andrzej Hajda Date: Wed, 08 Mar 2023 16:39:03 +0100 Subject: [PATCH v5 1/4] drm/i915/gt: make nop_clear_range public MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20230308-guard_error_capture-v5-1-6d1410d13540@intel.com> References: <20230308-guard_error_capture-v5-0-6d1410d13540@intel.com> In-Reply-To: <20230308-guard_error_capture-v5-0-6d1410d13540@intel.com> To: Jani Nikula , Joonas Lahtinen , Rodrigo Vivi , Tvrtko Ursulin Cc: intel-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org, Andi Shyti , Chris Wilson , Nirmoy Das , Andrzej Hajda X-Mailer: b4 0.11.1 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Function nop_clear_range can be used instead of local implementations. Signed-off-by: Andrzej Hajda Reviewed-by: Andi Shyti --- drivers/gpu/drm/i915/gt/intel_ggtt.c | 3 +-- drivers/gpu/drm/i915/gt/intel_gtt.h | 2 ++ 2 files changed, 3 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/gt/intel_ggtt.c b/drivers/gpu/drm/i915/gt= /intel_ggtt.c index 842e69c7b21e49..b925da42c7cfc4 100644 --- a/drivers/gpu/drm/i915/gt/intel_ggtt.c +++ b/drivers/gpu/drm/i915/gt/intel_ggtt.c @@ -345,8 +345,7 @@ static void gen6_ggtt_insert_entries(struct i915_addres= s_space *vm, ggtt->invalidate(ggtt); } =20 -static void nop_clear_range(struct i915_address_space *vm, - u64 start, u64 length) +void nop_clear_range(struct i915_address_space *vm, u64 start, u64 length) { } =20 diff --git a/drivers/gpu/drm/i915/gt/intel_gtt.h b/drivers/gpu/drm/i915/gt/= intel_gtt.h index 5a775310d3fcb5..c15a4892e9f45d 100644 --- a/drivers/gpu/drm/i915/gt/intel_gtt.h +++ b/drivers/gpu/drm/i915/gt/intel_gtt.h @@ -672,4 +672,6 @@ static inline struct sgt_dma { return (struct sgt_dma){ sg, addr, addr + sg_dma_len(sg) }; } =20 +void nop_clear_range(struct i915_address_space *vm, u64 start, u64 length); + #endif --=20 2.34.1 From nobody Wed Sep 10 05:46:15 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2EA65C678D5 for ; Wed, 8 Mar 2023 15:40:50 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231134AbjCHPkp (ORCPT ); Wed, 8 Mar 2023 10:40:45 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:32870 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232431AbjCHPkN (ORCPT ); Wed, 8 Mar 2023 10:40:13 -0500 Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id C576238667 for ; Wed, 8 Mar 2023 07:39:51 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1678289991; x=1709825991; h=from:date:subject:mime-version:content-transfer-encoding: message-id:references:in-reply-to:to:cc; bh=Se/biot0lVFjHYoy6HUt2Ws+mFr0uN1AGnXhhRrqKoQ=; b=ifRZDgduRD7frqZ+g68XDawNtJbLPkzR8BvZFhHMvMMvaoHdXUNyE96j 8PpL68NuKDPYiOfMF2os9kqA3hJWWOraIFYnqFLcxBqUWj0ZZjMFPdVG0 5pSWNkqKQWbQestNRibo89Ks4Vs1M1Xi0EcUstYZgA9hJU16q2iAcwjR7 bW3zLp6QA9rjAbOhcLTxZHXOnr/qC8gWCaWPz/BLcVU259YGGuXehFdrK RkQLhXLT+/P/s8QiPpBotHcFswtB30Jb1gcHrNqtNFdtOAxle7KUo1iTu qF4xJWHYmKHmUq5h+eVle5HTq0fkZXh3lue26BBDz8rADObHGwdVVJsFs Q==; X-IronPort-AV: E=McAfee;i="6500,9779,10642"; a="337703559" X-IronPort-AV: E=Sophos;i="5.98,244,1673942400"; d="scan'208";a="337703559" Received: from fmsmga002.fm.intel.com ([10.253.24.26]) by orsmga102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 08 Mar 2023 07:39:49 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10642"; a="787160261" X-IronPort-AV: E=Sophos;i="5.98,244,1673942400"; d="scan'208";a="787160261" Received: from lab-ah.igk.intel.com ([10.102.42.211]) by fmsmga002-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 08 Mar 2023 07:39:46 -0800 From: Andrzej Hajda Date: Wed, 08 Mar 2023 16:39:04 +0100 Subject: [PATCH v5 2/4] drm/i915/display: use nop_clear_range instead of local function MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20230308-guard_error_capture-v5-2-6d1410d13540@intel.com> References: <20230308-guard_error_capture-v5-0-6d1410d13540@intel.com> In-Reply-To: <20230308-guard_error_capture-v5-0-6d1410d13540@intel.com> To: Jani Nikula , Joonas Lahtinen , Rodrigo Vivi , Tvrtko Ursulin Cc: intel-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org, Andi Shyti , Chris Wilson , Nirmoy Das , Andrzej Hajda X-Mailer: b4 0.11.1 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Since nop_clear_range is visible it can be used here. Signed-off-by: Andrzej Hajda Reviewed-by: Andi Shyti --- drivers/gpu/drm/i915/display/intel_dpt.c | 7 +------ 1 file changed, 1 insertion(+), 6 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_dpt.c b/drivers/gpu/drm/i91= 5/display/intel_dpt.c index ad1a37b515fb1c..eb9d1a6cbfb9dd 100644 --- a/drivers/gpu/drm/i915/display/intel_dpt.c +++ b/drivers/gpu/drm/i915/display/intel_dpt.c @@ -73,11 +73,6 @@ static void dpt_insert_entries(struct i915_address_space= *vm, gen8_set_pte(&base[i++], pte_encode | addr); } =20 -static void dpt_clear_range(struct i915_address_space *vm, - u64 start, u64 length) -{ -} - static void dpt_bind_vma(struct i915_address_space *vm, struct i915_vm_pt_stash *stash, struct i915_vma_resource *vma_res, @@ -291,7 +286,7 @@ intel_dpt_create(struct intel_framebuffer *fb) i915_address_space_init(vm, VM_CLASS_DPT); =20 vm->insert_page =3D dpt_insert_page; - vm->clear_range =3D dpt_clear_range; + vm->clear_range =3D nop_clear_range; vm->insert_entries =3D dpt_insert_entries; vm->cleanup =3D dpt_cleanup; =20 --=20 2.34.1 From nobody Wed Sep 10 05:46:15 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id A9993C64EC4 for ; Wed, 8 Mar 2023 15:41:09 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231418AbjCHPlI (ORCPT ); Wed, 8 Mar 2023 10:41:08 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:39022 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232519AbjCHPkZ (ORCPT ); Wed, 8 Mar 2023 10:40:25 -0500 Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 7C9095D26A for ; Wed, 8 Mar 2023 07:40:09 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1678290009; x=1709826009; h=from:date:subject:mime-version:content-transfer-encoding: message-id:references:in-reply-to:to:cc; bh=wG3vf2+xlpzOKdj5dCj9/rgBBguHqYIRNINuZ3j1/Dc=; b=m+3DxtLKGcIi07Hge9SmupV9IN8MFNYT93ZRY2OtqsaBpp7/u1eBSJQB iOjfy+0SmPm22zxkeO4ycCoe8Iem6SYNqAH+0doNN0ckMY92UGxhQRkBT o422fkrOy2sH0aeDd6d4MnrZ7qInirdg1j+S8H/X4BkfyK1MxOnuN0Nwi R2oEkO3DyKdWnwEu+56kuxbyc4pPyFrV4qKjZsS8SsqB9wI8FK5eAfzCm wWIR77R0W+IxTA1q3mkMyEdQG9uM+NP8uphDlWWkvhEYsmP0LY3l4kfXS Tah2Ww5qmmeNWHi3xEXTR2XG5Azf5DRYgpV8VpQdaM6EkgrdQyAwhi3L6 Q==; X-IronPort-AV: E=McAfee;i="6500,9779,10642"; a="337703576" X-IronPort-AV: E=Sophos;i="5.98,244,1673942400"; d="scan'208";a="337703576" Received: from fmsmga002.fm.intel.com ([10.253.24.26]) by orsmga102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 08 Mar 2023 07:39:51 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10642"; a="787160279" X-IronPort-AV: E=Sophos;i="5.98,244,1673942400"; d="scan'208";a="787160279" Received: from lab-ah.igk.intel.com ([10.102.42.211]) by fmsmga002-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 08 Mar 2023 07:39:49 -0800 From: Andrzej Hajda Date: Wed, 08 Mar 2023 16:39:05 +0100 Subject: [PATCH v5 3/4] drm/i915/selftests: use nop_clear_range instead of local function MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20230308-guard_error_capture-v5-3-6d1410d13540@intel.com> References: <20230308-guard_error_capture-v5-0-6d1410d13540@intel.com> In-Reply-To: <20230308-guard_error_capture-v5-0-6d1410d13540@intel.com> To: Jani Nikula , Joonas Lahtinen , Rodrigo Vivi , Tvrtko Ursulin Cc: intel-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org, Andi Shyti , Chris Wilson , Nirmoy Das , Andrzej Hajda X-Mailer: b4 0.11.1 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Since nop_clear_range is visible it can be used here. Signed-off-by: Andrzej Hajda Reviewed-by: Andi Shyti --- drivers/gpu/drm/i915/selftests/mock_gtt.c | 9 ++------- 1 file changed, 2 insertions(+), 7 deletions(-) diff --git a/drivers/gpu/drm/i915/selftests/mock_gtt.c b/drivers/gpu/drm/i9= 15/selftests/mock_gtt.c index ece97e4faacb97..89119e3970279f 100644 --- a/drivers/gpu/drm/i915/selftests/mock_gtt.c +++ b/drivers/gpu/drm/i915/selftests/mock_gtt.c @@ -57,11 +57,6 @@ static void mock_cleanup(struct i915_address_space *vm) { } =20 -static void mock_clear_range(struct i915_address_space *vm, - u64 start, u64 length) -{ -} - struct i915_ppgtt *mock_ppgtt(struct drm_i915_private *i915, const char *n= ame) { struct i915_ppgtt *ppgtt; @@ -80,7 +75,7 @@ struct i915_ppgtt *mock_ppgtt(struct drm_i915_private *i9= 15, const char *name) ppgtt->vm.alloc_pt_dma =3D alloc_pt_dma; ppgtt->vm.alloc_scratch_dma =3D alloc_pt_dma; =20 - ppgtt->vm.clear_range =3D mock_clear_range; + ppgtt->vm.clear_range =3D nop_clear_range; ppgtt->vm.insert_page =3D mock_insert_page; ppgtt->vm.insert_entries =3D mock_insert_entries; ppgtt->vm.cleanup =3D mock_cleanup; @@ -119,7 +114,7 @@ void mock_init_ggtt(struct intel_gt *gt) ggtt->vm.alloc_pt_dma =3D alloc_pt_dma; ggtt->vm.alloc_scratch_dma =3D alloc_pt_dma; =20 - ggtt->vm.clear_range =3D mock_clear_range; + ggtt->vm.clear_range =3D nop_clear_range; ggtt->vm.insert_page =3D mock_insert_page; ggtt->vm.insert_entries =3D mock_insert_entries; ggtt->vm.cleanup =3D mock_cleanup; --=20 2.34.1 From nobody Wed Sep 10 05:46:15 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 73E3EC678D5 for ; Wed, 8 Mar 2023 15:41:13 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231546AbjCHPlL (ORCPT ); Wed, 8 Mar 2023 10:41:11 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:33646 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232533AbjCHPk1 (ORCPT ); Wed, 8 Mar 2023 10:40:27 -0500 Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 4BC1392BEB for ; Wed, 8 Mar 2023 07:40:10 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1678290010; x=1709826010; h=from:date:subject:mime-version:content-transfer-encoding: message-id:references:in-reply-to:to:cc; bh=W+jwVlTRdjvktA1nEkWNcAT5iygeBJ8dB2aSEBElQ1U=; b=bviiDxUMJdiXBZhjxH8bd0LGJ/qYjKA0oHf3Oq9Kc3oF0bwhOV0grBeP dKR5JZMdb3yCO9vsoZh0BKf4KdfXImhfT7OFTA9lacia0+Dl4hab1/9ah n32l+jfmZyq7uRK+EHdWaAdA5Aohexu1MknHh0woBT+AMq9uw19f+VHTS WBiGOW5TghS3XfxYuRh0dXMwvwxXTjsAlvctJa4IZylxbLHjQ+vlFf02m Xcg5eCMOn5Zhc7kK9dpXB+gIja/wZYTlmd4VuRQtgtlMWZo0sIBvPUTMn uOikrO3Rs/4N+x0Vx8UyCvyYonNXekj4AODuWoMBmigHs96NQzkOd7e3g g==; X-IronPort-AV: E=McAfee;i="6500,9779,10642"; a="337703592" X-IronPort-AV: E=Sophos;i="5.98,244,1673942400"; d="scan'208";a="337703592" Received: from fmsmga002.fm.intel.com ([10.253.24.26]) by orsmga102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 08 Mar 2023 07:39:53 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10642"; a="787160296" X-IronPort-AV: E=Sophos;i="5.98,244,1673942400"; d="scan'208";a="787160296" Received: from lab-ah.igk.intel.com ([10.102.42.211]) by fmsmga002-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 08 Mar 2023 07:39:51 -0800 From: Andrzej Hajda Date: Wed, 08 Mar 2023 16:39:06 +0100 Subject: [PATCH v5 4/4] drm/i915: add guard page to ggtt->error_capture MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20230308-guard_error_capture-v5-4-6d1410d13540@intel.com> References: <20230308-guard_error_capture-v5-0-6d1410d13540@intel.com> In-Reply-To: <20230308-guard_error_capture-v5-0-6d1410d13540@intel.com> To: Jani Nikula , Joonas Lahtinen , Rodrigo Vivi , Tvrtko Ursulin Cc: intel-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org, Andi Shyti , Chris Wilson , Nirmoy Das , Andrzej Hajda X-Mailer: b4 0.11.1 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Write-combining memory allows speculative reads by CPU. ggtt->error_capture is WC mapped to CPU, so CPU/MMU can try to prefetch memory beyond the error_capture, ie it tries to read memory pointed by next PTE in GGTT. If this PTE points to invalid address DMAR errors will occur. This behaviour was observed on ADL and RPL platforms. To avoid it, guard scratch page should be added after error_capture. The patch fixes the most annoying issue with error capture but since WC reads are used also in other places there is a risk similar problem can affect them as well. v2: - modified commit message (I hope the diagnosis is correct), - added bug checks to ensure scratch is initialized on gen3 platforms. CI produces strange stacktrace for it suggesting scratch[0] is NULL, to be removed after resolving the issue with gen3 platforms. v3: - removed bug checks, replaced with gen check. v4: - change code for scratch page insertion to support all platforms, - add info in commit message there could be more similar issues v5: - check for nop_clear_range instead of gen8 (Tvrtko), - re-insert scratch pages on resume (Tvrtko) Signed-off-by: Andrzej Hajda Reviewed-by: Andi Shyti --- drivers/gpu/drm/i915/gt/intel_ggtt.c | 35 +++++++++++++++++++++++++++++++-= --- 1 file changed, 31 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/i915/gt/intel_ggtt.c b/drivers/gpu/drm/i915/gt= /intel_ggtt.c index b925da42c7cfc4..8fb700fde85c8f 100644 --- a/drivers/gpu/drm/i915/gt/intel_ggtt.c +++ b/drivers/gpu/drm/i915/gt/intel_ggtt.c @@ -502,6 +502,21 @@ static void cleanup_init_ggtt(struct i915_ggtt *ggtt) mutex_destroy(&ggtt->error_mutex); } =20 +static void +ggtt_insert_scratch_pages(struct i915_ggtt *ggtt, u64 offset, u64 length) +{ + struct i915_address_space *vm =3D &ggtt->vm; + + if (vm->clear_range !=3D nop_clear_range) + return vm->clear_range(vm, offset, length); + + while (length > 0) { + vm->insert_page(vm, px_dma(vm->scratch[0]), offset, I915_CACHE_NONE, 0); + offset +=3D I915_GTT_PAGE_SIZE; + length -=3D I915_GTT_PAGE_SIZE; + } +} + static int init_ggtt(struct i915_ggtt *ggtt) { /* @@ -550,8 +565,12 @@ static int init_ggtt(struct i915_ggtt *ggtt) * paths, and we trust that 0 will remain reserved. However, * the only likely reason for failure to insert is a driver * bug, which we expect to cause other failures... + * + * Since CPU can perform speculative reads on error capture + * (write-combining allows it) add scratch page after error + * capture to avoid DMAR errors. */ - ggtt->error_capture.size =3D I915_GTT_PAGE_SIZE; + ggtt->error_capture.size =3D 2 * I915_GTT_PAGE_SIZE; ggtt->error_capture.color =3D I915_COLOR_UNEVICTABLE; if (drm_mm_reserve_node(&ggtt->vm.mm, &ggtt->error_capture)) drm_mm_insert_node_in_range(&ggtt->vm.mm, @@ -561,11 +580,15 @@ static int init_ggtt(struct i915_ggtt *ggtt) 0, ggtt->mappable_end, DRM_MM_INSERT_LOW); } - if (drm_mm_node_allocated(&ggtt->error_capture)) + if (drm_mm_node_allocated(&ggtt->error_capture)) { + u64 start =3D ggtt->error_capture.start; + u64 size =3D ggtt->error_capture.size; + + ggtt_insert_scratch_pages(ggtt, start, size); drm_dbg(&ggtt->vm.i915->drm, "Reserved GGTT:[%llx, %llx] for use by error capture\n", - ggtt->error_capture.start, - ggtt->error_capture.start + ggtt->error_capture.size); + start, start + size); + } =20 /* * The upper portion of the GuC address space has a sizeable hole @@ -1256,6 +1279,10 @@ void i915_ggtt_resume(struct i915_ggtt *ggtt) =20 flush =3D i915_ggtt_resume_vm(&ggtt->vm); =20 + if (drm_mm_node_allocated(&ggtt->error_capture)) + ggtt_insert_scratch_pages(ggtt, ggtt->error_capture.start, + ggtt->error_capture.size); + ggtt->invalidate(ggtt); =20 if (flush) --=20 2.34.1