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[90.24.137.155]) by smtp.gmail.com with ESMTPSA id t1-20020a5d49c1000000b002c563b124basm12778117wrs.103.2023.03.07.08.34.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 07 Mar 2023 08:34:15 -0800 (PST) From: bchihi@baylibre.com To: daniel.lezcano@linaro.org, angelogioacchino.delregno@collabora.com, rafael@kernel.org, amitk@kernel.org, rui.zhang@intel.com, matthias.bgg@gmail.com, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, rdunlap@infradead.org, ye.xingchen@zte.com.cn, p.zabel@pengutronix.de Cc: linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, devicetree@vger.kernel.org, khilman@baylibre.com, james.lo@mediatek.com, rex-bc.chen@mediatek.com Subject: [PATCH 1/4] dt-bindings: thermal: mediatek: Add LVTS thermal controller definition for mt8192 Date: Tue, 7 Mar 2023 17:34:10 +0100 Message-Id: <20230307163413.143334-2-bchihi@baylibre.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230307163413.143334-1-bchihi@baylibre.com> References: <20230307163413.143334-1-bchihi@baylibre.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Balsam CHIHI Add LVTS thermal controller definition for MT8192. Signed-off-by: Balsam CHIHI Acked-by: Krzysztof Kozlowski Reviewed-by: AngeloGioacchino Del Regno --- .../thermal/mediatek,lvts-thermal.h | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/include/dt-bindings/thermal/mediatek,lvts-thermal.h b/include/= dt-bindings/thermal/mediatek,lvts-thermal.h index 8fa5a46675c4..5e9eb6217426 100644 --- a/include/dt-bindings/thermal/mediatek,lvts-thermal.h +++ b/include/dt-bindings/thermal/mediatek,lvts-thermal.h @@ -26,4 +26,23 @@ #define MT8195_AP_CAM0 15 #define MT8195_AP_CAM1 16 =20 +#define MT8192_MCU_BIG_CPU0 0 +#define MT8192_MCU_BIG_CPU1 1 +#define MT8192_MCU_BIG_CPU2 2 +#define MT8192_MCU_BIG_CPU3 3 +#define MT8192_MCU_LITTLE_CPU0 4 +#define MT8192_MCU_LITTLE_CPU1 5 +#define MT8192_MCU_LITTLE_CPU2 6 +#define MT8192_MCU_LITTLE_CPU3 7 + +#define MT8192_AP_VPU0 8 +#define MT8192_AP_VPU1 9 +#define MT8192_AP_GPU0 10 +#define MT8192_AP_GPU1 11 +#define MT8192_AP_INFRA 12 +#define MT8192_AP_CAM 13 +#define MT8192_AP_MD0 14 +#define MT8192_AP_MD1 15 +#define MT8192_AP_MD2 16 + #endif /* __MEDIATEK_LVTS_DT_H */ --=20 2.34.1 From nobody Sat Sep 21 02:57:24 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id B6421C6FD1A for ; Tue, 7 Mar 2023 16:36:43 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230427AbjCGQgl (ORCPT ); Tue, 7 Mar 2023 11:36:41 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:39600 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229940AbjCGQfe (ORCPT ); Tue, 7 Mar 2023 11:35:34 -0500 Received: from mail-wm1-x335.google.com (mail-wm1-x335.google.com [IPv6:2a00:1450:4864:20::335]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id CC4EB50F84 for ; Tue, 7 Mar 2023 08:34:24 -0800 (PST) Received: by mail-wm1-x335.google.com with SMTP id ay29-20020a05600c1e1d00b003e9f4c2b623so10802178wmb.3 for ; Tue, 07 Mar 2023 08:34:24 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baylibre-com.20210112.gappssmtp.com; s=20210112; t=1678206856; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=xhm0Z58jGS6mpBjmYPCuuY9PZYL3NGQVLq4u+nizCEQ=; b=KcBWv2s7crANLMfzugYI+vnRfZEZRrsd3S1L73FqBlS6siIURtrV6OfqKgtomGifTy NiWulqYWlOMbizv4QZAUxIOo+1/l4G0Bss6fG8LtBCLIX1CeEUmXxUC8wy7jvZj7/lSJ tbMwyJ7rhijQHl2OqC9aUNe7LX9h/mGb+VirhjVCp+mcZzkqt9OlUgtG036CMdbgU6D8 eypO86HaWRXDaTJn9FDa/l/+4Nxle/KL3ObTDNd33xu8BggGZW7h6OHNUYubqviZBBiR jSqkyQ+tdXYCNfVNT4vdMnwle7c+7vWiZtIc23nO6vv/bMy0Ayjl2Q+F/ngFrvYBKNNo d9WQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1678206856; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=xhm0Z58jGS6mpBjmYPCuuY9PZYL3NGQVLq4u+nizCEQ=; b=smwWS2E7qPYxdI/eLkb9PgqAj74qzlfVNdknEA1rjI57WUnGRqEw97rctRXUyz7p26 Bz5qlE265G8xQl8zsMIULV0Rb10YOM7buoJJ0vPX8Qlc26HWiaIYu0jM9S1vpf9yOLoC K2lLfEduxGHmz9c68DzeMKi7SXtl9Wnz11ecWRXzSLOrnd67X70UMOtRgQx8xDMKQKVz 3ZLr7ThqjQUWsJCJznPsV1jsscGcmCOuy1C8lkpHYnLbVZQoXFGm9rMWhEFOdvq5xUm2 3RJD4A5Z+6fZTirswuzQs7NhOG5MEWbawgHdVFpvKu1Ab1P/+YzMZjvYlQi/bAM+YFxe zgjw== X-Gm-Message-State: AO0yUKVZ5/9Xcuc/So6RfcxJcC+VNSYZlfGdPfmD7uPdRFGbW8Ehz51k KSLRe3MXK6Kw0ibd8TQwAUD8cA== X-Google-Smtp-Source: AK7set967AMY43ARStWpd75nlbM3zZs1vUzYiU1BPa+bA49UF9gM1DkWOjDMGgpVYv0kwZXV0BzraA== X-Received: by 2002:a05:600c:5127:b0:3ea:f01d:2346 with SMTP id o39-20020a05600c512700b003eaf01d2346mr13773483wms.15.1678206856745; Tue, 07 Mar 2023 08:34:16 -0800 (PST) Received: from localhost.localdomain (laubervilliers-657-1-248-155.w90-24.abo.wanadoo.fr. [90.24.137.155]) by smtp.gmail.com with ESMTPSA id t1-20020a5d49c1000000b002c563b124basm12778117wrs.103.2023.03.07.08.34.16 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 07 Mar 2023 08:34:16 -0800 (PST) From: bchihi@baylibre.com To: daniel.lezcano@linaro.org, angelogioacchino.delregno@collabora.com, rafael@kernel.org, amitk@kernel.org, rui.zhang@intel.com, matthias.bgg@gmail.com, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, rdunlap@infradead.org, ye.xingchen@zte.com.cn, p.zabel@pengutronix.de Cc: linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, devicetree@vger.kernel.org, khilman@baylibre.com, james.lo@mediatek.com, rex-bc.chen@mediatek.com Subject: [PATCH 2/4] thermal/drivers/mediatek/lvts_thermal: Add mt8192 support Date: Tue, 7 Mar 2023 17:34:11 +0100 Message-Id: <20230307163413.143334-3-bchihi@baylibre.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230307163413.143334-1-bchihi@baylibre.com> References: <20230307163413.143334-1-bchihi@baylibre.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Balsam CHIHI Add LVTS Driver support for MT8192. Signed-off-by: Balsam CHIHI --- drivers/thermal/mediatek/lvts_thermal.c | 106 +++++++++++++++++++++++- 1 file changed, 104 insertions(+), 2 deletions(-) diff --git a/drivers/thermal/mediatek/lvts_thermal.c b/drivers/thermal/medi= atek/lvts_thermal.c index 7565def6b27c..b505c6b49031 100644 --- a/drivers/thermal/mediatek/lvts_thermal.c +++ b/drivers/thermal/mediatek/lvts_thermal.c @@ -80,6 +80,7 @@ #define LVTS_MSR_FILTERED_MODE 1 =20 #define LVTS_HW_SHUTDOWN_MT8195 105000 +#define LVTS_HW_SHUTDOWN_MT8192 105000 =20 static int golden_temp =3D LVTS_GOLDEN_TEMP_DEFAULT; static int coeff_b =3D LVTS_COEFF_B; @@ -528,7 +529,7 @@ static int lvts_sensor_init(struct device *dev, struct = lvts_ctrl *lvts_ctrl, * The efuse blob values follows the sensor enumeration per thermal * controller. The decoding of the stream is as follow: * - * stream index map for MCU Domain : + * stream index map for MCU Domain mt8195/mt8192 : * * <-----mcu-tc#0-----> <-----sensor#0-----> <-----sensor#1-----> * 0x01 | 0x02 | 0x03 | 0x04 | 0x05 | 0x06 | 0x07 | 0x08 | 0x09 @@ -539,7 +540,7 @@ static int lvts_sensor_init(struct device *dev, struct = lvts_ctrl *lvts_ctrl, * <-----mcu-tc#2-----> <-----sensor#4-----> <-----sensor#5-----> <-----se= nsor#6-----> <-----sensor#7-----> * 0x13 | 0x14 | 0x15 | 0x16 | 0x17 | 0x18 | 0x19 | 0x1A | 0x1B | 0x1C | = 0x1D | 0x1E | 0x1F | 0x20 | 0x21 * - * stream index map for AP Domain : + * stream index map for AP Domain mt8195/mt8192 : * * <-----ap--tc#0-----> <-----sensor#0-----> <-----sensor#1-----> * 0x22 | 0x23 | 0x24 | 0x25 | 0x26 | 0x27 | 0x28 | 0x29 | 0x2A @@ -547,12 +548,22 @@ static int lvts_sensor_init(struct device *dev, struc= t lvts_ctrl *lvts_ctrl, * <-----ap--tc#1-----> <-----sensor#2-----> <-----sensor#3-----> * 0x2B | 0x2C | 0x2D | 0x2E | 0x2F | 0x30 | 0x31 | 0x32 | 0x33 * + * stream index map for AP Domain mt8195 : + * * <-----ap--tc#2-----> <-----sensor#4-----> <-----sensor#5-----> <-----se= nsor#6-----> * 0x34 | 0x35 | 0x36 | 0x37 | 0x38 | 0x39 | 0x3A | 0x3B | 0x3C | 0x3D | = 0x3E | 0x3F * * <-----ap--tc#3-----> <-----sensor#7-----> <-----sensor#8-----> * 0x40 | 0x41 | 0x42 | 0x43 | 0x44 | 0x45 | 0x46 | 0x47 | 0x48 * + * stream index map for AP Domain mt8192 : + * + * <-----ap--tc#2-----> <-----sensor#4-----> <-----sensor#5-----> + * 0x34 | 0x35 | 0x36 | 0x37 | 0x38 | 0x39 | 0x3A | 0x3B | 0x3C + * + * <-----ap--tc#3-----> <-----sensor#6-----> <-----sensor#7-----> <-----se= nsor#8-----> + * 0x3D | 0x3E | 0x3F | 0x40 | 0x41 | 0x42 | 0x43 | 0x44 | 0x45 | 0x46 | = 0x47 | 0x48 + * * The data description gives the offset of the calibration data in * this bytes stream for each sensor. */ @@ -1246,6 +1257,85 @@ static const struct lvts_ctrl_data mt8195_lvts_ap_da= ta_ctrl[] =3D { } }; =20 +static const struct lvts_ctrl_data mt8192_lvts_mcu_data_ctrl[] =3D { + { + .cal_offset =3D { 0x04, 0x07 }, + .lvts_sensor =3D { + { .dt_id =3D MT8192_MCU_BIG_CPU0 }, + { .dt_id =3D MT8192_MCU_BIG_CPU1 } + }, + .num_lvts_sensor =3D 2, + .offset =3D 0x0, + .hw_tshut_temp =3D LVTS_HW_SHUTDOWN_MT8192, + }, + { + .cal_offset =3D { 0x0d, 0x10 }, + .lvts_sensor =3D { + { .dt_id =3D MT8192_MCU_BIG_CPU2 }, + { .dt_id =3D MT8192_MCU_BIG_CPU3 } + }, + .num_lvts_sensor =3D 2, + .offset =3D 0x100, + .hw_tshut_temp =3D LVTS_HW_SHUTDOWN_MT8192, + }, + { + .cal_offset =3D { 0x16, 0x19, 0x1c, 0x1f }, + .lvts_sensor =3D { + { .dt_id =3D MT8192_MCU_LITTLE_CPU0 }, + { .dt_id =3D MT8192_MCU_LITTLE_CPU1 }, + { .dt_id =3D MT8192_MCU_LITTLE_CPU2 }, + { .dt_id =3D MT8192_MCU_LITTLE_CPU3 } + }, + .num_lvts_sensor =3D 4, + .offset =3D 0x200, + .hw_tshut_temp =3D LVTS_HW_SHUTDOWN_MT8192, + } +}; + +static const struct lvts_ctrl_data mt8192_lvts_ap_data_ctrl[] =3D { + { + .cal_offset =3D { 0x25, 0x28 }, + .lvts_sensor =3D { + { .dt_id =3D MT8192_AP_VPU0 }, + { .dt_id =3D MT8192_AP_VPU1 } + }, + .num_lvts_sensor =3D 2, + .offset =3D 0x0, + .hw_tshut_temp =3D LVTS_HW_SHUTDOWN_MT8192, + }, + { + .cal_offset =3D { 0x2e, 0x31 }, + .lvts_sensor =3D { + { .dt_id =3D MT8192_AP_GPU0 }, + { .dt_id =3D MT8192_AP_GPU1 } + }, + .num_lvts_sensor =3D 2, + .offset =3D 0x100, + .hw_tshut_temp =3D LVTS_HW_SHUTDOWN_MT8192, + }, + { + .cal_offset =3D { 0x37, 0x3a }, + .lvts_sensor =3D { + { .dt_id =3D MT8192_AP_INFRA }, + { .dt_id =3D MT8192_AP_CAM }, + }, + .num_lvts_sensor =3D 2, + .offset =3D 0x200, + .hw_tshut_temp =3D LVTS_HW_SHUTDOWN_MT8192, + }, + { + .cal_offset =3D { 0x40, 0x43, 0x46 }, + .lvts_sensor =3D { + { .dt_id =3D MT8192_AP_MD0 }, + { .dt_id =3D MT8192_AP_MD1 }, + { .dt_id =3D MT8192_AP_MD2 } + }, + .num_lvts_sensor =3D 3, + .offset =3D 0x300, + .hw_tshut_temp =3D LVTS_HW_SHUTDOWN_MT8192, + } +}; + static const struct lvts_data mt8195_lvts_mcu_data =3D { .lvts_ctrl =3D mt8195_lvts_mcu_data_ctrl, .num_lvts_ctrl =3D ARRAY_SIZE(mt8195_lvts_mcu_data_ctrl), @@ -1256,9 +1346,21 @@ static const struct lvts_data mt8195_lvts_ap_data = =3D { .num_lvts_ctrl =3D ARRAY_SIZE(mt8195_lvts_ap_data_ctrl), }; =20 +static const struct lvts_data mt8192_lvts_mcu_data =3D { + .lvts_ctrl =3D mt8192_lvts_mcu_data_ctrl, + .num_lvts_ctrl =3D ARRAY_SIZE(mt8192_lvts_mcu_data_ctrl), +}; + +static const struct lvts_data mt8192_lvts_ap_data =3D { + .lvts_ctrl =3D mt8192_lvts_ap_data_ctrl, + .num_lvts_ctrl =3D ARRAY_SIZE(mt8192_lvts_ap_data_ctrl), +}; + static const struct of_device_id lvts_of_match[] =3D { { .compatible =3D "mediatek,mt8195-lvts-mcu", .data =3D &mt8195_lvts_mcu_= data }, { .compatible =3D "mediatek,mt8195-lvts-ap", .data =3D &mt8195_lvts_ap_da= ta }, + { .compatible =3D "mediatek,mt8192-lvts-mcu", .data =3D &mt8192_lvts_mcu_= data }, + { .compatible =3D "mediatek,mt8192-lvts-ap", .data =3D &mt8192_lvts_ap_da= ta }, {}, }; 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[90.24.137.155]) by smtp.gmail.com with ESMTPSA id t1-20020a5d49c1000000b002c563b124basm12778117wrs.103.2023.03.07.08.34.16 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 07 Mar 2023 08:34:17 -0800 (PST) From: bchihi@baylibre.com To: daniel.lezcano@linaro.org, angelogioacchino.delregno@collabora.com, rafael@kernel.org, amitk@kernel.org, rui.zhang@intel.com, matthias.bgg@gmail.com, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, rdunlap@infradead.org, ye.xingchen@zte.com.cn, p.zabel@pengutronix.de Cc: linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, devicetree@vger.kernel.org, khilman@baylibre.com, james.lo@mediatek.com, rex-bc.chen@mediatek.com Subject: [PATCH 3/4] arm64: dts: mediatek: mt8192: Add thermal zones and thermal nodes Date: Tue, 7 Mar 2023 17:34:12 +0100 Message-Id: <20230307163413.143334-4-bchihi@baylibre.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230307163413.143334-1-bchihi@baylibre.com> References: <20230307163413.143334-1-bchihi@baylibre.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Balsam CHIHI Add thermal zones and thermal nodes for the mt8192. Signed-off-by: Balsam CHIHI --- arch/arm64/boot/dts/mediatek/mt8192.dtsi | 263 +++++++++++++++++++++++ 1 file changed, 263 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts= /mediatek/mt8192.dtsi index 424fc89cc6f7..45c3d65a118a 100644 --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi @@ -14,6 +14,7 @@ #include #include #include +#include =20 / { compatible =3D "mediatek,mt8192"; @@ -620,6 +621,17 @@ spi0: spi@1100a000 { status =3D "disabled"; }; =20 + lvts_ap: thermal-sensor@1100b000 { + compatible =3D "mediatek,mt8192-lvts-ap"; + reg =3D <0 0x1100b000 0 0x1000>; + interrupts =3D ; + clocks =3D <&infracfg CLK_INFRA_THERM>; + resets =3D <&infracfg MT8192_INFRA_RST0_THERM_CTRL_SWRST>; + nvmem-cells =3D <&lvts_e_data1>; + nvmem-cell-names =3D "lvts-calib-data-1"; + #thermal-sensor-cells =3D <1>; + }; + pwm0: pwm@1100e000 { compatible =3D "mediatek,mt8183-disp-pwm"; reg =3D <0 0x1100e000 0 0x1000>; @@ -946,6 +958,17 @@ nor_flash: spi@11234000 { status =3D "disabled"; }; =20 + lvts_mcu: thermal-sensor@11278000 { + compatible =3D "mediatek,mt8192-lvts-mcu"; + reg =3D <0 0x11278000 0 0x1000>; + interrupts =3D ; + clocks =3D <&infracfg CLK_INFRA_THERM>; + resets =3D <&infracfg MT8192_INFRA_RST4_THERM_CTRL_MCU_SWRST>; + nvmem-cells =3D <&lvts_e_data1>; + nvmem-cell-names =3D "lvts-calib-data-1"; + #thermal-sensor-cells =3D <1>; + }; + efuse: efuse@11c10000 { compatible =3D "mediatek,mt8192-efuse", "mediatek,efuse"; reg =3D <0 0x11c10000 0 0x1000>; @@ -1650,4 +1673,244 @@ larb2: larb@1f002000 { power-domains =3D <&spm MT8192_POWER_DOMAIN_MDP>; }; }; + + thermal_zones: thermal-zones { + cpu0-thermal { + polling-delay =3D <0>; + polling-delay-passive =3D <0>; + thermal-sensors =3D <&lvts_mcu MT8192_MCU_LITTLE_CPU0>; + + trips { + cpu0_crit: trip-crit { + temperature =3D <100000>; + hysteresis =3D <2000>; + type =3D "critical"; + }; + }; + }; + + cpu1-thermal { + polling-delay =3D <0>; + polling-delay-passive =3D <0>; + thermal-sensors =3D <&lvts_mcu MT8192_MCU_LITTLE_CPU1>; + + trips { + cpu1_crit: trip-crit { + temperature =3D <100000>; + hysteresis =3D <2000>; + type =3D "critical"; + }; + }; + }; + + cpu2-thermal { + polling-delay =3D <0>; + polling-delay-passive =3D <0>; + thermal-sensors =3D <&lvts_mcu MT8192_MCU_LITTLE_CPU2>; + + trips { + cpu2_crit: trip-crit { + temperature =3D <100000>; + hysteresis =3D <2000>; + type =3D "critical"; + }; + }; + }; + + cpu3-thermal { + polling-delay =3D <0>; + polling-delay-passive =3D <0>; + thermal-sensors =3D <&lvts_mcu MT8192_MCU_LITTLE_CPU3>; + + trips { + cpu3_crit: trip-crit { + temperature =3D <100000>; + hysteresis =3D <2000>; + type =3D "critical"; + }; + }; + }; + + cpu4-thermal { + polling-delay =3D <0>; + polling-delay-passive =3D <0>; + thermal-sensors =3D <&lvts_mcu MT8192_MCU_BIG_CPU0>; + + trips { + cpu4_crit: trip-crit { + temperature =3D <100000>; + hysteresis =3D <2000>; + type =3D "critical"; + }; + }; + }; + + cpu5-thermal { + polling-delay =3D <0>; + polling-delay-passive =3D <0>; + thermal-sensors =3D <&lvts_mcu MT8192_MCU_BIG_CPU1>; + + trips { + cpu5_crit: trip-crit { + temperature =3D <100000>; + hysteresis =3D <2000>; + type =3D "critical"; + }; + }; + }; + + cpu6-thermal { + polling-delay =3D <0>; + polling-delay-passive =3D <0>; + thermal-sensors =3D <&lvts_mcu MT8192_MCU_BIG_CPU2>; + + trips { + cpu6_crit: trip-crit { + temperature =3D <100000>; + hysteresis =3D <2000>; + type =3D "critical"; + }; + }; + }; + + cpu7-thermal { + polling-delay =3D <0>; + polling-delay-passive =3D <0>; + thermal-sensors =3D <&lvts_mcu MT8192_MCU_BIG_CPU3>; + + trips { + cpu7_crit: trip-crit { + temperature =3D <100000>; + hysteresis =3D <2000>; + type =3D "critical"; + }; + }; + }; + + vpu0-thermal { + polling-delay =3D <0>; + polling-delay-passive =3D <0>; + thermal-sensors =3D <&lvts_ap MT8192_AP_VPU0>; + + trips { + vpu0_crit: trip-crit { + temperature =3D <100000>; + hysteresis =3D <2000>; + type =3D "critical"; + }; + }; + }; + + vpu1-thermal { + polling-delay =3D <0>; + polling-delay-passive =3D <0>; + thermal-sensors =3D <&lvts_ap MT8192_AP_VPU1>; + + trips { + vpu1_crit: trip-crit { + temperature =3D <100000>; + hysteresis =3D <2000>; + type =3D "critical"; + }; + }; + }; + + gpu0-thermal { + polling-delay =3D <0>; + polling-delay-passive =3D <0>; + thermal-sensors =3D <&lvts_ap MT8192_AP_GPU0>; + + trips { + gpu0_crit: trip-crit { + temperature =3D <100000>; + hysteresis =3D <2000>; + type =3D "critical"; + }; + }; + }; + + gpu1-thermal { + polling-delay =3D <0>; + polling-delay-passive =3D <0>; + thermal-sensors =3D <&lvts_ap MT8192_AP_GPU1>; + + trips { + gpu1_crit: trip-crit { + temperature =3D <100000>; + hysteresis =3D <2000>; + type =3D "critical"; + }; + }; + }; + + infra-thermal { + polling-delay =3D <0>; + polling-delay-passive =3D <0>; + thermal-sensors =3D <&lvts_ap MT8192_AP_INFRA>; + + trips { + infra_crit: trip-crit { + temperature =3D <100000>; + hysteresis =3D <2000>; + type =3D "critical"; + }; + }; + }; + + cam-thermal { + polling-delay =3D <0>; + polling-delay-passive =3D <0>; + thermal-sensors =3D <&lvts_ap MT8192_AP_CAM>; + + trips { + cam_crit: trip-crit { + temperature =3D <100000>; + hysteresis =3D <2000>; + type =3D "critical"; + }; + }; + }; + + md0-thermal { + polling-delay =3D <0>; + polling-delay-passive =3D <0>; + thermal-sensors =3D <&lvts_ap MT8192_AP_MD0>; + + trips { + md0_crit: trip-crit { + temperature =3D <100000>; + hysteresis =3D <2000>; + type =3D "critical"; + }; + }; + }; + + md1-thermal { + polling-delay =3D <0>; + polling-delay-passive =3D <0>; + thermal-sensors =3D <&lvts_ap MT8192_AP_MD1>; + + trips { + md1_crit: trip-crit { + temperature =3D <100000>; + hysteresis =3D <2000>; + type =3D "critical"; + }; + }; + }; + + md2-thermal { + polling-delay =3D <0>; + polling-delay-passive =3D <0>; + thermal-sensors =3D <&lvts_ap MT8192_AP_MD2>; + + trips { + md2_crit: trip-crit { + temperature =3D <100000>; + hysteresis =3D <2000>; + type =3D "critical"; + }; + }; + }; + }; }; --=20 2.34.1 From nobody Sat Sep 21 02:57:24 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id BF5A2C678D5 for ; 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[90.24.137.155]) by smtp.gmail.com with ESMTPSA id t1-20020a5d49c1000000b002c563b124basm12778117wrs.103.2023.03.07.08.34.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 07 Mar 2023 08:34:18 -0800 (PST) From: bchihi@baylibre.com To: daniel.lezcano@linaro.org, angelogioacchino.delregno@collabora.com, rafael@kernel.org, amitk@kernel.org, rui.zhang@intel.com, matthias.bgg@gmail.com, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, rdunlap@infradead.org, ye.xingchen@zte.com.cn, p.zabel@pengutronix.de Cc: linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, devicetree@vger.kernel.org, khilman@baylibre.com, james.lo@mediatek.com, rex-bc.chen@mediatek.com Subject: [PATCH 4/4] arm64: dts: mediatek: mt8192: Add temperature mitigation threshold Date: Tue, 7 Mar 2023 17:34:13 +0100 Message-Id: <20230307163413.143334-5-bchihi@baylibre.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230307163413.143334-1-bchihi@baylibre.com> References: <20230307163413.143334-1-bchihi@baylibre.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Balsam CHIHI The mt8192 SoC has several hotspots around the CPUs. Specify the targeted temperature threshold when to apply the mitigation and define the associated cooling devices. Signed-off-by: Balsam CHIHI --- arch/arm64/boot/dts/mediatek/mt8192.dtsi | 259 ++++++++++++++++++++--- 1 file changed, 225 insertions(+), 34 deletions(-) diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts= /mediatek/mt8192.dtsi index 45c3d65a118a..772b9229b2a9 100644 --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi @@ -14,6 +14,7 @@ #include #include #include +#include #include =20 / { @@ -57,6 +58,7 @@ cpu0: cpu@0 { cpu-idle-states =3D <&cpu_sleep_l &cluster_sleep_l>; next-level-cache =3D <&l2_0>; capacity-dmips-mhz =3D <530>; + #cooling-cells =3D <2>; }; =20 cpu1: cpu@100 { @@ -68,6 +70,7 @@ cpu1: cpu@100 { cpu-idle-states =3D <&cpu_sleep_l &cluster_sleep_l>; next-level-cache =3D <&l2_0>; capacity-dmips-mhz =3D <530>; + #cooling-cells =3D <2>; }; =20 cpu2: cpu@200 { @@ -79,6 +82,7 @@ cpu2: cpu@200 { cpu-idle-states =3D <&cpu_sleep_l &cluster_sleep_l>; next-level-cache =3D <&l2_0>; capacity-dmips-mhz =3D <530>; + #cooling-cells =3D <2>; }; =20 cpu3: cpu@300 { @@ -90,6 +94,7 @@ cpu3: cpu@300 { cpu-idle-states =3D <&cpu_sleep_l &cluster_sleep_l>; next-level-cache =3D <&l2_0>; capacity-dmips-mhz =3D <530>; + #cooling-cells =3D <2>; }; =20 cpu4: cpu@400 { @@ -101,6 +106,7 @@ cpu4: cpu@400 { cpu-idle-states =3D <&cpu_sleep_b &cluster_sleep_b>; next-level-cache =3D <&l2_1>; capacity-dmips-mhz =3D <1024>; + #cooling-cells =3D <2>; }; =20 cpu5: cpu@500 { @@ -112,6 +118,7 @@ cpu5: cpu@500 { cpu-idle-states =3D <&cpu_sleep_b &cluster_sleep_b>; next-level-cache =3D <&l2_1>; capacity-dmips-mhz =3D <1024>; + #cooling-cells =3D <2>; }; =20 cpu6: cpu@600 { @@ -123,6 +130,7 @@ cpu6: cpu@600 { cpu-idle-states =3D <&cpu_sleep_b &cluster_sleep_b>; next-level-cache =3D <&l2_1>; capacity-dmips-mhz =3D <1024>; + #cooling-cells =3D <2>; }; =20 cpu7: cpu@700 { @@ -134,6 +142,7 @@ cpu7: cpu@700 { cpu-idle-states =3D <&cpu_sleep_b &cluster_sleep_b>; next-level-cache =3D <&l2_1>; capacity-dmips-mhz =3D <1024>; + #cooling-cells =3D <2>; }; =20 cpu-map { @@ -1676,123 +1685,257 @@ larb2: larb@1f002000 { =20 thermal_zones: thermal-zones { cpu0-thermal { - polling-delay =3D <0>; - polling-delay-passive =3D <0>; + polling-delay =3D <1000>; + polling-delay-passive =3D <250>; thermal-sensors =3D <&lvts_mcu MT8192_MCU_LITTLE_CPU0>; =20 trips { + cpu0_alert: trip-alert { + temperature =3D <85000>; + hysteresis =3D <2000>; + type =3D "passive"; + }; + cpu0_crit: trip-crit { temperature =3D <100000>; hysteresis =3D <2000>; type =3D "critical"; }; }; + + cooling-maps { + map0 { + trip =3D <&cpu0_alert>; + cooling-device =3D <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; }; =20 cpu1-thermal { - polling-delay =3D <0>; - polling-delay-passive =3D <0>; + polling-delay =3D <1000>; + polling-delay-passive =3D <250>; thermal-sensors =3D <&lvts_mcu MT8192_MCU_LITTLE_CPU1>; =20 trips { + cpu1_alert: trip-alert { + temperature =3D <85000>; + hysteresis =3D <2000>; + type =3D "passive"; + }; + cpu1_crit: trip-crit { temperature =3D <100000>; hysteresis =3D <2000>; type =3D "critical"; }; }; + + cooling-maps { + map0 { + trip =3D <&cpu1_alert>; + cooling-device =3D <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; }; =20 cpu2-thermal { - polling-delay =3D <0>; - polling-delay-passive =3D <0>; + polling-delay =3D <1000>; + polling-delay-passive =3D <250>; thermal-sensors =3D <&lvts_mcu MT8192_MCU_LITTLE_CPU2>; =20 trips { + cpu2_alert: trip-alert { + temperature =3D <85000>; + hysteresis =3D <2000>; + type =3D "passive"; + }; + cpu2_crit: trip-crit { temperature =3D <100000>; hysteresis =3D <2000>; type =3D "critical"; }; }; + + cooling-maps { + map0 { + trip =3D <&cpu2_alert>; + cooling-device =3D <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; }; =20 cpu3-thermal { - polling-delay =3D <0>; - polling-delay-passive =3D <0>; + polling-delay =3D <1000>; + polling-delay-passive =3D <250>; thermal-sensors =3D <&lvts_mcu MT8192_MCU_LITTLE_CPU3>; =20 trips { + cpu3_alert: trip-alert { + temperature =3D <85000>; + hysteresis =3D <2000>; + type =3D "passive"; + }; + cpu3_crit: trip-crit { temperature =3D <100000>; hysteresis =3D <2000>; type =3D "critical"; }; }; + + cooling-maps { + map0 { + trip =3D <&cpu3_alert>; + cooling-device =3D <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; }; =20 cpu4-thermal { - polling-delay =3D <0>; - polling-delay-passive =3D <0>; + polling-delay =3D <1000>; + polling-delay-passive =3D <250>; thermal-sensors =3D <&lvts_mcu MT8192_MCU_BIG_CPU0>; =20 trips { + cpu4_alert: trip-alert { + temperature =3D <85000>; + hysteresis =3D <2000>; + type =3D "passive"; + }; + cpu4_crit: trip-crit { temperature =3D <100000>; hysteresis =3D <2000>; type =3D "critical"; }; }; + + cooling-maps { + map0 { + trip =3D <&cpu4_alert>; + cooling-device =3D <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; }; =20 cpu5-thermal { - polling-delay =3D <0>; - polling-delay-passive =3D <0>; + polling-delay =3D <1000>; + polling-delay-passive =3D <250>; thermal-sensors =3D <&lvts_mcu MT8192_MCU_BIG_CPU1>; =20 trips { + cpu5_alert: trip-alert { + temperature =3D <85000>; + hysteresis =3D <2000>; + type =3D "passive"; + }; + cpu5_crit: trip-crit { temperature =3D <100000>; hysteresis =3D <2000>; type =3D "critical"; }; }; + + cooling-maps { + map0 { + trip =3D <&cpu5_alert>; + cooling-device =3D <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; }; =20 cpu6-thermal { - polling-delay =3D <0>; - polling-delay-passive =3D <0>; + polling-delay =3D <1000>; + polling-delay-passive =3D <250>; thermal-sensors =3D <&lvts_mcu MT8192_MCU_BIG_CPU2>; =20 trips { + cpu6_alert: trip-alert { + temperature =3D <85000>; + hysteresis =3D <2000>; + type =3D "passive"; + }; + cpu6_crit: trip-crit { temperature =3D <100000>; hysteresis =3D <2000>; type =3D "critical"; }; }; + + cooling-maps { + map0 { + trip =3D <&cpu6_alert>; + cooling-device =3D <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; }; =20 cpu7-thermal { - polling-delay =3D <0>; - polling-delay-passive =3D <0>; + polling-delay =3D <1000>; + polling-delay-passive =3D <250>; thermal-sensors =3D <&lvts_mcu MT8192_MCU_BIG_CPU3>; =20 trips { + cpu7_alert: trip-alert { + temperature =3D <85000>; + hysteresis =3D <2000>; + type =3D "passive"; + }; + cpu7_crit: trip-crit { temperature =3D <100000>; hysteresis =3D <2000>; type =3D "critical"; }; }; + + cooling-maps { + map0 { + trip =3D <&cpu7_alert>; + cooling-device =3D <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; }; =20 vpu0-thermal { - polling-delay =3D <0>; - polling-delay-passive =3D <0>; + polling-delay =3D <1000>; + polling-delay-passive =3D <250>; thermal-sensors =3D <&lvts_ap MT8192_AP_VPU0>; =20 trips { + vpu0_alert: trip-alert { + temperature =3D <85000>; + hysteresis =3D <2000>; + type =3D "passive"; + }; + vpu0_crit: trip-crit { temperature =3D <100000>; hysteresis =3D <2000>; @@ -1802,11 +1945,17 @@ vpu0_crit: trip-crit { }; =20 vpu1-thermal { - polling-delay =3D <0>; - polling-delay-passive =3D <0>; + polling-delay =3D <1000>; + polling-delay-passive =3D <250>; thermal-sensors =3D <&lvts_ap MT8192_AP_VPU1>; =20 trips { + vpu1_alert: trip-alert { + temperature =3D <85000>; + hysteresis =3D <2000>; + type =3D "passive"; + }; + vpu1_crit: trip-crit { temperature =3D <100000>; hysteresis =3D <2000>; @@ -1816,11 +1965,17 @@ vpu1_crit: trip-crit { }; =20 gpu0-thermal { - polling-delay =3D <0>; - polling-delay-passive =3D <0>; + polling-delay =3D <1000>; + polling-delay-passive =3D <250>; thermal-sensors =3D <&lvts_ap MT8192_AP_GPU0>; =20 trips { + gpu0_alert: trip-alert { + temperature =3D <85000>; + hysteresis =3D <2000>; + type =3D "passive"; + }; + gpu0_crit: trip-crit { temperature =3D <100000>; hysteresis =3D <2000>; @@ -1830,11 +1985,17 @@ gpu0_crit: trip-crit { }; =20 gpu1-thermal { - polling-delay =3D <0>; - polling-delay-passive =3D <0>; + polling-delay =3D <1000>; + polling-delay-passive =3D <250>; thermal-sensors =3D <&lvts_ap MT8192_AP_GPU1>; =20 trips { + gpu1_alert: trip-alert { + temperature =3D <85000>; + hysteresis =3D <2000>; + type =3D "passive"; + }; + gpu1_crit: trip-crit { temperature =3D <100000>; hysteresis =3D <2000>; @@ -1844,11 +2005,17 @@ gpu1_crit: trip-crit { }; =20 infra-thermal { - polling-delay =3D <0>; - polling-delay-passive =3D <0>; + polling-delay =3D <1000>; + polling-delay-passive =3D <250>; thermal-sensors =3D <&lvts_ap MT8192_AP_INFRA>; =20 trips { + infra_alert: trip-alert { + temperature =3D <85000>; + hysteresis =3D <2000>; + type =3D "passive"; + }; + infra_crit: trip-crit { temperature =3D <100000>; hysteresis =3D <2000>; @@ -1858,11 +2025,17 @@ infra_crit: trip-crit { }; =20 cam-thermal { - polling-delay =3D <0>; - polling-delay-passive =3D <0>; + polling-delay =3D <1000>; + polling-delay-passive =3D <250>; thermal-sensors =3D <&lvts_ap MT8192_AP_CAM>; =20 trips { + cam_alert: trip-alert { + temperature =3D <85000>; + hysteresis =3D <2000>; + type =3D "passive"; + }; + cam_crit: trip-crit { temperature =3D <100000>; hysteresis =3D <2000>; @@ -1872,11 +2045,17 @@ cam_crit: trip-crit { }; =20 md0-thermal { - polling-delay =3D <0>; - polling-delay-passive =3D <0>; + polling-delay =3D <1000>; + polling-delay-passive =3D <250>; thermal-sensors =3D <&lvts_ap MT8192_AP_MD0>; =20 trips { + md0_alert: trip-alert { + temperature =3D <85000>; + hysteresis =3D <2000>; + type =3D "passive"; + }; + md0_crit: trip-crit { temperature =3D <100000>; hysteresis =3D <2000>; @@ -1886,11 +2065,17 @@ md0_crit: trip-crit { }; =20 md1-thermal { - polling-delay =3D <0>; - polling-delay-passive =3D <0>; + polling-delay =3D <1000>; + polling-delay-passive =3D <250>; thermal-sensors =3D <&lvts_ap MT8192_AP_MD1>; =20 trips { + md1_alert: trip-alert { + temperature =3D <85000>; + hysteresis =3D <2000>; + type =3D "passive"; + }; + md1_crit: trip-crit { temperature =3D <100000>; hysteresis =3D <2000>; @@ -1900,11 +2085,17 @@ md1_crit: trip-crit { }; =20 md2-thermal { - polling-delay =3D <0>; - polling-delay-passive =3D <0>; + polling-delay =3D <1000>; + polling-delay-passive =3D <250>; thermal-sensors =3D <&lvts_ap MT8192_AP_MD2>; =20 trips { + md2_alert: trip-alert { + temperature =3D <85000>; + hysteresis =3D <2000>; + type =3D "passive"; + }; + md2_crit: trip-crit { temperature =3D <100000>; hysteresis =3D <2000>; --=20 2.34.1