From nobody Sat Apr 11 12:59:13 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id D30B2C678D4 for ; Tue, 7 Mar 2023 10:25:38 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230281AbjCGKZg (ORCPT ); Tue, 7 Mar 2023 05:25:36 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:35390 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229525AbjCGKZ1 (ORCPT ); Tue, 7 Mar 2023 05:25:27 -0500 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 5EA6C5290F; Tue, 7 Mar 2023 02:25:21 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1678184721; x=1709720721; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=XVOGB1MKbCD9q0kwWf3Y939WJhlxGIP60HVW5R87Egg=; b=sVib/3ghsWOA/pyidmygcrT9U9ZQY7TuBI6NgDpH1qjN88FVgGR3Ewlm lqoyyWcUdhorxRNKupldnC6Ut2MDuYEgYWqy3Seb+AkzOnl/XG3rgJyF6 3+MqCn7RYB3BNhq4hs60oqI5/U66SSea57VqAFeHfxonWvIsOO3KH0LMI G4GtKROBOIBl/aee7tvvY8eMZNmqPVL7UFmP6WcPX0v2F+1wycrj94CMa WqHfSJVyvSYTpCkjyQgh0AP9f/y9OTICZuP7l/xbVbbTkFxwh0lz3Sw8x hPJdt8Hz4JEYP5xxJEwkPPn1e6dy6M90Q+oDHmVhvofT9xjgT/VVO5AkX g==; X-IronPort-AV: E=Sophos;i="5.98,240,1673938800"; d="scan'208";a="140694259" Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa6.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 07 Mar 2023 03:25:19 -0700 Received: from chn-vm-ex03.mchp-main.com (10.10.85.151) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.16; Tue, 7 Mar 2023 03:25:19 -0700 Received: from wendy.microchip.com (10.10.115.15) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server id 15.1.2507.16 via Frontend Transport; Tue, 7 Mar 2023 03:25:16 -0700 From: Conor Dooley To: CC: , , Miguel Ojeda , Alex Gaynor , Wedson Almeida Filho , Boqun Feng , Gary Guo , =?UTF-8?q?Bj=C3=B6rn=20Roy=20Baron?= , Jonathan Corbet , Paul Walmsley , Palmer Dabbelt , "Nathan Chancellor" , Nick Desaulniers , Tom Rix , , , , Subject: [PATCH v1 1/2] scripts: generate_rust_target: enable building on RISC-V Date: Tue, 7 Mar 2023 10:24:40 +0000 Message-ID: <20230307102441.94417-2-conor.dooley@microchip.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230307102441.94417-1-conor.dooley@microchip.com> References: <20230307102441.94417-1-conor.dooley@microchip.com> MIME-Version: 1.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=1821; i=conor.dooley@microchip.com; h=from:subject; bh=pr00Ws4xP6t9YpK/ZLk9y5gdrCaL6G8nYnSeAmZhBfg=; b=owGbwMvMwCFWscWwfUFT0iXG02pJDCnsAs9qpdez1rj9zF+iHerL/93bMvKB8jeJviVJhybu/Gd6 68z8jlIWBjEOBlkxRZbE230tUuv/uOxw7nkLM4eVCWQIAxenAEzEZyUjw2KV9qAllV8z2ve1q2iqfm rlu9qzNcK9bYd+ztKJZU6ZjQz/ayUOsLFt2TB1drtIkkjf9F3xt/UNFiqeuT6LKXBXxOtGTgA= X-Developer-Key: i=conor.dooley@microchip.com; a=openpgp; fpr=F9ECA03CF54F12CD01F1655722E2C55B37CF380C Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Miguel Ojeda Add the required bits from rust-for-linux to enable generating a RISC-V target for rust. The script, written by Miguel, was originally a config file contributed by Gary. Co-developed-by: Gary Guo Signed-off-by: Gary Guo Signed-off-by: Miguel Ojeda Signed-off-by: Conor Dooley --- Despite removing 32-bit support, I kept the structure of the if statement, despite early return being stylistically preferred, for alignment with the Rust-for-Linux tree. I'm happy to respin to sort that out of desired. --- scripts/generate_rust_target.rs | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/scripts/generate_rust_target.rs b/scripts/generate_rust_target= .rs index 3c6cbe2b278d3..85d690f764389 100644 --- a/scripts/generate_rust_target.rs +++ b/scripts/generate_rust_target.rs @@ -161,6 +161,22 @@ fn main() { ts.push("features", features); ts.push("llvm-target", "x86_64-linux-gnu"); ts.push("target-pointer-width", "64"); + } else if cfg.has("RISCV") { + if cfg.has("64BIT") { + ts.push("arch", "riscv64"); + ts.push("data-layout", "e-m:e-p:64:64-i64:64-i128:128-n64-S128= "); + ts.push("llvm-target", "riscv64-linux-gnu"); + ts.push("target-pointer-width", "64"); + } else { + panic!("32-bit RISC-V is an unsupported architecture") + } + ts.push("code-model", "medium"); + ts.push("disable-redzone", true); + let mut features =3D "+m,+a".to_string(); + if cfg.has("RISCV_ISA_C") { + features +=3D ",+c"; + } + ts.push("features", features); } else { panic!("Unsupported architecture"); } --=20 2.39.2 From nobody Sat Apr 11 12:59:13 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id ECE8BC6FD1B for ; Tue, 7 Mar 2023 10:25:45 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230255AbjCGKZo (ORCPT ); Tue, 7 Mar 2023 05:25:44 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:35486 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230236AbjCGKZb (ORCPT ); Tue, 7 Mar 2023 05:25:31 -0500 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id D567E5FF5; Tue, 7 Mar 2023 02:25:25 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1678184725; x=1709720725; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=qWB3e5tgDGUKCOsNQtNNw5AKYgfS2AJpadcC4RT6yqQ=; b=YWQES2dcbwVTCkleictX1E3V0UhpGGRfL/a0obG27EQyA1hDrcsxLXl2 FwcB+v9gys8cNnSTx3Wh6AUmNb7TUg+9IzoC+hAQrzPHNZJpnvghWCLp7 3mfgj1nn4PFxY0zlnOwmWVvP/71wmHzxkPzYLILb+LwU5SUaA4fXYfdFO EXfj/uMQ2jOewabptYdHL2Hwk0lpktOJj0JWzWRjHDTPdLBFdm89N4Xrx GRCizSYaKOtiYrYt6zYkIp3WIRsNyQeXrvCtTlqbjziyvfLc0+ZOtOhz4 +19rYCfKeblqP/illwnK+1uXVIkacxvAexKO9I96CG1IzZk48oTC8/SYc A==; X-IronPort-AV: E=Sophos;i="5.98,240,1673938800"; d="scan'208";a="204052299" Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa2.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 07 Mar 2023 03:25:24 -0700 Received: from chn-vm-ex03.mchp-main.com (10.10.85.151) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.16; Tue, 7 Mar 2023 03:25:22 -0700 Received: from wendy.microchip.com (10.10.115.15) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server id 15.1.2507.16 via Frontend Transport; Tue, 7 Mar 2023 03:25:19 -0700 From: Conor Dooley To: CC: , , Miguel Ojeda , Alex Gaynor , Wedson Almeida Filho , Boqun Feng , Gary Guo , =?UTF-8?q?Bj=C3=B6rn=20Roy=20Baron?= , Jonathan Corbet , Paul Walmsley , Palmer Dabbelt , "Nathan Chancellor" , Nick Desaulniers , Tom Rix , , , , Subject: [PATCH v1 2/2] RISC-V: enable building 64-bit kernels with rust support Date: Tue, 7 Mar 2023 10:24:41 +0000 Message-ID: <20230307102441.94417-3-conor.dooley@microchip.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230307102441.94417-1-conor.dooley@microchip.com> References: <20230307102441.94417-1-conor.dooley@microchip.com> MIME-Version: 1.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=2889; i=conor.dooley@microchip.com; h=from:subject; bh=yBD6MNol++6y2HAWMBBaDRLPC5EtLmNC6wyDPXZv0s4=; b=owGbwMvMwCFWscWwfUFT0iXG02pJDCnsAs+aOuwTWjpufIiaM2fzp6LVux5wqT1WnRVxQM+mrf5w VINVRykLgxgHg6yYIkvi7b4WqfV/XHY497yFmcPKBDKEgYtTACZyoI3hf4iJso1T2ZFneoqdb/5bWv Tebv2x8NxSR/1oV4uw6NaiVkaGdwZ6t/Wjz29b8GVH9OWbU7YeKJ5+V+Fi3plvhnYXf5s1sAAA X-Developer-Key: i=conor.dooley@microchip.com; a=openpgp; fpr=F9ECA03CF54F12CD01F1655722E2C55B37CF380C Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Miguel Ojeda The rust modules work on 64-bit RISC-V, with no twiddling required. Select HAVE_RUST and provide the required flags to kbuild so that the modules can be used. The Makefile and Kconfig changes are lifted from work done by Miguel in the Rust-for-Linux tree, hence his authorship. Following the rabbit hole, the Makefile changes originated in a script, created based on config files originally added by Gary, hence his co-authorship. 32-bit is broken in core rust code, so support is limited to 64-bit: ld.lld: error: undefined symbol: __udivdi3 As 64-bit RISC-V is now supported, add it to the arch support table, taking the opportunity to sort the table in alphabetical order. Co-developed-by: Gary Guo Signed-off-by: Gary Guo Signed-off-by: Miguel Ojeda Signed-off-by: Conor Dooley --- While adding RISC-V to the table, I took the chance to re-sort it alphabetically. I didn't think that warranted co-authorship, but given we had an authorship conversation already I am happy to provide one for that... --- Documentation/rust/arch-support.rst | 3 ++- arch/riscv/Kconfig | 1 + arch/riscv/Makefile | 2 ++ 3 files changed, 5 insertions(+), 1 deletion(-) diff --git a/Documentation/rust/arch-support.rst b/Documentation/rust/arch-= support.rst index ed7f4f5b3cf15..77765ffd5af41 100644 --- a/Documentation/rust/arch-support.rst +++ b/Documentation/rust/arch-support.rst @@ -15,7 +15,8 @@ support corresponds to ``S`` values in the ``MAINTAINERS`= ` file. =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D Architecture Level of support Constraints =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D -``x86`` Maintained ``x86_64`` only. +``riscv`` Maintained ``riscv64`` only. ``um`` Maintained ``x86_64`` only. +``x86`` Maintained ``x86_64`` only. =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D =20 diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig index c5e42cc376048..c3179b139361f 100644 --- a/arch/riscv/Kconfig +++ b/arch/riscv/Kconfig @@ -114,6 +114,7 @@ config RISCV select HAVE_POSIX_CPU_TIMERS_TASK_WORK select HAVE_REGS_AND_STACK_ACCESS_API select HAVE_RSEQ + select HAVE_RUST if 64BIT select HAVE_STACKPROTECTOR select HAVE_SYSCALL_TRACEPOINTS select IRQ_DOMAIN diff --git a/arch/riscv/Makefile b/arch/riscv/Makefile index 6203c33789228..950612bf193cf 100644 --- a/arch/riscv/Makefile +++ b/arch/riscv/Makefile @@ -31,6 +31,8 @@ ifeq ($(CONFIG_ARCH_RV64I),y) KBUILD_AFLAGS +=3D -mabi=3Dlp64 =20 KBUILD_LDFLAGS +=3D -melf64lriscv + + KBUILD_RUSTFLAGS +=3D -Ctarget-cpu=3Dgeneric-rv64 else BITS :=3D 32 UTS_MACHINE :=3D riscv32 --=20 2.39.2