From nobody Sat Apr 11 11:54:53 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id A75FEC6FD1D for ; Mon, 6 Mar 2023 16:36:56 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230254AbjCFQgo (ORCPT ); Mon, 6 Mar 2023 11:36:44 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:48268 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229930AbjCFQfx (ORCPT ); Mon, 6 Mar 2023 11:35:53 -0500 Received: from smtp-out1.suse.de (smtp-out1.suse.de [IPv6:2001:67c:2178:6::1c]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 1C1D739B8B for ; Mon, 6 Mar 2023 08:35:19 -0800 (PST) Received: from imap2.suse-dmz.suse.de (imap2.suse-dmz.suse.de [192.168.254.74]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (P-521) server-digest SHA512) (No client certificate requested) by smtp-out1.suse.de (Postfix) with ESMTPS id 694DC21C6C; Mon, 6 Mar 2023 16:34:33 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=suse.com; s=susede1; t=1678120473; h=from:from:reply-to:date:date:message-id:message-id:to:to:cc:cc: mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=wdZqXElp1B5EQPu6xSmwn38A5NK5TNGdQEx7TILYZLE=; b=UHmhOeQRK6Sy++tBvGVXthjYv7WqNFLqCX4CMLPwCve0KaCx8Wz1XB09BQlkb9YMNU7Jp3 th5A0ZTqwyvMf5kwHvBzhFpHuAuyDSbOKSJGdH9sNHPJaHKxKsslYoI+nxbCB+ZY/pAXKa /nnJrpGGPl4SVVwagBnyKD+PPbRyofk= Received: from imap2.suse-dmz.suse.de (imap2.suse-dmz.suse.de [192.168.254.74]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (P-521) server-digest SHA512) (No client certificate requested) by imap2.suse-dmz.suse.de (Postfix) with ESMTPS id 2C1D013A66; Mon, 6 Mar 2023 16:34:33 +0000 (UTC) Received: from dovecot-director2.suse.de ([192.168.254.65]) by imap2.suse-dmz.suse.de with ESMTPSA id LV5sCRkWBmQbUwAAMHmgww (envelope-from ); Mon, 06 Mar 2023 16:34:33 +0000 From: Juergen Gross To: linux-kernel@vger.kernel.org, x86@kernel.org Cc: Juergen Gross , Thomas Gleixner , Ingo Molnar , Borislav Petkov , Dave Hansen , "H. Peter Anvin" Subject: [PATCH v4 01/12] x86/mtrr: split off physical address size calculation Date: Mon, 6 Mar 2023 17:34:14 +0100 Message-Id: <20230306163425.8324-2-jgross@suse.com> X-Mailer: git-send-email 2.35.3 In-Reply-To: <20230306163425.8324-1-jgross@suse.com> References: <20230306163425.8324-1-jgross@suse.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Move the calculation of the physical address size in mtrr_bp_init() into a helper function. This will be needed later. Do only the pure code movement without optimizing it. Signed-off-by: Juergen Gross Tested-by: Michael Kelley --- V2: - new patch V3: - only move code, split off optimizations (Boris Petkov) --- arch/x86/kernel/cpu/mtrr/mtrr.c | 57 ++++++++++++++++++--------------- 1 file changed, 32 insertions(+), 25 deletions(-) diff --git a/arch/x86/kernel/cpu/mtrr/mtrr.c b/arch/x86/kernel/cpu/mtrr/mtr= r.c index 783f3210d582..8310bdb111d0 100644 --- a/arch/x86/kernel/cpu/mtrr/mtrr.c +++ b/arch/x86/kernel/cpu/mtrr/mtrr.c @@ -620,22 +620,14 @@ static struct syscore_ops mtrr_syscore_ops =3D { int __initdata changed_by_mtrr_cleanup; =20 #define SIZE_OR_MASK_BITS(n) (~((1ULL << ((n) - PAGE_SHIFT)) - 1)) -/** - * mtrr_bp_init - initialize mtrrs on the boot CPU - * - * This needs to be called early; before any of the other CPUs are - * initialized (i.e. before smp_init()). - * - */ -void __init mtrr_bp_init(void) + +static unsigned int __init mtrr_calc_physbits(bool generic) { - const char *why =3D "(not available)"; - u32 phys_addr; + unsigned int phys_addr; =20 phys_addr =3D 32; =20 - if (boot_cpu_has(X86_FEATURE_MTRR)) { - mtrr_if =3D &generic_mtrr_ops; + if (generic) { size_or_mask =3D SIZE_OR_MASK_BITS(36); size_and_mask =3D 0x00f00000; phys_addr =3D 36; @@ -667,29 +659,44 @@ void __init mtrr_bp_init(void) size_and_mask =3D 0; phys_addr =3D 32; } + } else { + size_or_mask =3D SIZE_OR_MASK_BITS(32); + size_and_mask =3D 0; + } + + return phys_addr; +} + +/** + * mtrr_bp_init - initialize mtrrs on the boot CPU + * + * This needs to be called early; before any of the other CPUs are + * initialized (i.e. before smp_init()). + * + */ +void __init mtrr_bp_init(void) +{ + const char *why =3D "(not available)"; + unsigned int phys_addr; + + phys_addr =3D mtrr_calc_physbits(boot_cpu_has(X86_FEATURE_MTRR)); + + if (boot_cpu_has(X86_FEATURE_MTRR)) { + mtrr_if =3D &generic_mtrr_ops; } else { switch (boot_cpu_data.x86_vendor) { case X86_VENDOR_AMD: - if (cpu_feature_enabled(X86_FEATURE_K6_MTRR)) { - /* Pre-Athlon (K6) AMD CPU MTRRs */ + /* Pre-Athlon (K6) AMD CPU MTRRs */ + if (cpu_feature_enabled(X86_FEATURE_K6_MTRR)) mtrr_if =3D &amd_mtrr_ops; - size_or_mask =3D SIZE_OR_MASK_BITS(32); - size_and_mask =3D 0; - } break; case X86_VENDOR_CENTAUR: - if (cpu_feature_enabled(X86_FEATURE_CENTAUR_MCR)) { + if (cpu_feature_enabled(X86_FEATURE_CENTAUR_MCR)) mtrr_if =3D ¢aur_mtrr_ops; - size_or_mask =3D SIZE_OR_MASK_BITS(32); - size_and_mask =3D 0; - } break; case X86_VENDOR_CYRIX: - if (cpu_feature_enabled(X86_FEATURE_CYRIX_ARR)) { + if (cpu_feature_enabled(X86_FEATURE_CYRIX_ARR)) mtrr_if =3D &cyrix_mtrr_ops; - size_or_mask =3D SIZE_OR_MASK_BITS(32); - size_and_mask =3D 0; - } break; default: break; --=20 2.35.3 From nobody Sat Apr 11 11:54:53 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id C9A89C6FD1F for ; Mon, 6 Mar 2023 16:36:56 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230360AbjCFQgx (ORCPT ); Mon, 6 Mar 2023 11:36:53 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:48344 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230007AbjCFQf4 (ORCPT ); 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Mon, 6 Mar 2023 16:34:38 +0000 (UTC) Received: from dovecot-director2.suse.de ([192.168.254.65]) by imap2.suse-dmz.suse.de with ESMTPSA id TJhGMR4WBmQpUwAAMHmgww (envelope-from ); Mon, 06 Mar 2023 16:34:38 +0000 From: Juergen Gross To: linux-kernel@vger.kernel.org, x86@kernel.org Cc: Juergen Gross , Thomas Gleixner , Ingo Molnar , Borislav Petkov , Dave Hansen , "H. Peter Anvin" Subject: [PATCH v4 02/12] x86/mtrr: optimize mtrr_calc_physbits() Date: Mon, 6 Mar 2023 17:34:15 +0100 Message-Id: <20230306163425.8324-3-jgross@suse.com> X-Mailer: git-send-email 2.35.3 In-Reply-To: <20230306163425.8324-1-jgross@suse.com> References: <20230306163425.8324-1-jgross@suse.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Optimize mtrr_calc_physbits() for better readability. Drop a stale comment, as reality has made it obsolete. Signed-off-by: Juergen Gross Tested-by: Michael Kelley --- V3: - new patch, split off from previous patch (Boris Petkov) --- arch/x86/kernel/cpu/mtrr/mtrr.c | 19 +++---------------- 1 file changed, 3 insertions(+), 16 deletions(-) diff --git a/arch/x86/kernel/cpu/mtrr/mtrr.c b/arch/x86/kernel/cpu/mtrr/mtr= r.c index 8310bdb111d0..7596ebeab929 100644 --- a/arch/x86/kernel/cpu/mtrr/mtrr.c +++ b/arch/x86/kernel/cpu/mtrr/mtrr.c @@ -619,8 +619,6 @@ static struct syscore_ops mtrr_syscore_ops =3D { =20 int __initdata changed_by_mtrr_cleanup; =20 -#define SIZE_OR_MASK_BITS(n) (~((1ULL << ((n) - PAGE_SHIFT)) - 1)) - static unsigned int __init mtrr_calc_physbits(bool generic) { unsigned int phys_addr; @@ -628,15 +626,8 @@ static unsigned int __init mtrr_calc_physbits(bool gen= eric) phys_addr =3D 32; =20 if (generic) { - size_or_mask =3D SIZE_OR_MASK_BITS(36); - size_and_mask =3D 0x00f00000; phys_addr =3D 36; =20 - /* - * This is an AMD specific MSR, but we assume(hope?) that - * Intel will implement it too when they extend the address - * bus of the Xeon. - */ if (cpuid_eax(0x80000000) >=3D 0x80000008) { phys_addr =3D cpuid_eax(0x80000008) & 0xff; /* CPUID workaround for Intel 0F33/0F34 CPU */ @@ -647,23 +638,19 @@ static unsigned int __init mtrr_calc_physbits(bool ge= neric) boot_cpu_data.x86_stepping =3D=3D 0x4)) phys_addr =3D 36; =20 - size_or_mask =3D SIZE_OR_MASK_BITS(phys_addr); - size_and_mask =3D ~size_or_mask & 0xfffff00000ULL; } else if (boot_cpu_data.x86_vendor =3D=3D X86_VENDOR_CENTAUR && boot_cpu_data.x86 =3D=3D 6) { /* * VIA C* family have Intel style MTRRs, * but don't support PAE */ - size_or_mask =3D SIZE_OR_MASK_BITS(32); - size_and_mask =3D 0; phys_addr =3D 32; } - } else { - size_or_mask =3D SIZE_OR_MASK_BITS(32); - size_and_mask =3D 0; } =20 + size_or_mask =3D ~((1ULL << (phys_addr - PAGE_SHIFT)) - 1); + size_and_mask =3D ~size_or_mask & 0xfffff00000ULL; + return phys_addr; } =20 --=20 2.35.3 From nobody Sat Apr 11 11:54:53 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 05B1BC6FA99 for ; Mon, 6 Mar 2023 16:37:11 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230379AbjCFQg4 (ORCPT ); Mon, 6 Mar 2023 11:36:56 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:47340 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230211AbjCFQgG (ORCPT ); Mon, 6 Mar 2023 11:36:06 -0500 Received: from smtp-out2.suse.de (smtp-out2.suse.de [IPv6:2001:67c:2178:6::1d]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id BB30242BD9 for ; Mon, 6 Mar 2023 08:35:29 -0800 (PST) Received: from imap2.suse-dmz.suse.de (imap2.suse-dmz.suse.de [192.168.254.74]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (P-521) server-digest SHA512) (No client certificate requested) by smtp-out2.suse.de (Postfix) with ESMTPS id AEEB01FDE5; Mon, 6 Mar 2023 16:34:44 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=suse.com; s=susede1; t=1678120484; h=from:from:reply-to:date:date:message-id:message-id:to:to:cc:cc: mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=mQIwzGwKV8auzcLGhE1h+Ttf3dgEINxZJAfs4KKmG8o=; b=lstrsomyfTeRwpQM78KPNKAwcec5755jNucEwcWtQmzFrgh5sgfsT8yRNpGYrDsAGSe2T9 5aXuR0fQ2EH8f0gHCn1QIhiogy9S3plHmqbnuOKmlU+H3L+8NZaYaUyQybDtJ9cZgCo/fs /ZNxnmdBFtMH8CgiohSEGtRvniUszWk= Received: from imap2.suse-dmz.suse.de (imap2.suse-dmz.suse.de [192.168.254.74]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (P-521) server-digest SHA512) (No client certificate requested) by imap2.suse-dmz.suse.de (Postfix) with ESMTPS id 72F0D13A66; Mon, 6 Mar 2023 16:34:44 +0000 (UTC) Received: from dovecot-director2.suse.de ([192.168.254.65]) by imap2.suse-dmz.suse.de with ESMTPSA id brHMGiQWBmQzUwAAMHmgww (envelope-from ); Mon, 06 Mar 2023 16:34:44 +0000 From: Juergen Gross To: linux-kernel@vger.kernel.org, x86@kernel.org Cc: Juergen Gross , Thomas Gleixner , Ingo Molnar , Borislav Petkov , Dave Hansen , "H. Peter Anvin" Subject: [PATCH v4 03/12] x86/mtrr: support setting MTRR state for software defined MTRRs Date: Mon, 6 Mar 2023 17:34:16 +0100 Message-Id: <20230306163425.8324-4-jgross@suse.com> X-Mailer: git-send-email 2.35.3 In-Reply-To: <20230306163425.8324-1-jgross@suse.com> References: <20230306163425.8324-1-jgross@suse.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" When running virtualized, MTRR access can be reduced (e.g. in Xen PV guests or when running as a SEV-SNP guest under Hyper-V). Typically the hypervisor will reset the MTRR feature in CPUID data, resulting in no MTRR memory type information being available for the kernel. This has turned out to result in problems: - Hyper-V SEV-SNP guests using uncached mappings where they shouldn't - Xen PV dom0 mapping memory as WB which should be UC- instead Solve those problems by supporting to set a static MTRR state, overwriting the empty state used today. In case such a state has been set, don't call get_mtrr_state() in mtrr_bp_init(). The set state will only be used by mtrr_type_lookup(), as in all other cases mtrr_enabled() is being checked, which will return false. Accept the overwrite call only for selected cases when running as a guest. Disable X86_FEATURE_MTRR in order to avoid any MTRR modifications by just refusing them. Signed-off-by: Juergen Gross Tested-by: Michael Kelley --- V2: - new patch V3: - omit fixed MTRRs, as those are currently not needed - disable X86_FEATURE_MTRR instead of testing it - provide a stub for !CONFIG_MTRR (Michael Kelley) - use cpu_feature_enabled() (Boris Petkov) - add tests for mtrr_overwrite_state() being allowed (Boris Petkov) V4: - add test for hv_is_isolation_supported() (Michael Kelley) --- arch/x86/include/asm/mtrr.h | 8 ++++++ arch/x86/kernel/cpu/mtrr/generic.c | 46 +++++++++++++++++++++++++++++- arch/x86/kernel/cpu/mtrr/mtrr.c | 9 ++++++ arch/x86/kernel/setup.c | 2 ++ 4 files changed, 64 insertions(+), 1 deletion(-) diff --git a/arch/x86/include/asm/mtrr.h b/arch/x86/include/asm/mtrr.h index f0eeaf6e5f5f..f1cb81330a64 100644 --- a/arch/x86/include/asm/mtrr.h +++ b/arch/x86/include/asm/mtrr.h @@ -31,6 +31,8 @@ */ # ifdef CONFIG_MTRR void mtrr_bp_init(void); +void mtrr_overwrite_state(struct mtrr_var_range *var, unsigned int num_var, + mtrr_type def_type); extern u8 mtrr_type_lookup(u64 addr, u64 end, u8 *uniform); extern void mtrr_save_fixed_ranges(void *); extern void mtrr_save_state(void); @@ -48,6 +50,12 @@ void mtrr_disable(void); void mtrr_enable(void); void mtrr_generic_set_state(void); # else +static inline void mtrr_overwrite_state(struct mtrr_var_range *var, + unsigned int num_var, + mtrr_type def_type) +{ +} + static inline u8 mtrr_type_lookup(u64 addr, u64 end, u8 *uniform) { /* diff --git a/arch/x86/kernel/cpu/mtrr/generic.c b/arch/x86/kernel/cpu/mtrr/= generic.c index ee09d359e08f..49b4cc923312 100644 --- a/arch/x86/kernel/cpu/mtrr/generic.c +++ b/arch/x86/kernel/cpu/mtrr/generic.c @@ -8,10 +8,12 @@ #include #include #include - +#include #include #include #include +#include +#include #include #include #include @@ -240,6 +242,48 @@ static u8 mtrr_type_lookup_variable(u64 start, u64 end= , u64 *partial_end, return mtrr_state.def_type; } =20 +/** + * mtrr_overwrite_state - set static MTRR state + * + * Used to set MTRR state via different means (e.g. with data obtained from + * a hypervisor). + * Is allowed only for special cases when running virtualized. Must be cal= led + * from the x86_init.hyper.init_platform() hook. X86_FEATURE_MTRR must be = off. + */ +void mtrr_overwrite_state(struct mtrr_var_range *var, unsigned int num_var, + mtrr_type def_type) +{ + unsigned int i; + + if (WARN_ON(mtrr_state_set || + hypervisor_is_type(X86_HYPER_NATIVE) || + !cpu_feature_enabled(X86_FEATURE_HYPERVISOR) || + (!cc_platform_has(CC_ATTR_GUEST_SEV_SNP) && + !hv_is_isolation_supported() && + !cpu_feature_enabled(X86_FEATURE_XENPV) && + !cpu_feature_enabled(X86_FEATURE_TDX_GUEST)))) + return; + + /* Disable MTRR in order to disable MTRR modifications. */ + setup_clear_cpu_cap(X86_FEATURE_MTRR); + + if (var) { + if (num_var > MTRR_MAX_VAR_RANGES) { + pr_warn("Trying to overwrite MTRR state with %u variable entries\n", + num_var); + num_var =3D MTRR_MAX_VAR_RANGES; + } + for (i =3D 0; i < num_var; i++) + mtrr_state.var_ranges[i] =3D var[i]; + num_var_ranges =3D num_var; + } + + mtrr_state.def_type =3D def_type; + mtrr_state.enabled |=3D MTRR_STATE_MTRR_ENABLED; + + mtrr_state_set =3D 1; +} + /** * mtrr_type_lookup - look up memory type in MTRR * diff --git a/arch/x86/kernel/cpu/mtrr/mtrr.c b/arch/x86/kernel/cpu/mtrr/mtr= r.c index 7596ebeab929..5fe62ee0361b 100644 --- a/arch/x86/kernel/cpu/mtrr/mtrr.c +++ b/arch/x86/kernel/cpu/mtrr/mtrr.c @@ -666,6 +666,15 @@ void __init mtrr_bp_init(void) const char *why =3D "(not available)"; unsigned int phys_addr; =20 + if (mtrr_state.enabled) { + /* Software overwrite of MTRR state, only for generic case. */ + mtrr_calc_physbits(true); + init_table(); + pr_info("MTRRs set to read-only\n"); + + return; + } + phys_addr =3D mtrr_calc_physbits(boot_cpu_has(X86_FEATURE_MTRR)); =20 if (boot_cpu_has(X86_FEATURE_MTRR)) { diff --git a/arch/x86/kernel/setup.c b/arch/x86/kernel/setup.c index 16babff771bd..0cccfeb67c3a 100644 --- a/arch/x86/kernel/setup.c +++ b/arch/x86/kernel/setup.c @@ -1037,6 +1037,8 @@ void __init setup_arch(char **cmdline_p) /* * VMware detection requires dmi to be available, so this * needs to be done after dmi_setup(), for the boot CPU. + * For some guest types (Xen PV, SEV-SNP, TDX) it is required to be + * called before cache_bp_init() for setting up MTRR state. */ init_hypervisor_platform(); =20 --=20 2.35.3 From nobody Sat Apr 11 11:54:53 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2EAF1C6FD1C for ; Mon, 6 Mar 2023 16:37:11 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229928AbjCFQhA (ORCPT ); Mon, 6 Mar 2023 11:37:00 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:48080 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230287AbjCFQgL (ORCPT ); Mon, 6 Mar 2023 11:36:11 -0500 Received: from smtp-out1.suse.de (smtp-out1.suse.de [195.135.220.28]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 53B2F4390C; Mon, 6 Mar 2023 08:35:37 -0800 (PST) Received: from imap2.suse-dmz.suse.de (imap2.suse-dmz.suse.de [192.168.254.74]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (P-521) server-digest SHA512) (No client certificate requested) by smtp-out1.suse.de (Postfix) with ESMTPS id 7789921E5D; Mon, 6 Mar 2023 16:34:50 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=suse.com; s=susede1; t=1678120490; h=from:from:reply-to:date:date:message-id:message-id:to:to:cc:cc: mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=EEyy0YGNrjiScFEJSCN9XqA2TAW4Ejl4yGBfINYDlUs=; b=hykKurK9/WXS6qISoyLDcDHoUPTa6DT2LVEsW+HX1QsXJ0G5yeT0pc2YbmUapmb9VennA3 yx5uPl6pHjSN+PR7U5sxC+wj8Z/kbztWb3NkzdcLlXeUJXYTivVOxlBOrfZl+IdV536VzX e3PDiwTRa+CSvX3UOk/PJo5Y3opyfRA= Received: from imap2.suse-dmz.suse.de (imap2.suse-dmz.suse.de [192.168.254.74]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (P-521) server-digest SHA512) (No client certificate requested) by imap2.suse-dmz.suse.de (Postfix) with ESMTPS id 2756B13A66; Mon, 6 Mar 2023 16:34:50 +0000 (UTC) Received: from dovecot-director2.suse.de ([192.168.254.65]) by imap2.suse-dmz.suse.de with ESMTPSA id yD1zCCoWBmREUwAAMHmgww (envelope-from ); Mon, 06 Mar 2023 16:34:50 +0000 From: Juergen Gross To: linux-kernel@vger.kernel.org, x86@kernel.org, linux-hyperv@vger.kernel.org Cc: Juergen Gross , "K. Y. Srinivasan" , Haiyang Zhang , Wei Liu , Dexuan Cui , Thomas Gleixner , Ingo Molnar , Borislav Petkov , Dave Hansen , "H. Peter Anvin" Subject: [PATCH v4 04/12] x86/hyperv: set MTRR state when running as SEV-SNP Hyper-V guest Date: Mon, 6 Mar 2023 17:34:17 +0100 Message-Id: <20230306163425.8324-5-jgross@suse.com> X-Mailer: git-send-email 2.35.3 In-Reply-To: <20230306163425.8324-1-jgross@suse.com> References: <20230306163425.8324-1-jgross@suse.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" In order to avoid mappings using the UC- cache attribute, set the MTRR state to use WB caching as the default. This is needed in order to cope with the fact that PAT is enabled, while MTRRs are not supported by the hypervisor. Fixes: 90b926e68f50 ("x86/pat: Fix pat_x_mtrr_type() for MTRR disabled case= ") Signed-off-by: Juergen Gross Tested-by: Michael Kelley --- V2: - new patch --- arch/x86/kernel/cpu/mshyperv.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/x86/kernel/cpu/mshyperv.c b/arch/x86/kernel/cpu/mshyperv.c index f36dc2f796c5..0a6cc3cf8919 100644 --- a/arch/x86/kernel/cpu/mshyperv.c +++ b/arch/x86/kernel/cpu/mshyperv.c @@ -34,6 +34,7 @@ #include #include #include +#include =20 /* Is Linux running as the root partition? */ bool hv_root_partition; @@ -408,6 +409,9 @@ static void __init ms_hyperv_init_platform(void) #ifdef CONFIG_SWIOTLB swiotlb_unencrypted_base =3D ms_hyperv.shared_gpa_boundary; #endif + + /* Set WB as the default cache mode. */ + mtrr_overwrite_state(NULL, 0, MTRR_TYPE_WRBACK); } /* Isolation VMs are unenlightened SEV-based VMs, thus this check: */ if (IS_ENABLED(CONFIG_AMD_MEM_ENCRYPT)) { --=20 2.35.3 From nobody Sat Apr 11 11:54:53 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; 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Mon, 06 Mar 2023 16:34:55 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: d43a97c4-bc3c-11ed-96b5-2f268f93b82a DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=suse.com; s=susede1; t=1678120496; h=from:from:reply-to:date:date:message-id:message-id:to:to:cc:cc: mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=QeDAQjSRqeP0iwOfsSlKaCLfsyacyLvFFynhKMg6itw=; b=L0ORxZJRMkPybl9qj+RAorA80nbejKg5XvHMdSpdYEzrYn4KgSUMFPaxfEgYjAJI2bDKF6 mzHQ5m87Ic6c/BgUzhbf/mMcZy2OPaG9/RLe5a2OW4fb8jiZZ/45mtEDztLmim1NkEWYVx QUxyHCFID5ix33QJnlXAQ1ezxKn5AN8= From: Juergen Gross To: linux-kernel@vger.kernel.org, x86@kernel.org Cc: Juergen Gross , Boris Ostrovsky , Thomas Gleixner , Ingo Molnar , Borislav Petkov , Dave Hansen , "H. Peter Anvin" , xen-devel@lists.xenproject.org Subject: [PATCH v4 05/12] x86/xen: set MTRR state when running as Xen PV initial domain Date: Mon, 6 Mar 2023 17:34:18 +0100 Message-Id: <20230306163425.8324-6-jgross@suse.com> X-Mailer: git-send-email 2.35.3 In-Reply-To: <20230306163425.8324-1-jgross@suse.com> References: <20230306163425.8324-1-jgross@suse.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @suse.com) X-ZM-MESSAGEID: 1678120520847100001 Content-Type: text/plain; charset="utf-8" When running as Xen PV initial domain (aka dom0), MTRRs are disabled by the hypervisor, but the system should nevertheless use correct cache memory types. This has always kind of worked, as disabled MTRRs resulted in disabled PAT, too, so that the kernel avoided code paths resulting in inconsistencies. This bypassed all of the sanity checks the kernel is doing with enabled MTRRs in order to avoid memory mappings with conflicting memory types. This has been changed recently, leading to PAT being accepted to be enabled, while MTRRs stayed disabled. The result is that mtrr_type_lookup() no longer is accepting all memory type requests, but started to return WB even if UC- was requested. This led to driver failures during initialization of some devices. In reality MTRRs are still in effect, but they are under complete control of the Xen hypervisor. It is possible, however, to retrieve the MTRR settings from the hypervisor. In order to fix those problems, overwrite the MTRR state via mtrr_overwrite_state() with the MTRR data from the hypervisor, if the system is running as a Xen dom0. Fixes: 72cbc8f04fe2 ("x86/PAT: Have pat_enabled() properly reflect state wh= en running on Xen") Signed-off-by: Juergen Gross Reviewed-by: Boris Ostrovsky Tested-by: Michael Kelley --- V2: - new patch V3: - move the call of mtrr_overwrite_state() to xen_pv_init_platform() V4: - only call mtrr_overwrite_state() if any MTRR got from Xen (Boris Ostrovsky) --- arch/x86/xen/enlighten_pv.c | 52 +++++++++++++++++++++++++++++++++++++ 1 file changed, 52 insertions(+) diff --git a/arch/x86/xen/enlighten_pv.c b/arch/x86/xen/enlighten_pv.c index bb59cc6ddb2d..12e6b6845870 100644 --- a/arch/x86/xen/enlighten_pv.c +++ b/arch/x86/xen/enlighten_pv.c @@ -68,6 +68,7 @@ #include #include #include +#include #include #include #include @@ -119,6 +120,54 @@ static int __init parse_xen_msr_safe(char *str) } early_param("xen_msr_safe", parse_xen_msr_safe); =20 +/* Get MTRR settings from Xen and put them into mtrr_state. */ +static void __init xen_set_mtrr_data(void) +{ +#ifdef CONFIG_MTRR + struct xen_platform_op op =3D { + .cmd =3D XENPF_read_memtype, + .interface_version =3D XENPF_INTERFACE_VERSION, + }; + unsigned int reg; + unsigned long mask; + uint32_t eax, width; + static struct mtrr_var_range var[MTRR_MAX_VAR_RANGES] __initdata; + + /* Get physical address width (only 64-bit cpus supported). */ + width =3D 36; + eax =3D cpuid_eax(0x80000000); + if ((eax >> 16) =3D=3D 0x8000 && eax >=3D 0x80000008) { + eax =3D cpuid_eax(0x80000008); + width =3D eax & 0xff; + } + + for (reg =3D 0; reg < MTRR_MAX_VAR_RANGES; reg++) { + op.u.read_memtype.reg =3D reg; + if (HYPERVISOR_platform_op(&op)) + break; + + /* + * Only called in dom0, which has all RAM PFNs mapped at + * RAM MFNs, and all PCI space etc. is identity mapped. + * This means we can treat MFN =3D=3D PFN regarding MTTR settings. + */ + var[reg].base_lo =3D op.u.read_memtype.type; + var[reg].base_lo |=3D op.u.read_memtype.mfn << PAGE_SHIFT; + var[reg].base_hi =3D op.u.read_memtype.mfn >> (32 - PAGE_SHIFT); + mask =3D ~((op.u.read_memtype.nr_mfns << PAGE_SHIFT) - 1); + mask &=3D (1UL << width) - 1; + if (mask) + mask |=3D 1 << 11; + var[reg].mask_lo =3D mask; + var[reg].mask_hi =3D mask >> 32; + } + + /* Only overwrite MTRR state if any MTRR could be got from Xen. */ + if (reg) + mtrr_overwrite_state(var, reg, MTRR_TYPE_UNCACHABLE); +#endif +} + static void __init xen_pv_init_platform(void) { /* PV guests can't operate virtio devices without grants. */ @@ -135,6 +184,9 @@ static void __init xen_pv_init_platform(void) =20 /* pvclock is in shared info area */ xen_init_time_ops(); + + if (xen_initial_domain()) + xen_set_mtrr_data(); } =20 static void __init xen_pv_guest_late_init(void) --=20 2.35.3 From nobody Sat Apr 11 11:54:53 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 46919C61DA4 for ; Mon, 6 Mar 2023 16:37:42 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230233AbjCFQhR (ORCPT ); Mon, 6 Mar 2023 11:37:17 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:48070 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230332AbjCFQgS (ORCPT ); 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Mon, 6 Mar 2023 16:35:01 +0000 (UTC) Received: from dovecot-director2.suse.de ([192.168.254.65]) by imap2.suse-dmz.suse.de with ESMTPSA id J+usITUWBmRoUwAAMHmgww (envelope-from ); Mon, 06 Mar 2023 16:35:01 +0000 From: Juergen Gross To: linux-kernel@vger.kernel.org, x86@kernel.org Cc: Juergen Gross , Thomas Gleixner , Ingo Molnar , Borislav Petkov , Dave Hansen , "H. Peter Anvin" Subject: [PATCH v4 06/12] x86/mtrr: replace vendor tests in MTRR code Date: Mon, 6 Mar 2023 17:34:19 +0100 Message-Id: <20230306163425.8324-7-jgross@suse.com> X-Mailer: git-send-email 2.35.3 In-Reply-To: <20230306163425.8324-1-jgross@suse.com> References: <20230306163425.8324-1-jgross@suse.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Modern CPUs all share the same MTRR interface implemented via generic_mtrr_ops. At several places in MTRR code this generic interface is deduced via is_cpu(INTEL) tests, which is only working due to X86_VENDOR_INTEL being 0 (the is_cpu() macro is testing mtrr_if->vendor, which isn't explicitly set in generic_mtrr_ops). Fix that by replacing the is_cpu(INTEL) tests with testing for mtrr_if to be &generic_mtrr_ops. The only other place where the .vendor member of struct mtrr_ops is being used is in set_num_var_ranges(), where depending on the vendor the number of MTRR registers is determined. This can easily be changed by replacing .vendor with the static number of MTRR registers. It should be noted that the test "is_cpu(HYGON)" wasn't ever returning true, as there is no struct mtrr_ops with that vendor information. Signed-off-by: Juergen Gross Tested-by: Michael Kelley --- V3: - new patch --- arch/x86/kernel/cpu/mtrr/amd.c | 2 +- arch/x86/kernel/cpu/mtrr/centaur.c | 2 +- arch/x86/kernel/cpu/mtrr/cleanup.c | 4 ++-- arch/x86/kernel/cpu/mtrr/cyrix.c | 2 +- arch/x86/kernel/cpu/mtrr/generic.c | 2 +- arch/x86/kernel/cpu/mtrr/mtrr.c | 8 +++----- arch/x86/kernel/cpu/mtrr/mtrr.h | 4 +--- 7 files changed, 10 insertions(+), 14 deletions(-) diff --git a/arch/x86/kernel/cpu/mtrr/amd.c b/arch/x86/kernel/cpu/mtrr/amd.c index eff6ac62c0ff..ef3e8e42b782 100644 --- a/arch/x86/kernel/cpu/mtrr/amd.c +++ b/arch/x86/kernel/cpu/mtrr/amd.c @@ -110,7 +110,7 @@ amd_validate_add_page(unsigned long base, unsigned long= size, unsigned int type) } =20 const struct mtrr_ops amd_mtrr_ops =3D { - .vendor =3D X86_VENDOR_AMD, + .var_regs =3D 2, .set =3D amd_set_mtrr, .get =3D amd_get_mtrr, .get_free_region =3D generic_get_free_region, diff --git a/arch/x86/kernel/cpu/mtrr/centaur.c b/arch/x86/kernel/cpu/mtrr/= centaur.c index b8a74eddde83..4466ddeb0125 100644 --- a/arch/x86/kernel/cpu/mtrr/centaur.c +++ b/arch/x86/kernel/cpu/mtrr/centaur.c @@ -112,7 +112,7 @@ centaur_validate_add_page(unsigned long base, unsigned = long size, unsigned int t } =20 const struct mtrr_ops centaur_mtrr_ops =3D { - .vendor =3D X86_VENDOR_CENTAUR, + .var_regs =3D 8, .set =3D centaur_set_mcr, .get =3D centaur_get_mcr, .get_free_region =3D centaur_get_free_region, diff --git a/arch/x86/kernel/cpu/mtrr/cleanup.c b/arch/x86/kernel/cpu/mtrr/= cleanup.c index b5f43049fa5f..1c2c0c252fa5 100644 --- a/arch/x86/kernel/cpu/mtrr/cleanup.c +++ b/arch/x86/kernel/cpu/mtrr/cleanup.c @@ -689,7 +689,7 @@ int __init mtrr_cleanup(unsigned address_bits) int index_good; int i; =20 - if (!is_cpu(INTEL) || enable_mtrr_cleanup < 1) + if (mtrr_if !=3D &generic_mtrr_ops || enable_mtrr_cleanup < 1) return 0; =20 rdmsr(MSR_MTRRdefType, def, dummy); @@ -886,7 +886,7 @@ int __init mtrr_trim_uncached_memory(unsigned long end_= pfn) * Make sure we only trim uncachable memory on machines that * support the Intel MTRR architecture: */ - if (!is_cpu(INTEL) || disable_mtrr_trim) + if (mtrr_if !=3D &generic_mtrr_ops || disable_mtrr_trim) return 0; =20 rdmsr(MSR_MTRRdefType, def, dummy); diff --git a/arch/x86/kernel/cpu/mtrr/cyrix.c b/arch/x86/kernel/cpu/mtrr/cy= rix.c index 173b9e01e623..238dad57d4d6 100644 --- a/arch/x86/kernel/cpu/mtrr/cyrix.c +++ b/arch/x86/kernel/cpu/mtrr/cyrix.c @@ -235,7 +235,7 @@ static void cyrix_set_arr(unsigned int reg, unsigned lo= ng base, } =20 const struct mtrr_ops cyrix_mtrr_ops =3D { - .vendor =3D X86_VENDOR_CYRIX, + .var_regs =3D 8, .set =3D cyrix_set_arr, .get =3D cyrix_get_arr, .get_free_region =3D cyrix_get_free_region, diff --git a/arch/x86/kernel/cpu/mtrr/generic.c b/arch/x86/kernel/cpu/mtrr/= generic.c index 49b4cc923312..e25a44c2c950 100644 --- a/arch/x86/kernel/cpu/mtrr/generic.c +++ b/arch/x86/kernel/cpu/mtrr/generic.c @@ -827,7 +827,7 @@ int generic_validate_add_page(unsigned long base, unsig= ned long size, * For Intel PPro stepping <=3D 7 * must be 4 MiB aligned and not touch 0x70000000 -> 0x7003FFFF */ - if (is_cpu(INTEL) && boot_cpu_data.x86 =3D=3D 6 && + if (mtrr_if =3D=3D &generic_mtrr_ops && boot_cpu_data.x86 =3D=3D 6 && boot_cpu_data.x86_model =3D=3D 1 && boot_cpu_data.x86_stepping <=3D 7) { if (base & ((1 << (22 - PAGE_SHIFT)) - 1)) { diff --git a/arch/x86/kernel/cpu/mtrr/mtrr.c b/arch/x86/kernel/cpu/mtrr/mtr= r.c index 5fe62ee0361b..0c83990501f5 100644 --- a/arch/x86/kernel/cpu/mtrr/mtrr.c +++ b/arch/x86/kernel/cpu/mtrr/mtrr.c @@ -108,14 +108,12 @@ static int have_wrcomb(void) /* This function returns the number of variable MTRRs */ static void __init set_num_var_ranges(bool use_generic) { - unsigned long config =3D 0, dummy; + unsigned long config, dummy; =20 if (use_generic) rdmsr(MSR_MTRRcap, config, dummy); - else if (is_cpu(AMD) || is_cpu(HYGON)) - config =3D 2; - else if (is_cpu(CYRIX) || is_cpu(CENTAUR)) - config =3D 8; + else + config =3D mtrr_if->var_regs; =20 num_var_ranges =3D config & 0xff; } diff --git a/arch/x86/kernel/cpu/mtrr/mtrr.h b/arch/x86/kernel/cpu/mtrr/mtr= r.h index 02eb5871492d..a3c362d3d5bf 100644 --- a/arch/x86/kernel/cpu/mtrr/mtrr.h +++ b/arch/x86/kernel/cpu/mtrr/mtrr.h @@ -13,7 +13,7 @@ extern unsigned int mtrr_usage_table[MTRR_MAX_VAR_RANGES]; =20 struct mtrr_ops { - u32 vendor; + u32 var_regs; void (*set)(unsigned int reg, unsigned long base, unsigned long size, mtrr_type type); void (*get)(unsigned int reg, unsigned long *base, @@ -54,8 +54,6 @@ bool get_mtrr_state(void); extern u64 size_or_mask, size_and_mask; extern const struct mtrr_ops *mtrr_if; =20 -#define is_cpu(vnd) (mtrr_if && mtrr_if->vendor =3D=3D X86_VENDOR_##vnd) - extern unsigned int num_var_ranges; extern u64 mtrr_tom2; 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Mon, 06 Mar 2023 16:35:07 +0000 From: Juergen Gross To: linux-kernel@vger.kernel.org, x86@kernel.org Cc: Juergen Gross , Thomas Gleixner , Ingo Molnar , Borislav Petkov , Dave Hansen , "H. Peter Anvin" Subject: [PATCH v4 07/12] x86/mtrr: allocate mtrr_value array dynamically Date: Mon, 6 Mar 2023 17:34:20 +0100 Message-Id: <20230306163425.8324-8-jgross@suse.com> X-Mailer: git-send-email 2.35.3 In-Reply-To: <20230306163425.8324-1-jgross@suse.com> References: <20230306163425.8324-1-jgross@suse.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" The mtrr_value[] array is a static variable, which is used only in a few configurations. Consuming 6kB is ridiculous for this case, especially as the array doesn't need to be that large and it can easily be allocated dynamically. Signed-off-by: Juergen Gross Tested-by: Michael Kelley --- arch/x86/kernel/cpu/mtrr/mtrr.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/arch/x86/kernel/cpu/mtrr/mtrr.c b/arch/x86/kernel/cpu/mtrr/mtr= r.c index 0c83990501f5..50cd2287b6e1 100644 --- a/arch/x86/kernel/cpu/mtrr/mtrr.c +++ b/arch/x86/kernel/cpu/mtrr/mtrr.c @@ -581,7 +581,7 @@ struct mtrr_value { unsigned long lsize; }; =20 -static struct mtrr_value mtrr_value[MTRR_MAX_VAR_RANGES]; +static struct mtrr_value *mtrr_value; =20 static int mtrr_save(void) { @@ -750,6 +750,7 @@ static int __init mtrr_init_finialize(void) * TBD: is there any system with such CPU which supports * suspend/resume? If no, we should remove the code. */ + mtrr_value =3D kcalloc(num_var_ranges, sizeof(*mtrr_value), GFP_KERNEL); register_syscore_ops(&mtrr_syscore_ops); =20 return 0; --=20 2.35.3 From nobody Sat Apr 11 11:54:53 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 833EDC6FD1B for ; Mon, 6 Mar 2023 16:39:51 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229870AbjCFQjW (ORCPT ); Mon, 6 Mar 2023 11:39:22 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:49542 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230332AbjCFQik (ORCPT ); Mon, 6 Mar 2023 11:38:40 -0500 Received: from smtp-out1.suse.de (smtp-out1.suse.de [IPv6:2001:67c:2178:6::1c]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 14F3839B84 for ; Mon, 6 Mar 2023 08:37:02 -0800 (PST) Received: from imap2.suse-dmz.suse.de (imap2.suse-dmz.suse.de [192.168.254.74]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (P-521) server-digest SHA512) (No client certificate requested) by smtp-out1.suse.de (Postfix) with ESMTPS id 1E29B21E64; Mon, 6 Mar 2023 16:35:13 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=suse.com; s=susede1; t=1678120513; h=from:from:reply-to:date:date:message-id:message-id:to:to:cc:cc: mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=+DUOEsA+UNBr/vO361m2bPY9yhOH/7VFzmsusEs0LhE=; b=Pnly3Qe54P15pQsm2Gv3mdlsTA+CmSfI+mxgNBvgPwAwFC9OyyDO0YvJw1Bra3RgzqdXUA /eSZnKUVSwejcla2/oigzvVqA++wpOjmGXu/x/TmRkNEXjdSrnqDeiBg9c+2GaTbHDmmb5 9+SwcLb+0Cj2CbdamNUnmZ+UyrxTBjU= Received: from imap2.suse-dmz.suse.de (imap2.suse-dmz.suse.de [192.168.254.74]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (P-521) server-digest SHA512) (No client certificate requested) by imap2.suse-dmz.suse.de (Postfix) with ESMTPS id D4FC713A66; Mon, 6 Mar 2023 16:35:12 +0000 (UTC) Received: from dovecot-director2.suse.de ([192.168.254.65]) by imap2.suse-dmz.suse.de with ESMTPSA id RcSdMkAWBmSLUwAAMHmgww (envelope-from ); Mon, 06 Mar 2023 16:35:12 +0000 From: Juergen Gross To: linux-kernel@vger.kernel.org, x86@kernel.org Cc: Juergen Gross , Thomas Gleixner , Ingo Molnar , Borislav Petkov , Dave Hansen , "H. Peter Anvin" Subject: [PATCH v4 08/12] x86/mtrr: add get_effective_type() service function Date: Mon, 6 Mar 2023 17:34:21 +0100 Message-Id: <20230306163425.8324-9-jgross@suse.com> X-Mailer: git-send-email 2.35.3 In-Reply-To: <20230306163425.8324-1-jgross@suse.com> References: <20230306163425.8324-1-jgross@suse.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add a service function for obtaining the effective cache mode of overlapping MTRR registers. Make use of that function in check_type_overlap(). Signed-off-by: Juergen Gross Tested-by: Michael Kelley --- V3: - new patch --- arch/x86/kernel/cpu/mtrr/generic.c | 39 +++++++++++++++--------------- 1 file changed, 19 insertions(+), 20 deletions(-) diff --git a/arch/x86/kernel/cpu/mtrr/generic.c b/arch/x86/kernel/cpu/mtrr/= generic.c index e25a44c2c950..d271e0c73775 100644 --- a/arch/x86/kernel/cpu/mtrr/generic.c +++ b/arch/x86/kernel/cpu/mtrr/generic.c @@ -78,31 +78,30 @@ static u64 get_mtrr_size(u64 mask) return size; } =20 +static u8 get_effective_type(u8 type1, u8 type2) +{ + if (type1 =3D=3D MTRR_TYPE_UNCACHABLE || type2 =3D=3D MTRR_TYPE_UNCACHABL= E) + return MTRR_TYPE_UNCACHABLE; + + if ((type1 =3D=3D MTRR_TYPE_WRBACK && type2 =3D=3D MTRR_TYPE_WRTHROUGH) || + (type1 =3D=3D MTRR_TYPE_WRTHROUGH && type2 =3D=3D MTRR_TYPE_WRBACK)) + return MTRR_TYPE_WRTHROUGH; + + if (type1 !=3D type2) + return MTRR_TYPE_UNCACHABLE; + + return type1; +} + /* * Check and return the effective type for MTRR-MTRR type overlap. - * Returns 1 if the effective type is UNCACHEABLE, else returns 0 + * Returns true if the effective type is UNCACHEABLE, else returns false */ -static int check_type_overlap(u8 *prev, u8 *curr) +static bool check_type_overlap(u8 *prev, u8 *curr) { - if (*prev =3D=3D MTRR_TYPE_UNCACHABLE || *curr =3D=3D MTRR_TYPE_UNCACHABL= E) { - *prev =3D MTRR_TYPE_UNCACHABLE; - *curr =3D MTRR_TYPE_UNCACHABLE; - return 1; - } - - if ((*prev =3D=3D MTRR_TYPE_WRBACK && *curr =3D=3D MTRR_TYPE_WRTHROUGH) || - (*prev =3D=3D MTRR_TYPE_WRTHROUGH && *curr =3D=3D MTRR_TYPE_WRBACK)) { - *prev =3D MTRR_TYPE_WRTHROUGH; - *curr =3D MTRR_TYPE_WRTHROUGH; - } + *prev =3D *curr =3D get_effective_type(*curr, *prev); =20 - if (*prev !=3D *curr) { - *prev =3D MTRR_TYPE_UNCACHABLE; - *curr =3D MTRR_TYPE_UNCACHABLE; - return 1; - } - - return 0; + return *prev =3D=3D MTRR_TYPE_UNCACHABLE; } =20 /** --=20 2.35.3 From nobody Sat Apr 11 11:54:53 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 71BB8C64EC4 for ; Mon, 6 Mar 2023 16:43:00 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229621AbjCFQm6 (ORCPT ); Mon, 6 Mar 2023 11:42:58 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:59388 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230128AbjCFQmp (ORCPT ); Mon, 6 Mar 2023 11:42:45 -0500 Received: from smtp-out2.suse.de (smtp-out2.suse.de [IPv6:2001:67c:2178:6::1d]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 935314DBF4 for ; Mon, 6 Mar 2023 08:42:12 -0800 (PST) Received: from imap2.suse-dmz.suse.de (imap2.suse-dmz.suse.de [192.168.254.74]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (P-521) server-digest SHA512) (No client certificate requested) by smtp-out2.suse.de (Postfix) with ESMTPS id C16561FDE7; Mon, 6 Mar 2023 16:35:18 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=suse.com; s=susede1; t=1678120518; h=from:from:reply-to:date:date:message-id:message-id:to:to:cc:cc: mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=bw0w1eBhUpbFZKSgzj5kXYLWi6kQdU238jtWFg3CObg=; b=XibzcWpX1B89uabdMHwYGnLtuKsnFTD+BhbQurP8ulwE8n7GGjO/Sc6U2roCSHkKND2ds1 bTLKdLV2aKW5sUq0OIPBz9M2T+KGb8bswiL0H582D3SH0CbtI7WqESWwTXiazXv1vc+BKH pSWd+jNL+WJ141aIDGtJGiQuK9/veUU= Received: from imap2.suse-dmz.suse.de (imap2.suse-dmz.suse.de [192.168.254.74]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (P-521) server-digest SHA512) (No client certificate requested) by imap2.suse-dmz.suse.de (Postfix) with ESMTPS id 8152A13A66; Mon, 6 Mar 2023 16:35:18 +0000 (UTC) Received: from dovecot-director2.suse.de ([192.168.254.65]) by imap2.suse-dmz.suse.de with ESMTPSA id wGYsHkYWBmSZUwAAMHmgww (envelope-from ); Mon, 06 Mar 2023 16:35:18 +0000 From: Juergen Gross To: linux-kernel@vger.kernel.org, x86@kernel.org Cc: Juergen Gross , Thomas Gleixner , Ingo Molnar , Borislav Petkov , Dave Hansen , "H. Peter Anvin" Subject: [PATCH v4 09/12] x86/mtrr: construct a memory map with cache modes Date: Mon, 6 Mar 2023 17:34:22 +0100 Message-Id: <20230306163425.8324-10-jgross@suse.com> X-Mailer: git-send-email 2.35.3 In-Reply-To: <20230306163425.8324-1-jgross@suse.com> References: <20230306163425.8324-1-jgross@suse.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" After MTRR initialization construct a memory map with cache modes from MTRR values. This will speed up lookups via mtrr_lookup_type() especially in case of overlapping MTRRs. This will be needed when switching the semantics of the "uniform" parameter of mtrr_lookup_type() from "only covered by one MTRR" to "memory range has a uniform cache mode", which is the data the callers really want to know. Today this information is not easily available, in case MTRRs are not well sorted regarding base address. The map will be built in __initdata. When memory management is up, the map will be moved to dynamically allocated memory, in order to avoid the need of an overly large array. The size of this array is calculated using the number of variable MTRR registers and the needed size for fixed entries. Only add the map creation and expansion for now. The lookup will be added later. When writing new MTRR entries in the running system rebuild the map inside the call from mtrr_rendezvous_handler() in order to avoid nasty race conditions with concurrent lookups. Signed-off-by: Juergen Gross Tested-by: Michael Kelley --- V3: - new patch --- arch/x86/kernel/cpu/mtrr/generic.c | 254 +++++++++++++++++++++++++++++ arch/x86/kernel/cpu/mtrr/mtrr.c | 6 +- arch/x86/kernel/cpu/mtrr/mtrr.h | 3 + 3 files changed, 262 insertions(+), 1 deletion(-) diff --git a/arch/x86/kernel/cpu/mtrr/generic.c b/arch/x86/kernel/cpu/mtrr/= generic.c index d271e0c73775..13bc637a50e9 100644 --- a/arch/x86/kernel/cpu/mtrr/generic.c +++ b/arch/x86/kernel/cpu/mtrr/generic.c @@ -33,6 +33,37 @@ static struct fixed_range_block fixed_range_blocks[] =3D= { {} }; =20 +struct cache_map { + u64 start; + u64 end; + u8 type; + bool fixed; +}; + +/* + * CACHE_MAP_MAX is the maximum number of memory ranges in cache_map, where + * no 2 adjacent ranges have the same cache mode (those would be merged). + * The number is based on the worst case: + * - no two adjacent fixed MTRRs share the same cache mode + * - one variable MTRR is spanning a huge area with mode WB + * - 255 variable MTRRs with mode UC all overlap with the WB MTRR, creatin= g 2 + * additional ranges each (result like "ababababa...aba" with a =3D WB, = b =3D UC), + * accounting for MTRR_MAX_VAR_RANGES * 2 - 1 range entries + * - a TOM2 area (even with overlapping an UC MTRR can't add 2 range entri= es + * to the possible maximum, as it always starts at 4GB, thus it can't be= in + * the middle of that MTRR, unless that MTRR starts at 0, which would re= move + * the initial "a" from the "abababa" pattern above) + * The map won't contain ranges with no matching MTRR (those fall back to = the + * default cache mode). + */ +#define CACHE_MAP_MAX (MTRR_NUM_FIXED_RANGES + MTRR_MAX_VAR_RANGES * 2) + +static struct cache_map init_cache_map[CACHE_MAP_MAX] __initdata; +static struct cache_map *cache_map __refdata =3D init_cache_map; +static unsigned int cache_map_size =3D CACHE_MAP_MAX; +static unsigned int cache_map_n; +static unsigned int cache_map_fixed; + static unsigned long smp_changes_mask; static int mtrr_state_set; u64 mtrr_tom2; @@ -78,6 +109,20 @@ static u64 get_mtrr_size(u64 mask) return size; } =20 +static u8 get_var_mtrr_state(unsigned int reg, u64 *start, u64 *size) +{ + struct mtrr_var_range *mtrr =3D mtrr_state.var_ranges + reg; + + if (!(mtrr->mask_lo & (1 << 11))) + return MTRR_TYPE_INVALID; + + *start =3D (((u64)mtrr->base_hi) << 32) + (mtrr->base_lo & PAGE_MASK); + *size =3D get_mtrr_size((((u64)mtrr->mask_hi) << 32) + + (mtrr->mask_lo & PAGE_MASK)); + + return mtrr->base_lo & 0xff; +} + static u8 get_effective_type(u8 type1, u8 type2) { if (type1 =3D=3D MTRR_TYPE_UNCACHABLE || type2 =3D=3D MTRR_TYPE_UNCACHABL= E) @@ -241,6 +286,211 @@ static u8 mtrr_type_lookup_variable(u64 start, u64 en= d, u64 *partial_end, return mtrr_state.def_type; } =20 +static void rm_map_entry_at(int idx) +{ + int i; + + for (i =3D idx; i < cache_map_n - 1; i++) + cache_map[i] =3D cache_map[i + 1]; + + cache_map_n--; +} + +/* + * Add an entry into cache_map at a specific index. + * Merges adjacent entries if appropriate. + * Return the number of merges for correcting the scan index. + */ +static int add_map_entry_at(u64 start, u64 end, u8 type, int idx) +{ + bool merge_prev, merge_next; + int i; + + if (start >=3D end) + return 0; + + merge_prev =3D (idx > 0 && !cache_map[idx - 1].fixed && + start =3D=3D cache_map[idx - 1].end && + type =3D=3D cache_map[idx - 1].type); + merge_next =3D (idx < cache_map_n && !cache_map[idx].fixed && + end =3D=3D cache_map[idx].start && + type =3D=3D cache_map[idx].type); + + if (merge_prev && merge_next) { + cache_map[idx - 1].end =3D cache_map[idx].end; + rm_map_entry_at(idx); + return 2; + } + if (merge_prev) { + cache_map[idx - 1].end =3D end; + return 1; + } + if (merge_next) { + cache_map[idx].start =3D start; + return 1; + } + + /* Sanity check: the array should NEVER be too small! */ + if (cache_map_n =3D=3D cache_map_size) { + WARN(1, "MTRR cache mode memory map exhausted!\n"); + cache_map_n =3D cache_map_fixed; + return 0; + } + + for (i =3D cache_map_n; i > idx; i--) + cache_map[i] =3D cache_map[i - 1]; + + cache_map[idx].start =3D start; + cache_map[idx].end =3D end; + cache_map[idx].type =3D type; + cache_map[idx].fixed =3D false; + cache_map_n++; + + return 0; +} + +/* Clear a part of an entry. Return 1 if start of entry is still valid. */ +static int clr_map_range_at(u64 start, u64 end, int idx) +{ + int ret =3D start !=3D cache_map[idx].start; + u64 tmp; + + if (start =3D=3D cache_map[idx].start && end =3D=3D cache_map[idx].end) { + rm_map_entry_at(idx); + } else if (start =3D=3D cache_map[idx].start) { + cache_map[idx].start =3D end; + } else if (end =3D=3D cache_map[idx].end) { + cache_map[idx].end =3D start; + } else { + tmp =3D cache_map[idx].end; + cache_map[idx].end =3D start; + add_map_entry_at(end, tmp, cache_map[idx].type, idx + 1); + } + + return ret; +} + +static void add_map_entry(u64 start, u64 end, u8 type) +{ + int i; + u8 new_type, old_type; + u64 tmp; + + for (i =3D 0; i < cache_map_n && start < end; i++) { + if (start >=3D cache_map[i].end) + continue; + + if (start < cache_map[i].start) { + /* Region start has no overlap. */ + tmp =3D min(end, cache_map[i].start); + i -=3D add_map_entry_at(start, tmp, type, i); + start =3D tmp; + continue; + } + + new_type =3D get_effective_type(type, cache_map[i].type); + old_type =3D cache_map[i].type; + + if (cache_map[i].fixed || new_type =3D=3D old_type) { + /* Cut off start of new entry. */ + start =3D cache_map[i].end; + continue; + } + + tmp =3D min(end, cache_map[i].end); + i +=3D clr_map_range_at(start, tmp, i); + i -=3D add_map_entry_at(start, tmp, new_type, i); + start =3D tmp; + } + + add_map_entry_at(start, end, type, i); +} + +/* Add variable MTRRs to cache map. */ +static void map_add_var(void) +{ + unsigned int i; + u64 start, size; + u8 type; + + /* Add AMD magic MTRR. */ + if (mtrr_tom2) { + add_map_entry(1ULL << 32, mtrr_tom2 - 1, MTRR_TYPE_WRBACK); + cache_map[cache_map_n - 1].fixed =3D true; + } + + for (i =3D 0; i < num_var_ranges; i++) { + type =3D get_var_mtrr_state(i, &start, &size); + if (type !=3D MTRR_TYPE_INVALID) + add_map_entry(start, start + size, type); + } +} + +/* Rebuild map by replacing variable entries. */ +static void rebuild_map(void) +{ + cache_map_n =3D cache_map_fixed; + + map_add_var(); +} + +/* Build the cache_map containing the cache modes per memory range. */ +void mtrr_build_map(void) +{ + unsigned int i; + u64 start, end, size; + u8 type; + + if (!mtrr_state.enabled) + return; + + /* Add fixed MTRRs, optimize for adjacent entries with same type. */ + if (mtrr_state.enabled & MTRR_STATE_MTRR_FIXED_ENABLED) { + start =3D 0; + end =3D size =3D 0x10000; + type =3D mtrr_state.fixed_ranges[0]; + + for (i =3D 1; i < MTRR_NUM_FIXED_RANGES; i++) { + if (i =3D=3D 8 || i =3D=3D 24) + size >>=3D 2; + + if (mtrr_state.fixed_ranges[i] !=3D type) { + add_map_entry(start, end, type); + start =3D end; + type =3D mtrr_state.fixed_ranges[i]; + } + end +=3D size; + } + add_map_entry(start, end, type); + } + + /* Mark fixed and magic MTRR as fixed, they take precedence. */ + for (i =3D 0; i < cache_map_n; i++) + cache_map[i].fixed =3D true; + cache_map_fixed =3D cache_map_n; + + map_add_var(); +} + +/* Copy the cache_map from __initdata memory to dynamically allocated one.= */ +void __init mtrr_copy_map(void) +{ + unsigned int new_size =3D cache_map_fixed + 2 * num_var_ranges; + + if (!mtrr_state.enabled || !new_size) { + cache_map =3D NULL; + return; + } + + mutex_lock(&mtrr_mutex); + + cache_map =3D kcalloc(new_size, sizeof(*cache_map), GFP_KERNEL); + memmove(cache_map, init_cache_map, cache_map_n * sizeof(*cache_map)); + cache_map_size =3D new_size; + + mutex_unlock(&mtrr_mutex); +} + /** * mtrr_overwrite_state - set static MTRR state * @@ -815,6 +1065,10 @@ static void generic_set_mtrr(unsigned int reg, unsign= ed long base, =20 cache_enable(); local_irq_restore(flags); + + /* On the first cpu rebuild the cache mode memory map. */ + if (smp_processor_id() =3D=3D cpumask_first(cpu_online_mask)) + rebuild_map(); } =20 int generic_validate_add_page(unsigned long base, unsigned long size, diff --git a/arch/x86/kernel/cpu/mtrr/mtrr.c b/arch/x86/kernel/cpu/mtrr/mtr= r.c index 50cd2287b6e1..1dbb9fdfd87b 100644 --- a/arch/x86/kernel/cpu/mtrr/mtrr.c +++ b/arch/x86/kernel/cpu/mtrr/mtrr.c @@ -65,7 +65,7 @@ static bool mtrr_enabled(void) } =20 unsigned int mtrr_usage_table[MTRR_MAX_VAR_RANGES]; -static DEFINE_MUTEX(mtrr_mutex); +DEFINE_MUTEX(mtrr_mutex); =20 u64 size_or_mask, size_and_mask; =20 @@ -668,6 +668,7 @@ void __init mtrr_bp_init(void) /* Software overwrite of MTRR state, only for generic case. */ mtrr_calc_physbits(true); init_table(); + mtrr_build_map(); pr_info("MTRRs set to read-only\n"); =20 return; @@ -705,6 +706,7 @@ void __init mtrr_bp_init(void) if (get_mtrr_state()) { memory_caching_control |=3D CACHE_MTRR; changed_by_mtrr_cleanup =3D mtrr_cleanup(phys_addr); + mtrr_build_map(); } else { mtrr_if =3D NULL; why =3D "by BIOS"; @@ -733,6 +735,8 @@ void mtrr_save_state(void) =20 static int __init mtrr_init_finialize(void) { + mtrr_copy_map(); + if (!mtrr_enabled()) return 0; =20 diff --git a/arch/x86/kernel/cpu/mtrr/mtrr.h b/arch/x86/kernel/cpu/mtrr/mtr= r.h index a3c362d3d5bf..6246a1d8650b 100644 --- a/arch/x86/kernel/cpu/mtrr/mtrr.h +++ b/arch/x86/kernel/cpu/mtrr/mtrr.h @@ -53,6 +53,7 @@ bool get_mtrr_state(void); =20 extern u64 size_or_mask, size_and_mask; extern const struct mtrr_ops *mtrr_if; +extern struct mutex mtrr_mutex; =20 extern unsigned int num_var_ranges; extern u64 mtrr_tom2; @@ -61,6 +62,8 @@ extern struct mtrr_state_type mtrr_state; void mtrr_state_warn(void); const char *mtrr_attrib_to_str(int x); void mtrr_wrmsr(unsigned, unsigned, unsigned); +void mtrr_build_map(void); +void mtrr_copy_map(void); =20 /* CPU specific mtrr_ops vectors. */ extern const struct mtrr_ops amd_mtrr_ops; --=20 2.35.3 From nobody Sat Apr 11 11:54:53 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id BE0BAC64EC4 for ; Mon, 6 Mar 2023 16:38:14 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229716AbjCFQho (ORCPT ); Mon, 6 Mar 2023 11:37:44 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:49204 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229640AbjCFQg4 (ORCPT ); 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Mon, 6 Mar 2023 16:35:24 +0000 (UTC) Received: from dovecot-director2.suse.de ([192.168.254.65]) by imap2.suse-dmz.suse.de with ESMTPSA id TV68DUwWBmSqUwAAMHmgww (envelope-from ); Mon, 06 Mar 2023 16:35:24 +0000 From: Juergen Gross To: linux-kernel@vger.kernel.org, x86@kernel.org Cc: Juergen Gross , Thomas Gleixner , Ingo Molnar , Borislav Petkov , Dave Hansen , "H. Peter Anvin" Subject: [PATCH v4 10/12] x86/mtrr: use new cache_map in mtrr_type_lookup() Date: Mon, 6 Mar 2023 17:34:23 +0100 Message-Id: <20230306163425.8324-11-jgross@suse.com> X-Mailer: git-send-email 2.35.3 In-Reply-To: <20230306163425.8324-1-jgross@suse.com> References: <20230306163425.8324-1-jgross@suse.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Instead of crawling through the MTRR register state, use the new cache_map for looking up the cache type(s) of a memory region. This allows now to set the uniform parameter according to the uniformity of the cache mode of the region, instead of setting it only if the complete region is mapped by a single MTRR. This now includes even the region covered by the fixed MTRR registers. Make sure uniform is always set. Signed-off-by: Juergen Gross Tested-by: Michael Kelley --- V3: - new patch V3.1: - fix type_merge() (Michael Kelley) V4: - fix type_merge() again (Michael Kelley) --- arch/x86/kernel/cpu/mtrr/generic.c | 227 ++++------------------------- 1 file changed, 32 insertions(+), 195 deletions(-) diff --git a/arch/x86/kernel/cpu/mtrr/generic.c b/arch/x86/kernel/cpu/mtrr/= generic.c index 13bc637a50e9..de6d74d6e3a0 100644 --- a/arch/x86/kernel/cpu/mtrr/generic.c +++ b/arch/x86/kernel/cpu/mtrr/generic.c @@ -138,154 +138,6 @@ static u8 get_effective_type(u8 type1, u8 type2) return type1; } =20 -/* - * Check and return the effective type for MTRR-MTRR type overlap. - * Returns true if the effective type is UNCACHEABLE, else returns false - */ -static bool check_type_overlap(u8 *prev, u8 *curr) -{ - *prev =3D *curr =3D get_effective_type(*curr, *prev); - - return *prev =3D=3D MTRR_TYPE_UNCACHABLE; -} - -/** - * mtrr_type_lookup_fixed - look up memory type in MTRR fixed entries - * - * Return the MTRR fixed memory type of 'start'. - * - * MTRR fixed entries are divided into the following ways: - * 0x00000 - 0x7FFFF : This range is divided into eight 64KB sub-ranges - * 0x80000 - 0xBFFFF : This range is divided into sixteen 16KB sub-ranges - * 0xC0000 - 0xFFFFF : This range is divided into sixty-four 4KB sub-rang= es - * - * Return Values: - * MTRR_TYPE_(type) - Matched memory type - * MTRR_TYPE_INVALID - Unmatched - */ -static u8 mtrr_type_lookup_fixed(u64 start, u64 end) -{ - int idx; - - if (start >=3D 0x100000) - return MTRR_TYPE_INVALID; - - /* 0x0 - 0x7FFFF */ - if (start < 0x80000) { - idx =3D 0; - idx +=3D (start >> 16); - return mtrr_state.fixed_ranges[idx]; - /* 0x80000 - 0xBFFFF */ - } else if (start < 0xC0000) { - idx =3D 1 * 8; - idx +=3D ((start - 0x80000) >> 14); - return mtrr_state.fixed_ranges[idx]; - } - - /* 0xC0000 - 0xFFFFF */ - idx =3D 3 * 8; - idx +=3D ((start - 0xC0000) >> 12); - return mtrr_state.fixed_ranges[idx]; -} - -/** - * mtrr_type_lookup_variable - look up memory type in MTRR variable entries - * - * Return Value: - * MTRR_TYPE_(type) - Matched memory type or default memory type (unmatche= d) - * - * Output Arguments: - * repeat - Set to 1 when [start:end] spanned across MTRR range and type - * returned corresponds only to [start:*partial_end]. Caller has - * to lookup again for [*partial_end:end]. - * - * uniform - Set to 1 when an MTRR covers the region uniformly, i.e. the - * region is fully covered by a single MTRR entry or the default - * type. - */ -static u8 mtrr_type_lookup_variable(u64 start, u64 end, u64 *partial_end, - int *repeat, u8 *uniform) -{ - int i; - u64 base, mask; - u8 prev_match, curr_match; - - *repeat =3D 0; - *uniform =3D 1; - - prev_match =3D MTRR_TYPE_INVALID; - for (i =3D 0; i < num_var_ranges; ++i) { - unsigned short start_state, end_state, inclusive; - - if (!(mtrr_state.var_ranges[i].mask_lo & (1 << 11))) - continue; - - base =3D (((u64)mtrr_state.var_ranges[i].base_hi) << 32) + - (mtrr_state.var_ranges[i].base_lo & PAGE_MASK); - mask =3D (((u64)mtrr_state.var_ranges[i].mask_hi) << 32) + - (mtrr_state.var_ranges[i].mask_lo & PAGE_MASK); - - start_state =3D ((start & mask) =3D=3D (base & mask)); - end_state =3D ((end & mask) =3D=3D (base & mask)); - inclusive =3D ((start < base) && (end > base)); - - if ((start_state !=3D end_state) || inclusive) { - /* - * We have start:end spanning across an MTRR. - * We split the region into either - * - * - start_state:1 - * (start:mtrr_end)(mtrr_end:end) - * - end_state:1 - * (start:mtrr_start)(mtrr_start:end) - * - inclusive:1 - * (start:mtrr_start)(mtrr_start:mtrr_end)(mtrr_end:end) - * - * depending on kind of overlap. - * - * Return the type of the first region and a pointer - * to the start of next region so that caller will be - * advised to lookup again after having adjusted start - * and end. - * - * Note: This way we handle overlaps with multiple - * entries and the default type properly. - */ - if (start_state) - *partial_end =3D base + get_mtrr_size(mask); - else - *partial_end =3D base; - - if (unlikely(*partial_end <=3D start)) { - WARN_ON(1); - *partial_end =3D start + PAGE_SIZE; - } - - end =3D *partial_end - 1; /* end is inclusive */ - *repeat =3D 1; - *uniform =3D 0; - } - - if ((start & mask) !=3D (base & mask)) - continue; - - curr_match =3D mtrr_state.var_ranges[i].base_lo & 0xff; - if (prev_match =3D=3D MTRR_TYPE_INVALID) { - prev_match =3D curr_match; - continue; - } - - *uniform =3D 0; - if (check_type_overlap(&prev_match, &curr_match)) - return curr_match; - } - - if (prev_match !=3D MTRR_TYPE_INVALID) - return prev_match; - - return mtrr_state.def_type; -} - static void rm_map_entry_at(int idx) { int i; @@ -533,6 +385,20 @@ void mtrr_overwrite_state(struct mtrr_var_range *var, = unsigned int num_var, mtrr_state_set =3D 1; } =20 +static u8 type_merge(u8 type, u8 new_type, u8 *uniform) +{ + u8 effective_type; + + if (type =3D=3D MTRR_TYPE_INVALID) + return new_type; + + effective_type =3D get_effective_type(type, new_type); + if (type !=3D effective_type) + *uniform =3D 0; + + return effective_type; +} + /** * mtrr_type_lookup - look up memory type in MTRR * @@ -541,66 +407,37 @@ void mtrr_overwrite_state(struct mtrr_var_range *var,= unsigned int num_var, * MTRR_TYPE_INVALID - MTRR is disabled * * Output Argument: - * uniform - Set to 1 when an MTRR covers the region uniformly, i.e. the - * region is fully covered by a single MTRR entry or the default - * type. + * uniform - Set to 1 when the returned MTRR type is valid for the whole + * region, set to 0 else. */ u8 mtrr_type_lookup(u64 start, u64 end, u8 *uniform) { - u8 type, prev_type, is_uniform =3D 1, dummy; - int repeat; - u64 partial_end; - - /* Make end inclusive instead of exclusive */ - end--; + u8 type =3D MTRR_TYPE_INVALID; + unsigned int i; =20 - if (!mtrr_state_set) + if (!mtrr_state_set) { + *uniform =3D 0; /* Uniformity is unknown. */ return MTRR_TYPE_INVALID; + } + + *uniform =3D 1; =20 if (!(mtrr_state.enabled & MTRR_STATE_MTRR_ENABLED)) return MTRR_TYPE_INVALID; =20 - /* - * Look up the fixed ranges first, which take priority over - * the variable ranges. - */ - if ((start < 0x100000) && - (mtrr_state.have_fixed) && - (mtrr_state.enabled & MTRR_STATE_MTRR_FIXED_ENABLED)) { - is_uniform =3D 0; - type =3D mtrr_type_lookup_fixed(start, end); - goto out; - } - - /* - * Look up the variable ranges. Look of multiple ranges matching - * this address and pick type as per MTRR precedence. - */ - type =3D mtrr_type_lookup_variable(start, end, &partial_end, - &repeat, &is_uniform); + for (i =3D 0; i < cache_map_n && start < end; i++) { + if (start >=3D cache_map[i].end) + continue; + if (start < cache_map[i].start) + type =3D type_merge(type, mtrr_state.def_type, uniform); + type =3D type_merge(type, cache_map[i].type, uniform); =20 - /* - * Common path is with repeat =3D 0. - * However, we can have cases where [start:end] spans across some - * MTRR ranges and/or the default type. Do repeated lookups for - * that case here. - */ - while (repeat) { - prev_type =3D type; - start =3D partial_end; - is_uniform =3D 0; - type =3D mtrr_type_lookup_variable(start, end, &partial_end, - &repeat, &dummy); - - if (check_type_overlap(&prev_type, &type)) - goto out; + start =3D cache_map[i].end; } =20 - if (mtrr_tom2 && (start >=3D (1ULL<<32)) && (end < mtrr_tom2)) - type =3D MTRR_TYPE_WRBACK; + if (start < end) + type =3D type_merge(type, mtrr_state.def_type, uniform); =20 -out: - *uniform =3D is_uniform; return type; } =20 --=20 2.35.3 From nobody Sat Apr 11 11:54:53 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 97268C678D4 for ; Mon, 6 Mar 2023 16:37:42 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230251AbjCFQhU (ORCPT ); Mon, 6 Mar 2023 11:37:20 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:49180 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229794AbjCFQg3 (ORCPT ); Mon, 6 Mar 2023 11:36:29 -0500 Received: from smtp-out2.suse.de (smtp-out2.suse.de [IPv6:2001:67c:2178:6::1d]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id B6AC03C17 for ; Mon, 6 Mar 2023 08:36:00 -0800 (PST) Received: from imap2.suse-dmz.suse.de (imap2.suse-dmz.suse.de [192.168.254.74]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (P-521) server-digest SHA512) (No client certificate requested) by smtp-out2.suse.de (Postfix) with ESMTPS id 301321FDEC; Mon, 6 Mar 2023 16:35:30 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=suse.com; s=susede1; t=1678120530; h=from:from:reply-to:date:date:message-id:message-id:to:to:cc:cc: mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=5wTDwZv06EmUbfQ1jDWIuEcre1E3183cNpPdoj5eT8U=; b=VAmf1J7BrJMNASYAzGdYE3xlWvYmcISrJbv3oJgYGvqbgLPfCDHFE+ZVdv2q5+kTN2HgDF 0tdvJ4bpn3Hg618ZiJDgubq5lopaHA6vh8KSQzTIeuJLqXv+/lGpOHU0E/n556tuAR8jvV RWy/qWkiQJXZnQ/1Qqu4sc4KH5Byhsk= Received: from imap2.suse-dmz.suse.de (imap2.suse-dmz.suse.de [192.168.254.74]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (P-521) server-digest SHA512) (No client certificate requested) by imap2.suse-dmz.suse.de (Postfix) with ESMTPS id DE67613A66; Mon, 6 Mar 2023 16:35:29 +0000 (UTC) Received: from dovecot-director2.suse.de ([192.168.254.65]) by imap2.suse-dmz.suse.de with ESMTPSA id Vaq7NFEWBmSvUwAAMHmgww (envelope-from ); Mon, 06 Mar 2023 16:35:29 +0000 From: Juergen Gross To: linux-kernel@vger.kernel.org, x86@kernel.org Cc: Juergen Gross , Thomas Gleixner , Ingo Molnar , Borislav Petkov , Dave Hansen , "H. Peter Anvin" , Linus Torvalds Subject: [PATCH v4 11/12] x86/mtrr: don't let mtrr_type_lookup() return MTRR_TYPE_INVALID Date: Mon, 6 Mar 2023 17:34:24 +0100 Message-Id: <20230306163425.8324-12-jgross@suse.com> X-Mailer: git-send-email 2.35.3 In-Reply-To: <20230306163425.8324-1-jgross@suse.com> References: <20230306163425.8324-1-jgross@suse.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" mtrr_type_lookup() should always return a valid memory type. In case there is no information available, it should return the default UC. This will remove the last case where mtrr_type_lookup() can return MTRR_TYPE_INVALID, so adjust the comment in include/uapi/asm/mtrr.h. Note that removing the MTRR_TYPE_INVALID #define from that header could break user code, so it has to stay. At the same time the mtrr_type_lookup() stub for the !CONFIG_MTRR case should set uniform to 1, as if the memory range would be covered by no MTRR at all. Suggested-by: Linus Torvalds Signed-off-by: Juergen Gross Tested-by: Michael Kelley --- V2: - always set uniform - set uniform to 1 in case of disabled MTRRs (Linus Torvalds) V3: - adjust include/uapi/asm/mtrr.h comment --- arch/x86/include/asm/mtrr.h | 7 +++++-- arch/x86/include/uapi/asm/mtrr.h | 6 +++--- arch/x86/kernel/cpu/mtrr/generic.c | 4 ++-- 3 files changed, 10 insertions(+), 7 deletions(-) diff --git a/arch/x86/include/asm/mtrr.h b/arch/x86/include/asm/mtrr.h index f1cb81330a64..0d7ea8a54d81 100644 --- a/arch/x86/include/asm/mtrr.h +++ b/arch/x86/include/asm/mtrr.h @@ -59,9 +59,12 @@ static inline void mtrr_overwrite_state(struct mtrr_var_= range *var, static inline u8 mtrr_type_lookup(u64 addr, u64 end, u8 *uniform) { /* - * Return no-MTRRs: + * Return the default MTRR type, without any known other types in + * that range. */ - return MTRR_TYPE_INVALID; + *uniform =3D 1; + + return MTRR_TYPE_UNCACHABLE; } #define mtrr_save_fixed_ranges(arg) do {} while (0) #define mtrr_save_state() do {} while (0) diff --git a/arch/x86/include/uapi/asm/mtrr.h b/arch/x86/include/uapi/asm/m= trr.h index 376563f2bac1..4aa05c2ffa78 100644 --- a/arch/x86/include/uapi/asm/mtrr.h +++ b/arch/x86/include/uapi/asm/mtrr.h @@ -115,9 +115,9 @@ struct mtrr_state_type { #define MTRR_NUM_TYPES 7 =20 /* - * Invalid MTRR memory type. mtrr_type_lookup() returns this value when - * MTRRs are disabled. Note, this value is allocated from the reserved - * values (0x7-0xff) of the MTRR memory types. + * Invalid MTRR memory type. No longer used outside of MTRR code. + * Note, this value is allocated from the reserved values (0x7-0xff) of + * the MTRR memory types. */ #define MTRR_TYPE_INVALID 0xff =20 diff --git a/arch/x86/kernel/cpu/mtrr/generic.c b/arch/x86/kernel/cpu/mtrr/= generic.c index de6d74d6e3a0..3d48e9d06bfb 100644 --- a/arch/x86/kernel/cpu/mtrr/generic.c +++ b/arch/x86/kernel/cpu/mtrr/generic.c @@ -417,13 +417,13 @@ u8 mtrr_type_lookup(u64 start, u64 end, u8 *uniform) =20 if (!mtrr_state_set) { *uniform =3D 0; /* Uniformity is unknown. */ - return MTRR_TYPE_INVALID; + return MTRR_TYPE_UNCACHABLE; } =20 *uniform =3D 1; =20 if (!(mtrr_state.enabled & MTRR_STATE_MTRR_ENABLED)) - return MTRR_TYPE_INVALID; + return MTRR_TYPE_UNCACHABLE; =20 for (i =3D 0; i < cache_map_n && start < end; i++) { if (start >=3D cache_map[i].end) --=20 2.35.3 From nobody Sat Apr 11 11:54:53 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1DC06C6FA99 for ; Mon, 6 Mar 2023 16:37:43 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229758AbjCFQh3 (ORCPT ); Mon, 6 Mar 2023 11:37:29 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:48374 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230143AbjCFQgi (ORCPT ); Mon, 6 Mar 2023 11:36:38 -0500 Received: from smtp-out1.suse.de (smtp-out1.suse.de [IPv6:2001:67c:2178:6::1c]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 900D338B63 for ; Mon, 6 Mar 2023 08:36:12 -0800 (PST) Received: from imap2.suse-dmz.suse.de (imap2.suse-dmz.suse.de [192.168.254.74]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (P-521) server-digest SHA512) (No client certificate requested) by smtp-out1.suse.de (Postfix) with ESMTPS id E23B821E68; Mon, 6 Mar 2023 16:35:35 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=suse.com; s=susede1; t=1678120535; h=from:from:reply-to:date:date:message-id:message-id:to:to:cc:cc: mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=/LnG+vviZFEmSplserK7lU8lrYy0Xhh7tv0XqJyR/Mo=; b=Pm4dbuFymyP28hC2S3dLLk5s9QEZCS4aQqKi80Fq1IBNB73YMwhWSuGo+/wrxAErADN/cN Kd+hgwoDljLDUWPLLH/Jng0pv8Fb9RyuangVMAuXAj+66tjANMk/zn/Fp/AjDR8u37KI0r +wVBlz4hM0ZY7RoAeJWXjixSGWZkKOo= Received: from imap2.suse-dmz.suse.de (imap2.suse-dmz.suse.de [192.168.254.74]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (P-521) server-digest SHA512) (No client certificate requested) by imap2.suse-dmz.suse.de (Postfix) with ESMTPS id 9544F13A66; Mon, 6 Mar 2023 16:35:35 +0000 (UTC) Received: from dovecot-director2.suse.de ([192.168.254.65]) by imap2.suse-dmz.suse.de with ESMTPSA id 7o0UI1cWBmS/UwAAMHmgww (envelope-from ); Mon, 06 Mar 2023 16:35:35 +0000 From: Juergen Gross To: linux-kernel@vger.kernel.org, x86@kernel.org Cc: Juergen Gross , Dave Hansen , Andy Lutomirski , Peter Zijlstra , Thomas Gleixner , Ingo Molnar , Borislav Petkov , "H. Peter Anvin" , Linus Torvalds Subject: [PATCH v4 12/12] x86/mm: only check uniform after calling mtrr_type_lookup() Date: Mon, 6 Mar 2023 17:34:25 +0100 Message-Id: <20230306163425.8324-13-jgross@suse.com> X-Mailer: git-send-email 2.35.3 In-Reply-To: <20230306163425.8324-1-jgross@suse.com> References: <20230306163425.8324-1-jgross@suse.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Today pud_set_huge() and pmd_set_huge() test for the MTRR type to be WB or INVALID after calling mtrr_type_lookup(). Those tests can be dropped, as the only reason to not use a large mapping would be uniform being 0. Any MTRR type can be accepted as long as it applies to the whole memory range covered by the mapping, as the alternative would only be to map the same region with smaller pages instead, using the same PAT type as for the large mapping. Suggested-by: Linus Torvalds Signed-off-by: Juergen Gross Tested-by: Michael Kelley --- V3: - adapt comment for pud_set_huge() --- arch/x86/mm/pgtable.c | 24 ++++++++---------------- 1 file changed, 8 insertions(+), 16 deletions(-) diff --git a/arch/x86/mm/pgtable.c b/arch/x86/mm/pgtable.c index e4f499eb0f29..15a8009a4480 100644 --- a/arch/x86/mm/pgtable.c +++ b/arch/x86/mm/pgtable.c @@ -702,14 +702,8 @@ void p4d_clear_huge(p4d_t *p4d) * pud_set_huge - setup kernel PUD mapping * * MTRRs can override PAT memory types with 4KiB granularity. Therefore, t= his - * function sets up a huge page only if any of the following conditions ar= e met: - * - * - MTRRs are disabled, or - * - * - MTRRs are enabled and the range is completely covered by a single MTR= R, or - * - * - MTRRs are enabled and the corresponding MTRR memory type is WB, which - * has no effect on the requested PAT memory type. + * function sets up a huge page only if the complete range has the same MT= RR + * caching mode. * * Callers should try to decrease page size (1GB -> 2MB -> 4K) if the bigg= er * page mapping attempt fails. @@ -718,11 +712,10 @@ void p4d_clear_huge(p4d_t *p4d) */ int pud_set_huge(pud_t *pud, phys_addr_t addr, pgprot_t prot) { - u8 mtrr, uniform; + u8 uniform; =20 - mtrr =3D mtrr_type_lookup(addr, addr + PUD_SIZE, &uniform); - if ((mtrr !=3D MTRR_TYPE_INVALID) && (!uniform) && - (mtrr !=3D MTRR_TYPE_WRBACK)) + mtrr_type_lookup(addr, addr + PUD_SIZE, &uniform); + if (!uniform) return 0; =20 /* Bail out if we are we on a populated non-leaf entry: */ @@ -745,11 +738,10 @@ int pud_set_huge(pud_t *pud, phys_addr_t addr, pgprot= _t prot) */ int pmd_set_huge(pmd_t *pmd, phys_addr_t addr, pgprot_t prot) { - u8 mtrr, uniform; + u8 uniform; =20 - mtrr =3D mtrr_type_lookup(addr, addr + PMD_SIZE, &uniform); - if ((mtrr !=3D MTRR_TYPE_INVALID) && (!uniform) && - (mtrr !=3D MTRR_TYPE_WRBACK)) { + mtrr_type_lookup(addr, addr + PMD_SIZE, &uniform); + if (!uniform) { pr_warn_once("%s: Cannot satisfy [mem %#010llx-%#010llx] with a huge-pag= e mapping due to MTRR override.\n", __func__, addr, addr + PMD_SIZE); return 0; --=20 2.35.3