From nobody Sat Apr 11 11:48:14 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id D0D98C6FA99 for ; Mon, 6 Mar 2023 15:33:23 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229891AbjCFPdV (ORCPT ); Mon, 6 Mar 2023 10:33:21 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:59098 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230166AbjCFPdO (ORCPT ); Mon, 6 Mar 2023 10:33:14 -0500 Received: from mail-pl1-x62b.google.com (mail-pl1-x62b.google.com [IPv6:2607:f8b0:4864:20::62b]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 675A031E0F for ; Mon, 6 Mar 2023 07:32:44 -0800 (PST) Received: by mail-pl1-x62b.google.com with SMTP id x11so6237295pln.12 for ; Mon, 06 Mar 2023 07:32:44 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1678116764; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=LgcUg9KBFxgyL7R+Ko0NRVJoBGhkBXsnNvmn89JO8A8=; b=LAE6hdwk6qjIrdlw31IZ5aLM1J/i+3pxZBCsxn8iXV5J2Ck311XWmpurDVEu3l9Nad w8tKkDed/aV3fCzm+k03Q2blxqBXJ220LXxZMrTAkO6DlSHCIQov+NmDWxvBD5UncZIN B0/MUDrfO29eAt/SEfNyOQesOVFDMsoyxy1uB9adAX3TszyK8WQg3Hucz37WLSDqpJ3W jBAuHfTe5+4SdJfGuMY92xLIdAay343AY//SH0iw8dSF3lzF93/VTBksGMEUmtW9srHR 3NJx6pAh3s5SXXkRLqtAiJef3tWjgx5pccuA17dnSOWUF3bC7inncARa1kiGS6GqN+xC PorQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1678116764; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=LgcUg9KBFxgyL7R+Ko0NRVJoBGhkBXsnNvmn89JO8A8=; b=B1qipnfDiaeN5MzBW83bouGAKqmGy80HGOHE49zfVHeEchnek2WQsP4MjCdhMxPOOz 7iiaup7FQo+WQw7xdAhfDEjNXWa6BJkHMh7p8/4m6RWKwpa48jJFqJ/ehrACa/n/ld4y Coe1pdXW7kbR5ka57uXQzJJQYvzZ6oXOZXVK3cpCLRcbEEM2DdRbH+Wp7ooKp0Gb7ZPz ZXXJxt5AP9Q87Dff4QYdYvZImTlSW7Fl7Ve7jOYb3VQG4fC7id2HNXyYiYkkrnGF8Unv rlrp7ri60QwJqXGHIN6WExvsJa1Jo/H2rfDxBgLzCzi0AYPzyWXqLM35mH7zOXIxYQsJ +gvQ== X-Gm-Message-State: AO0yUKUDRbOlurEwQCgH0gNa+wsv3t+MsKPksUnsa6eOcAdpDUqe/l9P Cw8jfkf7O+MOcvIplyfuZIIB X-Google-Smtp-Source: AK7set99ER9AC12rc/lxOF+DwUqqyfAISTapAlB5x+iDddskhYSRhil1E3XPFwOVI0/iWWJPkLGe4w== X-Received: by 2002:a17:902:a5c3:b0:19d:1a99:88 with SMTP id t3-20020a170902a5c300b0019d1a990088mr9947064plq.20.1678116763734; Mon, 06 Mar 2023 07:32:43 -0800 (PST) Received: from localhost.localdomain ([59.97.52.140]) by smtp.gmail.com with ESMTPSA id kl4-20020a170903074400b0019a7c890c61sm6837430plb.252.2023.03.06.07.32.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 06 Mar 2023 07:32:43 -0800 (PST) From: Manivannan Sadhasivam To: andersson@kernel.org, lpieralisi@kernel.org, kw@linux.com, krzysztof.kozlowski+dt@linaro.org, robh@kernel.org Cc: konrad.dybcio@linaro.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, quic_srichara@quicinc.com, Manivannan Sadhasivam Subject: [PATCH 01/19] PCI: qcom: Remove PCIE20_ prefix from register definitions Date: Mon, 6 Mar 2023 21:02:04 +0530 Message-Id: <20230306153222.157667-2-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230306153222.157667-1-manivannan.sadhasivam@linaro.org> References: <20230306153222.157667-1-manivannan.sadhasivam@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" The PCIE part is redundant and 20 doesn't represent anything across the SoCs supported now. So let's get rid of the prefix. This involves adding the IP version suffix to one definition of PARF_SLV_ADDR_SPACE_SIZE that defines offset specific to that version. The other definition is generic for the rest of the versions. Also, the register PCIE20_LNK_CONTROL2_LINK_STATUS2 is not used anywhere, hence removed. Signed-off-by: Manivannan Sadhasivam --- drivers/pci/controller/dwc/pcie-qcom.c | 184 ++++++++++++------------- 1 file changed, 91 insertions(+), 93 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controlle= r/dwc/pcie-qcom.c index a232b04af048..6930bc9ceeb5 100644 --- a/drivers/pci/controller/dwc/pcie-qcom.c +++ b/drivers/pci/controller/dwc/pcie-qcom.c @@ -33,7 +33,7 @@ #include "../../pci.h" #include "pcie-designware.h" =20 -#define PCIE20_PARF_SYS_CTRL 0x00 +#define PARF_SYS_CTRL 0x00 #define MST_WAKEUP_EN BIT(13) #define SLV_WAKEUP_EN BIT(12) #define MSTR_ACLK_CGC_DIS BIT(10) @@ -43,39 +43,39 @@ #define L23_CLK_RMV_DIS BIT(2) #define L1_CLK_RMV_DIS BIT(1) =20 -#define PCIE20_PARF_PM_CTRL 0x20 +#define PARF_PM_CTRL 0x20 #define REQ_NOT_ENTR_L1 BIT(5) =20 -#define PCIE20_PARF_PHY_CTRL 0x40 +#define PARF_PHY_CTRL 0x40 #define PHY_CTRL_PHY_TX0_TERM_OFFSET_MASK GENMASK(20, 16) #define PHY_CTRL_PHY_TX0_TERM_OFFSET(x) ((x) << 16) =20 -#define PCIE20_PARF_PHY_REFCLK 0x4C +#define PARF_PHY_REFCLK 0x4C #define PHY_REFCLK_SSP_EN BIT(16) #define PHY_REFCLK_USE_PAD BIT(12) =20 -#define PCIE20_PARF_DBI_BASE_ADDR 0x168 -#define PCIE20_PARF_SLV_ADDR_SPACE_SIZE 0x16C -#define PCIE20_PARF_MHI_CLOCK_RESET_CTRL 0x174 +#define PARF_DBI_BASE_ADDR 0x168 +#define PARF_SLV_ADDR_SPACE_SIZE_2_3_3 0x16C /* Register offset specific = to IP rev 2.3.3 */ +#define PARF_MHI_CLOCK_RESET_CTRL 0x174 #define AHB_CLK_EN BIT(0) #define MSTR_AXI_CLK_EN BIT(1) #define BYPASS BIT(4) =20 -#define PCIE20_PARF_AXI_MSTR_WR_ADDR_HALT 0x178 -#define PCIE20_PARF_AXI_MSTR_WR_ADDR_HALT_V2 0x1A8 -#define PCIE20_PARF_LTSSM 0x1B0 -#define PCIE20_PARF_SID_OFFSET 0x234 -#define PCIE20_PARF_BDF_TRANSLATE_CFG 0x24C -#define PCIE20_PARF_DEVICE_TYPE 0x1000 -#define PCIE20_PARF_BDF_TO_SID_TABLE_N 0x2000 +#define PARF_AXI_MSTR_WR_ADDR_HALT 0x178 +#define PARF_AXI_MSTR_WR_ADDR_HALT_V2 0x1A8 +#define PARF_LTSSM 0x1B0 +#define PARF_SID_OFFSET 0x234 +#define PARF_BDF_TRANSLATE_CFG 0x24C +#define PARF_DEVICE_TYPE 0x1000 +#define PARF_BDF_TO_SID_TABLE_N 0x2000 =20 -#define PCIE20_ELBI_SYS_CTRL 0x04 -#define PCIE20_ELBI_SYS_CTRL_LT_ENABLE BIT(0) +#define ELBI_SYS_CTRL 0x04 +#define ELBI_SYS_CTRL_LT_ENABLE BIT(0) =20 -#define PCIE20_AXI_MSTR_RESP_COMP_CTRL0 0x818 +#define AXI_MSTR_RESP_COMP_CTRL0 0x818 #define CFG_REMOTE_RD_REQ_BRIDGE_SIZE_2K 0x4 #define CFG_REMOTE_RD_REQ_BRIDGE_SIZE_4K 0x5 -#define PCIE20_AXI_MSTR_RESP_COMP_CTRL1 0x81c +#define AXI_MSTR_RESP_COMP_CTRL1 0x81c #define CFG_BRIDGE_SB_INIT BIT(0) =20 #define PCIE_CAP_SLOT_POWER_LIMIT_VAL FIELD_PREP(PCI_EXP_SLTCAP_SPLV, \ @@ -93,30 +93,28 @@ PCIE_CAP_SLOT_POWER_LIMIT_VAL | \ PCIE_CAP_SLOT_POWER_LIMIT_SCALE) =20 -#define PCIE20_PARF_Q2A_FLUSH 0x1AC +#define PARF_Q2A_FLUSH 0x1AC =20 -#define PCIE20_MISC_CONTROL_1_REG 0x8BC +#define MISC_CONTROL_1_REG 0x8BC #define DBI_RO_WR_EN 1 =20 #define PERST_DELAY_US 1000 /* PARF registers */ -#define PCIE20_PARF_PCS_DEEMPH 0x34 +#define PARF_PCS_DEEMPH 0x34 #define PCS_DEEMPH_TX_DEEMPH_GEN1(x) ((x) << 16) #define PCS_DEEMPH_TX_DEEMPH_GEN2_3_5DB(x) ((x) << 8) #define PCS_DEEMPH_TX_DEEMPH_GEN2_6DB(x) ((x) << 0) =20 -#define PCIE20_PARF_PCS_SWING 0x38 +#define PARF_PCS_SWING 0x38 #define PCS_SWING_TX_SWING_FULL(x) ((x) << 8) #define PCS_SWING_TX_SWING_LOW(x) ((x) << 0) =20 -#define PCIE20_PARF_CONFIG_BITS 0x50 +#define PARF_CONFIG_BITS 0x50 #define PHY_RX0_EQ(x) ((x) << 24) =20 -#define PCIE20_v3_PARF_SLV_ADDR_SPACE_SIZE 0x358 +#define PARF_SLV_ADDR_SPACE_SIZE 0x358 #define SLV_ADDR_SPACE_SZ 0x10000000 =20 -#define PCIE20_LNK_CONTROL2_LINK_STATUS2 0xa0 - #define DEVICE_TYPE_RC 0x4 =20 #define QCOM_PCIE_2_1_0_MAX_SUPPLY 3 @@ -261,9 +259,9 @@ static void qcom_pcie_2_1_0_ltssm_enable(struct qcom_pc= ie *pcie) u32 val; =20 /* enable link training */ - val =3D readl(pcie->elbi + PCIE20_ELBI_SYS_CTRL); - val |=3D PCIE20_ELBI_SYS_CTRL_LT_ENABLE; - writel(val, pcie->elbi + PCIE20_ELBI_SYS_CTRL); + val =3D readl(pcie->elbi + ELBI_SYS_CTRL); + val |=3D ELBI_SYS_CTRL_LT_ENABLE; + writel(val, pcie->elbi + ELBI_SYS_CTRL); } =20 static int qcom_pcie_get_resources_2_1_0(struct qcom_pcie *pcie) @@ -333,7 +331,7 @@ static void qcom_pcie_deinit_2_1_0(struct qcom_pcie *pc= ie) reset_control_assert(res->ext_reset); reset_control_assert(res->phy_reset); =20 - writel(1, pcie->parf + PCIE20_PARF_PHY_CTRL); + writel(1, pcie->parf + PARF_PHY_CTRL); =20 regulator_bulk_disable(ARRAY_SIZE(res->supplies), res->supplies); } @@ -423,9 +421,9 @@ static int qcom_pcie_post_init_2_1_0(struct qcom_pcie *= pcie) int ret; =20 /* enable PCIe clocks and resets */ - val =3D readl(pcie->parf + PCIE20_PARF_PHY_CTRL); + val =3D readl(pcie->parf + PARF_PHY_CTRL); val &=3D ~BIT(0); - writel(val, pcie->parf + PCIE20_PARF_PHY_CTRL); + writel(val, pcie->parf + PARF_PHY_CTRL); =20 ret =3D clk_bulk_prepare_enable(ARRAY_SIZE(res->clks), res->clks); if (ret) @@ -436,37 +434,37 @@ static int qcom_pcie_post_init_2_1_0(struct qcom_pcie= *pcie) writel(PCS_DEEMPH_TX_DEEMPH_GEN1(24) | PCS_DEEMPH_TX_DEEMPH_GEN2_3_5DB(24) | PCS_DEEMPH_TX_DEEMPH_GEN2_6DB(34), - pcie->parf + PCIE20_PARF_PCS_DEEMPH); + pcie->parf + PARF_PCS_DEEMPH); writel(PCS_SWING_TX_SWING_FULL(120) | PCS_SWING_TX_SWING_LOW(120), - pcie->parf + PCIE20_PARF_PCS_SWING); - writel(PHY_RX0_EQ(4), pcie->parf + PCIE20_PARF_CONFIG_BITS); + pcie->parf + PARF_PCS_SWING); + writel(PHY_RX0_EQ(4), pcie->parf + PARF_CONFIG_BITS); } =20 if (of_device_is_compatible(node, "qcom,pcie-ipq8064")) { /* set TX termination offset */ - val =3D readl(pcie->parf + PCIE20_PARF_PHY_CTRL); + val =3D readl(pcie->parf + PARF_PHY_CTRL); val &=3D ~PHY_CTRL_PHY_TX0_TERM_OFFSET_MASK; val |=3D PHY_CTRL_PHY_TX0_TERM_OFFSET(7); - writel(val, pcie->parf + PCIE20_PARF_PHY_CTRL); + writel(val, pcie->parf + PARF_PHY_CTRL); } =20 /* enable external reference clock */ - val =3D readl(pcie->parf + PCIE20_PARF_PHY_REFCLK); + val =3D readl(pcie->parf + PARF_PHY_REFCLK); /* USE_PAD is required only for ipq806x */ if (!of_device_is_compatible(node, "qcom,pcie-apq8064")) val &=3D ~PHY_REFCLK_USE_PAD; val |=3D PHY_REFCLK_SSP_EN; - writel(val, pcie->parf + PCIE20_PARF_PHY_REFCLK); + writel(val, pcie->parf + PARF_PHY_REFCLK); =20 /* wait for clock acquisition */ usleep_range(1000, 1500); =20 /* Set the Max TLP size to 2K, instead of using default of 4K */ writel(CFG_REMOTE_RD_REQ_BRIDGE_SIZE_2K, - pci->dbi_base + PCIE20_AXI_MSTR_RESP_COMP_CTRL0); + pci->dbi_base + AXI_MSTR_RESP_COMP_CTRL0); writel(CFG_BRIDGE_SB_INIT, - pci->dbi_base + PCIE20_AXI_MSTR_RESP_COMP_CTRL1); + pci->dbi_base + AXI_MSTR_RESP_COMP_CTRL1); =20 return 0; } @@ -574,13 +572,13 @@ static int qcom_pcie_init_1_0_0(struct qcom_pcie *pci= e) static int qcom_pcie_post_init_1_0_0(struct qcom_pcie *pcie) { /* change DBI base address */ - writel(0, pcie->parf + PCIE20_PARF_DBI_BASE_ADDR); + writel(0, pcie->parf + PARF_DBI_BASE_ADDR); =20 if (IS_ENABLED(CONFIG_PCI_MSI)) { - u32 val =3D readl(pcie->parf + PCIE20_PARF_AXI_MSTR_WR_ADDR_HALT); + u32 val =3D readl(pcie->parf + PARF_AXI_MSTR_WR_ADDR_HALT); =20 val |=3D BIT(31); - writel(val, pcie->parf + PCIE20_PARF_AXI_MSTR_WR_ADDR_HALT); + writel(val, pcie->parf + PARF_AXI_MSTR_WR_ADDR_HALT); } =20 return 0; @@ -591,9 +589,9 @@ static void qcom_pcie_2_3_2_ltssm_enable(struct qcom_pc= ie *pcie) u32 val; =20 /* enable link training */ - val =3D readl(pcie->parf + PCIE20_PARF_LTSSM); + val =3D readl(pcie->parf + PARF_LTSSM); val |=3D BIT(8); - writel(val, pcie->parf + PCIE20_PARF_LTSSM); + writel(val, pcie->parf + PARF_LTSSM); } =20 static int qcom_pcie_get_resources_2_3_2(struct qcom_pcie *pcie) @@ -698,25 +696,25 @@ static int qcom_pcie_post_init_2_3_2(struct qcom_pcie= *pcie) u32 val; =20 /* enable PCIe clocks and resets */ - val =3D readl(pcie->parf + PCIE20_PARF_PHY_CTRL); + val =3D readl(pcie->parf + PARF_PHY_CTRL); val &=3D ~BIT(0); - writel(val, pcie->parf + PCIE20_PARF_PHY_CTRL); + writel(val, pcie->parf + PARF_PHY_CTRL); =20 /* change DBI base address */ - writel(0, pcie->parf + PCIE20_PARF_DBI_BASE_ADDR); + writel(0, pcie->parf + PARF_DBI_BASE_ADDR); =20 /* MAC PHY_POWERDOWN MUX DISABLE */ - val =3D readl(pcie->parf + PCIE20_PARF_SYS_CTRL); + val =3D readl(pcie->parf + PARF_SYS_CTRL); val &=3D ~BIT(29); - writel(val, pcie->parf + PCIE20_PARF_SYS_CTRL); + writel(val, pcie->parf + PARF_SYS_CTRL); =20 - val =3D readl(pcie->parf + PCIE20_PARF_MHI_CLOCK_RESET_CTRL); + val =3D readl(pcie->parf + PARF_MHI_CLOCK_RESET_CTRL); val |=3D BIT(4); - writel(val, pcie->parf + PCIE20_PARF_MHI_CLOCK_RESET_CTRL); + writel(val, pcie->parf + PARF_MHI_CLOCK_RESET_CTRL); =20 - val =3D readl(pcie->parf + PCIE20_PARF_AXI_MSTR_WR_ADDR_HALT_V2); + val =3D readl(pcie->parf + PARF_AXI_MSTR_WR_ADDR_HALT_V2); val |=3D BIT(31); - writel(val, pcie->parf + PCIE20_PARF_AXI_MSTR_WR_ADDR_HALT_V2); + writel(val, pcie->parf + PARF_AXI_MSTR_WR_ADDR_HALT_V2); =20 return 0; } @@ -977,25 +975,25 @@ static int qcom_pcie_post_init_2_4_0(struct qcom_pcie= *pcie) u32 val; =20 /* enable PCIe clocks and resets */ - val =3D readl(pcie->parf + PCIE20_PARF_PHY_CTRL); + val =3D readl(pcie->parf + PARF_PHY_CTRL); val &=3D ~BIT(0); - writel(val, pcie->parf + PCIE20_PARF_PHY_CTRL); + writel(val, pcie->parf + PARF_PHY_CTRL); =20 /* change DBI base address */ - writel(0, pcie->parf + PCIE20_PARF_DBI_BASE_ADDR); + writel(0, pcie->parf + PARF_DBI_BASE_ADDR); =20 /* MAC PHY_POWERDOWN MUX DISABLE */ - val =3D readl(pcie->parf + PCIE20_PARF_SYS_CTRL); + val =3D readl(pcie->parf + PARF_SYS_CTRL); val &=3D ~BIT(29); - writel(val, pcie->parf + PCIE20_PARF_SYS_CTRL); + writel(val, pcie->parf + PARF_SYS_CTRL); =20 - val =3D readl(pcie->parf + PCIE20_PARF_MHI_CLOCK_RESET_CTRL); + val =3D readl(pcie->parf + PARF_MHI_CLOCK_RESET_CTRL); val |=3D BIT(4); - writel(val, pcie->parf + PCIE20_PARF_MHI_CLOCK_RESET_CTRL); + writel(val, pcie->parf + PARF_MHI_CLOCK_RESET_CTRL); =20 - val =3D readl(pcie->parf + PCIE20_PARF_AXI_MSTR_WR_ADDR_HALT_V2); + val =3D readl(pcie->parf + PARF_AXI_MSTR_WR_ADDR_HALT_V2); val |=3D BIT(31); - writel(val, pcie->parf + PCIE20_PARF_AXI_MSTR_WR_ADDR_HALT_V2); + writel(val, pcie->parf + PARF_AXI_MSTR_WR_ADDR_HALT_V2); =20 return 0; } @@ -1140,22 +1138,22 @@ static int qcom_pcie_post_init_2_3_3(struct qcom_pc= ie *pcie) u32 val; =20 writel(SLV_ADDR_SPACE_SZ, - pcie->parf + PCIE20_v3_PARF_SLV_ADDR_SPACE_SIZE); + pcie->parf + PARF_SLV_ADDR_SPACE_SIZE_2_3_3); =20 - val =3D readl(pcie->parf + PCIE20_PARF_PHY_CTRL); + val =3D readl(pcie->parf + PARF_PHY_CTRL); val &=3D ~BIT(0); - writel(val, pcie->parf + PCIE20_PARF_PHY_CTRL); + writel(val, pcie->parf + PARF_PHY_CTRL); =20 - writel(0, pcie->parf + PCIE20_PARF_DBI_BASE_ADDR); + writel(0, pcie->parf + PARF_DBI_BASE_ADDR); =20 writel(MST_WAKEUP_EN | SLV_WAKEUP_EN | MSTR_ACLK_CGC_DIS | SLV_ACLK_CGC_DIS | CORE_CLK_CGC_DIS | AUX_PWR_DET | L23_CLK_RMV_DIS | L1_CLK_RMV_DIS, - pcie->parf + PCIE20_PARF_SYS_CTRL); - writel(0, pcie->parf + PCIE20_PARF_Q2A_FLUSH); + pcie->parf + PARF_SYS_CTRL); + writel(0, pcie->parf + PARF_Q2A_FLUSH); =20 writel(PCI_COMMAND_MASTER, pci->dbi_base + PCI_COMMAND); - writel(DBI_RO_WR_EN, pci->dbi_base + PCIE20_MISC_CONTROL_1_REG); + writel(DBI_RO_WR_EN, pci->dbi_base + MISC_CONTROL_1_REG); writel(PCIE_CAP_SLOT_VAL, pci->dbi_base + offset + PCI_EXP_SLTCAP); =20 val =3D readl(pci->dbi_base + offset + PCI_EXP_LNKCAP); @@ -1255,34 +1253,34 @@ static int qcom_pcie_init_2_7_0(struct qcom_pcie *p= cie) usleep_range(1000, 1500); =20 /* configure PCIe to RC mode */ - writel(DEVICE_TYPE_RC, pcie->parf + PCIE20_PARF_DEVICE_TYPE); + writel(DEVICE_TYPE_RC, pcie->parf + PARF_DEVICE_TYPE); =20 /* enable PCIe clocks and resets */ - val =3D readl(pcie->parf + PCIE20_PARF_PHY_CTRL); + val =3D readl(pcie->parf + PARF_PHY_CTRL); val &=3D ~BIT(0); - writel(val, pcie->parf + PCIE20_PARF_PHY_CTRL); + writel(val, pcie->parf + PARF_PHY_CTRL); =20 /* change DBI base address */ - writel(0, pcie->parf + PCIE20_PARF_DBI_BASE_ADDR); + writel(0, pcie->parf + PARF_DBI_BASE_ADDR); =20 /* MAC PHY_POWERDOWN MUX DISABLE */ - val =3D readl(pcie->parf + PCIE20_PARF_SYS_CTRL); + val =3D readl(pcie->parf + PARF_SYS_CTRL); val &=3D ~BIT(29); - writel(val, pcie->parf + PCIE20_PARF_SYS_CTRL); + writel(val, pcie->parf + PARF_SYS_CTRL); =20 - val =3D readl(pcie->parf + PCIE20_PARF_MHI_CLOCK_RESET_CTRL); + val =3D readl(pcie->parf + PARF_MHI_CLOCK_RESET_CTRL); val |=3D BIT(4); - writel(val, pcie->parf + PCIE20_PARF_MHI_CLOCK_RESET_CTRL); + writel(val, pcie->parf + PARF_MHI_CLOCK_RESET_CTRL); =20 /* Enable L1 and L1SS */ - val =3D readl(pcie->parf + PCIE20_PARF_PM_CTRL); + val =3D readl(pcie->parf + PARF_PM_CTRL); val &=3D ~REQ_NOT_ENTR_L1; - writel(val, pcie->parf + PCIE20_PARF_PM_CTRL); + writel(val, pcie->parf + PARF_PM_CTRL); =20 if (IS_ENABLED(CONFIG_PCI_MSI)) { - val =3D readl(pcie->parf + PCIE20_PARF_AXI_MSTR_WR_ADDR_HALT); + val =3D readl(pcie->parf + PARF_AXI_MSTR_WR_ADDR_HALT); val |=3D BIT(31); - writel(val, pcie->parf + PCIE20_PARF_AXI_MSTR_WR_ADDR_HALT); + writel(val, pcie->parf + PARF_AXI_MSTR_WR_ADDR_HALT); } =20 return 0; @@ -1371,17 +1369,17 @@ static int qcom_pcie_post_init_2_9_0(struct qcom_pc= ie *pcie) int i; =20 writel(SLV_ADDR_SPACE_SZ, - pcie->parf + PCIE20_v3_PARF_SLV_ADDR_SPACE_SIZE); + pcie->parf + PARF_SLV_ADDR_SPACE_SIZE); =20 - val =3D readl(pcie->parf + PCIE20_PARF_PHY_CTRL); + val =3D readl(pcie->parf + PARF_PHY_CTRL); val &=3D ~BIT(0); - writel(val, pcie->parf + PCIE20_PARF_PHY_CTRL); + writel(val, pcie->parf + PARF_PHY_CTRL); =20 - writel(0, pcie->parf + PCIE20_PARF_DBI_BASE_ADDR); + writel(0, pcie->parf + PARF_DBI_BASE_ADDR); =20 - writel(DEVICE_TYPE_RC, pcie->parf + PCIE20_PARF_DEVICE_TYPE); + writel(DEVICE_TYPE_RC, pcie->parf + PARF_DEVICE_TYPE); writel(BYPASS | MSTR_AXI_CLK_EN | AHB_CLK_EN, - pcie->parf + PCIE20_PARF_MHI_CLOCK_RESET_CTRL); + pcie->parf + PARF_MHI_CLOCK_RESET_CTRL); writel(GEN3_RELATED_OFF_RXEQ_RGRDLESS_RXTS | GEN3_RELATED_OFF_GEN3_ZRXDC_NONCOMPL, pci->dbi_base + GEN3_RELATED_OFF); @@ -1389,9 +1387,9 @@ static int qcom_pcie_post_init_2_9_0(struct qcom_pcie= *pcie) writel(MST_WAKEUP_EN | SLV_WAKEUP_EN | MSTR_ACLK_CGC_DIS | SLV_ACLK_CGC_DIS | CORE_CLK_CGC_DIS | AUX_PWR_DET | L23_CLK_RMV_DIS | L1_CLK_RMV_DIS, - pcie->parf + PCIE20_PARF_SYS_CTRL); + pcie->parf + PARF_SYS_CTRL); =20 - writel(0, pcie->parf + PCIE20_PARF_Q2A_FLUSH); + writel(0, pcie->parf + PARF_Q2A_FLUSH); =20 dw_pcie_dbi_ro_wr_en(pci); writel(PCIE_CAP_SLOT_VAL, pci->dbi_base + offset + PCI_EXP_SLTCAP); @@ -1404,7 +1402,7 @@ static int qcom_pcie_post_init_2_9_0(struct qcom_pcie= *pcie) PCI_EXP_DEVCTL2); =20 for (i =3D 0; i < 256; i++) - writel(0, pcie->parf + PCIE20_PARF_BDF_TO_SID_TABLE_N + (4 * i)); + writel(0, pcie->parf + PARF_BDF_TO_SID_TABLE_N + (4 * i)); =20 return 0; } @@ -1426,7 +1424,7 @@ static int qcom_pcie_config_sid_sm8250(struct qcom_pc= ie *pcie) u32 smmu_sid; u32 smmu_sid_len; } *map; - void __iomem *bdf_to_sid_base =3D pcie->parf + PCIE20_PARF_BDF_TO_SID_TAB= LE_N; + void __iomem *bdf_to_sid_base =3D pcie->parf + PARF_BDF_TO_SID_TABLE_N; struct device *dev =3D pcie->pci->dev; u8 qcom_pcie_crc8_table[CRC8_TABLE_SIZE]; int i, nr_map, size =3D 0; --=20 2.25.1 From nobody Sat Apr 11 11:48:14 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 35B8BC64EC4 for ; Mon, 6 Mar 2023 15:33:27 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230036AbjCFPdZ (ORCPT ); Mon, 6 Mar 2023 10:33:25 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:59112 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229838AbjCFPdQ (ORCPT ); Mon, 6 Mar 2023 10:33:16 -0500 Received: from mail-pl1-x634.google.com (mail-pl1-x634.google.com [IPv6:2607:f8b0:4864:20::634]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 415A132529 for ; Mon, 6 Mar 2023 07:32:48 -0800 (PST) Received: by mail-pl1-x634.google.com with SMTP id i3so10769444plg.6 for ; Mon, 06 Mar 2023 07:32:48 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1678116767; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=dmhzqQp9Bpxccy6mDdW3lTo4tjr71oQJII7ujI7fl58=; b=ofBNg33OO1cIk2DNKGqqauZoRKBPFtQCz38D0poCdzva5H4Xt/q/VYXz9IX3RdHtlS JfkUCD193+J8gUc6tFuF+A5PT6orD2+cl2Np6wpJ6CVCF0RqwiBPkUA1SjwCDgTNp1/0 Drp6pjPBq/U+sFV2BAAlH35+VXaugjyP3dKAw6p6S+mPii0GNKgUK/gboW9VL5FihSVl dxKCbdGBbcq9IXTwKmV1c0ckurZdbkE/v5bMxGUoVnl51z2q4xo4/y66buslzG2QSrBa uGU0dLwfGt1iSlR95S6qpYR+AJoMX2L7cId4gr4CKbwZ7Pq30N+9/FKu4COu3qgRO4zY 80gg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1678116767; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=dmhzqQp9Bpxccy6mDdW3lTo4tjr71oQJII7ujI7fl58=; b=K84zcmLvlRriCChLgze/fYmQIE57A5M9Sick2pa7htx0fejgVqr27fz1MjFMGlUjYn VOgEJLZGdly6PzlgipKD4e4McUtzuJNclPvjDOAHpqoSmFY35kZpETDVjwazd751XS45 4an4PfRMPze4B4XpN2TQLTnu3Z/kAdAJfEkJ8xOzFLKOlGI7DQbAFRuJHqlb2NsGpiWr AjSjfWrrrGUkcV0IDHkXKslGaa88ay1TvgliW3je/jRESrCq2BuT16KuA0H5G3xcwUbb fonBJj1difHWULaSnGLVKi3mzDnP2LG1czb6lRr91eXRSHkLbA0GVu5lptsqAtrQjC3n O/CA== X-Gm-Message-State: AO0yUKVlt2TRsroVSmYXIn9YlQlBzvWzd0LC4jrDoJfvDyVDbIeGu+Cl 9Dc8TEdVs94+Gr+CrrGzye9q X-Google-Smtp-Source: AK7set+yWV/VhNLImyYR+KqbGXGA/kVZxgIdBcl+PNfyT9Hj1yZ9+quDo/uJqicyI+7UMgqwNaMOhQ== X-Received: by 2002:a17:902:dacd:b0:19a:96f0:b0f with SMTP id q13-20020a170902dacd00b0019a96f00b0fmr12034576plx.28.1678116767536; Mon, 06 Mar 2023 07:32:47 -0800 (PST) Received: from localhost.localdomain ([59.97.52.140]) by smtp.gmail.com with ESMTPSA id kl4-20020a170903074400b0019a7c890c61sm6837430plb.252.2023.03.06.07.32.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 06 Mar 2023 07:32:47 -0800 (PST) From: Manivannan Sadhasivam To: andersson@kernel.org, lpieralisi@kernel.org, kw@linux.com, krzysztof.kozlowski+dt@linaro.org, robh@kernel.org Cc: konrad.dybcio@linaro.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, quic_srichara@quicinc.com, Manivannan Sadhasivam Subject: [PATCH 02/19] PCI: qcom: Sort and group registers and bitfield definitions Date: Mon, 6 Mar 2023 21:02:05 +0530 Message-Id: <20230306153222.157667-3-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230306153222.157667-1-manivannan.sadhasivam@linaro.org> References: <20230306153222.157667-1-manivannan.sadhasivam@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Sorting the registers and their bit definitions will make it easier to add more definitions in the future and it also helps in maintenance. While at it, let's also group the registers and bit definitions separately as done in the pcie-qcom-ep driver. Signed-off-by: Manivannan Sadhasivam --- drivers/pci/controller/dwc/pcie-qcom.c | 108 ++++++++++++++----------- 1 file changed, 63 insertions(+), 45 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controlle= r/dwc/pcie-qcom.c index 6930bc9ceeb5..9223ca76640d 100644 --- a/drivers/pci/controller/dwc/pcie-qcom.c +++ b/drivers/pci/controller/dwc/pcie-qcom.c @@ -33,7 +33,36 @@ #include "../../pci.h" #include "pcie-designware.h" =20 +/* PARF registers */ #define PARF_SYS_CTRL 0x00 +#define PARF_PM_CTRL 0x20 +#define PARF_PCS_DEEMPH 0x34 +#define PARF_PCS_SWING 0x38 +#define PARF_PHY_CTRL 0x40 +#define PARF_PHY_REFCLK 0x4C +#define PARF_CONFIG_BITS 0x50 +#define PARF_DBI_BASE_ADDR 0x168 +#define PARF_SLV_ADDR_SPACE_SIZE_2_3_3 0x16C /* Register offset specific = to IP ver 2.3.3 */ +#define PARF_MHI_CLOCK_RESET_CTRL 0x174 +#define PARF_AXI_MSTR_WR_ADDR_HALT 0x178 +#define PARF_AXI_MSTR_WR_ADDR_HALT_V2 0x1A8 +#define PARF_Q2A_FLUSH 0x1AC +#define PARF_LTSSM 0x1B0 +#define PARF_SID_OFFSET 0x234 +#define PARF_BDF_TRANSLATE_CFG 0x24C +#define PARF_SLV_ADDR_SPACE_SIZE 0x358 +#define PARF_DEVICE_TYPE 0x1000 +#define PARF_BDF_TO_SID_TABLE_N 0x2000 + +/* ELBI registers */ +#define ELBI_SYS_CTRL 0x04 + +/* DBI registers */ +#define AXI_MSTR_RESP_COMP_CTRL0 0x818 +#define AXI_MSTR_RESP_COMP_CTRL1 0x81c +#define MISC_CONTROL_1_REG 0x8BC + +/* PARF_SYS_CTRL register fields */ #define MST_WAKEUP_EN BIT(13) #define SLV_WAKEUP_EN BIT(12) #define MSTR_ACLK_CGC_DIS BIT(10) @@ -43,45 +72,56 @@ #define L23_CLK_RMV_DIS BIT(2) #define L1_CLK_RMV_DIS BIT(1) =20 -#define PARF_PM_CTRL 0x20 +/* PARF_PM_CTRL register fields */ #define REQ_NOT_ENTR_L1 BIT(5) =20 -#define PARF_PHY_CTRL 0x40 +/* PARF_PCS_DEEMPH register fields */ +#define PCS_DEEMPH_TX_DEEMPH_GEN1(x) ((x) << 16) +#define PCS_DEEMPH_TX_DEEMPH_GEN2_3_5DB(x) ((x) << 8) +#define PCS_DEEMPH_TX_DEEMPH_GEN2_6DB(x) ((x) << 0) + +/* PARF_PCS_SWING register fields */ +#define PCS_SWING_TX_SWING_FULL(x) ((x) << 8) +#define PCS_SWING_TX_SWING_LOW(x) ((x) << 0) + +/* PARF_PHY_CTRL register fields */ #define PHY_CTRL_PHY_TX0_TERM_OFFSET_MASK GENMASK(20, 16) #define PHY_CTRL_PHY_TX0_TERM_OFFSET(x) ((x) << 16) =20 -#define PARF_PHY_REFCLK 0x4C +/* PARF_PHY_REFCLK register fields */ #define PHY_REFCLK_SSP_EN BIT(16) #define PHY_REFCLK_USE_PAD BIT(12) =20 -#define PARF_DBI_BASE_ADDR 0x168 -#define PARF_SLV_ADDR_SPACE_SIZE_2_3_3 0x16C /* Register offset specific = to IP rev 2.3.3 */ -#define PARF_MHI_CLOCK_RESET_CTRL 0x174 +/* PARF_CONFIG_BITS register fields */ +#define PHY_RX0_EQ(x) ((x) << 24) + +/* PARF_SLV_ADDR_SPACE_SIZE register value */ +#define SLV_ADDR_SPACE_SZ 0x10000000 + +/* PARF_MHI_CLOCK_RESET_CTRL register fields */ #define AHB_CLK_EN BIT(0) #define MSTR_AXI_CLK_EN BIT(1) #define BYPASS BIT(4) =20 -#define PARF_AXI_MSTR_WR_ADDR_HALT 0x178 -#define PARF_AXI_MSTR_WR_ADDR_HALT_V2 0x1A8 -#define PARF_LTSSM 0x1B0 -#define PARF_SID_OFFSET 0x234 -#define PARF_BDF_TRANSLATE_CFG 0x24C -#define PARF_DEVICE_TYPE 0x1000 -#define PARF_BDF_TO_SID_TABLE_N 0x2000 +/* PARF_DEVICE_TYPE register fields */ +#define DEVICE_TYPE_RC 0x4 =20 -#define ELBI_SYS_CTRL 0x04 +/* ELBI_SYS_CTRL register fields */ #define ELBI_SYS_CTRL_LT_ENABLE BIT(0) =20 -#define AXI_MSTR_RESP_COMP_CTRL0 0x818 +/* AXI_MSTR_RESP_COMP_CTRL0 register fields */ #define CFG_REMOTE_RD_REQ_BRIDGE_SIZE_2K 0x4 #define CFG_REMOTE_RD_REQ_BRIDGE_SIZE_4K 0x5 -#define AXI_MSTR_RESP_COMP_CTRL1 0x81c + +/* AXI_MSTR_RESP_COMP_CTRL1 register fields */ #define CFG_BRIDGE_SB_INIT BIT(0) =20 -#define PCIE_CAP_SLOT_POWER_LIMIT_VAL FIELD_PREP(PCI_EXP_SLTCAP_SPLV, \ - 250) -#define PCIE_CAP_SLOT_POWER_LIMIT_SCALE FIELD_PREP(PCI_EXP_SLTCAP_SPLS, \ - 1) +/* MISC_CONTROL_1_REG register fields */ +#define DBI_RO_WR_EN 1 + +/* PCI_EXP_SLTCAP register fields */ +#define PCIE_CAP_SLOT_POWER_LIMIT_VAL FIELD_PREP(PCI_EXP_SLTCAP_SPLV, 250) +#define PCIE_CAP_SLOT_POWER_LIMIT_SCALE FIELD_PREP(PCI_EXP_SLTCAP_SPLS, 1) #define PCIE_CAP_SLOT_VAL (PCI_EXP_SLTCAP_ABP | \ PCI_EXP_SLTCAP_PCP | \ PCI_EXP_SLTCAP_MRLSP | \ @@ -93,34 +133,12 @@ PCIE_CAP_SLOT_POWER_LIMIT_VAL | \ PCIE_CAP_SLOT_POWER_LIMIT_SCALE) =20 -#define PARF_Q2A_FLUSH 0x1AC - -#define MISC_CONTROL_1_REG 0x8BC -#define DBI_RO_WR_EN 1 - #define PERST_DELAY_US 1000 -/* PARF registers */ -#define PARF_PCS_DEEMPH 0x34 -#define PCS_DEEMPH_TX_DEEMPH_GEN1(x) ((x) << 16) -#define PCS_DEEMPH_TX_DEEMPH_GEN2_3_5DB(x) ((x) << 8) -#define PCS_DEEMPH_TX_DEEMPH_GEN2_6DB(x) ((x) << 0) - -#define PARF_PCS_SWING 0x38 -#define PCS_SWING_TX_SWING_FULL(x) ((x) << 8) -#define PCS_SWING_TX_SWING_LOW(x) ((x) << 0) - -#define PARF_CONFIG_BITS 0x50 -#define PHY_RX0_EQ(x) ((x) << 24) - -#define PARF_SLV_ADDR_SPACE_SIZE 0x358 -#define SLV_ADDR_SPACE_SZ 0x10000000 - -#define DEVICE_TYPE_RC 0x4 =20 -#define QCOM_PCIE_2_1_0_MAX_SUPPLY 3 -#define QCOM_PCIE_2_1_0_MAX_CLOCKS 5 +#define QCOM_PCIE_2_1_0_MAX_SUPPLY 3 +#define QCOM_PCIE_2_1_0_MAX_CLOCKS 5 =20 -#define QCOM_PCIE_CRC8_POLYNOMIAL (BIT(2) | BIT(1) | BIT(0)) +#define QCOM_PCIE_CRC8_POLYNOMIAL (BIT(2) | BIT(1) | BIT(0)) =20 struct qcom_pcie_resources_2_1_0 { struct clk_bulk_data clks[QCOM_PCIE_2_1_0_MAX_CLOCKS]; --=20 2.25.1 From nobody Sat Apr 11 11:48:14 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 55178C64EC4 for ; Mon, 6 Mar 2023 15:33:48 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229985AbjCFPd2 (ORCPT ); Mon, 6 Mar 2023 10:33:28 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:59224 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229938AbjCFPdU (ORCPT ); Mon, 6 Mar 2023 10:33:20 -0500 Received: from mail-pj1-x1036.google.com (mail-pj1-x1036.google.com [IPv6:2607:f8b0:4864:20::1036]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id A28391BED for ; Mon, 6 Mar 2023 07:32:52 -0800 (PST) Received: by mail-pj1-x1036.google.com with SMTP id qa18-20020a17090b4fd200b0023750b675f5so13519443pjb.3 for ; Mon, 06 Mar 2023 07:32:52 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1678116771; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=3tT4IStfyTS7c0lPgVozml2BSLbP+qQslzAxoVdPoGM=; b=qzFYJbB7hAFe7l46nHpK+q27pyKOro8dHeXLkSvKdgHRTDwrDJvyUujUSPZYQ9E0R3 KYRq24VUy+YZsbMCTHh5ZSYTwSlJ3owoPJWfAk+9h9ntwKEOY3MTr4wyMvraBRjfEa2C qYJCImXGHxsET7RQLe6K/OcDYFMh+qMcuOJBWyvMx20JN+PVgtRWqAIYXlCDwO/IYbZU 8P+k6hbuGqcI8nqTQVtl9VCb3YjDrl/slsZYXfLYkWsiPzC5HLQzf11f20Y4li9/jmQE RKkJM9s74mWLsvwp5yHrISGrnl97nHwk5Rag4jxMSmDoH8WQf50i87CnLCQTzSVpi1Hu pJyQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1678116771; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=3tT4IStfyTS7c0lPgVozml2BSLbP+qQslzAxoVdPoGM=; b=x/34iKysp5Gppq5xUay7xFPHN5LRRpQIXzyh1OBkcJB+sM+a0FwSMFwmip3LyCmEex IHjb2STz488Np8a/9JAfwCx7YKhq1jR2MksaW4xQ7/wen8PZwB3/uZvADw3Miya9mR71 9hHBRNBYVaPjBK27o9yj2AczxUI+Mamh9kUr5M/b884gQyEdgM/SfSq3cHBTry6ca6WE X5HTpm81YxDefa6Y9EtZWLzsnaHAom4uLkddIbE772guzs4IoiqN7jXzfFgB2WxB/Q2p UoYr70wN2llwpMlVX/nlQ6IR1Af6VmSkWleJdVPBG3kqQabN6D5Uw5BBZVX+pieXzuiK ogbA== X-Gm-Message-State: AO0yUKU08wNMG9Z+7cWMfDa9SyV3j4XqNmJd/EsBfzL7AjOMhFktO/+6 EgBl0smKc+EPhDj4ujNaz4Hg X-Google-Smtp-Source: AK7set+rfW5mUC6Jzv3XUSjoc31D9wyI3xcLM7qOSrxPZKjhLzoB90Ibrt4vWYqfAsj2sIV+sIHrmw== X-Received: by 2002:a17:902:e844:b0:19c:ef4d:ea35 with SMTP id t4-20020a170902e84400b0019cef4dea35mr13099075plg.21.1678116771509; Mon, 06 Mar 2023 07:32:51 -0800 (PST) Received: from localhost.localdomain ([59.97.52.140]) by smtp.gmail.com with ESMTPSA id kl4-20020a170903074400b0019a7c890c61sm6837430plb.252.2023.03.06.07.32.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 06 Mar 2023 07:32:51 -0800 (PST) From: Manivannan Sadhasivam To: andersson@kernel.org, lpieralisi@kernel.org, kw@linux.com, krzysztof.kozlowski+dt@linaro.org, robh@kernel.org Cc: konrad.dybcio@linaro.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, quic_srichara@quicinc.com, Manivannan Sadhasivam Subject: [PATCH 03/19] PCI: qcom: Use bitfield definitions for register fields Date: Mon, 6 Mar 2023 21:02:06 +0530 Message-Id: <20230306153222.157667-4-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230306153222.157667-1-manivannan.sadhasivam@linaro.org> References: <20230306153222.157667-1-manivannan.sadhasivam@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" To maintain uniformity throughout the driver and also to make the code easier to read, let's make use of bitfield definitions for register fields. Signed-off-by: Manivannan Sadhasivam --- drivers/pci/controller/dwc/pcie-qcom.c | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controlle= r/dwc/pcie-qcom.c index 9223ca76640d..e9f4c70b719a 100644 --- a/drivers/pci/controller/dwc/pcie-qcom.c +++ b/drivers/pci/controller/dwc/pcie-qcom.c @@ -76,24 +76,24 @@ #define REQ_NOT_ENTR_L1 BIT(5) =20 /* PARF_PCS_DEEMPH register fields */ -#define PCS_DEEMPH_TX_DEEMPH_GEN1(x) ((x) << 16) -#define PCS_DEEMPH_TX_DEEMPH_GEN2_3_5DB(x) ((x) << 8) -#define PCS_DEEMPH_TX_DEEMPH_GEN2_6DB(x) ((x) << 0) +#define PCS_DEEMPH_TX_DEEMPH_GEN1(x) FIELD_PREP(GENMASK(21, 16), x) +#define PCS_DEEMPH_TX_DEEMPH_GEN2_3_5DB(x) FIELD_PREP(GENMASK(13, 8), x) +#define PCS_DEEMPH_TX_DEEMPH_GEN2_6DB(x) FIELD_PREP(GENMASK(5, 0), x) =20 /* PARF_PCS_SWING register fields */ -#define PCS_SWING_TX_SWING_FULL(x) ((x) << 8) -#define PCS_SWING_TX_SWING_LOW(x) ((x) << 0) +#define PCS_SWING_TX_SWING_FULL(x) FIELD_PREP(GENMASK(14, 8), x) +#define PCS_SWING_TX_SWING_LOW(x) FIELD_PREP(GENMASK(6, 0), x) =20 /* PARF_PHY_CTRL register fields */ #define PHY_CTRL_PHY_TX0_TERM_OFFSET_MASK GENMASK(20, 16) -#define PHY_CTRL_PHY_TX0_TERM_OFFSET(x) ((x) << 16) +#define PHY_CTRL_PHY_TX0_TERM_OFFSET(x) FIELD_PREP(PHY_CTRL_PHY_TX0_TERM_= OFFSET_MASK, x) =20 /* PARF_PHY_REFCLK register fields */ #define PHY_REFCLK_SSP_EN BIT(16) #define PHY_REFCLK_USE_PAD BIT(12) =20 /* PARF_CONFIG_BITS register fields */ -#define PHY_RX0_EQ(x) ((x) << 24) +#define PHY_RX0_EQ(x) FIELD_PREP(GENMASK(26, 24), x) =20 /* PARF_SLV_ADDR_SPACE_SIZE register value */ #define SLV_ADDR_SPACE_SZ 0x10000000 --=20 2.25.1 From nobody Sat Apr 11 11:48:14 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id F0AA0C6FD1C for ; Mon, 6 Mar 2023 15:33:55 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230187AbjCFPdx (ORCPT ); Mon, 6 Mar 2023 10:33:53 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:59390 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230126AbjCFPdd (ORCPT ); Mon, 6 Mar 2023 10:33:33 -0500 Received: from mail-pl1-x62c.google.com (mail-pl1-x62c.google.com [IPv6:2607:f8b0:4864:20::62c]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id B342C9EC0 for ; Mon, 6 Mar 2023 07:32:57 -0800 (PST) Received: by mail-pl1-x62c.google.com with SMTP id v11so10763397plz.8 for ; Mon, 06 Mar 2023 07:32:57 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1678116775; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=98/PwVeFNeIxQrm0IqUyAA3dXph0wAaYOEANDm444S8=; b=A1e/RScdJkJm9bV3vORIbmXntCvyiLZ0oPFG+OkSsOq3JHkUdZkeZ4dZAPITPeroUu QICTLjQcp0mVKXKoWW3KGaSBVEG8xBHpujXfemnnD4heJYu8vk765X9zJ27asNqA5KHz h0SyW9RZhIuih7nkfYBazhZi+pviJablbY+K2qG/enrTFAfnLGSsfy/dTx9Zf5hjuRZM 7j/gvZJQMHoifMJ6XAxXiBReKp+K8aopKrubS9qOSQiA5/F67qr0tCicqv4M36Ft6iIh kUWJ55Ig9Y+hGYd1TnGHGmeP7sBB8N08qNrP6LWxU3zGVIQnR+uIEpG1V0uLemOoJ92t qqkg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1678116775; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=98/PwVeFNeIxQrm0IqUyAA3dXph0wAaYOEANDm444S8=; b=j+U0KyvZipPUTiXqMm9yxqSVfOMMfpAV+uYtUFfgSB5Y/4M1XvO+KeF8GWYh/A6QrM zCoc/VdmmkLXaakNmHOb/3WXPk1IvxyWiClLRYiyglyiOhzbd1UhGyeZvyEPbRx3uvDq zR9z21mNJzqpYWspbTwWvx8WVe2kI2flTmQjYdr1VZ6eS2Fm3n9xtdDR9GY7zFEHvk49 qXTWpdbwOgek5pAwYeN/rOmcU9Q4WTW1bvPJ+hBu7d7WwHZTZkzQvqmqX2F9zRW2UgA2 ZpW+IpZARkq9IMVYk5zQEIcvBW8vbf8avV0eIJwXU8wo3SSa3mSnCHsH+HdAeD8oUaeZ DLBQ== X-Gm-Message-State: AO0yUKVRXSlToDxV2wJQDB2S44YGSC/4f7V5n5bnINGS83K59OK+u4uh NZFit/6OMgZ69KtU7nv2O1W5 X-Google-Smtp-Source: AK7set/IwLf6A0+z3yMo6tDIwKR7A+i6IcvpEVK/5fVmZgnPXiP8s6rMFStPAIVtr/yo3nM6hcz/BQ== X-Received: by 2002:a17:902:e842:b0:19a:b4a9:9ddb with SMTP id t2-20020a170902e84200b0019ab4a99ddbmr14567372plg.49.1678116775561; Mon, 06 Mar 2023 07:32:55 -0800 (PST) Received: from localhost.localdomain ([59.97.52.140]) by smtp.gmail.com with ESMTPSA id kl4-20020a170903074400b0019a7c890c61sm6837430plb.252.2023.03.06.07.32.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 06 Mar 2023 07:32:54 -0800 (PST) From: Manivannan Sadhasivam To: andersson@kernel.org, lpieralisi@kernel.org, kw@linux.com, krzysztof.kozlowski+dt@linaro.org, robh@kernel.org Cc: konrad.dybcio@linaro.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, quic_srichara@quicinc.com, Manivannan Sadhasivam Subject: [PATCH 04/19] PCI: qcom: Add missing macros for register fields Date: Mon, 6 Mar 2023 21:02:07 +0530 Message-Id: <20230306153222.157667-5-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230306153222.157667-1-manivannan.sadhasivam@linaro.org> References: <20230306153222.157667-1-manivannan.sadhasivam@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Some of the registers are changed using hardcoded bitfields without macros. This provides no information on what the register setting is about. So add the macros to those fields for making the code more understandable. Signed-off-by: Manivannan Sadhasivam --- drivers/pci/controller/dwc/pcie-qcom.c | 42 +++++++++++++++----------- 1 file changed, 25 insertions(+), 17 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controlle= r/dwc/pcie-qcom.c index e9f4c70b719a..926a531fda3a 100644 --- a/drivers/pci/controller/dwc/pcie-qcom.c +++ b/drivers/pci/controller/dwc/pcie-qcom.c @@ -63,6 +63,7 @@ #define MISC_CONTROL_1_REG 0x8BC =20 /* PARF_SYS_CTRL register fields */ +#define MAC_PHY_POWERDOWN_IN_P2_D_MUX_EN BIT(29) #define MST_WAKEUP_EN BIT(13) #define SLV_WAKEUP_EN BIT(12) #define MSTR_ACLK_CGC_DIS BIT(10) @@ -87,6 +88,7 @@ /* PARF_PHY_CTRL register fields */ #define PHY_CTRL_PHY_TX0_TERM_OFFSET_MASK GENMASK(20, 16) #define PHY_CTRL_PHY_TX0_TERM_OFFSET(x) FIELD_PREP(PHY_CTRL_PHY_TX0_TERM_= OFFSET_MASK, x) +#define PHY_TEST_PWR_DOWN BIT(0) =20 /* PARF_PHY_REFCLK register fields */ #define PHY_REFCLK_SSP_EN BIT(16) @@ -103,6 +105,12 @@ #define MSTR_AXI_CLK_EN BIT(1) #define BYPASS BIT(4) =20 +/* PARF_AXI_MSTR_WR_ADDR_HALT register fields */ +#define EN BIT(31) + +/* PARF_LTSSM register fields */ +#define LTSSM_EN BIT(8) + /* PARF_DEVICE_TYPE register fields */ #define DEVICE_TYPE_RC 0x4 =20 @@ -440,7 +448,7 @@ static int qcom_pcie_post_init_2_1_0(struct qcom_pcie *= pcie) =20 /* enable PCIe clocks and resets */ val =3D readl(pcie->parf + PARF_PHY_CTRL); - val &=3D ~BIT(0); + val &=3D ~PHY_TEST_PWR_DOWN; writel(val, pcie->parf + PARF_PHY_CTRL); =20 ret =3D clk_bulk_prepare_enable(ARRAY_SIZE(res->clks), res->clks); @@ -595,7 +603,7 @@ static int qcom_pcie_post_init_1_0_0(struct qcom_pcie *= pcie) if (IS_ENABLED(CONFIG_PCI_MSI)) { u32 val =3D readl(pcie->parf + PARF_AXI_MSTR_WR_ADDR_HALT); =20 - val |=3D BIT(31); + val |=3D EN; writel(val, pcie->parf + PARF_AXI_MSTR_WR_ADDR_HALT); } =20 @@ -608,7 +616,7 @@ static void qcom_pcie_2_3_2_ltssm_enable(struct qcom_pc= ie *pcie) =20 /* enable link training */ val =3D readl(pcie->parf + PARF_LTSSM); - val |=3D BIT(8); + val |=3D LTSSM_EN; writel(val, pcie->parf + PARF_LTSSM); } =20 @@ -715,7 +723,7 @@ static int qcom_pcie_post_init_2_3_2(struct qcom_pcie *= pcie) =20 /* enable PCIe clocks and resets */ val =3D readl(pcie->parf + PARF_PHY_CTRL); - val &=3D ~BIT(0); + val &=3D ~PHY_TEST_PWR_DOWN; writel(val, pcie->parf + PARF_PHY_CTRL); =20 /* change DBI base address */ @@ -723,15 +731,15 @@ static int qcom_pcie_post_init_2_3_2(struct qcom_pcie= *pcie) =20 /* MAC PHY_POWERDOWN MUX DISABLE */ val =3D readl(pcie->parf + PARF_SYS_CTRL); - val &=3D ~BIT(29); + val &=3D ~MAC_PHY_POWERDOWN_IN_P2_D_MUX_EN; writel(val, pcie->parf + PARF_SYS_CTRL); =20 val =3D readl(pcie->parf + PARF_MHI_CLOCK_RESET_CTRL); - val |=3D BIT(4); + val |=3D BYPASS; writel(val, pcie->parf + PARF_MHI_CLOCK_RESET_CTRL); =20 val =3D readl(pcie->parf + PARF_AXI_MSTR_WR_ADDR_HALT_V2); - val |=3D BIT(31); + val |=3D EN; writel(val, pcie->parf + PARF_AXI_MSTR_WR_ADDR_HALT_V2); =20 return 0; @@ -994,7 +1002,7 @@ static int qcom_pcie_post_init_2_4_0(struct qcom_pcie = *pcie) =20 /* enable PCIe clocks and resets */ val =3D readl(pcie->parf + PARF_PHY_CTRL); - val &=3D ~BIT(0); + val &=3D ~PHY_TEST_PWR_DOWN; writel(val, pcie->parf + PARF_PHY_CTRL); =20 /* change DBI base address */ @@ -1002,15 +1010,15 @@ static int qcom_pcie_post_init_2_4_0(struct qcom_pc= ie *pcie) =20 /* MAC PHY_POWERDOWN MUX DISABLE */ val =3D readl(pcie->parf + PARF_SYS_CTRL); - val &=3D ~BIT(29); + val &=3D ~MAC_PHY_POWERDOWN_IN_P2_D_MUX_EN; writel(val, pcie->parf + PARF_SYS_CTRL); =20 val =3D readl(pcie->parf + PARF_MHI_CLOCK_RESET_CTRL); - val |=3D BIT(4); + val |=3D BYPASS; writel(val, pcie->parf + PARF_MHI_CLOCK_RESET_CTRL); =20 val =3D readl(pcie->parf + PARF_AXI_MSTR_WR_ADDR_HALT_V2); - val |=3D BIT(31); + val |=3D EN; writel(val, pcie->parf + PARF_AXI_MSTR_WR_ADDR_HALT_V2); =20 return 0; @@ -1159,7 +1167,7 @@ static int qcom_pcie_post_init_2_3_3(struct qcom_pcie= *pcie) pcie->parf + PARF_SLV_ADDR_SPACE_SIZE_2_3_3); =20 val =3D readl(pcie->parf + PARF_PHY_CTRL); - val &=3D ~BIT(0); + val &=3D ~PHY_TEST_PWR_DOWN; writel(val, pcie->parf + PARF_PHY_CTRL); =20 writel(0, pcie->parf + PARF_DBI_BASE_ADDR); @@ -1275,7 +1283,7 @@ static int qcom_pcie_init_2_7_0(struct qcom_pcie *pci= e) =20 /* enable PCIe clocks and resets */ val =3D readl(pcie->parf + PARF_PHY_CTRL); - val &=3D ~BIT(0); + val &=3D ~PHY_TEST_PWR_DOWN; writel(val, pcie->parf + PARF_PHY_CTRL); =20 /* change DBI base address */ @@ -1283,11 +1291,11 @@ static int qcom_pcie_init_2_7_0(struct qcom_pcie *p= cie) =20 /* MAC PHY_POWERDOWN MUX DISABLE */ val =3D readl(pcie->parf + PARF_SYS_CTRL); - val &=3D ~BIT(29); + val &=3D ~MAC_PHY_POWERDOWN_IN_P2_D_MUX_EN; writel(val, pcie->parf + PARF_SYS_CTRL); =20 val =3D readl(pcie->parf + PARF_MHI_CLOCK_RESET_CTRL); - val |=3D BIT(4); + val |=3D BYPASS; writel(val, pcie->parf + PARF_MHI_CLOCK_RESET_CTRL); =20 /* Enable L1 and L1SS */ @@ -1297,7 +1305,7 @@ static int qcom_pcie_init_2_7_0(struct qcom_pcie *pci= e) =20 if (IS_ENABLED(CONFIG_PCI_MSI)) { val =3D readl(pcie->parf + PARF_AXI_MSTR_WR_ADDR_HALT); - val |=3D BIT(31); + val |=3D EN; writel(val, pcie->parf + PARF_AXI_MSTR_WR_ADDR_HALT); } =20 @@ -1390,7 +1398,7 @@ static int qcom_pcie_post_init_2_9_0(struct qcom_pcie= *pcie) pcie->parf + PARF_SLV_ADDR_SPACE_SIZE); =20 val =3D readl(pcie->parf + PARF_PHY_CTRL); - val &=3D ~BIT(0); + val &=3D ~PHY_TEST_PWR_DOWN; writel(val, pcie->parf + PARF_PHY_CTRL); =20 writel(0, pcie->parf + PARF_DBI_BASE_ADDR); --=20 2.25.1 From nobody Sat Apr 11 11:48:14 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4CEB1C61DA4 for ; Mon, 6 Mar 2023 15:34:02 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230215AbjCFPd7 (ORCPT ); Mon, 6 Mar 2023 10:33:59 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:59828 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230167AbjCFPdn (ORCPT ); Mon, 6 Mar 2023 10:33:43 -0500 Received: from mail-pj1-x102c.google.com (mail-pj1-x102c.google.com [IPv6:2607:f8b0:4864:20::102c]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 3129526855 for ; Mon, 6 Mar 2023 07:33:11 -0800 (PST) Received: by mail-pj1-x102c.google.com with SMTP id m8-20020a17090a4d8800b002377bced051so13587827pjh.0 for ; Mon, 06 Mar 2023 07:33:11 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1678116779; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=hS/BEmRpdBxk7z2vn4cP+VagM+gkHpiXxJLmHI41D7s=; b=DLTKhluLIf0IiTpNHeDrmt8vRlpubL8ui2AjStd4vUha/wf1PfXT2IfZOKFkr59Llg KpyKSj1t7AkQQ3kacPQJItAdPJaIae+hjI+JqhpCOYmjmuqsFrFGUuPELOtKQyaO3+y4 MaRCQUfr84Z9GrUDTR8PefqV6J3hcO6EvyPuIHnM4kQ/EBZ3dAcstzK4M+e53Xgr53Lp IrvGWe6r6ogHUcHwHP/ZVh+jzKjvPBf5qAxw3q4YEPx/02Iv5fXpCl5Ox7e+wtKEf2vp 4G3YgYW5nwQNobgKPNQp2dCZNxbKZ/B5ftCqu1ILSKMPhGTulFFICgxmhJY5nFzRqwHG K/1Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1678116779; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=hS/BEmRpdBxk7z2vn4cP+VagM+gkHpiXxJLmHI41D7s=; b=4fPd9gtOAChFXPjvY2Yk8ozltHZd9sQpdk1Yt0RZ2MUm4qneDTYAlnx4O4oeUcDufJ gfjntjmF5VuvcT1bDA1TyqVEbVxvQqoKdCxoaX5ALiW/syhMlP61HZpotd0Pi5YfXkJ8 7ly9k5p7ecU4rmoOP2t5OcSmtfZ61QCSOZUFkmUVu7abbzuSSf+pE++vvd2bvuToxEY1 YUinOl05zvciA4qicKG5MYmIFOJIOddjbPcdHJ1CZXLknuajqfkagEM+zECvA7ZiW+Vv O9hhnE0TQljHQ9atgOXaTymMc/UAM4RifIWHoCJwd00W/Xp1zyVnm0mFVox/XXAEblqo JxLQ== X-Gm-Message-State: AO0yUKX+Dm1bAarJkBNmrZJ9HBtaGAitnWLHTCGCG3O+Gddd0v9jkOm9 ykdQ4HUIVxj96zu1SqzWLA4A X-Google-Smtp-Source: AK7set8sZfp6sQ6SgvwCNPs1Q+4jgzTymMOqILCjziXLWGsQI7/n5c/oVmkuG35voAzHWkcbvG1YMw== X-Received: by 2002:a17:903:22d2:b0:199:12d5:5b97 with SMTP id y18-20020a17090322d200b0019912d55b97mr15960253plg.12.1678116779431; Mon, 06 Mar 2023 07:32:59 -0800 (PST) Received: from localhost.localdomain ([59.97.52.140]) by smtp.gmail.com with ESMTPSA id kl4-20020a170903074400b0019a7c890c61sm6837430plb.252.2023.03.06.07.32.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 06 Mar 2023 07:32:58 -0800 (PST) From: Manivannan Sadhasivam To: andersson@kernel.org, lpieralisi@kernel.org, kw@linux.com, krzysztof.kozlowski+dt@linaro.org, robh@kernel.org Cc: konrad.dybcio@linaro.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, quic_srichara@quicinc.com, Manivannan Sadhasivam Subject: [PATCH 05/19] PCI: qcom: Use lower case for hex Date: Mon, 6 Mar 2023 21:02:08 +0530 Message-Id: <20230306153222.157667-6-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230306153222.157667-1-manivannan.sadhasivam@linaro.org> References: <20230306153222.157667-1-manivannan.sadhasivam@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" To maintain uniformity, let's use lower case for representing hexadecimal numbers. Signed-off-by: Manivannan Sadhasivam --- drivers/pci/controller/dwc/pcie-qcom.c | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controlle= r/dwc/pcie-qcom.c index 926a531fda3a..4179ac973147 100644 --- a/drivers/pci/controller/dwc/pcie-qcom.c +++ b/drivers/pci/controller/dwc/pcie-qcom.c @@ -39,17 +39,17 @@ #define PARF_PCS_DEEMPH 0x34 #define PARF_PCS_SWING 0x38 #define PARF_PHY_CTRL 0x40 -#define PARF_PHY_REFCLK 0x4C +#define PARF_PHY_REFCLK 0x4c #define PARF_CONFIG_BITS 0x50 #define PARF_DBI_BASE_ADDR 0x168 -#define PARF_SLV_ADDR_SPACE_SIZE_2_3_3 0x16C /* Register offset specific = to IP ver 2.3.3 */ +#define PARF_SLV_ADDR_SPACE_SIZE_2_3_3 0x16c /* Register offset specific = to IP ver 2.3.3 */ #define PARF_MHI_CLOCK_RESET_CTRL 0x174 #define PARF_AXI_MSTR_WR_ADDR_HALT 0x178 -#define PARF_AXI_MSTR_WR_ADDR_HALT_V2 0x1A8 -#define PARF_Q2A_FLUSH 0x1AC -#define PARF_LTSSM 0x1B0 +#define PARF_AXI_MSTR_WR_ADDR_HALT_V2 0x1a8 +#define PARF_Q2A_FLUSH 0x1ac +#define PARF_LTSSM 0x1b0 #define PARF_SID_OFFSET 0x234 -#define PARF_BDF_TRANSLATE_CFG 0x24C +#define PARF_BDF_TRANSLATE_CFG 0x24c #define PARF_SLV_ADDR_SPACE_SIZE 0x358 #define PARF_DEVICE_TYPE 0x1000 #define PARF_BDF_TO_SID_TABLE_N 0x2000 @@ -60,7 +60,7 @@ /* DBI registers */ #define AXI_MSTR_RESP_COMP_CTRL0 0x818 #define AXI_MSTR_RESP_COMP_CTRL1 0x81c -#define MISC_CONTROL_1_REG 0x8BC +#define MISC_CONTROL_1_REG 0x8bc =20 /* PARF_SYS_CTRL register fields */ #define MAC_PHY_POWERDOWN_IN_P2_D_MUX_EN BIT(29) --=20 2.25.1 From nobody Sat Apr 11 11:48:14 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 68829C64EC4 for ; Mon, 6 Mar 2023 15:34:05 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230227AbjCFPeD (ORCPT ); Mon, 6 Mar 2023 10:34:03 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:59908 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230380AbjCFPdq (ORCPT ); Mon, 6 Mar 2023 10:33:46 -0500 Received: from mail-pl1-x635.google.com (mail-pl1-x635.google.com [IPv6:2607:f8b0:4864:20::635]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id A008B32CC5 for ; Mon, 6 Mar 2023 07:33:12 -0800 (PST) Received: by mail-pl1-x635.google.com with SMTP id i10so10756712plr.9 for ; Mon, 06 Mar 2023 07:33:12 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1678116783; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=UJ4Ik+ZoB8puIUL4lEznFsK6NoJYzy77sft3aaSqBZo=; b=DL/hWjcip5WwJihBQjlGRTyZlqBoBlVO70mke6sPwAFBexxy0QGwmm2ijXriVql0oe TRVvfCp4t/xUO3qKZi8uh3VWBeZIITWyeHunerFBBr1gYlHI26R/e9WWDliuowslxNQh 6HdVnWrJA5XzwQUv3ISLrX3BxakQeZ0VBSeqXU9e7z58KrH/Aw+NltpoJ1RAxxzc0ns7 fN7Haa9QrqK9nhLpkpQhcaJ9WXYMGWJ9RMuT3Kwg6oViI1O3JJ465NMXo67heZTvWV66 HHqFeb22MWOpiesOEOHfbQ5f8g9+ONjRxSHaoaIUrlUbetYI22R/SQlqfTAFz84Jx6YL 92Og== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1678116783; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=UJ4Ik+ZoB8puIUL4lEznFsK6NoJYzy77sft3aaSqBZo=; b=gTCw4zg7vVhjczxx8paS8i7zCaeTd3lXk5xxxU69IjolgJ/NwAST3cm+A46dh2GCEn r8MS3/oAwQK1XnstJpmQnOUrXNAVcqFrvzKmJReVskBNOUNGZ5YC5tafy7ZMAcPeMxfa j9/Tfd4G+9Z9kFIbUZ3iRZNfroUfNm5Mfqh8ddXbx3h5whOn79nSWqFMbIYIgs8T92AD +blt1PmrXs1t3qYI0nu6qQItPl8rTs6C0byBkvIDC6kucprCA9uQkbmzSn9U07To5zwE STm520VeABQZM8DBHrkv16jpb4udZ8wmgIEuav/kGEvV9xErfVvAtbKiAhbkkXsmSddK Xypw== X-Gm-Message-State: AO0yUKXp6JeXWlqGtK/5A1eROGy55LY+Rd+VR1PjAMZFIkOW3cpfSvi1 SUN7BPU0MHGcy0E5yUQhDEaM X-Google-Smtp-Source: AK7set871MSWRLqqkyk9FYiJLBPTaygut8yRIHWpaPH8i7gzVxJsAqzV7/Ph7Yw86EW7lF47DB5VGQ== X-Received: by 2002:a17:902:ec8a:b0:19d:138b:7c4a with SMTP id x10-20020a170902ec8a00b0019d138b7c4amr13600090plg.3.1678116783618; Mon, 06 Mar 2023 07:33:03 -0800 (PST) Received: from localhost.localdomain ([59.97.52.140]) by smtp.gmail.com with ESMTPSA id kl4-20020a170903074400b0019a7c890c61sm6837430plb.252.2023.03.06.07.32.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 06 Mar 2023 07:33:03 -0800 (PST) From: Manivannan Sadhasivam To: andersson@kernel.org, lpieralisi@kernel.org, kw@linux.com, krzysztof.kozlowski+dt@linaro.org, robh@kernel.org Cc: konrad.dybcio@linaro.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, quic_srichara@quicinc.com, Manivannan Sadhasivam Subject: [PATCH 06/19] PCI: qcom: Use bulk reset APIs for handling resets for IP rev 2.1.0 Date: Mon, 6 Mar 2023 21:02:09 +0530 Message-Id: <20230306153222.157667-7-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230306153222.157667-1-manivannan.sadhasivam@linaro.org> References: <20230306153222.157667-1-manivannan.sadhasivam@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" All the resets are asserted and deasserted at the same time. So the bulk reset APIs can be used to handle them together. This simplifies the code a lot. While at it, let's also move the qcom_pcie_resources_2_1_0 struct below qcom_pcie_resources_1_0_0 to keep it sorted. Signed-off-by: Manivannan Sadhasivam --- drivers/pci/controller/dwc/pcie-qcom.c | 129 +++++++------------------ 1 file changed, 34 insertions(+), 95 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controlle= r/dwc/pcie-qcom.c index 4179ac973147..2d9116464842 100644 --- a/drivers/pci/controller/dwc/pcie-qcom.c +++ b/drivers/pci/controller/dwc/pcie-qcom.c @@ -143,22 +143,8 @@ =20 #define PERST_DELAY_US 1000 =20 -#define QCOM_PCIE_2_1_0_MAX_SUPPLY 3 -#define QCOM_PCIE_2_1_0_MAX_CLOCKS 5 - #define QCOM_PCIE_CRC8_POLYNOMIAL (BIT(2) | BIT(1) | BIT(0)) =20 -struct qcom_pcie_resources_2_1_0 { - struct clk_bulk_data clks[QCOM_PCIE_2_1_0_MAX_CLOCKS]; - struct reset_control *pci_reset; - struct reset_control *axi_reset; - struct reset_control *ahb_reset; - struct reset_control *por_reset; - struct reset_control *phy_reset; - struct reset_control *ext_reset; - struct regulator_bulk_data supplies[QCOM_PCIE_2_1_0_MAX_SUPPLY]; -}; - struct qcom_pcie_resources_1_0_0 { struct clk *iface; struct clk *aux; @@ -168,6 +154,16 @@ struct qcom_pcie_resources_1_0_0 { struct regulator *vdda; }; =20 +#define QCOM_PCIE_2_1_0_MAX_CLOCKS 5 +#define QCOM_PCIE_2_1_0_MAX_RESETS 6 +#define QCOM_PCIE_2_1_0_MAX_SUPPLY 3 +struct qcom_pcie_resources_2_1_0 { + struct clk_bulk_data clks[QCOM_PCIE_2_1_0_MAX_CLOCKS]; + struct reset_control_bulk_data resets[QCOM_PCIE_2_1_0_MAX_RESETS]; + int num_resets; + struct regulator_bulk_data supplies[QCOM_PCIE_2_1_0_MAX_SUPPLY]; +}; + #define QCOM_PCIE_2_3_2_MAX_SUPPLY 2 struct qcom_pcie_resources_2_3_2 { struct clk *aux_clk; @@ -295,6 +291,7 @@ static int qcom_pcie_get_resources_2_1_0(struct qcom_pc= ie *pcie) struct qcom_pcie_resources_2_1_0 *res =3D &pcie->res.v2_1_0; struct dw_pcie *pci =3D pcie->pci; struct device *dev =3D pci->dev; + bool is_apq =3D of_device_is_compatible(dev->of_node, "qcom,pcie-apq8064"= ); int ret; =20 res->supplies[0].supply =3D "vdda"; @@ -321,28 +318,20 @@ static int qcom_pcie_get_resources_2_1_0(struct qcom_= pcie *pcie) if (ret < 0) return ret; =20 - res->pci_reset =3D devm_reset_control_get_exclusive(dev, "pci"); - if (IS_ERR(res->pci_reset)) - return PTR_ERR(res->pci_reset); - - res->axi_reset =3D devm_reset_control_get_exclusive(dev, "axi"); - if (IS_ERR(res->axi_reset)) - return PTR_ERR(res->axi_reset); - - res->ahb_reset =3D devm_reset_control_get_exclusive(dev, "ahb"); - if (IS_ERR(res->ahb_reset)) - return PTR_ERR(res->ahb_reset); + res->resets[0].id =3D "pci"; + res->resets[1].id =3D "axi"; + res->resets[2].id =3D "ahb"; + res->resets[3].id =3D "por"; + res->resets[4].id =3D "phy"; + res->resets[5].id =3D "ext"; =20 - res->por_reset =3D devm_reset_control_get_exclusive(dev, "por"); - if (IS_ERR(res->por_reset)) - return PTR_ERR(res->por_reset); - - res->ext_reset =3D devm_reset_control_get_optional_exclusive(dev, "ext"); - if (IS_ERR(res->ext_reset)) - return PTR_ERR(res->ext_reset); + /* ext is optional on APQ8016 */ + res->num_resets =3D is_apq ? 5 : 6; + ret =3D devm_reset_control_bulk_get_exclusive(dev, res->num_resets, res->= resets); + if (ret < 0) + return ret; =20 - res->phy_reset =3D devm_reset_control_get_exclusive(dev, "phy"); - return PTR_ERR_OR_ZERO(res->phy_reset); + return 0; } =20 static void qcom_pcie_deinit_2_1_0(struct qcom_pcie *pcie) @@ -350,12 +339,7 @@ static void qcom_pcie_deinit_2_1_0(struct qcom_pcie *p= cie) struct qcom_pcie_resources_2_1_0 *res =3D &pcie->res.v2_1_0; =20 clk_bulk_disable_unprepare(ARRAY_SIZE(res->clks), res->clks); - reset_control_assert(res->pci_reset); - reset_control_assert(res->axi_reset); - reset_control_assert(res->ahb_reset); - reset_control_assert(res->por_reset); - reset_control_assert(res->ext_reset); - reset_control_assert(res->phy_reset); + reset_control_bulk_assert(res->num_resets, res->resets); =20 writel(1, pcie->parf + PARF_PHY_CTRL); =20 @@ -370,12 +354,11 @@ static int qcom_pcie_init_2_1_0(struct qcom_pcie *pci= e) int ret; =20 /* reset the PCIe interface as uboot can leave it undefined state */ - reset_control_assert(res->pci_reset); - reset_control_assert(res->axi_reset); - reset_control_assert(res->ahb_reset); - reset_control_assert(res->por_reset); - reset_control_assert(res->ext_reset); - reset_control_assert(res->phy_reset); + ret =3D reset_control_bulk_assert(res->num_resets, res->resets); + if (ret < 0) { + dev_err(dev, "cannot assert resets\n"); + return ret; + } =20 ret =3D regulator_bulk_enable(ARRAY_SIZE(res->supplies), res->supplies); if (ret < 0) { @@ -383,58 +366,14 @@ static int qcom_pcie_init_2_1_0(struct qcom_pcie *pci= e) return ret; } =20 - ret =3D reset_control_deassert(res->ahb_reset); - if (ret) { - dev_err(dev, "cannot deassert ahb reset\n"); - goto err_deassert_ahb; - } - - ret =3D reset_control_deassert(res->ext_reset); - if (ret) { - dev_err(dev, "cannot deassert ext reset\n"); - goto err_deassert_ext; - } - - ret =3D reset_control_deassert(res->phy_reset); - if (ret) { - dev_err(dev, "cannot deassert phy reset\n"); - goto err_deassert_phy; - } - - ret =3D reset_control_deassert(res->pci_reset); - if (ret) { - dev_err(dev, "cannot deassert pci reset\n"); - goto err_deassert_pci; - } - - ret =3D reset_control_deassert(res->por_reset); - if (ret) { - dev_err(dev, "cannot deassert por reset\n"); - goto err_deassert_por; - } - - ret =3D reset_control_deassert(res->axi_reset); - if (ret) { - dev_err(dev, "cannot deassert axi reset\n"); - goto err_deassert_axi; + ret =3D reset_control_bulk_deassert(res->num_resets, res->resets); + if (ret < 0) { + dev_err(dev, "cannot deassert resets\n"); + regulator_bulk_disable(ARRAY_SIZE(res->supplies), res->supplies); + return ret; } =20 return 0; - -err_deassert_axi: - reset_control_assert(res->por_reset); -err_deassert_por: - reset_control_assert(res->pci_reset); -err_deassert_pci: - reset_control_assert(res->phy_reset); -err_deassert_phy: - reset_control_assert(res->ext_reset); -err_deassert_ext: - reset_control_assert(res->ahb_reset); -err_deassert_ahb: - regulator_bulk_disable(ARRAY_SIZE(res->supplies), res->supplies); - - return ret; } =20 static int qcom_pcie_post_init_2_1_0(struct qcom_pcie *pcie) --=20 2.25.1 From nobody Sat Apr 11 11:48:14 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id A0B39C61DA4 for ; Mon, 6 Mar 2023 15:34:08 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230269AbjCFPeG (ORCPT ); Mon, 6 Mar 2023 10:34:06 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:59986 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229956AbjCFPds (ORCPT ); Mon, 6 Mar 2023 10:33:48 -0500 Received: from mail-pl1-x630.google.com (mail-pl1-x630.google.com [IPv6:2607:f8b0:4864:20::630]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id D624F32CF0 for ; Mon, 6 Mar 2023 07:33:19 -0800 (PST) Received: by mail-pl1-x630.google.com with SMTP id i3so10770720plg.6 for ; Mon, 06 Mar 2023 07:33:19 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1678116787; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=TSFkykYkB7c0gJwp2FwEg/ye5mEGILHD2HLR3ehwkBA=; b=U/e5DPkCAYc4DuIEzHJ4wKn48NyjWuspnRDAACIdrkqBBCIJ+3Ri1zhsw4oq5A1MY8 0v9BA0mJCY9WHhdqHCMXwo6tzQdtdlr063WhCJtBRwbJkXNIKVqxTUbh4+q45ZpUbvlP 6YBulhq3ADWyOqLni2op+AZ8wgjTZOObt694BYQq42NYPuR/N+Jh1cup9Or7VpjEYvF7 ioMYkNX7jFBg8lo7VMzD+8PG+SQdLR4pUxmieRL6IBNrpBVu7n5qAg6EIdwmCX6b+ETe TrdRivU4HxzPJ8s8nWg4CYX97a8cPTxpm0ALQvf8hRyI5dc+hHAfFBTCda8Ykc/kNjs3 QHbQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1678116787; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=TSFkykYkB7c0gJwp2FwEg/ye5mEGILHD2HLR3ehwkBA=; b=B357ueDxCUxe00o2GjqK3NnMsXF5RNWaCQrO8PJN6hE8XAM12bRjoR+ap0zb9EuZ3Y R0ov7uIlrniFTjoXFP89EeMY+j9RLTwL0rOBBx/APFCnfzsnSBqKLV2Gfi0UblAYRoWF kFReDisHWj0I2RuwMpnRZn/X9S2dVpgDMz2CjJhFo3m+oDRy4FlkxzY2EGsFBoc1u3Jq iFLI4wm3cpxX1px1Bfq/zx6OfNM4rlp3OMVnaeJAia2+6zJa1B+rKMs/tlyRf2VkBpLy 4CNchmJ1Tc3hlzzcdCW3g5/q1ugVfcYFW9XVMVsVnt68GkR8l7nVaAuIFa23Pz9zhRzx pllA== X-Gm-Message-State: AO0yUKW8pC9rw5I56lXt+NfFbLGAF5UOYY3jLBTqTP7fW+ayhxZeZ+hK afGHh1kemAZcSPHD81SE+zWX X-Google-Smtp-Source: AK7set+SJexBj2I4zW3bW+Ce+dM0uLswlSa/jNuGobvj1GZ69Lt2UJdV5gLpBBWFK8BgCLIJEwt90g== X-Received: by 2002:a17:902:ec88:b0:19a:e762:a1af with SMTP id x8-20020a170902ec8800b0019ae762a1afmr14320778plg.33.1678116787552; Mon, 06 Mar 2023 07:33:07 -0800 (PST) Received: from localhost.localdomain ([59.97.52.140]) by smtp.gmail.com with ESMTPSA id kl4-20020a170903074400b0019a7c890c61sm6837430plb.252.2023.03.06.07.33.03 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 06 Mar 2023 07:33:07 -0800 (PST) From: Manivannan Sadhasivam To: andersson@kernel.org, lpieralisi@kernel.org, kw@linux.com, krzysztof.kozlowski+dt@linaro.org, robh@kernel.org Cc: konrad.dybcio@linaro.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, quic_srichara@quicinc.com, Manivannan Sadhasivam Subject: [PATCH 07/19] PCI: qcom: Use bulk clock APIs for handling clocks for IP rev 1.0.0 Date: Mon, 6 Mar 2023 21:02:10 +0530 Message-Id: <20230306153222.157667-8-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230306153222.157667-1-manivannan.sadhasivam@linaro.org> References: <20230306153222.157667-1-manivannan.sadhasivam@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" All the clocks are enabled and disabled at the same time. So the bulk clock APIs can be used to handle them together. This simplifies the code a lot. Signed-off-by: Manivannan Sadhasivam --- drivers/pci/controller/dwc/pcie-qcom.c | 72 +++++++------------------- 1 file changed, 19 insertions(+), 53 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controlle= r/dwc/pcie-qcom.c index 2d9116464842..0bb27d3c95a0 100644 --- a/drivers/pci/controller/dwc/pcie-qcom.c +++ b/drivers/pci/controller/dwc/pcie-qcom.c @@ -145,11 +145,9 @@ =20 #define QCOM_PCIE_CRC8_POLYNOMIAL (BIT(2) | BIT(1) | BIT(0)) =20 +#define QCOM_PCIE_1_0_0_MAX_CLOCKS 4 struct qcom_pcie_resources_1_0_0 { - struct clk *iface; - struct clk *aux; - struct clk *master_bus; - struct clk *slave_bus; + struct clk_bulk_data clks[QCOM_PCIE_1_0_0_MAX_CLOCKS]; struct reset_control *core; struct regulator *vdda; }; @@ -439,26 +437,20 @@ static int qcom_pcie_get_resources_1_0_0(struct qcom_= pcie *pcie) struct qcom_pcie_resources_1_0_0 *res =3D &pcie->res.v1_0_0; struct dw_pcie *pci =3D pcie->pci; struct device *dev =3D pci->dev; + int ret; =20 res->vdda =3D devm_regulator_get(dev, "vdda"); if (IS_ERR(res->vdda)) return PTR_ERR(res->vdda); =20 - res->iface =3D devm_clk_get(dev, "iface"); - if (IS_ERR(res->iface)) - return PTR_ERR(res->iface); - - res->aux =3D devm_clk_get(dev, "aux"); - if (IS_ERR(res->aux)) - return PTR_ERR(res->aux); - - res->master_bus =3D devm_clk_get(dev, "master_bus"); - if (IS_ERR(res->master_bus)) - return PTR_ERR(res->master_bus); + res->clks[0].id =3D "iface"; + res->clks[1].id =3D "aux"; + res->clks[2].id =3D "master_bus"; + res->clks[3].id =3D "slave_bus"; =20 - res->slave_bus =3D devm_clk_get(dev, "slave_bus"); - if (IS_ERR(res->slave_bus)) - return PTR_ERR(res->slave_bus); + ret =3D devm_clk_bulk_get(dev, ARRAY_SIZE(res->clks), res->clks); + if (ret < 0) + return ret; =20 res->core =3D devm_reset_control_get_exclusive(dev, "core"); return PTR_ERR_OR_ZERO(res->core); @@ -469,10 +461,7 @@ static void qcom_pcie_deinit_1_0_0(struct qcom_pcie *p= cie) struct qcom_pcie_resources_1_0_0 *res =3D &pcie->res.v1_0_0; =20 reset_control_assert(res->core); - clk_disable_unprepare(res->slave_bus); - clk_disable_unprepare(res->master_bus); - clk_disable_unprepare(res->iface); - clk_disable_unprepare(res->aux); + clk_bulk_disable_unprepare(ARRAY_SIZE(res->clks), res->clks); regulator_disable(res->vdda); } =20 @@ -489,46 +478,23 @@ static int qcom_pcie_init_1_0_0(struct qcom_pcie *pci= e) return ret; } =20 - ret =3D clk_prepare_enable(res->aux); - if (ret) { - dev_err(dev, "cannot prepare/enable aux clock\n"); - goto err_res; - } - - ret =3D clk_prepare_enable(res->iface); - if (ret) { - dev_err(dev, "cannot prepare/enable iface clock\n"); - goto err_aux; - } - - ret =3D clk_prepare_enable(res->master_bus); - if (ret) { - dev_err(dev, "cannot prepare/enable master_bus clock\n"); - goto err_iface; - } - - ret =3D clk_prepare_enable(res->slave_bus); + ret =3D clk_bulk_prepare_enable(ARRAY_SIZE(res->clks), res->clks); if (ret) { - dev_err(dev, "cannot prepare/enable slave_bus clock\n"); - goto err_master; + dev_err(dev, "cannot prepare/enable clocks\n"); + goto err_assert_reset; } =20 ret =3D regulator_enable(res->vdda); if (ret) { dev_err(dev, "cannot enable vdda regulator\n"); - goto err_slave; + goto err_disable_clks; } =20 return 0; -err_slave: - clk_disable_unprepare(res->slave_bus); -err_master: - clk_disable_unprepare(res->master_bus); -err_iface: - clk_disable_unprepare(res->iface); -err_aux: - clk_disable_unprepare(res->aux); -err_res: + +err_disable_clks: + clk_bulk_disable_unprepare(ARRAY_SIZE(res->clks), res->clks); +err_assert_reset: reset_control_assert(res->core); =20 return ret; --=20 2.25.1 From nobody Sat Apr 11 11:48:14 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id BEA4BC61DA4 for ; Mon, 6 Mar 2023 15:34:14 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230391AbjCFPeM (ORCPT ); Mon, 6 Mar 2023 10:34:12 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:60002 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230272AbjCFPeH (ORCPT ); Mon, 6 Mar 2023 10:34:07 -0500 Received: from mail-pl1-x62e.google.com (mail-pl1-x62e.google.com [IPv6:2607:f8b0:4864:20::62e]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 506CA34022 for ; Mon, 6 Mar 2023 07:33:24 -0800 (PST) Received: by mail-pl1-x62e.google.com with SMTP id u5so10762341plq.7 for ; Mon, 06 Mar 2023 07:33:24 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1678116792; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=amLlMnvqqV/ACQXsqFtaJlfI0hCQH92ixpD+YcVSgsE=; b=GeZbKJur8/ECXVMvdE/iCuGPL98R+cQgfcpYGzyP8oeC6QEOMrgXyTo+o4C3i09BlS VoKSAFHbnQtpmsMrVreMCBpcS9vLYeriUd4wSxUV/XKKWm33rFSe2R2ikj462OPO/MPJ W0e+X+XJJ6yHcWmLg4eOyREhQgUInFGBKYoT3MbU0GWj//GwEE4XUD5TqPLoJ9xcHGeZ noG8oWTtx3jVS7PycN0HLI/zwD1xvat2l+t1wwfH6d9zAH8yeClzepTm0+wOotsUXt5B Wog8AzTZWW+/PoQDcPcJhhRkz3m1zelEXISHWJ2yxP8az5FBWIOrdjMVuoWwD4vR/6QK /kWg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1678116792; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=amLlMnvqqV/ACQXsqFtaJlfI0hCQH92ixpD+YcVSgsE=; b=WovQ9B7A3X+aXHY0N0s7K/a0Mu7xN0lmDi5DyOpKB9e/2UUf7kAG4sGo7L8I1uPqAi AEekKb02I671LemrQcoV+7V2YPqJkWmFI6GsII6HLlK7zzcsH3wUEukaolw2Y2cCTrM7 ukCRUXIsLUaaUtX/CE3HgFZMt+bIhy2pQ3CknD5X0ZouALpWZ+PHnUFq0o4YPkob2KMQ MZ2011TUvziLeOXAerVb7FgI1cNHYsY2dIRXY5BixEVu5L5lUrIcsB8nyIksMU0s8yla zHLh3qm+9TxnFXDPVPsMHquskIETqLRhGlE1SCIRc+M6YRY2bsglelTte9UpDnTtvRRn BFhw== X-Gm-Message-State: AO0yUKWLgnnXzRl5bOjui+Z5Y2S19HfGDu8q2E+leVgC/sWgnt+y1pBb wGFENhOtoxUhI4ePcHj5F6LX X-Google-Smtp-Source: AK7set+YIQGecqYbNVKVz5rM05gFtbtQRV5Tx9YLSB/WUz9Mz8gZwHtks67MdFSBYvBczOL9NMdexg== X-Received: by 2002:a17:903:228b:b0:19c:bae2:681a with SMTP id b11-20020a170903228b00b0019cbae2681amr11872205plh.66.1678116791770; Mon, 06 Mar 2023 07:33:11 -0800 (PST) Received: from localhost.localdomain ([59.97.52.140]) by smtp.gmail.com with ESMTPSA id kl4-20020a170903074400b0019a7c890c61sm6837430plb.252.2023.03.06.07.33.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 06 Mar 2023 07:33:11 -0800 (PST) From: Manivannan Sadhasivam To: andersson@kernel.org, lpieralisi@kernel.org, kw@linux.com, krzysztof.kozlowski+dt@linaro.org, robh@kernel.org Cc: konrad.dybcio@linaro.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, quic_srichara@quicinc.com, Manivannan Sadhasivam Subject: [PATCH 08/19] PCI: qcom: Use bulk clock APIs for handling clocks for IP rev 2.3.2 Date: Mon, 6 Mar 2023 21:02:11 +0530 Message-Id: <20230306153222.157667-9-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230306153222.157667-1-manivannan.sadhasivam@linaro.org> References: <20230306153222.157667-1-manivannan.sadhasivam@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" All the clocks are enabled and disabled at the same time. So the bulk clock APIs can be used to handle them together. This simplifies the code a lot. Signed-off-by: Manivannan Sadhasivam --- drivers/pci/controller/dwc/pcie-qcom.c | 72 ++++++-------------------- 1 file changed, 15 insertions(+), 57 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controlle= r/dwc/pcie-qcom.c index 0bb27d3c95a0..939973733a1e 100644 --- a/drivers/pci/controller/dwc/pcie-qcom.c +++ b/drivers/pci/controller/dwc/pcie-qcom.c @@ -162,12 +162,10 @@ struct qcom_pcie_resources_2_1_0 { struct regulator_bulk_data supplies[QCOM_PCIE_2_1_0_MAX_SUPPLY]; }; =20 -#define QCOM_PCIE_2_3_2_MAX_SUPPLY 2 +#define QCOM_PCIE_2_3_2_MAX_CLOCKS 4 +#define QCOM_PCIE_2_3_2_MAX_SUPPLY 2 struct qcom_pcie_resources_2_3_2 { - struct clk *aux_clk; - struct clk *master_clk; - struct clk *slave_clk; - struct clk *cfg_clk; + struct clk_bulk_data clks[QCOM_PCIE_2_3_2_MAX_CLOCKS]; struct regulator_bulk_data supplies[QCOM_PCIE_2_3_2_MAX_SUPPLY]; }; =20 @@ -539,21 +537,14 @@ static int qcom_pcie_get_resources_2_3_2(struct qcom_= pcie *pcie) if (ret) return ret; =20 - res->aux_clk =3D devm_clk_get(dev, "aux"); - if (IS_ERR(res->aux_clk)) - return PTR_ERR(res->aux_clk); - - res->cfg_clk =3D devm_clk_get(dev, "cfg"); - if (IS_ERR(res->cfg_clk)) - return PTR_ERR(res->cfg_clk); - - res->master_clk =3D devm_clk_get(dev, "bus_master"); - if (IS_ERR(res->master_clk)) - return PTR_ERR(res->master_clk); + res->clks[0].id =3D "aux"; + res->clks[1].id =3D "cfg"; + res->clks[2].id =3D "bus_master"; + res->clks[3].id =3D "bus_slave"; =20 - res->slave_clk =3D devm_clk_get(dev, "bus_slave"); - if (IS_ERR(res->slave_clk)) - return PTR_ERR(res->slave_clk); + ret =3D devm_clk_bulk_get(dev, ARRAY_SIZE(res->clks), res->clks); + if (ret < 0) + return ret; =20 return 0; } @@ -562,11 +553,7 @@ static void qcom_pcie_deinit_2_3_2(struct qcom_pcie *p= cie) { struct qcom_pcie_resources_2_3_2 *res =3D &pcie->res.v2_3_2; =20 - clk_disable_unprepare(res->slave_clk); - clk_disable_unprepare(res->master_clk); - clk_disable_unprepare(res->cfg_clk); - clk_disable_unprepare(res->aux_clk); - + clk_bulk_disable_unprepare(ARRAY_SIZE(res->clks), res->clks); regulator_bulk_disable(ARRAY_SIZE(res->supplies), res->supplies); } =20 @@ -583,43 +570,14 @@ static int qcom_pcie_init_2_3_2(struct qcom_pcie *pci= e) return ret; } =20 - ret =3D clk_prepare_enable(res->aux_clk); - if (ret) { - dev_err(dev, "cannot prepare/enable aux clock\n"); - goto err_aux_clk; - } - - ret =3D clk_prepare_enable(res->cfg_clk); - if (ret) { - dev_err(dev, "cannot prepare/enable cfg clock\n"); - goto err_cfg_clk; - } - - ret =3D clk_prepare_enable(res->master_clk); - if (ret) { - dev_err(dev, "cannot prepare/enable master clock\n"); - goto err_master_clk; - } - - ret =3D clk_prepare_enable(res->slave_clk); + ret =3D clk_bulk_prepare_enable(ARRAY_SIZE(res->clks), res->clks); if (ret) { - dev_err(dev, "cannot prepare/enable slave clock\n"); - goto err_slave_clk; + dev_err(dev, "cannot prepare/enable clocks\n"); + regulator_bulk_disable(ARRAY_SIZE(res->supplies), res->supplies); + return ret; } =20 return 0; - -err_slave_clk: - clk_disable_unprepare(res->master_clk); -err_master_clk: - clk_disable_unprepare(res->cfg_clk); -err_cfg_clk: - clk_disable_unprepare(res->aux_clk); - -err_aux_clk: - regulator_bulk_disable(ARRAY_SIZE(res->supplies), res->supplies); - - return ret; } =20 static int qcom_pcie_post_init_2_3_2(struct qcom_pcie *pcie) --=20 2.25.1 From nobody Sat Apr 11 11:48:14 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 11604C6FA99 for ; Mon, 6 Mar 2023 15:34:22 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230500AbjCFPeU (ORCPT ); Mon, 6 Mar 2023 10:34:20 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:60686 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230274AbjCFPeH (ORCPT ); Mon, 6 Mar 2023 10:34:07 -0500 Received: from mail-pj1-x1035.google.com (mail-pj1-x1035.google.com [IPv6:2607:f8b0:4864:20::1035]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 0198934C0B for ; Mon, 6 Mar 2023 07:33:24 -0800 (PST) Received: by mail-pj1-x1035.google.com with SMTP id h11-20020a17090a2ecb00b00237c740335cso9145312pjs.3 for ; Mon, 06 Mar 2023 07:33:24 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1678116796; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=HLaHkNbeR3pTSpm3EckvQkVoLPurUbKikH/yYKtcjD0=; b=thnWH9V+PUlOUgjdtGqI99SmuYfo4Yz63ZHz0BFPBNPEV/bIUh/hIRX/iNVaz4ryVX TkGOanFhVf12pylEudeQNgzqlK1LdHLuvO0x4AhPbRL//L81mUowTCRMKkCyrV/plp4K 6K/a5Ppt0f3gPoSQAHpBe6xNsr5ZW+OUXCq5s+QRqzAUc8L5b8xzMdu6WSUc/uZmYBGf rJ3KWI4LCSQtfQQzQs9ZPJa/W+7SX/aIkCnrO9yqiCZkHF2CInJga1Gk+RIJHKHBc/TC 2wJ+OcYVRKV8dGhQzK78q1xTWjvmcLoO62umVvWboX2pThM+HmLsYkN2/bx0CnyJHB7S r0CA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1678116796; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=HLaHkNbeR3pTSpm3EckvQkVoLPurUbKikH/yYKtcjD0=; b=gVBrONIZ7sEVxhgGg7TNu4nK8RqbP/D2/4A4mjGtr4hRceh4yONOv9SToMDkj+Iqub Q1UiZ5/3adobuasc510N6oX4z4HsH5KgJ5ffrSSd92oCn1nGgynvI0H0oV7ThPtMIMei xizjoj+/+KFvESxfVxWbdjp69Bsn5Fv/59u0Lexmseqb9u4+PxhACBAGgupkeWjhXfcx +DJU40zGelyCXvso50rH+R6OCdZnOCWxkkQZnRUDZmXoQUCR89ekJPkdNrfXZTVM0VIM C73xwfnxNyY8EPAu3fJTR4+3mTIq5lRsWNAZXqnnmBWp5w/suDCGiObmXjuKXJuYGItn 2v4g== X-Gm-Message-State: AO0yUKWZkM0IRmdwFqrRIhAB55rUwY9SwJ4jeGnHNWrURrgWRlJdSXlc 6Evs3+NgijbLuSPo3/O0EPjs X-Google-Smtp-Source: AK7set8zmFEsZnK4AI9bdbHTvMbp2MgLVAQPYAHKGXs8ZD8mvu/1dBBvZt8F+IdanvlQP0r8ulzHyg== X-Received: by 2002:a17:902:e80f:b0:19e:747e:813e with SMTP id u15-20020a170902e80f00b0019e747e813emr12933698plg.23.1678116796557; Mon, 06 Mar 2023 07:33:16 -0800 (PST) Received: from localhost.localdomain ([59.97.52.140]) by smtp.gmail.com with ESMTPSA id kl4-20020a170903074400b0019a7c890c61sm6837430plb.252.2023.03.06.07.33.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 06 Mar 2023 07:33:16 -0800 (PST) From: Manivannan Sadhasivam To: andersson@kernel.org, lpieralisi@kernel.org, kw@linux.com, krzysztof.kozlowski+dt@linaro.org, robh@kernel.org Cc: konrad.dybcio@linaro.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, quic_srichara@quicinc.com, Manivannan Sadhasivam Subject: [PATCH 09/19] PCI: qcom: Use bulk clock APIs for handling clocks for IP rev 2.3.3 Date: Mon, 6 Mar 2023 21:02:12 +0530 Message-Id: <20230306153222.157667-10-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230306153222.157667-1-manivannan.sadhasivam@linaro.org> References: <20230306153222.157667-1-manivannan.sadhasivam@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" All the clocks are enabled and disabled at the same time. So the bulk clock APIs can be used to handle them together. This simplifies the code a lot. Signed-off-by: Manivannan Sadhasivam --- drivers/pci/controller/dwc/pcie-qcom.c | 88 ++++++-------------------- 1 file changed, 20 insertions(+), 68 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controlle= r/dwc/pcie-qcom.c index 939973733a1e..6b83e3627336 100644 --- a/drivers/pci/controller/dwc/pcie-qcom.c +++ b/drivers/pci/controller/dwc/pcie-qcom.c @@ -169,6 +169,12 @@ struct qcom_pcie_resources_2_3_2 { struct regulator_bulk_data supplies[QCOM_PCIE_2_3_2_MAX_SUPPLY]; }; =20 +#define QCOM_PCIE_2_3_3_MAX_CLOCKS 5 +struct qcom_pcie_resources_2_3_3 { + struct clk_bulk_data clks[QCOM_PCIE_2_3_3_MAX_CLOCKS]; + struct reset_control *rst[7]; +}; + #define QCOM_PCIE_2_4_0_MAX_CLOCKS 4 struct qcom_pcie_resources_2_4_0 { struct clk_bulk_data clks[QCOM_PCIE_2_4_0_MAX_CLOCKS]; @@ -187,15 +193,6 @@ struct qcom_pcie_resources_2_4_0 { struct reset_control *phy_ahb_reset; }; =20 -struct qcom_pcie_resources_2_3_3 { - struct clk *iface; - struct clk *axi_m_clk; - struct clk *axi_s_clk; - struct clk *ahb_clk; - struct clk *aux_clk; - struct reset_control *rst[7]; -}; - /* 6 clocks typically, 7 for sm8250 */ struct qcom_pcie_resources_2_7_0 { struct clk_bulk_data clks[12]; @@ -896,26 +893,17 @@ static int qcom_pcie_get_resources_2_3_3(struct qcom_= pcie *pcie) const char *rst_names[] =3D { "axi_m", "axi_s", "pipe", "axi_m_sticky", "sticky", "ahb", "sleep", }; + int ret; =20 - res->iface =3D devm_clk_get(dev, "iface"); - if (IS_ERR(res->iface)) - return PTR_ERR(res->iface); - - res->axi_m_clk =3D devm_clk_get(dev, "axi_m"); - if (IS_ERR(res->axi_m_clk)) - return PTR_ERR(res->axi_m_clk); - - res->axi_s_clk =3D devm_clk_get(dev, "axi_s"); - if (IS_ERR(res->axi_s_clk)) - return PTR_ERR(res->axi_s_clk); - - res->ahb_clk =3D devm_clk_get(dev, "ahb"); - if (IS_ERR(res->ahb_clk)) - return PTR_ERR(res->ahb_clk); + res->clks[0].id =3D "iface"; + res->clks[1].id =3D "axi_m"; + res->clks[2].id =3D "axi_s"; + res->clks[3].id =3D "ahb"; + res->clks[4].id =3D "aux"; =20 - res->aux_clk =3D devm_clk_get(dev, "aux"); - if (IS_ERR(res->aux_clk)) - return PTR_ERR(res->aux_clk); + ret =3D devm_clk_bulk_get(dev, ARRAY_SIZE(res->clks), res->clks); + if (ret < 0) + return ret; =20 for (i =3D 0; i < ARRAY_SIZE(rst_names); i++) { res->rst[i] =3D devm_reset_control_get(dev, rst_names[i]); @@ -930,11 +918,7 @@ static void qcom_pcie_deinit_2_3_3(struct qcom_pcie *p= cie) { struct qcom_pcie_resources_2_3_3 *res =3D &pcie->res.v2_3_3; =20 - clk_disable_unprepare(res->iface); - clk_disable_unprepare(res->axi_m_clk); - clk_disable_unprepare(res->axi_s_clk); - clk_disable_unprepare(res->ahb_clk); - clk_disable_unprepare(res->aux_clk); + clk_bulk_disable_unprepare(ARRAY_SIZE(res->clks), res->clks); } =20 static int qcom_pcie_init_2_3_3(struct qcom_pcie *pcie) @@ -969,47 +953,15 @@ static int qcom_pcie_init_2_3_3(struct qcom_pcie *pci= e) */ usleep_range(2000, 2500); =20 - ret =3D clk_prepare_enable(res->iface); - if (ret) { - dev_err(dev, "cannot prepare/enable core clock\n"); - goto err_clk_iface; - } - - ret =3D clk_prepare_enable(res->axi_m_clk); - if (ret) { - dev_err(dev, "cannot prepare/enable core clock\n"); - goto err_clk_axi_m; - } - - ret =3D clk_prepare_enable(res->axi_s_clk); - if (ret) { - dev_err(dev, "cannot prepare/enable axi slave clock\n"); - goto err_clk_axi_s; - } - - ret =3D clk_prepare_enable(res->ahb_clk); - if (ret) { - dev_err(dev, "cannot prepare/enable ahb clock\n"); - goto err_clk_ahb; - } - - ret =3D clk_prepare_enable(res->aux_clk); + ret =3D clk_bulk_prepare_enable(ARRAY_SIZE(res->clks), res->clks); if (ret) { - dev_err(dev, "cannot prepare/enable aux clock\n"); - goto err_clk_aux; + dev_err(dev, "cannot prepare/enable clocks\n"); + goto err_assert_resets; } =20 return 0; =20 -err_clk_aux: - clk_disable_unprepare(res->ahb_clk); -err_clk_ahb: - clk_disable_unprepare(res->axi_s_clk); -err_clk_axi_s: - clk_disable_unprepare(res->axi_m_clk); -err_clk_axi_m: - clk_disable_unprepare(res->iface); -err_clk_iface: +err_assert_resets: /* * Not checking for failure, will anyway return * the original failure in 'ret'. --=20 2.25.1 From nobody Sat Apr 11 11:48:14 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id E8B5DC61DA4 for ; Mon, 6 Mar 2023 15:34:10 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230160AbjCFPeJ (ORCPT ); Mon, 6 Mar 2023 10:34:09 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:60002 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229990AbjCFPdt (ORCPT ); Mon, 6 Mar 2023 10:33:49 -0500 Received: from mail-pl1-x634.google.com (mail-pl1-x634.google.com [IPv6:2607:f8b0:4864:20::634]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 02C7132E5F for ; Mon, 6 Mar 2023 07:33:21 -0800 (PST) Received: by mail-pl1-x634.google.com with SMTP id i3so10771556plg.6 for ; Mon, 06 Mar 2023 07:33:20 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1678116800; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=KBoZXs7oWaG22XZASLiUsiWHjHyRIoI/eDEhjgIXc7Q=; b=UVA9L/s90wCetrJd7EWLPjzEaKsVJA4hZV1B6VwH1cVGOOM4qO6ZOJTilvRuvM5Dvn 9QDcLqQ58ey26VH4oZ2hVAdJ4GYglmq0Jho9P6jM8E7eR2VHRFBBbW7hiJiJ0EWr4oTQ iqYyNnYUNGWNCdnxKwQtrqtmvma2w8tqVov87jFgv2KaJemrao85uCP9CKRNenJzi4xO 2Oi0wb+T1gj+tnuUkz15KaqDac6cV9rHfgeYJ9InmGgcC1jFN7P3bF5ZgCEmCITnln9v CCOPROPJ1RmOerq95hMKAhFiV5zFXMkIs8qGMMWhWaY5RXThtV5eQQfKXFAXfEkE3iM7 xbbQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1678116800; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=KBoZXs7oWaG22XZASLiUsiWHjHyRIoI/eDEhjgIXc7Q=; b=baxSX5WX8qJhX29XPyRS013j7QDcVLuI3ZOxB8XEpHTzfFAKbHK8OXX3BKsJhizuxa qiKgQfSYqHYGqcGh1e+XaiRG4/Qg2n9hUNOklVQhakt+ywHcr1ld5243NKqR50hefCHX bQbyDcJ+bvfn2y4Aw6K3chfJwD7hMReDLnSP+qrcZ6Uzzs/RG8NQBbvkRjzGJUE/RktW tkgQkJ9vy5uS4EyGFNCWb0k8w2eGexb3dEDxVRWjS5tV2VOUFOqQ0jTHt/fj9tFZdkcm 49i7OLrdtATbOCO6ECunSDIuq9KKhCXFCgteKSCDjt7/EJskwGssMyDWMSgCnPfFWkm5 Cwug== X-Gm-Message-State: AO0yUKXxQNhn+gfERK0pMm3ShLfzxAmuNoHf0nCzWjfMYOOcA+tN4u+e xZmh4CLH9E9v/gWjNTm33n2iveoQBm63ZVrC7Q== X-Google-Smtp-Source: AK7set+hzSZX+ORf5IOG1kTrSNfNx3PyXjEdR0admtfuyQIsPjVgZeIfb9D2Ich8EGvBE+brpqN0dA== X-Received: by 2002:a17:902:e542:b0:19b:78:539e with SMTP id n2-20020a170902e54200b0019b0078539emr14724926plf.68.1678116800657; Mon, 06 Mar 2023 07:33:20 -0800 (PST) Received: from localhost.localdomain ([59.97.52.140]) by smtp.gmail.com with ESMTPSA id kl4-20020a170903074400b0019a7c890c61sm6837430plb.252.2023.03.06.07.33.16 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 06 Mar 2023 07:33:20 -0800 (PST) From: Manivannan Sadhasivam To: andersson@kernel.org, lpieralisi@kernel.org, kw@linux.com, krzysztof.kozlowski+dt@linaro.org, robh@kernel.org Cc: konrad.dybcio@linaro.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, quic_srichara@quicinc.com, Manivannan Sadhasivam Subject: [PATCH 10/19] PCI: qcom: Use bulk reset APIs for handling resets for IP rev 2.3.3 Date: Mon, 6 Mar 2023 21:02:13 +0530 Message-Id: <20230306153222.157667-11-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230306153222.157667-1-manivannan.sadhasivam@linaro.org> References: <20230306153222.157667-1-manivannan.sadhasivam@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" All the resets are asserted and deasserted at the same time. So the bulk reset APIs can be used to handle them together. This simplifies the code a lot. Signed-off-by: Manivannan Sadhasivam --- drivers/pci/controller/dwc/pcie-qcom.c | 49 ++++++++++++-------------- 1 file changed, 23 insertions(+), 26 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controlle= r/dwc/pcie-qcom.c index 6b83e3627336..8c39fc554a89 100644 --- a/drivers/pci/controller/dwc/pcie-qcom.c +++ b/drivers/pci/controller/dwc/pcie-qcom.c @@ -170,9 +170,10 @@ struct qcom_pcie_resources_2_3_2 { }; =20 #define QCOM_PCIE_2_3_3_MAX_CLOCKS 5 +#define QCOM_PCIE_2_3_3_MAX_RESETS 7 struct qcom_pcie_resources_2_3_3 { struct clk_bulk_data clks[QCOM_PCIE_2_3_3_MAX_CLOCKS]; - struct reset_control *rst[7]; + struct reset_control_bulk_data rst[QCOM_PCIE_2_3_3_MAX_RESETS]; }; =20 #define QCOM_PCIE_2_4_0_MAX_CLOCKS 4 @@ -889,10 +890,6 @@ static int qcom_pcie_get_resources_2_3_3(struct qcom_p= cie *pcie) struct qcom_pcie_resources_2_3_3 *res =3D &pcie->res.v2_3_3; struct dw_pcie *pci =3D pcie->pci; struct device *dev =3D pci->dev; - int i; - const char *rst_names[] =3D { "axi_m", "axi_s", "pipe", - "axi_m_sticky", "sticky", - "ahb", "sleep", }; int ret; =20 res->clks[0].id =3D "iface"; @@ -905,11 +902,17 @@ static int qcom_pcie_get_resources_2_3_3(struct qcom_= pcie *pcie) if (ret < 0) return ret; =20 - for (i =3D 0; i < ARRAY_SIZE(rst_names); i++) { - res->rst[i] =3D devm_reset_control_get(dev, rst_names[i]); - if (IS_ERR(res->rst[i])) - return PTR_ERR(res->rst[i]); - } + res->rst[0].id =3D "axi_m"; + res->rst[1].id =3D "axi_s"; + res->rst[2].id =3D "pipe"; + res->rst[3].id =3D "axi_m_sticky"; + res->rst[4].id =3D "sticky"; + res->rst[5].id =3D "ahb"; + res->rst[6].id =3D "sleep"; + + ret =3D devm_reset_control_bulk_get_exclusive(dev, ARRAY_SIZE(res->rst), = res->rst); + if (ret < 0) + return ret; =20 return 0; } @@ -926,25 +929,20 @@ static int qcom_pcie_init_2_3_3(struct qcom_pcie *pci= e) struct qcom_pcie_resources_2_3_3 *res =3D &pcie->res.v2_3_3; struct dw_pcie *pci =3D pcie->pci; struct device *dev =3D pci->dev; - int i, ret; + int ret; =20 - for (i =3D 0; i < ARRAY_SIZE(res->rst); i++) { - ret =3D reset_control_assert(res->rst[i]); - if (ret) { - dev_err(dev, "reset #%d assert failed (%d)\n", i, ret); - return ret; - } + ret =3D reset_control_bulk_assert(ARRAY_SIZE(res->rst), res->rst); + if (ret < 0) { + dev_err(dev, "cannot assert resets\n"); + return ret; } =20 usleep_range(2000, 2500); =20 - for (i =3D 0; i < ARRAY_SIZE(res->rst); i++) { - ret =3D reset_control_deassert(res->rst[i]); - if (ret) { - dev_err(dev, "reset #%d deassert failed (%d)\n", i, - ret); - return ret; - } + ret =3D reset_control_bulk_deassert(ARRAY_SIZE(res->rst), res->rst); + if (ret < 0) { + dev_err(dev, "cannot deassert resets\n"); + return ret; } =20 /* @@ -966,8 +964,7 @@ static int qcom_pcie_init_2_3_3(struct qcom_pcie *pcie) * Not checking for failure, will anyway return * the original failure in 'ret'. */ - for (i =3D 0; i < ARRAY_SIZE(res->rst); i++) - reset_control_assert(res->rst[i]); + reset_control_bulk_assert(ARRAY_SIZE(res->rst), res->rst); =20 return ret; } --=20 2.25.1 From nobody Sat Apr 11 11:48:14 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7A7CCC6FD1B for ; Mon, 6 Mar 2023 15:34:31 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231264AbjCFPe3 (ORCPT ); Mon, 6 Mar 2023 10:34:29 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:60014 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230409AbjCFPeR (ORCPT ); Mon, 6 Mar 2023 10:34:17 -0500 Received: from mail-pl1-x633.google.com (mail-pl1-x633.google.com [IPv6:2607:f8b0:4864:20::633]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 4280736456 for ; Mon, 6 Mar 2023 07:33:33 -0800 (PST) Received: by mail-pl1-x633.google.com with SMTP id p6so10844879plf.0 for ; Mon, 06 Mar 2023 07:33:33 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1678116808; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=FO7UUoMk85axnIoB/AfOqhv33JLBE3PRqs5r0gMesdo=; b=P/iaONH9ii28ji34Ov7o+sz8hqZo0qBVB/DcbCFzchV0HldizqbhsM4o4CCZSvZi58 aaFC0q1/Jeb3vwleiVZrokO5kc61uUYo+xD4HGUGt5NHIF6kWPbLmFleEyx8RwMtooOk 5HuNGffp6z5MzOwmgqGK14Z7VrtXBEVir2CB5yzjh68DtV5u0Fs6PKHfSlc0ldYturNB V4l0GSQaNQ3M3/kVgUr03mI1EslpAtXqwekA55jKakxrjq4LYfZcKMvNQCSqtJk/BPh/ B2zYZe8LaLm+X9UCbRm/FZuQa/3VI/g2fNKq+5mjnThzpBr3CsIYYmz1DVoYJf4g+Nlo TTaA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1678116808; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=FO7UUoMk85axnIoB/AfOqhv33JLBE3PRqs5r0gMesdo=; b=qQ/i7fI8lOFufGflUuaO9CZwBjEY4OFX1P4SI/wOfhluRXI87CxpLbl2Nbyrp7QBhY IEC6vCCYIKarKUAvMsZTbrsZW9eLH3qKmanGTWYLSIXC8Yh+ETt9nt3scyFSrCEWioyd P8ez0lzM0mrVTVfx9tm+o3wouZ6Mw+q7XUvwiTgyRIBv2ZMv3SYqsG/teOU5GXFqMDVG 6ZYYBy7wHksZiJvmc9KF6JPNKsu68jS/wJtFuW/Lm8Jwimas6aevimTk0aZn4o/faFsm XXCF2sUzKlgPehwW6agXuEfR97IFuuzuuk7T/t7+hHCDgAqEd0+aqZ9KK0DraEXy5iuu 9HIQ== X-Gm-Message-State: AO0yUKXiDxDq70o5LW4gMhpB4dXw5mzWJJ8ukn2hpMKTfr9g3vvgNIPS xxPXNPtdhkL88T930kekG7OIn7QekRznwn6/bg== X-Google-Smtp-Source: AK7set+GBOA6jEOTRQKRKCvfEOdIIAnNGGUYRA30QBx9olRqh2b1eYjgh4ZpdrQ6tM/YDJMQycA4KQ== X-Received: by 2002:a17:903:2290:b0:19c:dbce:dce8 with SMTP id b16-20020a170903229000b0019cdbcedce8mr14292386plh.15.1678116807708; Mon, 06 Mar 2023 07:33:27 -0800 (PST) Received: from localhost.localdomain ([59.97.52.140]) by smtp.gmail.com with ESMTPSA id kl4-20020a170903074400b0019a7c890c61sm6837430plb.252.2023.03.06.07.33.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 06 Mar 2023 07:33:27 -0800 (PST) From: Manivannan Sadhasivam To: andersson@kernel.org, lpieralisi@kernel.org, kw@linux.com, krzysztof.kozlowski+dt@linaro.org, robh@kernel.org Cc: konrad.dybcio@linaro.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, quic_srichara@quicinc.com, Manivannan Sadhasivam Subject: [PATCH 11/19] PCI: qcom: Use bulk reset APIs for handling resets for IP rev 2.4.0 Date: Mon, 6 Mar 2023 21:02:14 +0530 Message-Id: <20230306153222.157667-12-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230306153222.157667-1-manivannan.sadhasivam@linaro.org> References: <20230306153222.157667-1-manivannan.sadhasivam@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" All the resets are asserted and deasserted at the same time. So the bulk reset APIs can be used to handle them together. This simplifies the code a lot. It should be noted that there were delays in-between the reset asserts and deasserts. But going by the config used by other revisions, those delays are not really necessary. So a single delay after all asserts and one after deasserts is used. The total number of resets supported is 12 but only ipq4019 is using all of them. Signed-off-by: Manivannan Sadhasivam --- drivers/pci/controller/dwc/pcie-qcom.c | 238 ++++--------------------- 1 file changed, 30 insertions(+), 208 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controlle= r/dwc/pcie-qcom.c index 8c39fc554a89..ed43e03b972f 100644 --- a/drivers/pci/controller/dwc/pcie-qcom.c +++ b/drivers/pci/controller/dwc/pcie-qcom.c @@ -176,22 +176,13 @@ struct qcom_pcie_resources_2_3_3 { struct reset_control_bulk_data rst[QCOM_PCIE_2_3_3_MAX_RESETS]; }; =20 -#define QCOM_PCIE_2_4_0_MAX_CLOCKS 4 +#define QCOM_PCIE_2_4_0_MAX_CLOCKS 4 +#define QCOM_PCIE_2_4_0_MAX_RESETS 12 struct qcom_pcie_resources_2_4_0 { struct clk_bulk_data clks[QCOM_PCIE_2_4_0_MAX_CLOCKS]; int num_clks; - struct reset_control *axi_m_reset; - struct reset_control *axi_s_reset; - struct reset_control *pipe_reset; - struct reset_control *axi_m_vmid_reset; - struct reset_control *axi_s_xpu_reset; - struct reset_control *parf_reset; - struct reset_control *phy_reset; - struct reset_control *axi_m_sticky_reset; - struct reset_control *pipe_sticky_reset; - struct reset_control *pwr_reset; - struct reset_control *ahb_reset; - struct reset_control *phy_ahb_reset; + struct reset_control_bulk_data resets[QCOM_PCIE_2_4_0_MAX_RESETS]; + int num_resets; }; =20 /* 6 clocks typically, 7 for sm8250 */ @@ -626,65 +617,24 @@ static int qcom_pcie_get_resources_2_4_0(struct qcom_= pcie *pcie) if (ret < 0) return ret; =20 - res->axi_m_reset =3D devm_reset_control_get_exclusive(dev, "axi_m"); - if (IS_ERR(res->axi_m_reset)) - return PTR_ERR(res->axi_m_reset); - - res->axi_s_reset =3D devm_reset_control_get_exclusive(dev, "axi_s"); - if (IS_ERR(res->axi_s_reset)) - return PTR_ERR(res->axi_s_reset); - - if (is_ipq) { - /* - * These resources relates to the PHY or are secure clocks, but - * are controlled here for IPQ4019 - */ - res->pipe_reset =3D devm_reset_control_get_exclusive(dev, "pipe"); - if (IS_ERR(res->pipe_reset)) - return PTR_ERR(res->pipe_reset); - - res->axi_m_vmid_reset =3D devm_reset_control_get_exclusive(dev, - "axi_m_vmid"); - if (IS_ERR(res->axi_m_vmid_reset)) - return PTR_ERR(res->axi_m_vmid_reset); - - res->axi_s_xpu_reset =3D devm_reset_control_get_exclusive(dev, - "axi_s_xpu"); - if (IS_ERR(res->axi_s_xpu_reset)) - return PTR_ERR(res->axi_s_xpu_reset); - - res->parf_reset =3D devm_reset_control_get_exclusive(dev, "parf"); - if (IS_ERR(res->parf_reset)) - return PTR_ERR(res->parf_reset); - - res->phy_reset =3D devm_reset_control_get_exclusive(dev, "phy"); - if (IS_ERR(res->phy_reset)) - return PTR_ERR(res->phy_reset); - } - - res->axi_m_sticky_reset =3D devm_reset_control_get_exclusive(dev, - "axi_m_sticky"); - if (IS_ERR(res->axi_m_sticky_reset)) - return PTR_ERR(res->axi_m_sticky_reset); - - res->pipe_sticky_reset =3D devm_reset_control_get_exclusive(dev, - "pipe_sticky"); - if (IS_ERR(res->pipe_sticky_reset)) - return PTR_ERR(res->pipe_sticky_reset); - - res->pwr_reset =3D devm_reset_control_get_exclusive(dev, "pwr"); - if (IS_ERR(res->pwr_reset)) - return PTR_ERR(res->pwr_reset); - - res->ahb_reset =3D devm_reset_control_get_exclusive(dev, "ahb"); - if (IS_ERR(res->ahb_reset)) - return PTR_ERR(res->ahb_reset); + res->resets[0].id =3D "axi_m"; + res->resets[1].id =3D "axi_s"; + res->resets[2].id =3D "axi_m_sticky"; + res->resets[3].id =3D "pipe_sticky"; + res->resets[4].id =3D "pwr"; + res->resets[5].id =3D "ahb"; + res->resets[6].id =3D "pipe"; + res->resets[7].id =3D "axi_m_vmid"; + res->resets[8].id =3D "axi_s_xpu"; + res->resets[9].id =3D "parf"; + res->resets[10].id =3D "phy"; + res->resets[11].id =3D "phy_ahb"; + + res->num_resets =3D is_ipq ? 12 : 6; =20 - if (is_ipq) { - res->phy_ahb_reset =3D devm_reset_control_get_exclusive(dev, "phy_ahb"); - if (IS_ERR(res->phy_ahb_reset)) - return PTR_ERR(res->phy_ahb_reset); - } + ret =3D devm_reset_control_bulk_get_exclusive(dev, res->num_resets, res->= resets); + if (ret < 0) + return ret; =20 return 0; } @@ -693,15 +643,7 @@ static void qcom_pcie_deinit_2_4_0(struct qcom_pcie *p= cie) { struct qcom_pcie_resources_2_4_0 *res =3D &pcie->res.v2_4_0; =20 - reset_control_assert(res->axi_m_reset); - reset_control_assert(res->axi_s_reset); - reset_control_assert(res->pipe_reset); - reset_control_assert(res->pipe_sticky_reset); - reset_control_assert(res->phy_reset); - reset_control_assert(res->phy_ahb_reset); - reset_control_assert(res->axi_m_sticky_reset); - reset_control_assert(res->pwr_reset); - reset_control_assert(res->ahb_reset); + reset_control_bulk_assert(res->num_resets, res->resets); clk_bulk_disable_unprepare(res->num_clks, res->clks); } =20 @@ -712,149 +654,29 @@ static int qcom_pcie_init_2_4_0(struct qcom_pcie *pc= ie) struct device *dev =3D pci->dev; int ret; =20 - ret =3D reset_control_assert(res->axi_m_reset); - if (ret) { - dev_err(dev, "cannot assert axi master reset\n"); - return ret; - } - - ret =3D reset_control_assert(res->axi_s_reset); - if (ret) { - dev_err(dev, "cannot assert axi slave reset\n"); - return ret; - } - - usleep_range(10000, 12000); - - ret =3D reset_control_assert(res->pipe_reset); - if (ret) { - dev_err(dev, "cannot assert pipe reset\n"); - return ret; - } - - ret =3D reset_control_assert(res->pipe_sticky_reset); - if (ret) { - dev_err(dev, "cannot assert pipe sticky reset\n"); - return ret; - } - - ret =3D reset_control_assert(res->phy_reset); - if (ret) { - dev_err(dev, "cannot assert phy reset\n"); - return ret; - } - - ret =3D reset_control_assert(res->phy_ahb_reset); - if (ret) { - dev_err(dev, "cannot assert phy ahb reset\n"); + ret =3D reset_control_bulk_assert(res->num_resets, res->resets); + if (ret < 0) { + dev_err(dev, "cannot assert resets\n"); return ret; } =20 usleep_range(10000, 12000); =20 - ret =3D reset_control_assert(res->axi_m_sticky_reset); - if (ret) { - dev_err(dev, "cannot assert axi master sticky reset\n"); - return ret; - } - - ret =3D reset_control_assert(res->pwr_reset); - if (ret) { - dev_err(dev, "cannot assert power reset\n"); - return ret; - } - - ret =3D reset_control_assert(res->ahb_reset); - if (ret) { - dev_err(dev, "cannot assert ahb reset\n"); + ret =3D reset_control_bulk_deassert(res->num_resets, res->resets); + if (ret < 0) { + dev_err(dev, "cannot deassert resets\n"); return ret; } =20 usleep_range(10000, 12000); =20 - ret =3D reset_control_deassert(res->phy_ahb_reset); + ret =3D clk_bulk_prepare_enable(res->num_clks, res->clks); if (ret) { - dev_err(dev, "cannot deassert phy ahb reset\n"); + reset_control_bulk_assert(res->num_resets, res->resets); return ret; } =20 - ret =3D reset_control_deassert(res->phy_reset); - if (ret) { - dev_err(dev, "cannot deassert phy reset\n"); - goto err_rst_phy; - } - - ret =3D reset_control_deassert(res->pipe_reset); - if (ret) { - dev_err(dev, "cannot deassert pipe reset\n"); - goto err_rst_pipe; - } - - ret =3D reset_control_deassert(res->pipe_sticky_reset); - if (ret) { - dev_err(dev, "cannot deassert pipe sticky reset\n"); - goto err_rst_pipe_sticky; - } - - usleep_range(10000, 12000); - - ret =3D reset_control_deassert(res->axi_m_reset); - if (ret) { - dev_err(dev, "cannot deassert axi master reset\n"); - goto err_rst_axi_m; - } - - ret =3D reset_control_deassert(res->axi_m_sticky_reset); - if (ret) { - dev_err(dev, "cannot deassert axi master sticky reset\n"); - goto err_rst_axi_m_sticky; - } - - ret =3D reset_control_deassert(res->axi_s_reset); - if (ret) { - dev_err(dev, "cannot deassert axi slave reset\n"); - goto err_rst_axi_s; - } - - ret =3D reset_control_deassert(res->pwr_reset); - if (ret) { - dev_err(dev, "cannot deassert power reset\n"); - goto err_rst_pwr; - } - - ret =3D reset_control_deassert(res->ahb_reset); - if (ret) { - dev_err(dev, "cannot deassert ahb reset\n"); - goto err_rst_ahb; - } - - usleep_range(10000, 12000); - - ret =3D clk_bulk_prepare_enable(res->num_clks, res->clks); - if (ret) - goto err_clks; - return 0; - -err_clks: - reset_control_assert(res->ahb_reset); -err_rst_ahb: - reset_control_assert(res->pwr_reset); -err_rst_pwr: - reset_control_assert(res->axi_s_reset); -err_rst_axi_s: - reset_control_assert(res->axi_m_sticky_reset); -err_rst_axi_m_sticky: - reset_control_assert(res->axi_m_reset); -err_rst_axi_m: - reset_control_assert(res->pipe_sticky_reset); -err_rst_pipe_sticky: - reset_control_assert(res->pipe_reset); -err_rst_pipe: - reset_control_assert(res->phy_reset); -err_rst_phy: - reset_control_assert(res->phy_ahb_reset); - return ret; } =20 static int qcom_pcie_post_init_2_4_0(struct qcom_pcie *pcie) --=20 2.25.1 From nobody Sat Apr 11 11:48:14 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 98362C64EC4 for ; Mon, 6 Mar 2023 15:34:36 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229870AbjCFPee (ORCPT ); Mon, 6 Mar 2023 10:34:34 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:33040 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230433AbjCFPeS (ORCPT ); Mon, 6 Mar 2023 10:34:18 -0500 Received: from mail-pj1-x102a.google.com (mail-pj1-x102a.google.com [IPv6:2607:f8b0:4864:20::102a]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id D2740B46A for ; Mon, 6 Mar 2023 07:33:34 -0800 (PST) Received: by mail-pj1-x102a.google.com with SMTP id 6-20020a17090a190600b00237c5b6ecd7so13510002pjg.4 for ; Mon, 06 Mar 2023 07:33:34 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1678116812; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=gtO470wsQrdefT/eZbqt8rDglQCA1uZJNkLG9oF8ql8=; b=WIfdJaBzivm0SsoyXJxtpP+FVDfpCIb19DMrUIZn9JmoLmViOtWHq4gK5rEsmeeDTN p0Zw70DhepV42ULj/DwelLZzjimaV+AdWta7ZG5VzeCVpFbh0jmdEx1TVwmus2m+OphR ewqslEtnFf/eGNM/v8lVcOcK/P9bmEiabnNKZxJGLCI+Uh/H3Wlb9Iw6yxbJReyllOfP PhOzAhll0LFfLWg7suSZFt4l/lUAAOVa+AVDxrHgCybXpe7fiOCiid9AteZLAwOxypQE KL84IBC+HEYeopdOStra85mlBOp8+8x6BLUzEfuhrjymSDwqXnhUU3cfpVeo6fpBVhuv YsGw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1678116812; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=gtO470wsQrdefT/eZbqt8rDglQCA1uZJNkLG9oF8ql8=; b=DIzTr1FqBViULv6VvWQM1xR35hJyFPGii3RMIcvTruAs94fxQA8UCQhzQAR4uw0iUg 314QymwvpYueCfrPBT6cv3k/tTjjxbqkKC/X9dkycDOT1nW/9kUTtErF4ZigoocIfMCh vBW48bLG1y6m9jgRp6iPWgpSqhHV6HYIem91crXI6JJQtaDGLnP6OdUhypiZayGAHXf0 AFMl8BTj2R4Mxz0QIGCEd0yBbkQ/36tF3e6LzUkua6wM2ElSTD3dY4g6NRMmf0INVvO3 SoT3wR2YP7NTo+kkGjFBGZyNchsnhTianbyM3h7FuzhjmXz6RxlPKyvvhZpYW9oQ8JMV vYWA== X-Gm-Message-State: AO0yUKXkFNXiplY96XNFcfbx0cQ8XSyOpFA0+3wh0jNXxtAYErRvtOXr B4HGm3upLyJdVT8MIQbmWo0k X-Google-Smtp-Source: AK7set9i5rke2x6vgk1ILaEXl7fOJW1AdeiwtHqSdSsE5yjGB9Aw3Ks55LT7hsCqA6yRIpbwv9WLTw== X-Received: by 2002:a17:903:2290:b0:19e:25b4:7740 with SMTP id b16-20020a170903229000b0019e25b47740mr13907218plh.28.1678116811714; Mon, 06 Mar 2023 07:33:31 -0800 (PST) Received: from localhost.localdomain ([59.97.52.140]) by smtp.gmail.com with ESMTPSA id kl4-20020a170903074400b0019a7c890c61sm6837430plb.252.2023.03.06.07.33.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 06 Mar 2023 07:33:31 -0800 (PST) From: Manivannan Sadhasivam To: andersson@kernel.org, lpieralisi@kernel.org, kw@linux.com, krzysztof.kozlowski+dt@linaro.org, robh@kernel.org Cc: konrad.dybcio@linaro.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, quic_srichara@quicinc.com, Manivannan Sadhasivam Subject: [PATCH 12/19] PCI: qcom: Use macros for defining total no. of clocks & supplies Date: Mon, 6 Mar 2023 21:02:15 +0530 Message-Id: <20230306153222.157667-13-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230306153222.157667-1-manivannan.sadhasivam@linaro.org> References: <20230306153222.157667-1-manivannan.sadhasivam@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" To keep uniformity, let's use macros to define the total number of clocks and supplies in qcom_pcie_resources_{2_7_0/2_9_0} structs. Signed-off-by: Manivannan Sadhasivam --- drivers/pci/controller/dwc/pcie-qcom.c | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controlle= r/dwc/pcie-qcom.c index ed43e03b972f..e1180c84f0fa 100644 --- a/drivers/pci/controller/dwc/pcie-qcom.c +++ b/drivers/pci/controller/dwc/pcie-qcom.c @@ -185,16 +185,18 @@ struct qcom_pcie_resources_2_4_0 { int num_resets; }; =20 -/* 6 clocks typically, 7 for sm8250 */ +#define QCOM_PCIE_2_7_0_MAX_CLOCKS 12 +#define QCOM_PCIE_2_7_0_MAX_SUPPLIES 2 struct qcom_pcie_resources_2_7_0 { - struct clk_bulk_data clks[12]; + struct clk_bulk_data clks[QCOM_PCIE_2_7_0_MAX_CLOCKS]; int num_clks; - struct regulator_bulk_data supplies[2]; + struct regulator_bulk_data supplies[QCOM_PCIE_2_7_0_MAX_SUPPLIES]; struct reset_control *pci_reset; }; =20 +#define QCOM_PCIE_2_9_0_MAX_CLOCKS 5 struct qcom_pcie_resources_2_9_0 { - struct clk_bulk_data clks[5]; + struct clk_bulk_data clks[QCOM_PCIE_2_9_0_MAX_CLOCKS]; struct reset_control *rst; }; =20 --=20 2.25.1 From nobody Sat Apr 11 11:48:14 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9BC56C6FD1B for ; Mon, 6 Mar 2023 15:34:39 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231317AbjCFPeh (ORCPT ); Mon, 6 Mar 2023 10:34:37 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:60040 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229981AbjCFPeT (ORCPT ); Mon, 6 Mar 2023 10:34:19 -0500 Received: from mail-pl1-x636.google.com (mail-pl1-x636.google.com [IPv6:2607:f8b0:4864:20::636]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id E36C54EFC for ; Mon, 6 Mar 2023 07:33:38 -0800 (PST) Received: by mail-pl1-x636.google.com with SMTP id i5so10798814pla.2 for ; Mon, 06 Mar 2023 07:33:38 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1678116815; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=xOXj9qXaJS4g+fALdy49YGqe1mwntIry9f6pr0EizBs=; b=O5bjJSoiFmcJzY9G0N/Mt3gXgh6Gp8IMpLyQOrBxHgq5nzAPNZYW/y9HHvHxjcr2Gr Sx+ZNkwM11QaoSe2KDWc24V+acgw0X/hJTcOYWMW5KwitR59DIR0qGDU1GTAAXL/xwUr rEVYcwUV1RiMLy/dBgdugHpDm/QGmA7TONkMIFsytsqaCOdHOde9KI0qkWZDHR58+tUT GEudD6rIbUqX1rQqJA7DtGnPDZe6XJQczXpbbcIyEe+C6dmnxXaRF6IzINzsXJbEvm7o C5/We/I/sPE5B0lIAqFCuqLORl9Za9zm5/BANRCfVFlCMXsdKto3GrcJ01bF6C3cyNPI v51w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1678116815; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=xOXj9qXaJS4g+fALdy49YGqe1mwntIry9f6pr0EizBs=; b=CQuEXNWM3HcJQChNBunIw0+cZdmQXbg8dxECKkhAWIbLxN4ILRQyRNM74nlPQcD9vL 9j8+VJ5y1fgq+nHJ+iPNcmejj2ggibSJ7p++AUNeZOnRcVkGBLnZsrUhGDXRNYsAx4KY mA9JYSo5ORUmwNrAB0+yfK8GQd0LHiPBtpG7zKzExKlmhZzb+Vj0h8zA5E0KmeglyRvo 7n0TZv410mYsfj4BiGzCSXP651uPm4dxyB5TzYOX9eNkQimzlcR1O47XbegKWdOqkGu6 kOmjAUDoWd0gYlwRD+vqT71y37R3pvXd4IVCzSDHSUYSw8NZ7MSuJLEAPqCXZDf1cINg Gymg== X-Gm-Message-State: AO0yUKUDzc1VXCUwB0wR4RhY18QKg7tj6usnT7vGwqteIAgdEOAMACRU Yzc5POTNupmIfzzAu2DpA95V X-Google-Smtp-Source: AK7set/D9pgUx7exlNXxw7fqopGeYzin7aYL14Kdu8M4ifco6YGKADfFyG9jbcTPFAYKVjxbPzGvuw== X-Received: by 2002:a17:903:2290:b0:19c:dbce:dce8 with SMTP id b16-20020a170903229000b0019cdbcedce8mr14292691plh.15.1678116815512; Mon, 06 Mar 2023 07:33:35 -0800 (PST) Received: from localhost.localdomain ([59.97.52.140]) by smtp.gmail.com with ESMTPSA id kl4-20020a170903074400b0019a7c890c61sm6837430plb.252.2023.03.06.07.33.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 06 Mar 2023 07:33:35 -0800 (PST) From: Manivannan Sadhasivam To: andersson@kernel.org, lpieralisi@kernel.org, kw@linux.com, krzysztof.kozlowski+dt@linaro.org, robh@kernel.org Cc: konrad.dybcio@linaro.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, quic_srichara@quicinc.com, Manivannan Sadhasivam Subject: [PATCH 13/19] dt-bindings: PCI: qcom-ep: Rename "mmio" region to "mhi" Date: Mon, 6 Mar 2023 21:02:16 +0530 Message-Id: <20230306153222.157667-14-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230306153222.157667-1-manivannan.sadhasivam@linaro.org> References: <20230306153222.157667-1-manivannan.sadhasivam@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" As per Qualcomm's internal documentation, the name of the region is "mhi" and not "mmio". So let's rename it to follow the convention. Signed-off-by: Manivannan Sadhasivam --- Documentation/devicetree/bindings/pci/qcom,pcie-ep.yaml | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie-ep.yaml b/Docu= mentation/devicetree/bindings/pci/qcom,pcie-ep.yaml index 89cfdee4b89f..c2d50f42cb4c 100644 --- a/Documentation/devicetree/bindings/pci/qcom,pcie-ep.yaml +++ b/Documentation/devicetree/bindings/pci/qcom,pcie-ep.yaml @@ -22,7 +22,7 @@ properties: - description: External local bus interface registers - description: Address Translation Unit (ATU) registers - description: Memory region used to map remote RC address space - - description: BAR memory region + - description: MHI register region used as BAR =20 reg-names: items: @@ -31,7 +31,7 @@ properties: - const: elbi - const: atu - const: addr_space - - const: mmio + - const: mhi =20 clocks: minItems: 7 @@ -175,7 +175,7 @@ examples: <0x40002000 0x1000>, <0x01c03000 0x3000>; reg-names =3D "parf", "dbi", "elbi", "atu", "addr_space", - "mmio"; + "mhi"; =20 clocks =3D <&gcc GCC_PCIE_AUX_CLK>, <&gcc GCC_PCIE_CFG_AHB_CLK>, --=20 2.25.1 From nobody Sat Apr 11 11:48:14 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 82369C64EC4 for ; Mon, 6 Mar 2023 15:35:04 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231400AbjCFPep (ORCPT ); Mon, 6 Mar 2023 10:34:45 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:60066 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230274AbjCFPeU (ORCPT ); Mon, 6 Mar 2023 10:34:20 -0500 Received: from mail-pj1-x1032.google.com (mail-pj1-x1032.google.com [IPv6:2607:f8b0:4864:20::1032]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 0D5259EC0 for ; Mon, 6 Mar 2023 07:33:43 -0800 (PST) Received: by mail-pj1-x1032.google.com with SMTP id oj5so10131600pjb.5 for ; Mon, 06 Mar 2023 07:33:43 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1678116819; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=FSZTsxFvrcK51n2zirybFkKL1X1N/PtWqccn7VlsBoE=; b=CMF2lbQmJRo/nSmptNkmWK25ase0/6LStx4Q+kyliXRBjgF8nMVTfzYXz5xRwHy+Uv s+3dRUyQXoGOMT/psC+HQXqSQhG9talllgrxQD+Pnsuk4fPpHoJit7axA7AvnkB8btqk meyPqkjSgSQUrdMta+uFqNIbTvTXqJmPa13TztxaJWrSjFHQK/nEpyvbKStVlm42ieNM qn62Q4fQgXauS6szDyp+a6ckwa9dMilh4FrY9G/czNTeMtZtFReH8VaQmCi1KiUa3uFV wL/hqCcj4DM+qlvfnZ//SIAmRixAbI2MI9Iotny/xoGllPvYPbQEB+0iTg5XBQIaVkrS 65yg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1678116819; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=FSZTsxFvrcK51n2zirybFkKL1X1N/PtWqccn7VlsBoE=; b=qOolxrkghnBxy73uuIv00k9ECgbCAKEgzwgqEEttb5zfrSGMEphmV+GnksltjyqS1X SBZbje9QqrgzWbeutWTpiwxv+DNroTOrz4JGMOrwGewXuuE9xFVQeg+El6yMv+ENuSwP Fxy03epGQ+sFi4POd9wA+PvhTQpTEyh1NaYPecGcurnDDFxr9bB9kMQM6p73+kQfyB4J iM9u0jD8ubOhagNIt5KaKVyqlENjlfopAhpWVY/A1KibdS2OhsRwvNJQWukvgkAhd3Fd Hv5dObT1lhj6/AqDGUOoUO+qHGTPilfifbJJVOJ7pIryJyFwRX8D3/15FdEf0DIhBZsr uVeg== X-Gm-Message-State: AO0yUKVy7RB2TJwcXiSyj10hZrffC/v5/Bt3cqu661+nLUbKJTHxQr4q 9zFk+MlEZ3Krmg7tFoxBF2GO X-Google-Smtp-Source: AK7set82IVvmz55x2cDlnkyaJV0+PnXaPQyULxNMeE+2vqBXVrH5YGgrlSTA2fAZcnEoKeHTkfXNCw== X-Received: by 2002:a17:903:2290:b0:19e:25b4:7740 with SMTP id b16-20020a170903229000b0019e25b47740mr13907805plh.28.1678116819521; Mon, 06 Mar 2023 07:33:39 -0800 (PST) Received: from localhost.localdomain ([59.97.52.140]) by smtp.gmail.com with ESMTPSA id kl4-20020a170903074400b0019a7c890c61sm6837430plb.252.2023.03.06.07.33.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 06 Mar 2023 07:33:39 -0800 (PST) From: Manivannan Sadhasivam To: andersson@kernel.org, lpieralisi@kernel.org, kw@linux.com, krzysztof.kozlowski+dt@linaro.org, robh@kernel.org Cc: konrad.dybcio@linaro.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, quic_srichara@quicinc.com, Manivannan Sadhasivam Subject: [PATCH 14/19] PCI: qcom-ep: Rename "mmio" region to "mhi" Date: Mon, 6 Mar 2023 21:02:17 +0530 Message-Id: <20230306153222.157667-15-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230306153222.157667-1-manivannan.sadhasivam@linaro.org> References: <20230306153222.157667-1-manivannan.sadhasivam@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" As per Qualcomm's internal documentation, the name of the region is "mhi" and not "mmio". So let's rename it to follow the convention. Signed-off-by: Manivannan Sadhasivam --- drivers/pci/controller/dwc/pcie-qcom-ep.c | 38 +++++++++++------------ 1 file changed, 19 insertions(+), 19 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-qcom-ep.c b/drivers/pci/contro= ller/dwc/pcie-qcom-ep.c index 19b32839ea26..a4983d3844f7 100644 --- a/drivers/pci/controller/dwc/pcie-qcom-ep.c +++ b/drivers/pci/controller/dwc/pcie-qcom-ep.c @@ -147,9 +147,9 @@ enum qcom_pcie_ep_link_status { * @pci: Designware PCIe controller struct * @parf: Qualcomm PCIe specific PARF register base * @elbi: Designware PCIe specific ELBI register base - * @mmio: MMIO register base + * @mhi: MHI register base * @perst_map: PERST regmap - * @mmio_res: MMIO region resource + * @mhi_res: MHI region resource * @core_reset: PCIe Endpoint core reset * @reset: PERST# GPIO * @wake: WAKE# GPIO @@ -168,9 +168,9 @@ struct qcom_pcie_ep { =20 void __iomem *parf; void __iomem *elbi; - void __iomem *mmio; + void __iomem *mhi; struct regmap *perst_map; - struct resource *mmio_res; + struct resource *mhi_res; =20 struct reset_control *core_reset; struct gpio_desc *reset; @@ -405,10 +405,10 @@ static int qcom_pcie_perst_deassert(struct dw_pcie *p= ci) } =20 /* - * The physical address of the MMIO region which is exposed as the BAR - * should be written to MHI BASE registers. + * The physical address of the MHI region which is exposed as the BAR + * should be written to PARF_MHI_BASE registers. */ - writel_relaxed(pcie_ep->mmio_res->start, + writel_relaxed(pcie_ep->mhi_res->start, pcie_ep->parf + PARF_MHI_BASE_ADDR_LOWER); writel_relaxed(0, pcie_ep->parf + PARF_MHI_BASE_ADDR_UPPER); =20 @@ -477,16 +477,16 @@ static int qcom_pcie_ep_get_io_resources(struct platf= orm_device *pdev, if (IS_ERR(pcie_ep->elbi)) return PTR_ERR(pcie_ep->elbi); =20 - pcie_ep->mmio_res =3D platform_get_resource_byname(pdev, IORESOURCE_MEM, - "mmio"); - if (!pcie_ep->mmio_res) { - dev_err(dev, "Failed to get mmio resource\n"); + pcie_ep->mhi_res =3D platform_get_resource_byname(pdev, IORESOURCE_MEM, + "mhi"); + if (!pcie_ep->mhi_res) { + dev_err(dev, "Failed to get mhi resource\n"); return -EINVAL; } =20 - pcie_ep->mmio =3D devm_pci_remap_cfg_resource(dev, pcie_ep->mmio_res); - if (IS_ERR(pcie_ep->mmio)) - return PTR_ERR(pcie_ep->mmio); + pcie_ep->mhi =3D devm_pci_remap_cfg_resource(dev, pcie_ep->mhi_res); + if (IS_ERR(pcie_ep->mhi)) + return PTR_ERR(pcie_ep->mhi); =20 syscon =3D of_parse_phandle(dev->of_node, "qcom,perst-regs", 0); if (!syscon) { @@ -674,19 +674,19 @@ static int qcom_pcie_ep_link_transition_count(struct = seq_file *s, void *data) dev_get_drvdata(s->private); =20 seq_printf(s, "L0s transition count: %u\n", - readl_relaxed(pcie_ep->mmio + PARF_DEBUG_CNT_PM_LINKST_IN_L0S)); + readl_relaxed(pcie_ep->mhi + PARF_DEBUG_CNT_PM_LINKST_IN_L0S)); =20 seq_printf(s, "L1 transition count: %u\n", - readl_relaxed(pcie_ep->mmio + PARF_DEBUG_CNT_PM_LINKST_IN_L1)); + readl_relaxed(pcie_ep->mhi + PARF_DEBUG_CNT_PM_LINKST_IN_L1)); =20 seq_printf(s, "L1.1 transition count: %u\n", - readl_relaxed(pcie_ep->mmio + PARF_DEBUG_CNT_AUX_CLK_IN_L1SUB_L1)); + readl_relaxed(pcie_ep->mhi + PARF_DEBUG_CNT_AUX_CLK_IN_L1SUB_L1)); =20 seq_printf(s, "L1.2 transition count: %u\n", - readl_relaxed(pcie_ep->mmio + PARF_DEBUG_CNT_AUX_CLK_IN_L1SUB_L2)); + readl_relaxed(pcie_ep->mhi + PARF_DEBUG_CNT_AUX_CLK_IN_L1SUB_L2)); =20 seq_printf(s, "L2 transition count: %u\n", - readl_relaxed(pcie_ep->mmio + PARF_DEBUG_CNT_PM_LINKST_IN_L2)); + readl_relaxed(pcie_ep->mhi + PARF_DEBUG_CNT_PM_LINKST_IN_L2)); =20 return 0; } --=20 2.25.1 From nobody Sat Apr 11 11:48:14 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 92A82C61DA4 for ; Mon, 6 Mar 2023 15:35:12 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230380AbjCFPfJ (ORCPT ); Mon, 6 Mar 2023 10:35:09 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:33134 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231128AbjCFPeV (ORCPT ); Mon, 6 Mar 2023 10:34:21 -0500 Received: from mail-pj1-x1030.google.com (mail-pj1-x1030.google.com [IPv6:2607:f8b0:4864:20::1030]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 4F57D93D1 for ; Mon, 6 Mar 2023 07:33:44 -0800 (PST) Received: by mail-pj1-x1030.google.com with SMTP id qa18-20020a17090b4fd200b0023750b675f5so13521961pjb.3 for ; Mon, 06 Mar 2023 07:33:44 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1678116823; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=ZjVJSbpM4JHJqj6krv3lIQKDxhwB+dMqIuVDDztiVfQ=; b=lq3LCCOxjEEkFrpCl5klok4qbkFBi4U5sOn1wrDGtT83/vF23/qAYHM0ZThwR+kQSG JjXJnoCOAKWlGcJn7LqkEEAbxp3nLA1VtnLnNOO1+kx6BZjedrB2AkZiNkNvmfQfEuek /NZzRRZYrsEc8VlLVcO7nMaPkkezgD2R8p2SYJfmDuffn5FM12i2Q7YUzo38/bdNgvBP tc/2vyDhJHoyWEaV+rGvFVW949sf/YQ9AIQ8Ts/CoV7SJ+rTKf9+LsVXN5ca8j8jPTaI j8YUobKBXP3hwzqc4txh6JuzH+/tRSZegs8ctiNh2nOamhov/emD7RLGTfSKpSJygHit AFBg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1678116823; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=ZjVJSbpM4JHJqj6krv3lIQKDxhwB+dMqIuVDDztiVfQ=; b=dajWxn0oIWr3Rlfy78HbtJu6qvjmEdhT4FkKLdH7pkiLAn2TQQ7dAtCvau6gyu5ftc 63lsacPuwIO72Cd/l/cuqcxGG/5geRMTAjHW6WWDGRzSiUeMBlhoIK731tP3rZMpy3Wa 2BsgrKywlQVxbDQANr1wntbPV5eFB48r9IsqWSeb31qqK1Gwv+ndZjkLG84hfI13DqR+ d5oi3Ss2Wiwsh1Hoz4az7SnYNU4ValJFdcvvWzZlr7EpCvOeqX+9E43LOn330W8grUM/ 8ouVIkj8DjDnuwqYGqks8AkXA3IKa64KZvd+kK/duImhHqjWTpARB/TS41V3MCU0jJv5 rIzA== X-Gm-Message-State: AO0yUKVpzS/GAitiQL+vVshZMsMTKYAz148Z/zfhCzNG021BcXhVxS+L azhw1ch74gue30jpFSwvNljM X-Google-Smtp-Source: AK7set+tvsgC/gt8pVwsFXsv3pBtQFnZtVgPVi+YHiD0roBeKelE9q9Ag+mrYIaR9+tEdyklDdfNpg== X-Received: by 2002:a17:902:7007:b0:19d:47b:67c8 with SMTP id y7-20020a170902700700b0019d047b67c8mr9574772plk.48.1678116823681; Mon, 06 Mar 2023 07:33:43 -0800 (PST) Received: from localhost.localdomain ([59.97.52.140]) by smtp.gmail.com with ESMTPSA id kl4-20020a170903074400b0019a7c890c61sm6837430plb.252.2023.03.06.07.33.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 06 Mar 2023 07:33:43 -0800 (PST) From: Manivannan Sadhasivam To: andersson@kernel.org, lpieralisi@kernel.org, kw@linux.com, krzysztof.kozlowski+dt@linaro.org, robh@kernel.org Cc: konrad.dybcio@linaro.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, quic_srichara@quicinc.com, Manivannan Sadhasivam Subject: [PATCH 15/19] dt-bindings: PCI: qcom: Add "mhi" register region to supported SoCs Date: Mon, 6 Mar 2023 21:02:18 +0530 Message-Id: <20230306153222.157667-16-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230306153222.157667-1-manivannan.sadhasivam@linaro.org> References: <20230306153222.157667-1-manivannan.sadhasivam@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" "mhi" register region contains the MHI registers that could be used by the PCIe controller drivers to get debug information like PCIe link transition counts on newer SoCs. Signed-off-by: Manivannan Sadhasivam --- Documentation/devicetree/bindings/pci/qcom,pcie.yaml | 12 ++++++++---- 1 file changed, 8 insertions(+), 4 deletions(-) diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml b/Documen= tation/devicetree/bindings/pci/qcom,pcie.yaml index fb32c43dd12d..2de6e7154025 100644 --- a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml +++ b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml @@ -44,11 +44,11 @@ properties: =20 reg: minItems: 4 - maxItems: 5 + maxItems: 6 =20 reg-names: minItems: 4 - maxItems: 5 + maxItems: 6 =20 interrupts: minItems: 1 @@ -185,10 +185,12 @@ allOf: properties: reg: minItems: 4 - maxItems: 4 + maxItems: 5 reg-names: + minItems: 4 items: - const: parf # Qualcomm specific registers + - const: mhi # MHI registers - const: dbi # DesignWare PCIe registers - const: elbi # External local bus interface registers - const: config # PCIe configuration space @@ -209,10 +211,12 @@ allOf: properties: reg: minItems: 5 - maxItems: 5 + maxItems: 6 reg-names: + minItems: 5 items: - const: parf # Qualcomm specific registers + - const: mhi # MHI registers - const: dbi # DesignWare PCIe registers - const: elbi # External local bus interface registers - const: atu # ATU address space --=20 2.25.1 From nobody Sat Apr 11 11:48:14 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id A328EC64EC4 for ; Mon, 6 Mar 2023 15:35:19 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231194AbjCFPfR (ORCPT ); Mon, 6 Mar 2023 10:35:17 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:60002 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230332AbjCFPeW (ORCPT ); Mon, 6 Mar 2023 10:34:22 -0500 Received: from mail-pj1-x1032.google.com (mail-pj1-x1032.google.com [IPv6:2607:f8b0:4864:20::1032]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id CC5E32A981 for ; Mon, 6 Mar 2023 07:33:51 -0800 (PST) Received: by mail-pj1-x1032.google.com with SMTP id u3-20020a17090a450300b00239db6d7d47so9142247pjg.4 for ; Mon, 06 Mar 2023 07:33:51 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1678116827; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=tvJuD70O+H+sPQNrNpV5HwBBDKIiVR9W0oL4sqQ+c8g=; b=hgfdfPgxkzcoWcZ/R+cq9xjZ3F6NPOCBDoWdMpYZLOFAF1F9eqXSUFis9etAEsA3P6 cqSXs+FE5vKO0+/xzpXvA/wRUetLvClJrh5V+Tl4rErDmC2KNHRM9vkKxOrbo8AwOEr4 8lVLoF9Z52QSqqL223eR/O+B/ejROiWY20j6lvtnqOyuakBrwe5jsaajtIx2zOLz3Xml hSF2JFuNbrU2CY2Ov9qYh9elL48M5cw/I8KT6xKqfYCIPulaWBpxUNrikv7NF2tSQpHw DMBbL5HPbURUYsUwQ4jAlq09YtLArS6G42UOQ6WcbbHdZ1U/01up84YfHWZSMjEG1Lg4 Urbg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1678116827; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=tvJuD70O+H+sPQNrNpV5HwBBDKIiVR9W0oL4sqQ+c8g=; b=aoz+hkpQq4+VEaQhfijRI2Vlm6KlEFe0/i7lXEqCEf4GTrKfHluEjVuNaROQbFB0R5 l9kIRbuCtIyhiyr1aO9YT8Qf3PeQuh6lLzzRSN/PR7LDZmJ4U+w+6HxJIpqaqmy9wALS IZHkpHHd+pU7ph7aicnK9MoJ0FO4Dyqpe9VLkuwHXpsX/nHYTH/7xA5xor3LAAnTnXHQ 4ti5gQ26g7pd0z7+gQ2pqrxJOEXz7jYm7iVpfumvMxkdncT/jbDX42xFbJhtxy35KUv2 94SIt8nmGIHjiMyE+hx5OUzUXmEjW6c2mMWz9/UZsHY2Lxd6pUIyy7T3iTdgjNtqDaiR RIVQ== X-Gm-Message-State: AO0yUKVnhiCeAWjZgC1GrYm4m8zTrMHsiNBW7Gq2tUY9Wej/rmXDd3Vh xrwDpF6nettTIEJZxqPQJzp+ X-Google-Smtp-Source: AK7set8n1ClaD9Wh3bK6TU1KDVp/KEv/S2xbAzslWozdEkohVawwinrk2XH41iXV+jORtEOXWDPvJQ== X-Received: by 2002:a17:902:d4c5:b0:199:30a6:376c with SMTP id o5-20020a170902d4c500b0019930a6376cmr12206287plg.68.1678116827601; Mon, 06 Mar 2023 07:33:47 -0800 (PST) Received: from localhost.localdomain ([59.97.52.140]) by smtp.gmail.com with ESMTPSA id kl4-20020a170903074400b0019a7c890c61sm6837430plb.252.2023.03.06.07.33.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 06 Mar 2023 07:33:47 -0800 (PST) From: Manivannan Sadhasivam To: andersson@kernel.org, lpieralisi@kernel.org, kw@linux.com, krzysztof.kozlowski+dt@linaro.org, robh@kernel.org Cc: konrad.dybcio@linaro.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, quic_srichara@quicinc.com, Manivannan Sadhasivam Subject: [PATCH 16/19] arm64: dts: qcom: sdm845: Add "mhi" region to the PCIe nodes Date: Mon, 6 Mar 2023 21:02:19 +0530 Message-Id: <20230306153222.157667-17-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230306153222.157667-1-manivannan.sadhasivam@linaro.org> References: <20230306153222.157667-1-manivannan.sadhasivam@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" The "mhi" region contains the debug registers that could be used to monitor the PCIe link transitions. Signed-off-by: Manivannan Sadhasivam --- arch/arm64/boot/dts/qcom/sdm845.dtsi | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qco= m/sdm845.dtsi index 479859bd8ab3..0104e77dd8d5 100644 --- a/arch/arm64/boot/dts/qcom/sdm845.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi @@ -2280,10 +2280,11 @@ opp-4 { pcie0: pci@1c00000 { compatible =3D "qcom,pcie-sdm845"; reg =3D <0 0x01c00000 0 0x2000>, + <0 0x01c07000 0 0x1000>, <0 0x60000000 0 0xf1d>, <0 0x60000f20 0 0xa8>, <0 0x60100000 0 0x100000>; - reg-names =3D "parf", "dbi", "elbi", "config"; + reg-names =3D "parf", "mhi", "dbi", "elbi", "config"; device_type =3D "pci"; linux,pci-domain =3D <0>; bus-range =3D <0x00 0xff>; @@ -2385,10 +2386,11 @@ pcie0_lane: phy@1c06200 { pcie1: pci@1c08000 { compatible =3D "qcom,pcie-sdm845"; reg =3D <0 0x01c08000 0 0x2000>, + <0 0x01c0c000 0 0x1000>, <0 0x40000000 0 0xf1d>, <0 0x40000f20 0 0xa8>, <0 0x40100000 0 0x100000>; - reg-names =3D "parf", "dbi", "elbi", "config"; + reg-names =3D "parf", "mhi", "dbi", "elbi", "config"; device_type =3D "pci"; linux,pci-domain =3D <1>; bus-range =3D <0x00 0xff>; --=20 2.25.1 From nobody Sat Apr 11 11:48:14 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4792EC61DA4 for ; Mon, 6 Mar 2023 15:35:25 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231250AbjCFPfX (ORCPT ); Mon, 6 Mar 2023 10:35:23 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:33070 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231256AbjCFPe3 (ORCPT ); Mon, 6 Mar 2023 10:34:29 -0500 Received: from mail-pl1-x62c.google.com (mail-pl1-x62c.google.com [IPv6:2607:f8b0:4864:20::62c]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 950AF34F68 for ; Mon, 6 Mar 2023 07:34:02 -0800 (PST) Received: by mail-pl1-x62c.google.com with SMTP id y11so10809273plg.1 for ; Mon, 06 Mar 2023 07:34:02 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1678116831; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=NnPVqWv6iSzBmDnxQc4VtSAKgeV8Xu0ZVFuxyGJ5/8Q=; b=h9uEWO6MOAu8R7oW01Eab9sj4rXAsIZfUU+xWyhcxB366lWeKzn7pv00CfbimSIrtX EeTW/z/YBT96JZGC68KsI+78UQXq+NXbC+9dxjwQYZOey5o251mVzlhzboseG/WerupV j/XdbgssE/pY1Z5Un3yjPGc2nHKiql3Cxkm4M58qHBqPIMEcZ53C3jDk87gomYNqLf8z bgc/I7GVjZAH07Nkk1tOLE2u60mK3kY58mG6IRHK4cpLQdwhZEz83CufpWPjC+Vrt+aX mq8z9eclucGOenuw9arhwubVCliOorgA7cRF5MCn3Ft8BxcB2zd4e95rlQXCrhHQFEmp IHtg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1678116831; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=NnPVqWv6iSzBmDnxQc4VtSAKgeV8Xu0ZVFuxyGJ5/8Q=; b=NU/UArLb40A83CzYvP7wbSvezsUc12IcpzAQodNLVsJTyMsZ2uhqyStulAkv9N4uPv Q8H/492F4MQn9mNpJ3QqkYKusxT9Y6H48zf3gDyh19FrqcVMmT/XaNKnsrWzwjb/kFfH EEPKxMzts91L3UKvSC+KJJSgv+kzENouODaK6MEXPHWuoGmPsdjNUbpmLUAHtZJcEGjl faPnuzLR1Di2TDIW/QHx7Fx6Aiux/Z76J34+sKzqlv+g4XPlJGDP81j4N6JG55X+Za2U PP20dibs54vkUgjz0LY4T9K5KjH+n5z5a0cHnxZ6Q+tSWqPQcHEC1BysZ8dCLcMJutQx EZEw== X-Gm-Message-State: AO0yUKWE5/xIusH/+ffwsQWyL792fcpEK+bP1n44CBlnd3whmJIdH0H4 I+4ah00QkkJ6qWkRFjEfQ4rL X-Google-Smtp-Source: AK7set9zmvGkTRpSH11+q0AiJ5xXaYFf56ZC5NPxNyiv0IgCyLPG7CKjLpDvo4xSVw5x4EHOQctamA== X-Received: by 2002:a17:902:ec8d:b0:19a:a9dd:ed3f with SMTP id x13-20020a170902ec8d00b0019aa9dded3fmr13880439plg.49.1678116831680; Mon, 06 Mar 2023 07:33:51 -0800 (PST) Received: from localhost.localdomain ([59.97.52.140]) by smtp.gmail.com with ESMTPSA id kl4-20020a170903074400b0019a7c890c61sm6837430plb.252.2023.03.06.07.33.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 06 Mar 2023 07:33:51 -0800 (PST) From: Manivannan Sadhasivam To: andersson@kernel.org, lpieralisi@kernel.org, kw@linux.com, krzysztof.kozlowski+dt@linaro.org, robh@kernel.org Cc: konrad.dybcio@linaro.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, quic_srichara@quicinc.com, Manivannan Sadhasivam Subject: [PATCH 17/19] arm64: dts: qcom: sm8250: Add "mhi" region to the PCIe nodes Date: Mon, 6 Mar 2023 21:02:20 +0530 Message-Id: <20230306153222.157667-18-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230306153222.157667-1-manivannan.sadhasivam@linaro.org> References: <20230306153222.157667-1-manivannan.sadhasivam@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" The "mhi" region contains the debug registers that could be used to monitor the PCIe link transitions. Signed-off-by: Manivannan Sadhasivam --- arch/arm64/boot/dts/qcom/sm8250.dtsi | 9 ++++++--- 1 file changed, 6 insertions(+), 3 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm8250.dtsi b/arch/arm64/boot/dts/qco= m/sm8250.dtsi index 2f0e460acccd..1987ec97546a 100644 --- a/arch/arm64/boot/dts/qcom/sm8250.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8250.dtsi @@ -1821,11 +1821,12 @@ mmss_noc: interconnect@1740000 { pcie0: pci@1c00000 { compatible =3D "qcom,pcie-sm8250"; reg =3D <0 0x01c00000 0 0x3000>, + <0 0x01c03000 0 0x1000>, <0 0x60000000 0 0xf1d>, <0 0x60000f20 0 0xa8>, <0 0x60001000 0 0x1000>, <0 0x60100000 0 0x100000>; - reg-names =3D "parf", "dbi", "elbi", "atu", "config"; + reg-names =3D "parf", "mhi", "dbi", "elbi", "atu", "config"; device_type =3D "pci"; linux,pci-domain =3D <0>; bus-range =3D <0x00 0xff>; @@ -1930,11 +1931,12 @@ pcie0_lane: phy@1c06200 { pcie1: pci@1c08000 { compatible =3D "qcom,pcie-sm8250"; reg =3D <0 0x01c08000 0 0x3000>, + <0 0x01c0b000 0 0x1000>, <0 0x40000000 0 0xf1d>, <0 0x40000f20 0 0xa8>, <0 0x40001000 0 0x1000>, <0 0x40100000 0 0x100000>; - reg-names =3D "parf", "dbi", "elbi", "atu", "config"; + reg-names =3D "parf", "mhi", "dbi", "elbi", "atu", "config"; device_type =3D "pci"; linux,pci-domain =3D <1>; bus-range =3D <0x00 0xff>; @@ -2038,11 +2040,12 @@ pcie1_lane: phy@1c0e200 { pcie2: pci@1c10000 { compatible =3D "qcom,pcie-sm8250"; reg =3D <0 0x01c10000 0 0x3000>, + <0 0x01c13000 0 0x1000>, <0 0x64000000 0 0xf1d>, <0 0x64000f20 0 0xa8>, <0 0x64001000 0 0x1000>, <0 0x64100000 0 0x100000>; - reg-names =3D "parf", "dbi", "elbi", "atu", "config"; + reg-names =3D "parf", "mhi", "dbi", "elbi", "atu", "config"; device_type =3D "pci"; linux,pci-domain =3D <2>; bus-range =3D <0x00 0xff>; --=20 2.25.1 From nobody Sat Apr 11 11:48:15 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id A5F00C61DA4 for ; Mon, 6 Mar 2023 15:35:21 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231210AbjCFPfU (ORCPT ); Mon, 6 Mar 2023 10:35:20 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:33332 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231196AbjCFPe1 (ORCPT ); Mon, 6 Mar 2023 10:34:27 -0500 Received: from mail-pl1-x62e.google.com (mail-pl1-x62e.google.com [IPv6:2607:f8b0:4864:20::62e]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 06BED34F54 for ; Mon, 6 Mar 2023 07:33:56 -0800 (PST) Received: by mail-pl1-x62e.google.com with SMTP id u5so10765138plq.7 for ; Mon, 06 Mar 2023 07:33:56 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1678116835; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=g0HkTzoYYR05RgcCQCmtwD2GE4b0NXnbyOM+nFetWrg=; b=D6ntHtnnhgHWVvdz49MO9xHA9ktXCiifFFruGqkj+XK0Llmish+oypJoKvF1aXcxkB gA9UsiwmRd40G4dVn3kxhUEv9Bex3SAtOVK51AF/pRf1SVAH+BAPnTVyn1f9v5tgFWWO z/XsI1zkXQXtybcTtnK9MP6aC8dD7aPBZM1AU8HIW1JXnrb1Uou49wVvGVsTomg1WyG5 H+29IkkNL2xFvpYPZZGq0aTXJnSaH1UEkaNekiaGPL11MsH5R5TKSlsxHX00GKUxQx6Y opywpDXyu1WG3Vs2y4aYh3G/6bpHXGi4fUijb2qTN/sWk+/YxBc7SlvyhBmTLWbBmxhz VAxQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1678116835; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=g0HkTzoYYR05RgcCQCmtwD2GE4b0NXnbyOM+nFetWrg=; b=trClI7pa145oLhNEj4sv+EEWDmczYcowbdiPuKsAYu5API0PGvHuO3n30hNryT5WqC 6foIC/tMXQYdixEYPM0WBufqsHa9uIWoqMGP4SiVUGrwaZ7R4O2ZMoNrXX4eXxKfdwTd ewJRDn9RRBgLycJAY+4HFCVoD0hGfigpZg6ghfpJ74Arap/T2Vhc7XTr/Tdp98b830fA sQIgL6ccQJyE7Qvtfleoi9gsgfWbT84yblXL6qK6Osl/kufuNTReUFUzhAET2Pv9rIlr w1oTdLkIBgBuozkM++YfIGyE8rsmZBwUuXmhpNP1gylqc02/7jbT+DcIBpKaIs1wP9uU 9PCA== X-Gm-Message-State: AO0yUKVOfEQCREiv8eXjfRW3ynbfz9QGnKkgwsyJKU9kTw6lDQ8rbz3e TGcsxP8RQAUteoadSI3iSJ5U X-Google-Smtp-Source: AK7set8S2Uvm5ccNl5/5SvtHMVLLac00gbXkO3lCAa+QYPC2cMP3c30S7MdEPCb1bDH10QBVjtdyYA== X-Received: by 2002:a17:902:e741:b0:19e:7bd2:a224 with SMTP id p1-20020a170902e74100b0019e7bd2a224mr14494148plf.62.1678116835643; Mon, 06 Mar 2023 07:33:55 -0800 (PST) Received: from localhost.localdomain ([59.97.52.140]) by smtp.gmail.com with ESMTPSA id kl4-20020a170903074400b0019a7c890c61sm6837430plb.252.2023.03.06.07.33.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 06 Mar 2023 07:33:55 -0800 (PST) From: Manivannan Sadhasivam To: andersson@kernel.org, lpieralisi@kernel.org, kw@linux.com, krzysztof.kozlowski+dt@linaro.org, robh@kernel.org Cc: konrad.dybcio@linaro.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, quic_srichara@quicinc.com, Manivannan Sadhasivam Subject: [PATCH 18/19] arm64: dts: qcom: sc8280xp: Add "mhi" region to the PCIe nodes Date: Mon, 6 Mar 2023 21:02:21 +0530 Message-Id: <20230306153222.157667-19-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230306153222.157667-1-manivannan.sadhasivam@linaro.org> References: <20230306153222.157667-1-manivannan.sadhasivam@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" The "mhi" region contains the debug registers that could be used to monitor the PCIe link transitions. Signed-off-by: Manivannan Sadhasivam --- arch/arm64/boot/dts/qcom/sc8280xp.dtsi | 15 ++++++++++----- 1 file changed, 10 insertions(+), 5 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi b/arch/arm64/boot/dts/q= com/sc8280xp.dtsi index 0d02599d8867..5c7f40345992 100644 --- a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi +++ b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi @@ -1650,11 +1650,12 @@ pcie4: pcie@1c00000 { device_type =3D "pci"; compatible =3D "qcom,pcie-sc8280xp"; reg =3D <0x0 0x01c00000 0x0 0x3000>, + <0x0 0x01c03000 0x0 0x1000>, <0x0 0x30000000 0x0 0xf1d>, <0x0 0x30000f20 0x0 0xa8>, <0x0 0x30001000 0x0 0x1000>, <0x0 0x30100000 0x0 0x100000>; - reg-names =3D "parf", "dbi", "elbi", "atu", "config"; + reg-names =3D "parf", "mhi", "dbi", "elbi", "atu", "config"; #address-cells =3D <3>; #size-cells =3D <2>; ranges =3D <0x01000000 0x0 0x30200000 0x0 0x30200000 0x0 0x100000>, @@ -1749,11 +1750,12 @@ pcie3b: pcie@1c08000 { device_type =3D "pci"; compatible =3D "qcom,pcie-sc8280xp"; reg =3D <0x0 0x01c08000 0x0 0x3000>, + <0x0 0x01c0b000 0x0 0x1000>, <0x0 0x32000000 0x0 0xf1d>, <0x0 0x32000f20 0x0 0xa8>, <0x0 0x32001000 0x0 0x1000>, <0x0 0x32100000 0x0 0x100000>; - reg-names =3D "parf", "dbi", "elbi", "atu", "config"; + reg-names =3D "parf", "mhi", "dbi", "elbi", "atu", "config"; #address-cells =3D <3>; #size-cells =3D <2>; ranges =3D <0x01000000 0x0 0x32200000 0x0 0x32200000 0x0 0x100000>, @@ -1846,11 +1848,12 @@ pcie3a: pcie@1c10000 { device_type =3D "pci"; compatible =3D "qcom,pcie-sc8280xp"; reg =3D <0x0 0x01c10000 0x0 0x3000>, + <0x0 0x01c13000 0x0 0x1000>, <0x0 0x34000000 0x0 0xf1d>, <0x0 0x34000f20 0x0 0xa8>, <0x0 0x34001000 0x0 0x1000>, <0x0 0x34100000 0x0 0x100000>; - reg-names =3D "parf", "dbi", "elbi", "atu", "config"; + reg-names =3D "parf", "mhi", "dbi", "elbi", "atu", "config"; #address-cells =3D <3>; #size-cells =3D <2>; ranges =3D <0x01000000 0x0 0x34200000 0x0 0x34200000 0x0 0x100000>, @@ -1946,11 +1949,12 @@ pcie2b: pcie@1c18000 { device_type =3D "pci"; compatible =3D "qcom,pcie-sc8280xp"; reg =3D <0x0 0x01c18000 0x0 0x3000>, + <0x0 0x01c1b000 0x0 0x1000>, <0x0 0x38000000 0x0 0xf1d>, <0x0 0x38000f20 0x0 0xa8>, <0x0 0x38001000 0x0 0x1000>, <0x0 0x38100000 0x0 0x100000>; - reg-names =3D "parf", "dbi", "elbi", "atu", "config"; + reg-names =3D "parf", "mhi", "dbi", "elbi", "atu", "config"; #address-cells =3D <3>; #size-cells =3D <2>; ranges =3D <0x01000000 0x0 0x38200000 0x0 0x38200000 0x0 0x100000>, @@ -2043,11 +2047,12 @@ pcie2a: pcie@1c20000 { device_type =3D "pci"; compatible =3D "qcom,pcie-sc8280xp"; reg =3D <0x0 0x01c20000 0x0 0x3000>, + <0x0 0x01c23000 0x0 0x1000>, <0x0 0x3c000000 0x0 0xf1d>, <0x0 0x3c000f20 0x0 0xa8>, <0x0 0x3c001000 0x0 0x1000>, <0x0 0x3c100000 0x0 0x100000>; - reg-names =3D "parf", "dbi", "elbi", "atu", "config"; + reg-names =3D "parf", "mhi", "dbi", "elbi", "atu", "config"; #address-cells =3D <3>; #size-cells =3D <2>; ranges =3D <0x01000000 0x0 0x3c200000 0x0 0x3c200000 0x0 0x100000>, --=20 2.25.1 From nobody Sat Apr 11 11:48:15 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id A34CFC61DA4 for ; Mon, 6 Mar 2023 15:35:28 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231308AbjCFPf1 (ORCPT ); Mon, 6 Mar 2023 10:35:27 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:60824 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231408AbjCFPeq (ORCPT ); Mon, 6 Mar 2023 10:34:46 -0500 Received: from mail-pj1-x102c.google.com (mail-pj1-x102c.google.com [IPv6:2607:f8b0:4864:20::102c]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 0D2E036476 for ; Mon, 6 Mar 2023 07:34:11 -0800 (PST) Received: by mail-pj1-x102c.google.com with SMTP id oj5so10132967pjb.5 for ; Mon, 06 Mar 2023 07:34:11 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1678116839; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=uQSjdI7jzklikUEcdFC/m9MKhjlXYCglW0uRGmTAYhE=; b=oGw/hu1X4G3ndPSHZlB2CwZ1u14B1WYeLN+VJ8vLY/537eulqI4hhOd+tY+F7gtwk0 EInBDUc+DABgs4PmoOYDoiYk6FEHTIERbt72x/NncWPS16cdys8sucX+bevwtwx1FY0W VMKdDGoB+7dx3BkQ1kz/1FfKkvYRDh56UI7Tc0rsHrAWFuVG5PkGim35BpxIAH+MnO25 q7JeT+F4sg53C0HbJb12ZM9+9CYi44QI4pGiLbbzXET54AliynlVtCs0dzCo0uGbAD1R uaG/5KwjQ5TnqA0fpf5HfQr31lCvGgcQCcPXyfEoFjZn8ZXPkpdilC7+uXRhGwaZrv2c WhRQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1678116839; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=uQSjdI7jzklikUEcdFC/m9MKhjlXYCglW0uRGmTAYhE=; b=Vs+bquhVOomt//Sxu64BYUcOLqoHhRMjPKmJwby7CKWLBbnHUTwqXm5ZOE+cEKcAgl 4FOzs417yVkqhpNtq7hc86qa6t53GH6x4nYRnRyQs2hrOdgkM/fDelwyYJL/7nEy5zga AE8noN7UQ9UM5/fJSAwpPnBDD0aNZ++/M0J8tUqOzH8mh5CESxwkKBSAsG1QkV99j2Ft wJ/atMqhY4jcatTXO2rNE69gc1ERnDzcgo6nzR7cLKdaHhJmh3YdqCwfkaAFyiIhPFOr T2DDLXqtCP7bW552kTzdDKCTjs8jM4MGHXva4gTG6WCsvBfOnlzFlsyRUaKb265DUhaz CEmQ== X-Gm-Message-State: AO0yUKWMTg1NGF+QdkexiG7hBC9KcdxUaCAp8ewkRnbbTk3p5WJtXfe5 17WPyAAseKWNI/puKHlQ2Hpu X-Google-Smtp-Source: AK7set8YCJcbzbYudivA+ICnxXe6OZxc8x4lQ7rD0D0O7XCz0vraQeG88OIyptrFcyxV7E/UdRgKUQ== X-Received: by 2002:a17:903:283:b0:19c:d309:4612 with SMTP id j3-20020a170903028300b0019cd3094612mr14325092plr.6.1678116839683; Mon, 06 Mar 2023 07:33:59 -0800 (PST) Received: from localhost.localdomain ([59.97.52.140]) by smtp.gmail.com with ESMTPSA id kl4-20020a170903074400b0019a7c890c61sm6837430plb.252.2023.03.06.07.33.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 06 Mar 2023 07:33:59 -0800 (PST) From: Manivannan Sadhasivam To: andersson@kernel.org, lpieralisi@kernel.org, kw@linux.com, krzysztof.kozlowski+dt@linaro.org, robh@kernel.org Cc: konrad.dybcio@linaro.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, quic_srichara@quicinc.com, Manivannan Sadhasivam Subject: [PATCH 19/19] PCI: qcom: Expose link transition counts via debugfs Date: Mon, 6 Mar 2023 21:02:22 +0530 Message-Id: <20230306153222.157667-20-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230306153222.157667-1-manivannan.sadhasivam@linaro.org> References: <20230306153222.157667-1-manivannan.sadhasivam@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Qualcomm PCIe controllers have debug registers in the MHI region that count PCIe link transitions. Expose them over debugfs to userspace to help debug the low power issues. Note that even though the registers are prefixed as PARF_, they don't live under the "parf" register region. The register naming is following the Qualcomm's internal documentation as like other registers. Signed-off-by: Manivannan Sadhasivam --- drivers/pci/controller/dwc/pcie-qcom.c | 59 ++++++++++++++++++++++++++ 1 file changed, 59 insertions(+) diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controlle= r/dwc/pcie-qcom.c index e1180c84f0fa..6d9bde64c9e9 100644 --- a/drivers/pci/controller/dwc/pcie-qcom.c +++ b/drivers/pci/controller/dwc/pcie-qcom.c @@ -10,6 +10,7 @@ =20 #include #include +#include #include #include #include @@ -62,6 +63,13 @@ #define AXI_MSTR_RESP_COMP_CTRL1 0x81c #define MISC_CONTROL_1_REG 0x8bc =20 +/* MHI registers */ +#define PARF_DEBUG_CNT_PM_LINKST_IN_L2 0xc04 +#define PARF_DEBUG_CNT_PM_LINKST_IN_L1 0xc0c +#define PARF_DEBUG_CNT_PM_LINKST_IN_L0S 0xc10 +#define PARF_DEBUG_CNT_AUX_CLK_IN_L1SUB_L1 0xc84 +#define PARF_DEBUG_CNT_AUX_CLK_IN_L1SUB_L2 0xc88 + /* PARF_SYS_CTRL register fields */ #define MAC_PHY_POWERDOWN_IN_P2_D_MUX_EN BIT(29) #define MST_WAKEUP_EN BIT(13) @@ -229,11 +237,13 @@ struct qcom_pcie { struct dw_pcie *pci; void __iomem *parf; /* DT parf */ void __iomem *elbi; /* DT elbi */ + void __iomem *mhi; union qcom_pcie_resources res; struct phy *phy; struct gpio_desc *reset; struct icc_path *icc_mem; const struct qcom_pcie_cfg *cfg; + struct dentry *debugfs; }; =20 #define to_qcom_pcie(x) dev_get_drvdata((x)->dev) @@ -1385,6 +1395,37 @@ static void qcom_pcie_icc_update(struct qcom_pcie *p= cie) } } =20 +static int qcom_pcie_link_transition_count(struct seq_file *s, void *data) +{ + struct qcom_pcie *pcie =3D (struct qcom_pcie *) + dev_get_drvdata(s->private); + + seq_printf(s, "L0s transition count: %u\n", + readl_relaxed(pcie->mhi + PARF_DEBUG_CNT_PM_LINKST_IN_L0S)); + + seq_printf(s, "L1 transition count: %u\n", + readl_relaxed(pcie->mhi + PARF_DEBUG_CNT_PM_LINKST_IN_L1)); + + seq_printf(s, "L1.1 transition count: %u\n", + readl_relaxed(pcie->mhi + PARF_DEBUG_CNT_AUX_CLK_IN_L1SUB_L1)); + + seq_printf(s, "L1.2 transition count: %u\n", + readl_relaxed(pcie->mhi + PARF_DEBUG_CNT_AUX_CLK_IN_L1SUB_L2)); + + seq_printf(s, "L2 transition count: %u\n", + readl_relaxed(pcie->mhi + PARF_DEBUG_CNT_PM_LINKST_IN_L2)); + + return 0; +} + +static void qcom_pcie_init_debugfs(struct qcom_pcie *pcie) +{ + struct dw_pcie *pci =3D pcie->pci; + + debugfs_create_devm_seqfile(pci->dev, "link_transition_count", pcie->debu= gfs, + qcom_pcie_link_transition_count); +} + static int qcom_pcie_probe(struct platform_device *pdev) { struct device *dev =3D &pdev->dev; @@ -1392,6 +1433,7 @@ static int qcom_pcie_probe(struct platform_device *pd= ev) struct dw_pcie *pci; struct qcom_pcie *pcie; const struct qcom_pcie_cfg *pcie_cfg; + char *name; int ret; =20 pcie_cfg =3D of_device_get_match_data(dev); @@ -1439,6 +1481,12 @@ static int qcom_pcie_probe(struct platform_device *p= dev) goto err_pm_runtime_put; } =20 + pcie->mhi =3D devm_platform_ioremap_resource_byname(pdev, "mhi"); + if (IS_ERR(pcie->mhi)) { + ret =3D PTR_ERR(pcie->mhi); + goto err_pm_runtime_put; + } + pcie->phy =3D devm_phy_optional_get(dev, "pciephy"); if (IS_ERR(pcie->phy)) { ret =3D PTR_ERR(pcie->phy); @@ -1469,8 +1517,19 @@ static int qcom_pcie_probe(struct platform_device *p= dev) =20 qcom_pcie_icc_update(pcie); =20 + name =3D devm_kasprintf(dev, GFP_KERNEL, "%pOFP", dev->of_node); + if (!name) { + ret =3D -ENOMEM; + goto err_host_deinit; + } + + pcie->debugfs =3D debugfs_create_dir(name, NULL); + qcom_pcie_init_debugfs(pcie); + return 0; =20 +err_host_deinit: + dw_pcie_host_deinit(&pcie->pci->pp); err_phy_exit: phy_exit(pcie->phy); err_pm_runtime_put: --=20 2.25.1