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[83.9.29.16]) by smtp.gmail.com with ESMTPSA id b8-20020ac25e88000000b004e845a08567sm824678lfq.291.2023.03.15.07.11.24 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 15 Mar 2023 07:11:25 -0700 (PDT) From: Konrad Dybcio Date: Wed, 15 Mar 2023 15:11:19 +0100 Subject: [PATCH v3 1/7] dt-bindings: interconnect: qcom,msm8998-bwmon: Resolve MSM8998 support MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20230304-topic-ddr_bwmon-v3-1-77a050c2fbda@linaro.org> References: <20230304-topic-ddr_bwmon-v3-0-77a050c2fbda@linaro.org> In-Reply-To: <20230304-topic-ddr_bwmon-v3-0-77a050c2fbda@linaro.org> To: Andy Gross , Bjorn Andersson , Krzysztof Kozlowski , Georgi Djakov , Rob Herring , Thara Gopinath , Krzysztof Kozlowski Cc: linux-arm-msm@vger.kernel.org, linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Konrad Dybcio , Marijn Suijten X-Mailer: b4 0.12.1 X-Developer-Signature: v=1; a=ed25519-sha256; t=1678889480; l=3198; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=46GX24BwrnA0NyNxXdAtsdOmycpBdNb3M3oef2DCgaI=; b=WWKutA0jBcYE25QwX++BpXSspC7Fp3hZSBClmXDaadptiAxrADsX0C6EleInwHhzoTY6QeHRr0wi ctno1RGrAPxxz5R0JFl7Uhj6Hej8dn8hVdWghI/57tb9b+q51Gx8 X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org BWMONv4 has two sets of registers: one for handling the monitor itself and one called "global" which hosts some sort of a headswitch and an interrupt control register. We did not handle that one before, as on SoCs starting with SDM845 they have been merged into a single contiguous range. To make the qcom,msm8998-bwmon less confusing and in preparation for actual MSM8998 support, describe the global register space and introduce new "qcom,sdm845-cpu-bwmon" compatible while keeping the "qcom,sdm845-bwmon" as a fallback for SoCs with this merged register space scheme. Reviewed-by: Krzysztof Kozlowski Signed-off-by: Konrad Dybcio --- .../bindings/interconnect/qcom,msm8998-bwmon.yaml | 41 ++++++++++++++++++= ---- 1 file changed, 34 insertions(+), 7 deletions(-) diff --git a/Documentation/devicetree/bindings/interconnect/qcom,msm8998-bw= mon.yaml b/Documentation/devicetree/bindings/interconnect/qcom,msm8998-bwmo= n.yaml index 12a0d3ecbabb..5d17bdcfdf70 100644 --- a/Documentation/devicetree/bindings/interconnect/qcom,msm8998-bwmon.yaml +++ b/Documentation/devicetree/bindings/interconnect/qcom,msm8998-bwmon.yaml @@ -22,14 +22,14 @@ description: | properties: compatible: oneOf: + - const: qcom,msm8998-bwmon # BWMON v4 - items: - enum: - qcom,sc7280-cpu-bwmon - qcom,sc8280xp-cpu-bwmon - - qcom,sdm845-bwmon + - qcom,sdm845-cpu-bwmon - qcom,sm8550-cpu-bwmon - - const: qcom,msm8998-bwmon - - const: qcom,msm8998-bwmon # BWMON v4 + - const: qcom,sdm845-bwmon # BWMON v4, unified register space - items: - enum: - qcom,sc8280xp-llcc-bwmon @@ -49,9 +49,13 @@ properties: type: object =20 reg: - # BWMON v4 (currently described) and BWMON v5 use one register address - # space. BWMON v2 uses two register spaces - not yet described. - maxItems: 1 + # BWMON v5 uses one register address space, v1-v4 use one or two. + minItems: 1 + maxItems: 2 + + reg-names: + minItems: 1 + maxItems: 2 =20 required: - compatible @@ -63,13 +67,36 @@ required: =20 additionalProperties: false =20 +allOf: + - if: + properties: + compatible: + const: qcom,msm8998-bwmon + then: + properties: + reg: + minItems: 2 + + reg-names: + items: + - const: monitor + - const: global + + else: + properties: + reg: + maxItems: 1 + + reg-names: + maxItems: 1 + examples: - | #include #include =20 pmu@1436400 { - compatible =3D "qcom,sdm845-bwmon", "qcom,msm8998-bwmon"; + compatible =3D "qcom,sdm845-cpu-bwmon", "qcom,sdm845-bwmon"; reg =3D <0x01436400 0x600>; interrupts =3D ; interconnects =3D <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLA= VE_LLCC 3>; --=20 2.39.2 From nobody Wed Feb 11 10:20:59 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 96A5BC61DA4 for ; Wed, 15 Mar 2023 14:11:43 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232381AbjCOOLl (ORCPT ); Wed, 15 Mar 2023 10:11:41 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:49524 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232878AbjCOOLd (ORCPT ); Wed, 15 Mar 2023 10:11:33 -0400 Received: from mail-lf1-x132.google.com (mail-lf1-x132.google.com [IPv6:2a00:1450:4864:20::132]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id A06F76772B for ; Wed, 15 Mar 2023 07:11:30 -0700 (PDT) Received: by mail-lf1-x132.google.com with SMTP id y20so1898353lfj.2 for ; Wed, 15 Mar 2023 07:11:30 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1678889489; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=3GQC372p350UPtIPazu4oAK/bKFzzByhaQ607sxvNsw=; b=bMCLdOfJluKG93B8X14Nwvuclf3pIxYV9nJ44F8j74KokL5uGvwX6qtV/nIERxr1MI 4tELUHZqrpzvfSc2j7VvQhq62SkbPdt6P8DlFlk6uNflt0wALcX49ZDOBBI590gBwmev TwhTDO5zBH0JlLwREURezNvS4tngu339X61BXg1JYkvG6t4P3Sllg6t5BSRfRzQZbitl Ud6irwWAPtybBBI0ppbyQoAUR2CA9XIXzCDsS+4iweP4l4nt8i1VgswZD0dl2w2uzQl3 j+Eq18n9brkSU1mI30uYOM1krysO2lgfH5+oKIIy+accMdfBK2SVjSpz+sIUzI0kCcII nQpQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1678889489; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=3GQC372p350UPtIPazu4oAK/bKFzzByhaQ607sxvNsw=; b=ZV4tE8/7TFp0Npj3gwZzwWikOCnvHthllovlC0kYbMYLTSHsMRgJo7pDaoXF/E+Kki zOm3Ny+JVUT/dettwDFFg/yAH46g3v6PyMsnm6AygjWgQ/7CW7QrpQpkQ8Dk8tZoE63D QMwTYvb8KWwrGuR+QeyRg3S8YjPm6Gk0UQroeIYF8wKe9luio3nDOFgnwr0YsTD4H+xm zN8YXQZG0Nn8RYhzofbwcDfuya/vaQJobXKsVdcCrCOEsKgRNEyonLBHR5lpTZVIzwDZ r4vFsrjio0BMpGe0X0Fdsc0YdcOACVySdL8gieVAQkeNTAZZmflmoCt2t4jqMNIcDrsv oHjA== X-Gm-Message-State: AO0yUKX2/WaNd6FdcCo7YGL3yuh6dBt3WpQLiK7JAH2d8uqUZHD3Rp3d rAc70Obj2R1PQNILxw5KgfNQjQ== X-Google-Smtp-Source: AK7set9o805hGVxYPiz65okFpyO220Y0Q8INLHwXyZy6iH2TNwPx1vH5IdQY6ziOwj2AlfmjrlnkjA== X-Received: by 2002:ac2:531c:0:b0:4e8:595c:60f9 with SMTP id c28-20020ac2531c000000b004e8595c60f9mr929959lfh.32.1678889488911; Wed, 15 Mar 2023 07:11:28 -0700 (PDT) Received: from [192.168.1.101] (abyj16.neoplus.adsl.tpnet.pl. [83.9.29.16]) by smtp.gmail.com with ESMTPSA id b8-20020ac25e88000000b004e845a08567sm824678lfq.291.2023.03.15.07.11.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 15 Mar 2023 07:11:27 -0700 (PDT) From: Konrad Dybcio Date: Wed, 15 Mar 2023 15:11:20 +0100 Subject: [PATCH v3 2/7] soc: qcom: icc-bwmon: Remove unused struct member MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20230304-topic-ddr_bwmon-v3-2-77a050c2fbda@linaro.org> References: <20230304-topic-ddr_bwmon-v3-0-77a050c2fbda@linaro.org> In-Reply-To: <20230304-topic-ddr_bwmon-v3-0-77a050c2fbda@linaro.org> To: Andy Gross , Bjorn Andersson , Krzysztof Kozlowski , Georgi Djakov , Rob Herring , Thara Gopinath , Krzysztof Kozlowski Cc: linux-arm-msm@vger.kernel.org, linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Konrad Dybcio , Marijn Suijten X-Mailer: b4 0.12.1 X-Developer-Signature: v=1; a=ed25519-sha256; t=1678889480; l=829; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=GxK3RcvPqvln4dblV3dJH1wiiHqaQgKRfsfh0wbDHFI=; b=IUdpG314IQktpj0Td1iiXq+sbbjJkBs31p8n7U7SlhJh3ZNTYng5PeMJKje6xOBOjPvqSKy7MQgE SY083UvyAnLJYhlQyxXXqSPDcNogGDYi64sglWLpWELQH3mkFn86 X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org bwmon->regmap was never used, as the regmap for bwmon is registered through devres and accessed through bwmon's regmap_field members. Remove it Fixes: ec63dcd3c863 ("soc: qcom: icc-bwmon: use regmap and prepare for BWMO= N v5") Reviewed-by: Krzysztof Kozlowski Signed-off-by: Konrad Dybcio --- drivers/soc/qcom/icc-bwmon.c | 1 - 1 file changed, 1 deletion(-) diff --git a/drivers/soc/qcom/icc-bwmon.c b/drivers/soc/qcom/icc-bwmon.c index d07be3700db6..d45caf512e2d 100644 --- a/drivers/soc/qcom/icc-bwmon.c +++ b/drivers/soc/qcom/icc-bwmon.c @@ -164,7 +164,6 @@ struct icc_bwmon { const struct icc_bwmon_data *data; int irq; =20 - struct regmap *regmap; struct regmap_field *regs[F_NUM_FIELDS]; =20 unsigned int max_bw_kbps; --=20 2.39.2 From nobody Wed Feb 11 10:20:59 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 29F3CC61DA4 for ; Wed, 15 Mar 2023 14:11:48 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232353AbjCOOLq (ORCPT ); Wed, 15 Mar 2023 10:11:46 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:49704 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232946AbjCOOLh (ORCPT ); Wed, 15 Mar 2023 10:11:37 -0400 Received: from mail-lf1-x12c.google.com (mail-lf1-x12c.google.com [IPv6:2a00:1450:4864:20::12c]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id B29C1521EB for ; Wed, 15 Mar 2023 07:11:31 -0700 (PDT) Received: by mail-lf1-x12c.google.com with SMTP id g17so24500785lfv.4 for ; Wed, 15 Mar 2023 07:11:31 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1678889491; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=3N7Hjcr2PZGVfKJQdXc+HZpWhdde40yz4tbRtMjIzn4=; b=xWHah0xmgpZ/mKNlmVhUkznJxDid2Y2Vrf5LUZ3Hl8dEJSwj3WgHsb+e+rldyq4WxC pxy2wlOnjEHRku4STkdF4RBhvMlTQ6ohRE7sY2TEhIzuUxapC2hEL9NZzLUGEXS62j+C 0cYtCRuVj/5rO19UagynVC5kMo8yL3nuImBKQRjhmHd54M35k/dTog1waO4Z1Hi3LF/L j6UH+BkCPOWOhSqiVZFYw66zwWG7esOJwqqD79M1YWme5M6G+OHHzn07k/tNHiYgqby4 1nfybkLwE8J/umhD7yNLvOkJeRh1ApJfW1tnjAjCZR2Qy+P79Le3ljj95pi/cGlM8VnT fNvg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1678889491; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=3N7Hjcr2PZGVfKJQdXc+HZpWhdde40yz4tbRtMjIzn4=; b=ACZpmtyJUJrzauKp45koPvE5gTHH7wwd+jkJLpelzxRlXTVDK4WSaR0/TEGTtutrAg rZm4H3yvHPByo7XJjWbCK7MsMiCnLVgHkqXwkN3dTpuGgpVuDH8YoMyE/qHarxM3kQyl 3RGtCM66jH8ceQE4INeLi/pPRVu3ojMSxgAsRD45cgP0Nmc0zYvLMFQUewDX5Nizj9CR DauVqjdxAay0UVEEZXoRLs8fnKTp5vBBXIcB7QYguLmPXFW8TzSkYxNWIZXbGkCJ99zz dUEK/r7L/Cq5CluflT3HN8TkN9TIwMs1vYnzzQpsfml3S77JHdKZSk11urCDy+kPgnBV JyJQ== X-Gm-Message-State: AO0yUKWyy8D/baCazKlZOeMdAkvp9Gg6lB+ZuwZZKbFPAXhdfmGIcqon Lri4vNxrspsyh+H3zSO3Ve4ufQ== X-Google-Smtp-Source: AK7set808RvWuOaT9i1uSL0FnsaeK8jB0OlgMQ/hLwKTN+gDkPYl2DupbjcE6nOdmMItz4Bb8n9hmw== X-Received: by 2002:a05:6512:4dc:b0:4e8:49f6:674f with SMTP id w28-20020a05651204dc00b004e849f6674fmr1676008lfq.36.1678889490768; Wed, 15 Mar 2023 07:11:30 -0700 (PDT) Received: from [192.168.1.101] (abyj16.neoplus.adsl.tpnet.pl. [83.9.29.16]) by smtp.gmail.com with ESMTPSA id b8-20020ac25e88000000b004e845a08567sm824678lfq.291.2023.03.15.07.11.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 15 Mar 2023 07:11:30 -0700 (PDT) From: Konrad Dybcio Date: Wed, 15 Mar 2023 15:11:21 +0100 Subject: [PATCH v3 3/7] soc: qcom: icc-bwmon: Handle global registers correctly MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20230304-topic-ddr_bwmon-v3-3-77a050c2fbda@linaro.org> References: <20230304-topic-ddr_bwmon-v3-0-77a050c2fbda@linaro.org> In-Reply-To: <20230304-topic-ddr_bwmon-v3-0-77a050c2fbda@linaro.org> To: Andy Gross , Bjorn Andersson , Krzysztof Kozlowski , Georgi Djakov , Rob Herring , Thara Gopinath , Krzysztof Kozlowski Cc: linux-arm-msm@vger.kernel.org, linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Konrad Dybcio , Marijn Suijten X-Mailer: b4 0.12.1 X-Developer-Signature: v=1; a=ed25519-sha256; t=1678889480; l=15677; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=+E/FiEc3YfiZWKRvWhE0s83huKfmblgyJVvmNE9VGcc=; b=MPAGQUW9Hn2+Y1VtmbmgxsPZrEyIeps4lu8VO+suJiPkAhGBWt2wfTAjYfbEzRp/7UCvmuE3YWik imobrtXbCIjCvT3VEhaWelor1fEyCqL8MP545yd1ucTeR8YSJxvB X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The BWMON hardware has two sets of registers: one for the monitor itself and one called "global". It has what seems to be some kind of a head switch and an interrupt control register. It's usually 0x200 in size. On fairly recent SoCs (with the starting point seemingly being moving the OSM programming to the firmware) these two register sets are contiguous and overlapping, like this (on sm8450): /* notice how base.start =3D=3D global_base.start+0x100 */ reg =3D <0x90b6400 0x300>, <0x90b6300 0x200>; reg-names =3D "base", "global_base"; Which led to some confusion and the assumption that since the "interesting" global registers begin right after global_base+0x100, there's no need to map two separate regions and one can simply subtract 0x100 from the offsets. This is however not the case for anything older than SDM845, as the global region can appear in seemingly random spots on the register map. Handle the case where the global registers are mapped separately to allow proper functioning of BWMONv4 on MSM8998 and older. Add specific compatibles for 845, 8280xp, 7280 and 8550 (all of which use the single reg space scheme) to keep backwards compatibility with old DTs. Signed-off-by: Konrad Dybcio Reviewed-by: Krzysztof Kozlowski --- drivers/soc/qcom/icc-bwmon.c | 230 +++++++++++++++++++++++++++++++++++++++= ---- 1 file changed, 209 insertions(+), 21 deletions(-) diff --git a/drivers/soc/qcom/icc-bwmon.c b/drivers/soc/qcom/icc-bwmon.c index d45caf512e2d..fd58c5b69897 100644 --- a/drivers/soc/qcom/icc-bwmon.c +++ b/drivers/soc/qcom/icc-bwmon.c @@ -34,14 +34,27 @@ /* Internal sampling clock frequency */ #define HW_TIMER_HZ 19200000 =20 -#define BWMON_V4_GLOBAL_IRQ_CLEAR 0x008 -#define BWMON_V4_GLOBAL_IRQ_ENABLE 0x00c +#define BWMON_V4_GLOBAL_IRQ_CLEAR 0x108 +#define BWMON_V4_GLOBAL_IRQ_ENABLE 0x10c /* * All values here and further are matching regmap fields, so without abso= lute * register offsets. */ #define BWMON_V4_GLOBAL_IRQ_ENABLE_ENABLE BIT(0) =20 +/* + * Starting with SDM845, the BWMON4 register space has changed a bit: + * the global registers were jammed into the beginning of the monitor regi= on. + * To keep the proper offsets, one would have to map a= nd + * , which is straight up wrong. + * To facilitate for that, while allowing the older, arguably more proper + * implementations to work, offset the global registers by -0x100 to avoid + * having to map half of the global registers twice. + */ +#define BWMON_V4_845_OFFSET 0x100 +#define BWMON_V4_GLOBAL_IRQ_CLEAR_845 (BWMON_V4_GLOBAL_IRQ_CLEAR - BWMON_= V4_845_OFFSET) +#define BWMON_V4_GLOBAL_IRQ_ENABLE_845 (BWMON_V4_GLOBAL_IRQ_ENABLE - BWMO= N_V4_845_OFFSET) + #define BWMON_V4_IRQ_STATUS 0x100 #define BWMON_V4_IRQ_CLEAR 0x108 =20 @@ -118,9 +131,13 @@ #define BWMON_NEEDS_FORCE_CLEAR BIT(1) =20 enum bwmon_fields { + /* Global region fields, keep them at the top */ F_GLOBAL_IRQ_CLEAR, F_GLOBAL_IRQ_ENABLE, - F_IRQ_STATUS, + F_NUM_GLOBAL_FIELDS, + + /* Monitor region fields */ + F_IRQ_STATUS =3D F_NUM_GLOBAL_FIELDS, F_IRQ_CLEAR, F_IRQ_ENABLE, F_ENABLE, @@ -157,6 +174,9 @@ struct icc_bwmon_data { =20 const struct regmap_config *regmap_cfg; const struct reg_field *regmap_fields; + + const struct regmap_config *global_regmap_cfg; + const struct reg_field *global_regmap_fields; }; =20 struct icc_bwmon { @@ -165,6 +185,7 @@ struct icc_bwmon { int irq; =20 struct regmap_field *regs[F_NUM_FIELDS]; + struct regmap_field *global_regs[F_NUM_GLOBAL_FIELDS]; =20 unsigned int max_bw_kbps; unsigned int min_bw_kbps; @@ -174,8 +195,8 @@ struct icc_bwmon { =20 /* BWMON v4 */ static const struct reg_field msm8998_bwmon_reg_fields[] =3D { - [F_GLOBAL_IRQ_CLEAR] =3D REG_FIELD(BWMON_V4_GLOBAL_IRQ_CLEAR, 0, 0), - [F_GLOBAL_IRQ_ENABLE] =3D REG_FIELD(BWMON_V4_GLOBAL_IRQ_ENABLE, 0, 0), + [F_GLOBAL_IRQ_CLEAR] =3D {}, + [F_GLOBAL_IRQ_ENABLE] =3D {}, [F_IRQ_STATUS] =3D REG_FIELD(BWMON_V4_IRQ_STATUS, 4, 7), [F_IRQ_CLEAR] =3D REG_FIELD(BWMON_V4_IRQ_CLEAR, 4, 7), [F_IRQ_ENABLE] =3D REG_FIELD(BWMON_V4_IRQ_ENABLE, 4, 7), @@ -201,7 +222,6 @@ static const struct reg_field msm8998_bwmon_reg_fields[= ] =3D { }; =20 static const struct regmap_range msm8998_bwmon_reg_noread_ranges[] =3D { - regmap_reg_range(BWMON_V4_GLOBAL_IRQ_CLEAR, BWMON_V4_GLOBAL_IRQ_CLEAR), regmap_reg_range(BWMON_V4_IRQ_CLEAR, BWMON_V4_IRQ_CLEAR), regmap_reg_range(BWMON_V4_CLEAR, BWMON_V4_CLEAR), }; @@ -221,16 +241,33 @@ static const struct regmap_access_table msm8998_bwmon= _reg_volatile_table =3D { .n_yes_ranges =3D ARRAY_SIZE(msm8998_bwmon_reg_volatile_ranges), }; =20 +static const struct reg_field msm8998_bwmon_global_reg_fields[] =3D { + [F_GLOBAL_IRQ_CLEAR] =3D REG_FIELD(BWMON_V4_GLOBAL_IRQ_CLEAR, 0, 0), + [F_GLOBAL_IRQ_ENABLE] =3D REG_FIELD(BWMON_V4_GLOBAL_IRQ_ENABLE, 0, 0), +}; + +static const struct regmap_range msm8998_bwmon_global_reg_noread_ranges[] = =3D { + regmap_reg_range(BWMON_V4_GLOBAL_IRQ_CLEAR, BWMON_V4_GLOBAL_IRQ_CLEAR), +}; + +static const struct regmap_access_table msm8998_bwmon_global_reg_read_tabl= e =3D { + .no_ranges =3D msm8998_bwmon_global_reg_noread_ranges, + .n_no_ranges =3D ARRAY_SIZE(msm8998_bwmon_global_reg_noread_ranges), +}; + /* * Fill the cache for non-readable registers only as rest does not really * matter and can be read from the device. */ static const struct reg_default msm8998_bwmon_reg_defaults[] =3D { - { BWMON_V4_GLOBAL_IRQ_CLEAR, 0x0 }, { BWMON_V4_IRQ_CLEAR, 0x0 }, { BWMON_V4_CLEAR, 0x0 }, }; =20 +static const struct reg_default msm8998_bwmon_global_reg_defaults[] =3D { + { BWMON_V4_GLOBAL_IRQ_CLEAR, 0x0 }, +}; + static const struct regmap_config msm8998_bwmon_regmap_cfg =3D { .reg_bits =3D 32, .reg_stride =3D 4, @@ -251,6 +288,93 @@ static const struct regmap_config msm8998_bwmon_regmap= _cfg =3D { .cache_type =3D REGCACHE_RBTREE, }; =20 +static const struct regmap_config msm8998_bwmon_global_regmap_cfg =3D { + .reg_bits =3D 32, + .reg_stride =3D 4, + .val_bits =3D 32, + /* + * No concurrent access expected - driver has one interrupt handler, + * regmap is not shared, no driver or user-space API. + */ + .disable_locking =3D true, + .rd_table =3D &msm8998_bwmon_global_reg_read_table, + .reg_defaults =3D msm8998_bwmon_global_reg_defaults, + .num_reg_defaults =3D ARRAY_SIZE(msm8998_bwmon_global_reg_defaults), + /* + * Cache is necessary for using regmap fields with non-readable + * registers. + */ + .cache_type =3D REGCACHE_RBTREE, +}; + +static const struct reg_field sdm845_cpu_bwmon_reg_fields[] =3D { + [F_GLOBAL_IRQ_CLEAR] =3D REG_FIELD(BWMON_V4_GLOBAL_IRQ_CLEAR_845, 0, 0), + [F_GLOBAL_IRQ_ENABLE] =3D REG_FIELD(BWMON_V4_GLOBAL_IRQ_ENABLE_845, 0, 0), + [F_IRQ_STATUS] =3D REG_FIELD(BWMON_V4_IRQ_STATUS, 4, 7), + [F_IRQ_CLEAR] =3D REG_FIELD(BWMON_V4_IRQ_CLEAR, 4, 7), + [F_IRQ_ENABLE] =3D REG_FIELD(BWMON_V4_IRQ_ENABLE, 4, 7), + /* F_ENABLE covers entire register to disable other features */ + [F_ENABLE] =3D REG_FIELD(BWMON_V4_ENABLE, 0, 31), + [F_CLEAR] =3D REG_FIELD(BWMON_V4_CLEAR, 0, 1), + [F_SAMPLE_WINDOW] =3D REG_FIELD(BWMON_V4_SAMPLE_WINDOW, 0, 23), + [F_THRESHOLD_HIGH] =3D REG_FIELD(BWMON_V4_THRESHOLD_HIGH, 0, 11), + [F_THRESHOLD_MED] =3D REG_FIELD(BWMON_V4_THRESHOLD_MED, 0, 11), + [F_THRESHOLD_LOW] =3D REG_FIELD(BWMON_V4_THRESHOLD_LOW, 0, 11), + [F_ZONE_ACTIONS_ZONE0] =3D REG_FIELD(BWMON_V4_ZONE_ACTIONS, 0, 7), + [F_ZONE_ACTIONS_ZONE1] =3D REG_FIELD(BWMON_V4_ZONE_ACTIONS, 8, 15), + [F_ZONE_ACTIONS_ZONE2] =3D REG_FIELD(BWMON_V4_ZONE_ACTIONS, 16, 23), + [F_ZONE_ACTIONS_ZONE3] =3D REG_FIELD(BWMON_V4_ZONE_ACTIONS, 24, 31), + [F_THRESHOLD_COUNT_ZONE0] =3D REG_FIELD(BWMON_V4_THRESHOLD_COUNT, 0, 7), + [F_THRESHOLD_COUNT_ZONE1] =3D REG_FIELD(BWMON_V4_THRESHOLD_COUNT, 8, 15), + [F_THRESHOLD_COUNT_ZONE2] =3D REG_FIELD(BWMON_V4_THRESHOLD_COUNT, 16, 23), + [F_THRESHOLD_COUNT_ZONE3] =3D REG_FIELD(BWMON_V4_THRESHOLD_COUNT, 24, 31), + [F_ZONE0_MAX] =3D REG_FIELD(BWMON_V4_ZONE_MAX(0), 0, 11), + [F_ZONE1_MAX] =3D REG_FIELD(BWMON_V4_ZONE_MAX(1), 0, 11), + [F_ZONE2_MAX] =3D REG_FIELD(BWMON_V4_ZONE_MAX(2), 0, 11), + [F_ZONE3_MAX] =3D REG_FIELD(BWMON_V4_ZONE_MAX(3), 0, 11), +}; + +static const struct regmap_range sdm845_cpu_bwmon_reg_noread_ranges[] =3D { + regmap_reg_range(BWMON_V4_GLOBAL_IRQ_CLEAR_845, BWMON_V4_GLOBAL_IRQ_CLEAR= _845), + regmap_reg_range(BWMON_V4_IRQ_CLEAR, BWMON_V4_IRQ_CLEAR), + regmap_reg_range(BWMON_V4_CLEAR, BWMON_V4_CLEAR), +}; + +static const struct regmap_access_table sdm845_cpu_bwmon_reg_read_table = =3D { + .no_ranges =3D sdm845_cpu_bwmon_reg_noread_ranges, + .n_no_ranges =3D ARRAY_SIZE(sdm845_cpu_bwmon_reg_noread_ranges), +}; + +/* + * Fill the cache for non-readable registers only as rest does not really + * matter and can be read from the device. + */ +static const struct reg_default sdm845_cpu_bwmon_reg_defaults[] =3D { + { BWMON_V4_GLOBAL_IRQ_CLEAR_845, 0x0 }, + { BWMON_V4_IRQ_CLEAR, 0x0 }, + { BWMON_V4_CLEAR, 0x0 }, +}; + +static const struct regmap_config sdm845_cpu_bwmon_regmap_cfg =3D { + .reg_bits =3D 32, + .reg_stride =3D 4, + .val_bits =3D 32, + /* + * No concurrent access expected - driver has one interrupt handler, + * regmap is not shared, no driver or user-space API. + */ + .disable_locking =3D true, + .rd_table =3D &sdm845_cpu_bwmon_reg_read_table, + .volatile_table =3D &msm8998_bwmon_reg_volatile_table, + .reg_defaults =3D sdm845_cpu_bwmon_reg_defaults, + .num_reg_defaults =3D ARRAY_SIZE(sdm845_cpu_bwmon_reg_defaults), + /* + * Cache is necessary for using regmap fields with non-readable + * registers. + */ + .cache_type =3D REGCACHE_RBTREE, +}; + /* BWMON v5 */ static const struct reg_field sdm845_llcc_bwmon_reg_fields[] =3D { [F_GLOBAL_IRQ_CLEAR] =3D {}, @@ -349,6 +473,13 @@ static void bwmon_clear_counters(struct icc_bwmon *bwm= on, bool clear_all) =20 static void bwmon_clear_irq(struct icc_bwmon *bwmon) { + struct regmap_field *global_irq_clr; + + if (bwmon->data->global_regmap_fields) + global_irq_clr =3D bwmon->global_regs[F_GLOBAL_IRQ_CLEAR]; + else + global_irq_clr =3D bwmon->regs[F_GLOBAL_IRQ_CLEAR]; + /* * Clear zone and global interrupts. The order and barriers are * important. Quoting downstream Qualcomm msm-4.9 tree: @@ -369,15 +500,22 @@ static void bwmon_clear_irq(struct icc_bwmon *bwmon) if (bwmon->data->quirks & BWMON_NEEDS_FORCE_CLEAR) regmap_field_force_write(bwmon->regs[F_IRQ_CLEAR], 0); if (bwmon->data->quirks & BWMON_HAS_GLOBAL_IRQ) - regmap_field_force_write(bwmon->regs[F_GLOBAL_IRQ_CLEAR], + regmap_field_force_write(global_irq_clr, BWMON_V4_GLOBAL_IRQ_ENABLE_ENABLE); } =20 static void bwmon_disable(struct icc_bwmon *bwmon) { + struct regmap_field *global_irq_en; + + if (bwmon->data->global_regmap_fields) + global_irq_en =3D bwmon->global_regs[F_GLOBAL_IRQ_ENABLE]; + else + global_irq_en =3D bwmon->regs[F_GLOBAL_IRQ_ENABLE]; + /* Disable interrupts. Strict ordering, see bwmon_clear_irq(). */ if (bwmon->data->quirks & BWMON_HAS_GLOBAL_IRQ) - regmap_field_write(bwmon->regs[F_GLOBAL_IRQ_ENABLE], 0x0); + regmap_field_write(global_irq_en, 0x0); regmap_field_write(bwmon->regs[F_IRQ_ENABLE], 0x0); =20 /* @@ -389,10 +527,18 @@ static void bwmon_disable(struct icc_bwmon *bwmon) =20 static void bwmon_enable(struct icc_bwmon *bwmon, unsigned int irq_enable) { + struct regmap_field *global_irq_en; + + if (bwmon->data->global_regmap_fields) + global_irq_en =3D bwmon->global_regs[F_GLOBAL_IRQ_ENABLE]; + else + global_irq_en =3D bwmon->regs[F_GLOBAL_IRQ_ENABLE]; + /* Enable interrupts */ if (bwmon->data->quirks & BWMON_HAS_GLOBAL_IRQ) - regmap_field_write(bwmon->regs[F_GLOBAL_IRQ_ENABLE], + regmap_field_write(global_irq_en, BWMON_V4_GLOBAL_IRQ_ENABLE_ENABLE); + regmap_field_write(bwmon->regs[F_IRQ_ENABLE], irq_enable); =20 /* Enable bwmon */ @@ -555,7 +701,9 @@ static int bwmon_init_regmap(struct platform_device *pd= ev, struct device *dev =3D &pdev->dev; void __iomem *base; struct regmap *map; + int ret; =20 + /* Map the monitor base */ base =3D devm_platform_ioremap_resource(pdev, 0); if (IS_ERR(base)) return dev_err_probe(dev, PTR_ERR(base), @@ -566,12 +714,35 @@ static int bwmon_init_regmap(struct platform_device *= pdev, return dev_err_probe(dev, PTR_ERR(map), "failed to initialize regmap\n"); =20 + BUILD_BUG_ON(ARRAY_SIZE(msm8998_bwmon_global_reg_fields) !=3D F_NUM_GLOBA= L_FIELDS); BUILD_BUG_ON(ARRAY_SIZE(msm8998_bwmon_reg_fields) !=3D F_NUM_FIELDS); + BUILD_BUG_ON(ARRAY_SIZE(sdm845_cpu_bwmon_reg_fields) !=3D F_NUM_FIELDS); BUILD_BUG_ON(ARRAY_SIZE(sdm845_llcc_bwmon_reg_fields) !=3D F_NUM_FIELDS); =20 - return devm_regmap_field_bulk_alloc(dev, map, bwmon->regs, + ret =3D devm_regmap_field_bulk_alloc(dev, map, bwmon->regs, bwmon->data->regmap_fields, F_NUM_FIELDS); + if (ret) + return ret; + + if (bwmon->data->global_regmap_cfg) { + /* Map the global base, if separate */ + base =3D devm_platform_ioremap_resource(pdev, 1); + if (IS_ERR(base)) + return dev_err_probe(dev, PTR_ERR(base), + "failed to map bwmon global registers\n"); + + map =3D devm_regmap_init_mmio(dev, base, bwmon->data->global_regmap_cfg); + if (IS_ERR(map)) + return dev_err_probe(dev, PTR_ERR(map), + "failed to initialize global regmap\n"); + + ret =3D devm_regmap_field_bulk_alloc(dev, map, bwmon->global_regs, + bwmon->data->global_regmap_fields, + F_NUM_GLOBAL_FIELDS); + } + + return ret; } =20 static int bwmon_probe(struct platform_device *pdev) @@ -644,6 +815,21 @@ static const struct icc_bwmon_data msm8998_bwmon_data = =3D { .quirks =3D BWMON_HAS_GLOBAL_IRQ, .regmap_fields =3D msm8998_bwmon_reg_fields, .regmap_cfg =3D &msm8998_bwmon_regmap_cfg, + .global_regmap_fields =3D msm8998_bwmon_global_reg_fields, + .global_regmap_cfg =3D &msm8998_bwmon_global_regmap_cfg, +}; + +static const struct icc_bwmon_data sdm845_cpu_bwmon_data =3D { + .sample_ms =3D 4, + .count_unit_kb =3D 64, + .default_highbw_kbps =3D 4800 * 1024, /* 4.8 GBps */ + .default_medbw_kbps =3D 512 * 1024, /* 512 MBps */ + .default_lowbw_kbps =3D 0, + .zone1_thres_count =3D 16, + .zone3_thres_count =3D 1, + .quirks =3D BWMON_HAS_GLOBAL_IRQ, + .regmap_fields =3D sdm845_cpu_bwmon_reg_fields, + .regmap_cfg =3D &sdm845_cpu_bwmon_regmap_cfg, }; =20 static const struct icc_bwmon_data sdm845_llcc_bwmon_data =3D { @@ -672,16 +858,18 @@ static const struct icc_bwmon_data sc7280_llcc_bwmon_= data =3D { }; =20 static const struct of_device_id bwmon_of_match[] =3D { - { - .compatible =3D "qcom,msm8998-bwmon", - .data =3D &msm8998_bwmon_data - }, { - .compatible =3D "qcom,sdm845-llcc-bwmon", - .data =3D &sdm845_llcc_bwmon_data - }, { - .compatible =3D "qcom,sc7280-llcc-bwmon", - .data =3D &sc7280_llcc_bwmon_data - }, + /* BWMONv4, separate monitor and global register spaces */ + { .compatible =3D "qcom,msm8998-bwmon", .data =3D &msm8998_bwmon_data }, + /* BWMONv4, unified register space */ + { .compatible =3D "qcom,sdm845-bwmon", .data =3D &sdm845_cpu_bwmon_data }, + /* BWMONv5 */ + { .compatible =3D "qcom,sdm845-llcc-bwmon", .data =3D &sdm845_llcc_bwmon_= data }, + { .compatible =3D "qcom,sc7280-llcc-bwmon", .data =3D &sc7280_llcc_bwmon_= data }, + + /* Compatibles kept for legacy reasons */ + { .compatible =3D "qcom,sc7280-cpu-bwmon", .data =3D &sdm845_cpu_bwmon_da= ta }, + { .compatible =3D "qcom,sc8280xp-cpu-bwmon", .data =3D &sdm845_cpu_bwmon_= data }, + { .compatible =3D "qcom,sm8550-cpu-bwmon", .data =3D &sdm845_cpu_bwmon_da= ta }, {} }; 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[83.9.29.16]) by smtp.gmail.com with ESMTPSA id b8-20020ac25e88000000b004e845a08567sm824678lfq.291.2023.03.15.07.11.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 15 Mar 2023 07:11:31 -0700 (PDT) From: Konrad Dybcio Date: Wed, 15 Mar 2023 15:11:22 +0100 Subject: [PATCH v3 4/7] arm64: dts: qcom: sc7280: Use the correct BWMON fallback compatible MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20230304-topic-ddr_bwmon-v3-4-77a050c2fbda@linaro.org> References: <20230304-topic-ddr_bwmon-v3-0-77a050c2fbda@linaro.org> In-Reply-To: <20230304-topic-ddr_bwmon-v3-0-77a050c2fbda@linaro.org> To: Andy Gross , Bjorn Andersson , Krzysztof Kozlowski , Georgi Djakov , Rob Herring , Thara Gopinath , Krzysztof Kozlowski Cc: linux-arm-msm@vger.kernel.org, linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Konrad Dybcio , Marijn Suijten X-Mailer: b4 0.12.1 X-Developer-Signature: v=1; a=ed25519-sha256; t=1678889480; l=842; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=/FA8iJU+xOaUyv9UYrNahdRUlOvSv0Jd6XSfSid+KYo=; b=lrQRuh8qqZeZulRS4E1XsAEx13EVi2LqqCzNULl3s1oWdRuIDyeNEw6VKRUYp3bsk7VsVP3SK2OA NlqXWCFhDbEDilq8MDspHfqMXrMNB25MCf85PkQOiZb/zhihU5TJ X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Use the correct fallback compatible for the BWMONv4 with merged global and monitor register spaces. Reviewed-by: Krzysztof Kozlowski Signed-off-by: Konrad Dybcio --- arch/arm64/boot/dts/qcom/sc7280.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qco= m/sc7280.dtsi index 8f4ab6bd2886..f15fea6cc316 100644 --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi @@ -3533,7 +3533,7 @@ opp-7 { }; =20 pmu@90b6400 { - compatible =3D "qcom,sc7280-cpu-bwmon", "qcom,msm8998-bwmon"; + compatible =3D "qcom,sc7280-cpu-bwmon", "qcom,sdm845-bwmon"; reg =3D <0 0x090b6400 0 0x600>; =20 interrupts =3D ; --=20 2.39.2 From nobody Wed Feb 11 10:20:59 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 157BCC76195 for ; Wed, 15 Mar 2023 14:12:14 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233141AbjCOOMM (ORCPT ); Wed, 15 Mar 2023 10:12:12 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:50212 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232067AbjCOOLr (ORCPT ); Wed, 15 Mar 2023 10:11:47 -0400 Received: from mail-lf1-x12b.google.com (mail-lf1-x12b.google.com [IPv6:2a00:1450:4864:20::12b]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 6B140664EE for ; Wed, 15 Mar 2023 07:11:35 -0700 (PDT) Received: by mail-lf1-x12b.google.com with SMTP id y20so1898694lfj.2 for ; Wed, 15 Mar 2023 07:11:34 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1678889494; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=nqvdp07J1HQLjVavRExVgoZODvgCx91QmPizlq7Sg94=; b=wj+H/ZKxHvYweQFezs3ZKdnU8Q1gnb+TlnRTdhbCS3/LlQz369hyBlu1fFt175i7OC YO5DOErPxyjDcbUHr8DmM667zEvIa4IjoQPsWv4YTCmV2hXdEftwos3ix8XuqyiaCE4n qAJUGHZjbn0IDuFFEbYva1RV+Y7AkZ0KU+18iEcyLwKJR0+2ZJYTS1UW69k4My0UBfEy 9iJ103JTQrR2uStCp2mwtX8dQkkJK/Lc/mYaAKk7LVaHCneST7dbtMx4x2FUbVt+INCD 5Y6Gvil/+umOg+RwmKGQDfeDJ0+Wb5qYYf8nbZk4hbMsAYyJoX7luVW/re5UxATjINFG C/ZQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1678889494; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=nqvdp07J1HQLjVavRExVgoZODvgCx91QmPizlq7Sg94=; b=vqWIk6TI5qqRtQdr4sLgIkEgrzr6cVuwewyzGSOJSf/Cpn/NX+bZLRJmIwXuANgxW2 6hQRHpuxUrBGDA+lHrjiBVw3AmBpQefh15OmSaAPMgVNQTrPe7kkbMaDewEScJlqR1RZ uymHBe+uga9TjKMIz1bJGDgWxprEQuQ8V+OxvA9N8SXm5OMGbyDe96AfboM/e1bqbUY0 aW4Y5e6FRA795udOJByOEbla97vUAXivtfVqoe5w7vSHKOBrzZEH+rgr39XnEnSd016c GjEPgi7PclDnR9hdtFFmmx/da+m2Jt3YKLk1/umy2SGyj/h5qUXWvneZ4TKUIBevfxY6 hxbQ== X-Gm-Message-State: AO0yUKWuA6xVFJjoNuIpw7DbOPYQQnnMQmiU8VgniOqmwy8TExXfmuAn ng/zq3nsY9FWeqgn793wSR7Nrg== X-Google-Smtp-Source: AK7set+AHcT5QASEAJR/bf5kUGeTcpFKhBI86DCMSOaTk2/DhlWMFk8OmJN0q1mf+td2wEsxXOkwdA== X-Received: by 2002:a19:f511:0:b0:4e1:b880:ba1c with SMTP id j17-20020a19f511000000b004e1b880ba1cmr1640962lfb.9.1678889494617; Wed, 15 Mar 2023 07:11:34 -0700 (PDT) Received: from [192.168.1.101] (abyj16.neoplus.adsl.tpnet.pl. [83.9.29.16]) by smtp.gmail.com with ESMTPSA id b8-20020ac25e88000000b004e845a08567sm824678lfq.291.2023.03.15.07.11.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 15 Mar 2023 07:11:34 -0700 (PDT) From: Konrad Dybcio Date: Wed, 15 Mar 2023 15:11:23 +0100 Subject: [PATCH v3 5/7] arm64: dts: qcom: sc8280xp: Use the correct BWMON fallback compatible MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20230304-topic-ddr_bwmon-v3-5-77a050c2fbda@linaro.org> References: <20230304-topic-ddr_bwmon-v3-0-77a050c2fbda@linaro.org> In-Reply-To: <20230304-topic-ddr_bwmon-v3-0-77a050c2fbda@linaro.org> To: Andy Gross , Bjorn Andersson , Krzysztof Kozlowski , Georgi Djakov , Rob Herring , Thara Gopinath , Krzysztof Kozlowski Cc: linux-arm-msm@vger.kernel.org, linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Konrad Dybcio , Marijn Suijten X-Mailer: b4 0.12.1 X-Developer-Signature: v=1; a=ed25519-sha256; t=1678889480; l=857; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=1DZfsRNhr1OAkCF3p7xVoJYWjPDaei4Vd+17mLHBDz0=; b=sGJ1D/caceEmjC9PDr1xTNrAWwLRHMU5A9DG7ARV3xwKMnXuVMIbV8nLuYpvCG6AFeE54Mr8C0Fq /rrLrJ1ZCJkkEg1yd++oIKpkXcib945I6leZTcr+xO++XLClL0Dl X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Use the correct fallback compatible for the BWMONv4 with merged global and monitor register spaces. Reviewed-by: Krzysztof Kozlowski Signed-off-by: Konrad Dybcio --- arch/arm64/boot/dts/qcom/sc8280xp.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi b/arch/arm64/boot/dts/q= com/sc8280xp.dtsi index 0d02599d8867..131b99bfe771 100644 --- a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi +++ b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi @@ -2946,7 +2946,7 @@ opp-12 { }; =20 pmu@90b6400 { - compatible =3D "qcom,sc8280xp-cpu-bwmon", "qcom,msm8998-bwmon"; + compatible =3D "qcom,sc8280xp-cpu-bwmon", "qcom,sdm845-bwmon"; reg =3D <0 0x090b6400 0 0x600>; =20 interrupts =3D ; --=20 2.39.2 From nobody Wed Feb 11 10:20:59 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id B281DC7618B for ; Wed, 15 Mar 2023 14:12:25 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233024AbjCOOMY (ORCPT ); Wed, 15 Mar 2023 10:12:24 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:50082 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233084AbjCOOMI (ORCPT ); Wed, 15 Mar 2023 10:12:08 -0400 Received: from mail-lf1-x129.google.com (mail-lf1-x129.google.com [IPv6:2a00:1450:4864:20::129]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 7F93697B67 for ; Wed, 15 Mar 2023 07:11:39 -0700 (PDT) Received: by mail-lf1-x129.google.com with SMTP id x17so8352762lfu.5 for ; Wed, 15 Mar 2023 07:11:39 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1678889497; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=IH0ZCvPL/3GU0CeiB2YhHJI9Er8cEK0jH1qxynvAopg=; b=PjKAf6X3eFI/0MCgnJCdHc9AL15IWihL5/Kw7NJ+krTegNtKwSiVRHpodRJMt0bVuk sNEaIEgdhCKPGXO76ZkgRAQMgqAJxGbx5dNwatztsZ/97indPCbHwadrlwz9CqFoW0Ne okyFFrhA57JJuYJaSdr2K2gnLjAx2WdIbQZFotLVnZQuy2RpYLE8C5t9m5x6Uf5dSonU glQ/2wGbxcDV89p0itlzWMTi8H6i9RFc3iirgGW2xnbrcnTPV7oYd0goN0Rf/KuWtMz/ +MZTBtD4TPQKafC1r8Nx1i6s6p688crckHrXl3WJL+xUw3tXaQ/atnG39UQR05Dro880 +K4w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1678889497; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=IH0ZCvPL/3GU0CeiB2YhHJI9Er8cEK0jH1qxynvAopg=; b=boJ8E7cuyVMfQGeV9vzV56pYXB67Qqj59/XsktgH9igddDp8PTMcz+QX1hoNZmdGDp HmpdMV5y16WF7kdBVKdcAqjvg9ueC1EReQ6tpW1ILc8sJNY1DTzEV3TTPAKY4tfqDw88 LG7o9dE5+Gi0cwxPgOramtYeczv8/U7pQDPX74hYm2/afjqJjTqr8thZfkSMC+tJudRq TgZOstPeHdjXK3aLsIJqzD75yPk4GzYbHgDj0RuIjE6rqp/zmA/kh4nu7KrLSsNZkrNH xYs+O5pyajVazR/LjgRIaRJKBlYvQrh4jwUB8jEA3f8vzgvaTMYtF2TgiQ3wYN+GnKmm NxDA== X-Gm-Message-State: AO0yUKWe0I4q2pU28GalDYRtq3saWpmGNlI3se7ezeGBEw15KdN0v0FE SZUHOCByODkmViqUKRkv+tZUFQJbJfS4FdanTA4= X-Google-Smtp-Source: AK7set9/4xpsujgcrVzF+YSyF91LdK1odpZ3atDaQLKajYDk0IISydOJyU8ZDVTDJfIRV8IFT0Z4kQ== X-Received: by 2002:ac2:508f:0:b0:4e8:44a5:6018 with SMTP id f15-20020ac2508f000000b004e844a56018mr1912896lfm.44.1678889497508; Wed, 15 Mar 2023 07:11:37 -0700 (PDT) Received: from [192.168.1.101] (abyj16.neoplus.adsl.tpnet.pl. [83.9.29.16]) by smtp.gmail.com with ESMTPSA id b8-20020ac25e88000000b004e845a08567sm824678lfq.291.2023.03.15.07.11.34 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 15 Mar 2023 07:11:36 -0700 (PDT) From: Konrad Dybcio Date: Wed, 15 Mar 2023 15:11:24 +0100 Subject: [PATCH v3 6/7] arm64: dts: qcom: sdm845: Use the correct BWMON compatible MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20230304-topic-ddr_bwmon-v3-6-77a050c2fbda@linaro.org> References: <20230304-topic-ddr_bwmon-v3-0-77a050c2fbda@linaro.org> In-Reply-To: <20230304-topic-ddr_bwmon-v3-0-77a050c2fbda@linaro.org> To: Andy Gross , Bjorn Andersson , Krzysztof Kozlowski , Georgi Djakov , Rob Herring , Thara Gopinath , Krzysztof Kozlowski Cc: linux-arm-msm@vger.kernel.org, linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Konrad Dybcio , Marijn Suijten X-Mailer: b4 0.12.1 X-Developer-Signature: v=1; a=ed25519-sha256; t=1678889480; l=954; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=IFc3qKQ/mzYt/DYUL06igVAb6D7fe/8j8f5wmJWco+Y=; b=GX6YCA+EVcASk66NmRcaCbYhYHJGj5/eoBll4XT8Qsp0Cl4XcBcXpzEzdmOzBaiZFF4WvXzWuxWZ oLsT6VFNC89txHmw/qTWlRNtC9Nvc2sw6rx+0aQtBSIBOl2TLwDU X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Drop the incorrect msm8998 fallback and use the new qcom,sdm845-cpu-bwmon compatible to distinguish the CPU BWMON found on this platform. Reviewed-by: Krzysztof Kozlowski Signed-off-by: Konrad Dybcio --- arch/arm64/boot/dts/qcom/sdm845.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qco= m/sdm845.dtsi index 479859bd8ab3..1f2a97a20ef3 100644 --- a/arch/arm64/boot/dts/qcom/sdm845.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi @@ -2241,7 +2241,7 @@ opp-4 { }; =20 pmu@1436400 { - compatible =3D "qcom,sdm845-bwmon", "qcom,msm8998-bwmon"; + compatible =3D "qcom,sdm845-cpu-bwmon", "qcom,sdm845-bwmon"; reg =3D <0 0x01436400 0 0x600>; interrupts =3D ; interconnects =3D <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_LL= CC 3>; --=20 2.39.2 From nobody Wed Feb 11 10:20:59 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id BF864C61DA4 for ; Wed, 15 Mar 2023 14:12:32 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232970AbjCOOMb (ORCPT ); Wed, 15 Mar 2023 10:12:31 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:51002 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233130AbjCOOMM (ORCPT ); Wed, 15 Mar 2023 10:12:12 -0400 Received: from mail-lf1-x131.google.com (mail-lf1-x131.google.com [IPv6:2a00:1450:4864:20::131]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 46C25A028D for ; Wed, 15 Mar 2023 07:11:42 -0700 (PDT) Received: by mail-lf1-x131.google.com with SMTP id y15so14973212lfa.7 for ; Wed, 15 Mar 2023 07:11:42 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1678889502; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=NtJ3vFNxN3ulWegLUMLxPGL5fEpN3EwC/SH8BmcFyaA=; b=r5bmp5Qi8GsB9iOnryLlnMBm6qMhM3jE8e/AWc8v/jVHcajTLDlslJwCIcOBBcHWVc y11HdcZJ8EJrDylYysW+brO87vMx/MHiqCbDA+VeIqhAIio883RtITf+Ko4yQMEo2B9r NmhZ/+XYkXR4gHK2Fpn3G7lJP6Amz8y13ikCwMsfkTS/a+C7eAKvzJMzNp2aHJKW+Ped aGw7qOmTDCkroXtE/biZj1aEQ0fwiutwOBXZJNxXK7r18hzfpefUMSsRhkOukfXFXnLG l2IoXeyeYqgLlMshOd8u32rhL7yEss4T327JhozOwijEiF/CRWmBZtm+aCc+MN2KTOL0 rolQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1678889502; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=NtJ3vFNxN3ulWegLUMLxPGL5fEpN3EwC/SH8BmcFyaA=; b=fYaQSlypQ2t7K+gewvrJSUkHJDfKXQpVN26Y80Gk6xXlu0yPq1Cvb+JhcKE16gVHCG wO7ylpJOXnF/RVvQcnwQeQs4uBcXnJtVgshqNNlr/jeLNjj3V6f8pqmEEl8Hn0kg3t6D +AEjJQVjCK6Nn23pwnN4jMf+zG5om45BS6aA6Hk7TcHl3vKh+YZY1AyS9NU1YlBCEXJW Z7SlP4UbSZCXLoM5n2+mQJju/ktoLh/+VMebhF0BYcYnHBaN0zNwzpsNTilm9dP6bC/q RKN9dwmQDIhd5uvTkk1U/KR2pBIzJ77C2RltTPSN5HS0s44Zl8XT8nxDfkBbTXK7jQTJ 9l+g== X-Gm-Message-State: AO0yUKVyitYD4RPpJ6l1iUP8w6nanNbVIP/Qp/d+3YC0iNfC9F0dYsq/ qLEgPw8af8to4MlQqIS7BrPnpg== X-Google-Smtp-Source: AK7set8U2f2jJCQnZGyHhK2xJ2jiR6mdyeJRvBJFzc4XJF6ufYMJwWid97m84I2qPGtny7eB77zUTg== X-Received: by 2002:ac2:4297:0:b0:4cd:7fe0:24 with SMTP id m23-20020ac24297000000b004cd7fe00024mr2186112lfh.27.1678889502079; Wed, 15 Mar 2023 07:11:42 -0700 (PDT) Received: from [192.168.1.101] (abyj16.neoplus.adsl.tpnet.pl. [83.9.29.16]) by smtp.gmail.com with ESMTPSA id b8-20020ac25e88000000b004e845a08567sm824678lfq.291.2023.03.15.07.11.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 15 Mar 2023 07:11:38 -0700 (PDT) From: Konrad Dybcio Date: Wed, 15 Mar 2023 15:11:25 +0100 Subject: [PATCH v3 7/7] arm64: dts: qcom: sm8550: Use the correct BWMON fallback compatible MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20230304-topic-ddr_bwmon-v3-7-77a050c2fbda@linaro.org> References: <20230304-topic-ddr_bwmon-v3-0-77a050c2fbda@linaro.org> In-Reply-To: <20230304-topic-ddr_bwmon-v3-0-77a050c2fbda@linaro.org> To: Andy Gross , Bjorn Andersson , Krzysztof Kozlowski , Georgi Djakov , Rob Herring , Thara Gopinath , Krzysztof Kozlowski Cc: linux-arm-msm@vger.kernel.org, linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Konrad Dybcio , Marijn Suijten X-Mailer: b4 0.12.1 X-Developer-Signature: v=1; a=ed25519-sha256; t=1678889480; l=915; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=dMLX1nr86ibogtZfftMqjl+ZEaZVlp2gW/2Ekfh4Qg4=; b=mMcmR4y/gsZjUv2tlyJ0SIklkEDolVPgP57/9+mWsULUFgqpDVqjV7uPqWeWFjPx1kCvQH2+XD4H 91/t24IgDvQwqivh8870zKvltnkQHeHB0FsUya3rbMU+kimWCO0Z X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Use the correct fallback compatible for the BWMONv4 with merged global and monitor register spaces. Reviewed-by: Krzysztof Kozlowski Signed-off-by: Konrad Dybcio Reviewed-by: Neil Armstrong --- arch/arm64/boot/dts/qcom/sm8550.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sm8550.dtsi b/arch/arm64/boot/dts/qco= m/sm8550.dtsi index 25f51245fe9b..b5488c6822bd 100644 --- a/arch/arm64/boot/dts/qcom/sm8550.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8550.dtsi @@ -3391,7 +3391,7 @@ opp-8 { }; =20 pmu@240b6400 { - compatible =3D "qcom,sm8550-cpu-bwmon", "qcom,msm8998-bwmon"; + compatible =3D "qcom,sm8550-cpu-bwmon", "qcom,sdm845-bwmon"; reg =3D <0 0x240b6400 0 0x600>; interrupts =3D ; interconnects =3D <&gem_noc MASTER_APPSS_PROC 3 &gem_noc SLAVE_LLCC 3>; --=20 2.39.2