From nobody Sat Apr 11 08:29:30 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id BB6D8C64EC4 for ; Fri, 3 Mar 2023 15:15:43 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231404AbjCCPPm (ORCPT ); Fri, 3 Mar 2023 10:15:42 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:59630 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230463AbjCCPPj (ORCPT ); Fri, 3 Mar 2023 10:15:39 -0500 Received: from mail-pf1-x429.google.com (mail-pf1-x429.google.com [IPv6:2607:f8b0:4864:20::429]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id EA1A715550; Fri, 3 Mar 2023 07:15:34 -0800 (PST) Received: by mail-pf1-x429.google.com with SMTP id a7so1741710pfx.10; Fri, 03 Mar 2023 07:15:34 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; t=1677856534; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=g9Mn0jwkvOokLptdjMTn8t5cF0UBdVv812btjIaJ5HM=; b=lVjhbB513I23fQKL89tqSgsaVQJAFNJIDa68pYxJBL6LcM/wJ9Kx0xC6eFyWx+snf3 wjKYxq1PCjESWEf/vT4+oM2kk1a6RyJSOwLPjJdSuJE/lMboX5auTaBeRIzLDZDk71F9 mSURDW42UjlSoPHWqxHWJ1/uOMKh17svyn8OT6eLVqOXxS5W9tGwcZl8fp40LXKSZL0o D1JxJxrc+MD/0ImZrZYxVUnK7PglA7Ty6dK4JLh/UIglQ5Kk2+iqmxXqouibYerQO7aM 4vcJgHQluyaZ5NgIhRCwzkEb6iWmbdsRtELlDbs7sWkDt43Ew1fi97nsVYFI90hyvZvj 84Bg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1677856534; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=g9Mn0jwkvOokLptdjMTn8t5cF0UBdVv812btjIaJ5HM=; b=L/MdmTdE0Wnqk0GOJ3pMU7qFuC1l1T5t8LMpxgsdS7thjl1lkCBI7G35v8Hs7/TBiT y30iUXRKhoQcqPoDW3qx6OBlnyh5MQya/eeSeSrl4wuo+Q2w1RomdObWBJfCp4u4ktP+ 2M+qOc1nvbPYM4KSgM3ZkcYP+HisCfQsXGNLbm8MP1rEuyesttbxO7sW3vGEakH0L8vf OHWYy2JXcbfXHdYjgS9XmF0sI+GZ91bRpjbA8u/zjrt/s3mHsyusjh/uuCxb3RHzU0bz eQ5Zk1B5ZfgIkllXyP50hBNqScLNNbo1MngfCm/c1gc5XSkIP1l0o5copsmZADyEJZgd Icyw== X-Gm-Message-State: AO0yUKUtDxW/Nn3HEUJe3gfW7lZnXuY7ePv0ws1cHHtzVUuyITjTH67W 3Fn8vw0SCkW/uXCe+O1FuS0wSAW8ydJVygDEAAY= X-Google-Smtp-Source: AK7set+XmeV0eCw0LWdK05XWeTmWruk2bL894nmtGT6IK1qycdFqXMHARhoKKdhp7/3MX0SdJSda4g== X-Received: by 2002:a62:2581:0:b0:5a9:cb6b:7843 with SMTP id l123-20020a622581000000b005a9cb6b7843mr2077259pfl.27.1677856534120; Fri, 03 Mar 2023 07:15:34 -0800 (PST) Received: from y.ha.lan ([104.28.213.199]) by smtp.gmail.com with ESMTPSA id p4-20020aa78604000000b005a8bdc18453sm1739721pfn.35.2023.03.03.07.15.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 03 Mar 2023 07:15:33 -0800 (PST) From: David Yang To: mmyangfl@gmail.com Cc: Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 1/5] clk: hisilicon: Rename Hi3798CV200 to Hi3798 Date: Fri, 3 Mar 2023 23:14:09 +0800 Message-Id: <20230303151417.104321-2-mmyangfl@gmail.com> X-Mailer: git-send-email 2.39.1 In-Reply-To: <20230303151417.104321-1-mmyangfl@gmail.com> References: <20230303151417.104321-1-mmyangfl@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Rename Hisilicon Hi3798CV200 to Hi3798, to be reused with other Hi3798 series SoCs. Signed-off-by: David Yang --- drivers/clk/hisilicon/Kconfig | 6 +- drivers/clk/hisilicon/Makefile | 2 +- .../{crg-hi3798cv200.c =3D> crg-hi3798.c} | 151 +++++++++--------- 3 files changed, 80 insertions(+), 79 deletions(-) rename drivers/clk/hisilicon/{crg-hi3798cv200.c =3D> crg-hi3798.c} (73%) diff --git a/drivers/clk/hisilicon/Kconfig b/drivers/clk/hisilicon/Kconfig index c1ec75aa4..fa2d9920f 100644 --- a/drivers/clk/hisilicon/Kconfig +++ b/drivers/clk/hisilicon/Kconfig @@ -37,13 +37,13 @@ config COMMON_CLK_HI3670 help Build the clock driver for hi3670. =20 -config COMMON_CLK_HI3798CV200 - tristate "Hi3798CV200 Clock Driver" +config COMMON_CLK_HI3798 + tristate "Hi3798 Clock Driver" depends on ARCH_HISI || COMPILE_TEST select RESET_HISI default ARCH_HISI help - Build the clock driver for hi3798cv200. + Build the clock driver for hi3798. =20 config COMMON_CLK_HI6220 bool "Hi6220 Clock Driver" diff --git a/drivers/clk/hisilicon/Makefile b/drivers/clk/hisilicon/Makefile index 2978e56cb..cfef47a19 100644 --- a/drivers/clk/hisilicon/Makefile +++ b/drivers/clk/hisilicon/Makefile @@ -13,7 +13,7 @@ obj-$(CONFIG_COMMON_CLK_HI3519) +=3D clk-hi3519.o obj-$(CONFIG_COMMON_CLK_HI3559A) +=3D clk-hi3559a.o obj-$(CONFIG_COMMON_CLK_HI3660) +=3D clk-hi3660.o obj-$(CONFIG_COMMON_CLK_HI3670) +=3D clk-hi3670.o -obj-$(CONFIG_COMMON_CLK_HI3798CV200) +=3D crg-hi3798cv200.o +obj-$(CONFIG_COMMON_CLK_HI3798) +=3D crg-hi3798.o obj-$(CONFIG_COMMON_CLK_HI6220) +=3D clk-hi6220.o obj-$(CONFIG_RESET_HISI) +=3D reset.o obj-$(CONFIG_STUB_CLK_HI6220) +=3D clk-hi6220-stub.o diff --git a/drivers/clk/hisilicon/crg-hi3798cv200.c b/drivers/clk/hisilico= n/crg-hi3798.c similarity index 73% rename from drivers/clk/hisilicon/crg-hi3798cv200.c rename to drivers/clk/hisilicon/crg-hi3798.c index 08a19ba77..bdce43fbe 100644 --- a/drivers/clk/hisilicon/crg-hi3798cv200.c +++ b/drivers/clk/hisilicon/crg-hi3798.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-or-later /* - * Hi3798CV200 Clock and Reset Generator Driver + * Hi3798 Clock and Reset Generator Driver * * Copyright (c) 2016 HiSilicon Technologies Co., Ltd. */ @@ -14,49 +14,49 @@ #include "crg.h" #include "reset.h" =20 -/* hi3798CV200 core CRG */ -#define HI3798CV200_INNER_CLK_OFFSET 64 -#define HI3798CV200_FIXED_24M 65 -#define HI3798CV200_FIXED_25M 66 -#define HI3798CV200_FIXED_50M 67 -#define HI3798CV200_FIXED_75M 68 -#define HI3798CV200_FIXED_100M 69 -#define HI3798CV200_FIXED_150M 70 -#define HI3798CV200_FIXED_200M 71 -#define HI3798CV200_FIXED_250M 72 -#define HI3798CV200_FIXED_300M 73 -#define HI3798CV200_FIXED_400M 74 -#define HI3798CV200_MMC_MUX 75 -#define HI3798CV200_ETH_PUB_CLK 76 -#define HI3798CV200_ETH_BUS_CLK 77 -#define HI3798CV200_ETH_BUS0_CLK 78 -#define HI3798CV200_ETH_BUS1_CLK 79 -#define HI3798CV200_COMBPHY1_MUX 80 -#define HI3798CV200_FIXED_12M 81 -#define HI3798CV200_FIXED_48M 82 -#define HI3798CV200_FIXED_60M 83 -#define HI3798CV200_FIXED_166P5M 84 -#define HI3798CV200_SDIO0_MUX 85 -#define HI3798CV200_COMBPHY0_MUX 86 - -#define HI3798CV200_CRG_NR_CLKS 128 - -static const struct hisi_fixed_rate_clock hi3798cv200_fixed_rate_clks[] = =3D { +/* hi3798 core CRG */ +#define HI3798_INNER_CLK_OFFSET 64 +#define HI3798_FIXED_24M 65 +#define HI3798_FIXED_25M 66 +#define HI3798_FIXED_50M 67 +#define HI3798_FIXED_75M 68 +#define HI3798_FIXED_100M 69 +#define HI3798_FIXED_150M 70 +#define HI3798_FIXED_200M 71 +#define HI3798_FIXED_250M 72 +#define HI3798_FIXED_300M 73 +#define HI3798_FIXED_400M 74 +#define HI3798_MMC_MUX 75 +#define HI3798_ETH_PUB_CLK 76 +#define HI3798_ETH_BUS_CLK 77 +#define HI3798_ETH_BUS0_CLK 78 +#define HI3798_ETH_BUS1_CLK 79 +#define HI3798_COMBPHY1_MUX 80 +#define HI3798_FIXED_12M 81 +#define HI3798_FIXED_48M 82 +#define HI3798_FIXED_60M 83 +#define HI3798_FIXED_166P5M 84 +#define HI3798_SDIO0_MUX 85 +#define HI3798_COMBPHY0_MUX 86 + +#define HI3798_CRG_NR_CLKS 128 + +static const struct hisi_fixed_rate_clock hi3798_fixed_rate_clks[] =3D { { HISTB_OSC_CLK, "clk_osc", NULL, 0, 24000000, }, { HISTB_APB_CLK, "clk_apb", NULL, 0, 100000000, }, { HISTB_AHB_CLK, "clk_ahb", NULL, 0, 200000000, }, - { HI3798CV200_FIXED_12M, "12m", NULL, 0, 12000000, }, - { HI3798CV200_FIXED_24M, "24m", NULL, 0, 24000000, }, - { HI3798CV200_FIXED_25M, "25m", NULL, 0, 25000000, }, - { HI3798CV200_FIXED_48M, "48m", NULL, 0, 48000000, }, - { HI3798CV200_FIXED_50M, "50m", NULL, 0, 50000000, }, - { HI3798CV200_FIXED_60M, "60m", NULL, 0, 60000000, }, - { HI3798CV200_FIXED_75M, "75m", NULL, 0, 75000000, }, - { HI3798CV200_FIXED_100M, "100m", NULL, 0, 100000000, }, - { HI3798CV200_FIXED_150M, "150m", NULL, 0, 150000000, }, - { HI3798CV200_FIXED_166P5M, "166p5m", NULL, 0, 165000000, }, - { HI3798CV200_FIXED_200M, "200m", NULL, 0, 200000000, }, - { HI3798CV200_FIXED_250M, "250m", NULL, 0, 250000000, }, + { HI3798_FIXED_12M, "12m", NULL, 0, 12000000, }, + { HI3798_FIXED_24M, "24m", NULL, 0, 24000000, }, + { HI3798_FIXED_25M, "25m", NULL, 0, 25000000, }, + { HI3798_FIXED_48M, "48m", NULL, 0, 48000000, }, + { HI3798_FIXED_50M, "50m", NULL, 0, 50000000, }, + { HI3798_FIXED_60M, "60m", NULL, 0, 60000000, }, + { HI3798_FIXED_75M, "75m", NULL, 0, 75000000, }, + { HI3798_FIXED_100M, "100m", NULL, 0, 100000000, }, + { HI3798_FIXED_150M, "150m", NULL, 0, 150000000, }, + { HI3798_FIXED_166P5M, "166p5m", NULL, 0, 165000000, }, + { HI3798_FIXED_200M, "200m", NULL, 0, 200000000, }, + { HI3798_FIXED_250M, "250m", NULL, 0, 250000000, }, }; =20 static const char *const mmc_mux_p[] =3D { @@ -72,15 +72,15 @@ static const char *const sdio_mux_p[] =3D { static u32 sdio_mux_table[] =3D {0, 1, 2, 3}; =20 static struct hisi_mux_clock hi3798cv200_mux_clks[] =3D { - { HI3798CV200_MMC_MUX, "mmc_mux", mmc_mux_p, ARRAY_SIZE(mmc_mux_p), + { HI3798_MMC_MUX, "mmc_mux", mmc_mux_p, ARRAY_SIZE(mmc_mux_p), CLK_SET_RATE_PARENT, 0xa0, 8, 3, 0, mmc_mux_table, }, - { HI3798CV200_COMBPHY0_MUX, "combphy0_mux", + { HI3798_COMBPHY0_MUX, "combphy0_mux", comphy_mux_p, ARRAY_SIZE(comphy_mux_p), CLK_SET_RATE_PARENT, 0x188, 2, 2, 0, comphy_mux_table, }, - { HI3798CV200_COMBPHY1_MUX, "combphy1_mux", + { HI3798_COMBPHY1_MUX, "combphy1_mux", comphy_mux_p, ARRAY_SIZE(comphy_mux_p), CLK_SET_RATE_PARENT, 0x188, 10, 2, 0, comphy_mux_table, }, - { HI3798CV200_SDIO0_MUX, "sdio0_mux", sdio_mux_p, + { HI3798_SDIO0_MUX, "sdio0_mux", sdio_mux_p, ARRAY_SIZE(sdio_mux_p), CLK_SET_RATE_PARENT, 0x9c, 8, 2, 0, sdio_mux_table, }, }; @@ -135,13 +135,13 @@ static const struct hisi_gate_clock hi3798cv200_gate_= clks[] =3D { { HISTB_PCIE_AUX_CLK, "clk_pcie_aux", "24m", CLK_SET_RATE_PARENT, 0x18c, 3, 0, }, /* Ethernet */ - { HI3798CV200_ETH_PUB_CLK, "clk_pub", NULL, + { HI3798_ETH_PUB_CLK, "clk_pub", NULL, CLK_SET_RATE_PARENT, 0xcc, 5, 0, }, - { HI3798CV200_ETH_BUS_CLK, "clk_bus", "clk_pub", + { HI3798_ETH_BUS_CLK, "clk_bus", "clk_pub", CLK_SET_RATE_PARENT, 0xcc, 0, 0, }, - { HI3798CV200_ETH_BUS0_CLK, "clk_bus_m0", "clk_bus", + { HI3798_ETH_BUS0_CLK, "clk_bus_m0", "clk_bus", CLK_SET_RATE_PARENT, 0xcc, 1, 0, }, - { HI3798CV200_ETH_BUS1_CLK, "clk_bus_m1", "clk_bus", + { HI3798_ETH_BUS1_CLK, "clk_bus_m1", "clk_bus", CLK_SET_RATE_PARENT, 0xcc, 2, 0, }, { HISTB_ETH0_MAC_CLK, "clk_mac0", "clk_bus_m0", CLK_SET_RATE_PARENT, 0xcc, 3, 0, }, @@ -199,7 +199,7 @@ static struct hisi_clock_data *hi3798cv200_clk_register( struct hisi_clock_data *clk_data; int ret; =20 - clk_data =3D hisi_clk_alloc(pdev, HI3798CV200_CRG_NR_CLKS); + clk_data =3D hisi_clk_alloc(pdev, HI3798_CRG_NR_CLKS); if (!clk_data) return ERR_PTR(-ENOMEM); =20 @@ -211,8 +211,8 @@ static struct hisi_clock_data *hi3798cv200_clk_register( if (ret) return ERR_PTR(ret); =20 - ret =3D hisi_clk_register_fixed_rate(hi3798cv200_fixed_rate_clks, - ARRAY_SIZE(hi3798cv200_fixed_rate_clks), + ret =3D hisi_clk_register_fixed_rate(hi3798_fixed_rate_clks, + ARRAY_SIZE(hi3798_fixed_rate_clks), clk_data); if (ret) return ERR_PTR(ret); @@ -245,8 +245,8 @@ static struct hisi_clock_data *hi3798cv200_clk_register( ARRAY_SIZE(hi3798cv200_mux_clks), clk_data); unregister_fixed_rate: - hisi_clk_unregister_fixed_rate(hi3798cv200_fixed_rate_clks, - ARRAY_SIZE(hi3798cv200_fixed_rate_clks), + hisi_clk_unregister_fixed_rate(hi3798_fixed_rate_clks, + ARRAY_SIZE(hi3798_fixed_rate_clks), clk_data); return ERR_PTR(ret); } @@ -263,8 +263,8 @@ static void hi3798cv200_clk_unregister(struct platform_= device *pdev) hisi_clk_unregister_mux(hi3798cv200_mux_clks, ARRAY_SIZE(hi3798cv200_mux_clks), crg->clk_data); - hisi_clk_unregister_fixed_rate(hi3798cv200_fixed_rate_clks, - ARRAY_SIZE(hi3798cv200_fixed_rate_clks), + hisi_clk_unregister_fixed_rate(hi3798_fixed_rate_clks, + ARRAY_SIZE(hi3798_fixed_rate_clks), crg->clk_data); } =20 @@ -273,9 +273,9 @@ static const struct hisi_crg_funcs hi3798cv200_crg_func= s =3D { .unregister_clks =3D hi3798cv200_clk_unregister, }; =20 -/* hi3798CV200 sysctrl CRG */ +/* hi3798 sysctrl CRG */ =20 -#define HI3798CV200_SYSCTRL_NR_CLKS 16 +#define HI3798_SYSCTRL_NR_CLKS 16 =20 static const struct hisi_gate_clock hi3798cv200_sysctrl_gate_clks[] =3D { { HISTB_IR_CLK, "clk_ir", "24m", @@ -292,7 +292,7 @@ static struct hisi_clock_data *hi3798cv200_sysctrl_clk_= register( struct hisi_clock_data *clk_data; int ret; =20 - clk_data =3D hisi_clk_alloc(pdev, HI3798CV200_SYSCTRL_NR_CLKS); + clk_data =3D hisi_clk_alloc(pdev, HI3798_SYSCTRL_NR_CLKS); if (!clk_data) return ERR_PTR(-ENOMEM); =20 @@ -332,16 +332,16 @@ static const struct hisi_crg_funcs hi3798cv200_sysctr= l_funcs =3D { .unregister_clks =3D hi3798cv200_sysctrl_clk_unregister, }; =20 -static const struct of_device_id hi3798cv200_crg_match_table[] =3D { +static const struct of_device_id hi3798_crg_match_table[] =3D { { .compatible =3D "hisilicon,hi3798cv200-crg", .data =3D &hi3798cv200_crg_funcs }, { .compatible =3D "hisilicon,hi3798cv200-sysctrl", .data =3D &hi3798cv200_sysctrl_funcs }, { } }; -MODULE_DEVICE_TABLE(of, hi3798cv200_crg_match_table); +MODULE_DEVICE_TABLE(of, hi3798_crg_match_table); =20 -static int hi3798cv200_crg_probe(struct platform_device *pdev) +static int hi3798_crg_probe(struct platform_device *pdev) { struct hisi_crg_dev *crg; =20 @@ -367,7 +367,7 @@ static int hi3798cv200_crg_probe(struct platform_device= *pdev) return 0; } =20 -static int hi3798cv200_crg_remove(struct platform_device *pdev) +static int hi3798_crg_remove(struct platform_device *pdev) { struct hisi_crg_dev *crg =3D platform_get_drvdata(pdev); =20 @@ -376,26 +376,27 @@ static int hi3798cv200_crg_remove(struct platform_dev= ice *pdev) return 0; } =20 -static struct platform_driver hi3798cv200_crg_driver =3D { - .probe =3D hi3798cv200_crg_probe, - .remove =3D hi3798cv200_crg_remove, +static struct platform_driver hi3798_crg_driver =3D { + .probe =3D hi3798_crg_probe, + .remove =3D hi3798_crg_remove, .driver =3D { - .name =3D "hi3798cv200-crg", - .of_match_table =3D hi3798cv200_crg_match_table, + .name =3D "hi3798-crg", + .of_match_table =3D hi3798_crg_match_table, + .of_match_table =3D hi3798_crg_match_table, }, }; =20 -static int __init hi3798cv200_crg_init(void) +static int __init hi3798_crg_init(void) { - return platform_driver_register(&hi3798cv200_crg_driver); + return platform_driver_register(&hi3798_crg_driver); } -core_initcall(hi3798cv200_crg_init); +core_initcall(hi3798_crg_init); =20 -static void __exit hi3798cv200_crg_exit(void) +static void __exit hi3798_crg_exit(void) { - platform_driver_unregister(&hi3798cv200_crg_driver); + platform_driver_unregister(&hi3798_crg_driver); } -module_exit(hi3798cv200_crg_exit); +module_exit(hi3798_crg_exit); =20 MODULE_LICENSE("GPL v2"); -MODULE_DESCRIPTION("HiSilicon Hi3798CV200 CRG Driver"); +MODULE_DESCRIPTION("HiSilicon Hi3798 CRG Driver"); --=20 2.39.1 From nobody Sat Apr 11 08:29:30 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 717CFC7EE2F for ; Fri, 3 Mar 2023 15:15:54 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230482AbjCCPPx (ORCPT ); Fri, 3 Mar 2023 10:15:53 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:59990 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231461AbjCCPPs (ORCPT ); Fri, 3 Mar 2023 10:15:48 -0500 Received: from mail-pf1-x429.google.com (mail-pf1-x429.google.com [IPv6:2607:f8b0:4864:20::429]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 387BD1F4AB; Fri, 3 Mar 2023 07:15:46 -0800 (PST) Received: by mail-pf1-x429.google.com with SMTP id a7so1742117pfx.10; Fri, 03 Mar 2023 07:15:46 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; t=1677856546; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=giFfJwXNPJLMNED9GYpA4et3XffJ1cdsmrq2P3gr9F4=; b=KwqYBsWktWCPQfD45lhXLzcJcD3IQizu11gLk+QCTCCHOetHJopzX22oQL8CL3J5Z7 n5jq+OEOuepE3M/Lo33QN2+cPKrL1vAARthBxSoYqrzL8AoCJWZ/4k3YqhVpWBYpE4Vf wofWl3P771ngFdiryBquX/af3RgvAeS+qlsA6T9BGxwG8MBwlVJ/usxT5pCI821R+SYH GmI+KTVTMe6GRJbxmC2uT3Rs0VtunPU+jgEJX+zI4WccYC/pWKLaZpUr2YLBG8/lMDrH jsSh5L/Jsq49rwW3fZ6Z/s444ayWEMsEkanPA2lPFXOC43mZ01LlHM0iAZxbtLQBfCFy VTrw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1677856546; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=giFfJwXNPJLMNED9GYpA4et3XffJ1cdsmrq2P3gr9F4=; b=kTr/E3wz5DR+RijvwX68+45Ug3FjdU1X9U8xmikfztdD7qXFDxs7LedxvHGnl5cMtV IpzERUluqW05e5y1DrLjOFq9Wyv2uMrtHlXHeMU74nk9Cai48o88xYHbKc2qsVUVvHgr kOmOgFzb4v1NnPH/B1tJktCevGUrU/Oj28fu/ggICP0ZYtkHW2AnNmuKUDo6hjRAju5v kgxB46qT9IhqmGW3/e30StWFK8cyBdnjQZrFsOHosuYaglKkV2fS2ChwZbl0rnH4D7u8 tdeuEc9jj99D4pHxZaGHkfahO+ZgIQieOR3VJAZXuPYk7IC1Wy3hNsH72fLTYC6Zw9kS dsKA== X-Gm-Message-State: AO0yUKV6bazK9oRdpj0M5lGEGRCvSpLOCUH04VcnpZuUWpAbDV4w9wMA ZYKWe5d6sJULSzQ63TRzsVA= X-Google-Smtp-Source: AK7set+/pDyTMpQl5g9S6TNhvVuTBZM8P8wmwB9xIwSvjPnB4aYzc0fr2aSs7TMZnNTOebjAu2x3Bw== X-Received: by 2002:aa7:9464:0:b0:600:cc40:2587 with SMTP id t4-20020aa79464000000b00600cc402587mr2051066pfq.6.1677856545863; Fri, 03 Mar 2023 07:15:45 -0800 (PST) Received: from y.ha.lan ([104.28.213.199]) by smtp.gmail.com with ESMTPSA id p4-20020aa78604000000b005a8bdc18453sm1739721pfn.35.2023.03.03.07.15.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 03 Mar 2023 07:15:45 -0800 (PST) From: David Yang To: mmyangfl@gmail.com Cc: Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 2/5] clk: hisilicon: Extract common functions Date: Fri, 3 Mar 2023 23:14:10 +0800 Message-Id: <20230303151417.104321-3-mmyangfl@gmail.com> X-Mailer: git-send-email 2.39.1 In-Reply-To: <20230303151417.104321-1-mmyangfl@gmail.com> References: <20230303151417.104321-1-mmyangfl@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" To be reused with other Hi3798 series SoCs. Signed-off-by: David Yang --- drivers/clk/hisilicon/crg-hi3798.c | 238 ++++++++++++++++------------- 1 file changed, 136 insertions(+), 102 deletions(-) diff --git a/drivers/clk/hisilicon/crg-hi3798.c b/drivers/clk/hisilicon/crg= -hi3798.c index bdce43fbe..9c933172b 100644 --- a/drivers/clk/hisilicon/crg-hi3798.c +++ b/drivers/clk/hisilicon/crg-hi3798.c @@ -59,6 +59,124 @@ static const struct hisi_fixed_rate_clock hi3798_fixed_= rate_clks[] =3D { { HI3798_FIXED_250M, "250m", NULL, 0, 250000000, }, }; =20 +struct hi3798_crg_clks { + const struct hisi_phase_clock *phase_clks; + int phase_clks_nums; + const struct hisi_mux_clock *mux_clks; + int mux_clks_nums; + const struct hisi_gate_clock *gate_clks; + int gate_clks_nums; +}; + +static struct hisi_clock_data *hi3798_clk_register( + struct platform_device *pdev, const struct hi3798_crg_clks *clks) +{ + struct hisi_clock_data *clk_data; + int ret; + + clk_data =3D hisi_clk_alloc(pdev, HI3798_CRG_NR_CLKS); + if (!clk_data) + return ERR_PTR(-ENOMEM); + + /* hisi_phase_clock is resource managed */ + ret =3D hisi_clk_register_phase(&pdev->dev, clks->phase_clks, + clks->phase_clks_nums, clk_data); + if (ret) + return ERR_PTR(ret); + + ret =3D hisi_clk_register_fixed_rate(hi3798_fixed_rate_clks, + ARRAY_SIZE(hi3798_fixed_rate_clks), + clk_data); + if (ret) + return ERR_PTR(ret); + + ret =3D hisi_clk_register_mux(clks->mux_clks, clks->mux_clks_nums, clk_da= ta); + if (ret) + goto unregister_fixed_rate; + + ret =3D hisi_clk_register_gate(clks->gate_clks, clks->gate_clks_nums, clk= _data); + if (ret) + goto unregister_mux; + + ret =3D of_clk_add_provider(pdev->dev.of_node, + of_clk_src_onecell_get, &clk_data->clk_data); + if (ret) + goto unregister_gate; + + return clk_data; + +unregister_gate: + hisi_clk_unregister_gate(clks->gate_clks, clks->gate_clks_nums, clk_data); +unregister_mux: + hisi_clk_unregister_mux(clks->mux_clks, clks->mux_clks_nums, clk_data); +unregister_fixed_rate: + hisi_clk_unregister_fixed_rate(hi3798_fixed_rate_clks, + ARRAY_SIZE(hi3798_fixed_rate_clks), + clk_data); + return ERR_PTR(ret); +} + +static void hi3798_clk_unregister( + struct platform_device *pdev, const struct hi3798_crg_clks *clks) +{ + struct hisi_crg_dev *crg =3D platform_get_drvdata(pdev); + + of_clk_del_provider(pdev->dev.of_node); + + hisi_clk_unregister_gate(clks->gate_clks, clks->gate_clks_nums, crg->clk_= data); + hisi_clk_unregister_mux(clks->mux_clks, clks->mux_clks_nums, crg->clk_dat= a); + hisi_clk_unregister_fixed_rate(hi3798_fixed_rate_clks, + ARRAY_SIZE(hi3798_fixed_rate_clks), + crg->clk_data); +} + +/* hi3798 sysctrl CRG */ + +#define HI3798_SYSCTRL_NR_CLKS 16 + +struct hi3798_sysctrl_clks { + const struct hisi_gate_clock *gate_clks; + int gate_clks_nums; +}; + +static struct hisi_clock_data *hi3798_sysctrl_clk_register( + struct platform_device *pdev, const struct hi3798_sysctrl_clks *clks) +{ + struct hisi_clock_data *clk_data; + int ret; + + clk_data =3D hisi_clk_alloc(pdev, HI3798_SYSCTRL_NR_CLKS); + if (!clk_data) + return ERR_PTR(-ENOMEM); + + ret =3D hisi_clk_register_gate(clks->gate_clks, clks->gate_clks_nums, clk= _data); + if (ret) + return ERR_PTR(ret); + + ret =3D of_clk_add_provider(pdev->dev.of_node, + of_clk_src_onecell_get, &clk_data->clk_data); + if (ret) + goto unregister_gate; + + return clk_data; + +unregister_gate: + hisi_clk_unregister_gate(clks->gate_clks, clks->gate_clks_nums, clk_data); + return ERR_PTR(ret); +} + +static void hi3798_sysctrl_clk_unregister( + struct platform_device *pdev, const struct hi3798_sysctrl_clks *clks) +{ + struct hisi_crg_dev *crg =3D platform_get_drvdata(pdev); + + of_clk_del_provider(pdev->dev.of_node); + + hisi_clk_unregister_gate(clks->gate_clks, clks->gate_clks_nums, crg->clk_= data); +} + +/* hi3798CV200 */ + static const char *const mmc_mux_p[] =3D { "100m", "50m", "25m", "200m", "150m" }; static u32 mmc_mux_table[] =3D {0, 1, 2, 3, 6}; @@ -193,79 +311,24 @@ static const struct hisi_gate_clock hi3798cv200_gate_= clks[] =3D { CLK_SET_RATE_PARENT, 0xb0, 18, 0 }, }; =20 +static const struct hi3798_crg_clks hi3798cv200_crg_clks_data =3D { + .phase_clks =3D hi3798cv200_phase_clks, + .phase_clks_nums =3D ARRAY_SIZE(hi3798cv200_phase_clks), + .mux_clks =3D hi3798cv200_mux_clks, + .mux_clks_nums =3D ARRAY_SIZE(hi3798cv200_mux_clks), + .gate_clks =3D hi3798cv200_gate_clks, + .gate_clks_nums =3D ARRAY_SIZE(hi3798cv200_gate_clks), +}; + static struct hisi_clock_data *hi3798cv200_clk_register( struct platform_device *pdev) { - struct hisi_clock_data *clk_data; - int ret; - - clk_data =3D hisi_clk_alloc(pdev, HI3798_CRG_NR_CLKS); - if (!clk_data) - return ERR_PTR(-ENOMEM); - - /* hisi_phase_clock is resource managed */ - ret =3D hisi_clk_register_phase(&pdev->dev, - hi3798cv200_phase_clks, - ARRAY_SIZE(hi3798cv200_phase_clks), - clk_data); - if (ret) - return ERR_PTR(ret); - - ret =3D hisi_clk_register_fixed_rate(hi3798_fixed_rate_clks, - ARRAY_SIZE(hi3798_fixed_rate_clks), - clk_data); - if (ret) - return ERR_PTR(ret); - - ret =3D hisi_clk_register_mux(hi3798cv200_mux_clks, - ARRAY_SIZE(hi3798cv200_mux_clks), - clk_data); - if (ret) - goto unregister_fixed_rate; - - ret =3D hisi_clk_register_gate(hi3798cv200_gate_clks, - ARRAY_SIZE(hi3798cv200_gate_clks), - clk_data); - if (ret) - goto unregister_mux; - - ret =3D of_clk_add_provider(pdev->dev.of_node, - of_clk_src_onecell_get, &clk_data->clk_data); - if (ret) - goto unregister_gate; - - return clk_data; - -unregister_gate: - hisi_clk_unregister_gate(hi3798cv200_gate_clks, - ARRAY_SIZE(hi3798cv200_gate_clks), - clk_data); -unregister_mux: - hisi_clk_unregister_mux(hi3798cv200_mux_clks, - ARRAY_SIZE(hi3798cv200_mux_clks), - clk_data); -unregister_fixed_rate: - hisi_clk_unregister_fixed_rate(hi3798_fixed_rate_clks, - ARRAY_SIZE(hi3798_fixed_rate_clks), - clk_data); - return ERR_PTR(ret); + return hi3798_clk_register(pdev, &hi3798cv200_crg_clks_data); } =20 static void hi3798cv200_clk_unregister(struct platform_device *pdev) { - struct hisi_crg_dev *crg =3D platform_get_drvdata(pdev); - - of_clk_del_provider(pdev->dev.of_node); - - hisi_clk_unregister_gate(hi3798cv200_gate_clks, - ARRAY_SIZE(hi3798cv200_gate_clks), - crg->clk_data); - hisi_clk_unregister_mux(hi3798cv200_mux_clks, - ARRAY_SIZE(hi3798cv200_mux_clks), - crg->clk_data); - hisi_clk_unregister_fixed_rate(hi3798_fixed_rate_clks, - ARRAY_SIZE(hi3798_fixed_rate_clks), - crg->clk_data); + hi3798_clk_unregister(pdev, &hi3798cv200_crg_clks_data); } =20 static const struct hisi_crg_funcs hi3798cv200_crg_funcs =3D { @@ -273,10 +336,6 @@ static const struct hisi_crg_funcs hi3798cv200_crg_fun= cs =3D { .unregister_clks =3D hi3798cv200_clk_unregister, }; =20 -/* hi3798 sysctrl CRG */ - -#define HI3798_SYSCTRL_NR_CLKS 16 - static const struct hisi_gate_clock hi3798cv200_sysctrl_gate_clks[] =3D { { HISTB_IR_CLK, "clk_ir", "24m", CLK_SET_RATE_PARENT, 0x48, 4, 0, }, @@ -286,45 +345,20 @@ static const struct hisi_gate_clock hi3798cv200_sysct= rl_gate_clks[] =3D { CLK_SET_RATE_PARENT, 0x48, 10, 0, }, }; =20 +static const struct hi3798_sysctrl_clks hi3798cv200_sysctrl_clks_data =3D { + .gate_clks =3D hi3798cv200_sysctrl_gate_clks, + .gate_clks_nums =3D ARRAY_SIZE(hi3798cv200_sysctrl_gate_clks), +}; + static struct hisi_clock_data *hi3798cv200_sysctrl_clk_register( struct platform_device *pdev) { - struct hisi_clock_data *clk_data; - int ret; - - clk_data =3D hisi_clk_alloc(pdev, HI3798_SYSCTRL_NR_CLKS); - if (!clk_data) - return ERR_PTR(-ENOMEM); - - ret =3D hisi_clk_register_gate(hi3798cv200_sysctrl_gate_clks, - ARRAY_SIZE(hi3798cv200_sysctrl_gate_clks), - clk_data); - if (ret) - return ERR_PTR(ret); - - ret =3D of_clk_add_provider(pdev->dev.of_node, - of_clk_src_onecell_get, &clk_data->clk_data); - if (ret) - goto unregister_gate; - - return clk_data; - -unregister_gate: - hisi_clk_unregister_gate(hi3798cv200_sysctrl_gate_clks, - ARRAY_SIZE(hi3798cv200_sysctrl_gate_clks), - clk_data); - return ERR_PTR(ret); + return hi3798_sysctrl_clk_register(pdev, &hi3798cv200_sysctrl_clks_data); } =20 static void hi3798cv200_sysctrl_clk_unregister(struct platform_device *pde= v) { - struct hisi_crg_dev *crg =3D platform_get_drvdata(pdev); - - of_clk_del_provider(pdev->dev.of_node); - - hisi_clk_unregister_gate(hi3798cv200_sysctrl_gate_clks, - ARRAY_SIZE(hi3798cv200_sysctrl_gate_clks), - crg->clk_data); + hi3798_sysctrl_clk_unregister(pdev, &hi3798cv200_sysctrl_clks_data); } =20 static const struct hisi_crg_funcs hi3798cv200_sysctrl_funcs =3D { --=20 2.39.1 From nobody Sat Apr 11 08:29:30 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 15E35C7EE2D for ; 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Fri, 03 Mar 2023 07:15:57 -0800 (PST) From: David Yang To: mmyangfl@gmail.com Cc: Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 3/5] clk: hisilicon: Rename some symbols for Hi3798CV200 Date: Fri, 3 Mar 2023 23:14:11 +0800 Message-Id: <20230303151417.104321-4-mmyangfl@gmail.com> X-Mailer: git-send-email 2.39.1 In-Reply-To: <20230303151417.104321-1-mmyangfl@gmail.com> References: <20230303151417.104321-1-mmyangfl@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" These symbols might cause confusion when adding support for other Hi3798 series SoCs. Signed-off-by: David Yang --- drivers/clk/hisilicon/crg-hi3798.c | 41 ++++++++++++------------- include/dt-bindings/clock/histb-clock.h | 2 ++ 2 files changed, 22 insertions(+), 21 deletions(-) diff --git a/drivers/clk/hisilicon/crg-hi3798.c b/drivers/clk/hisilicon/crg= -hi3798.c index 9c933172b..f834805d7 100644 --- a/drivers/clk/hisilicon/crg-hi3798.c +++ b/drivers/clk/hisilicon/crg-hi3798.c @@ -27,8 +27,6 @@ #define HI3798_FIXED_300M 73 #define HI3798_FIXED_400M 74 #define HI3798_MMC_MUX 75 -#define HI3798_ETH_PUB_CLK 76 -#define HI3798_ETH_BUS_CLK 77 #define HI3798_ETH_BUS0_CLK 78 #define HI3798_ETH_BUS1_CLK 79 #define HI3798_COMBPHY1_MUX 80 @@ -177,30 +175,31 @@ static void hi3798_sysctrl_clk_unregister( =20 /* hi3798CV200 */ =20 -static const char *const mmc_mux_p[] =3D { +static const char *const hi3798cv200_mmc_mux_p[] =3D { "100m", "50m", "25m", "200m", "150m" }; -static u32 mmc_mux_table[] =3D {0, 1, 2, 3, 6}; +static u32 hi3798cv200_mmc_mux_table[] =3D {0, 1, 2, 3, 6}; =20 -static const char *const comphy_mux_p[] =3D { +static const char *const hi3798cv200_comphy_mux_p[] =3D { "100m", "25m"}; -static u32 comphy_mux_table[] =3D {2, 3}; +static u32 hi3798cv200_comphy_mux_table[] =3D {2, 3}; =20 -static const char *const sdio_mux_p[] =3D { +static const char *const hi3798cv200_sdio_mux_p[] =3D { "100m", "50m", "150m", "166p5m" }; -static u32 sdio_mux_table[] =3D {0, 1, 2, 3}; +static u32 hi3798cv200_sdio_mux_table[] =3D {0, 1, 2, 3}; =20 static struct hisi_mux_clock hi3798cv200_mux_clks[] =3D { - { HI3798_MMC_MUX, "mmc_mux", mmc_mux_p, ARRAY_SIZE(mmc_mux_p), - CLK_SET_RATE_PARENT, 0xa0, 8, 3, 0, mmc_mux_table, }, - { HI3798_COMBPHY0_MUX, "combphy0_mux", - comphy_mux_p, ARRAY_SIZE(comphy_mux_p), - CLK_SET_RATE_PARENT, 0x188, 2, 2, 0, comphy_mux_table, }, - { HI3798_COMBPHY1_MUX, "combphy1_mux", - comphy_mux_p, ARRAY_SIZE(comphy_mux_p), - CLK_SET_RATE_PARENT, 0x188, 10, 2, 0, comphy_mux_table, }, - { HI3798_SDIO0_MUX, "sdio0_mux", sdio_mux_p, - ARRAY_SIZE(sdio_mux_p), CLK_SET_RATE_PARENT, - 0x9c, 8, 2, 0, sdio_mux_table, }, + { HI3798_MMC_MUX, "mmc_mux", hi3798cv200_mmc_mux_p, + ARRAY_SIZE(hi3798cv200_mmc_mux_p), CLK_SET_RATE_PARENT, + 0xa0, 8, 3, 0, hi3798cv200_mmc_mux_table, }, + { HI3798_COMBPHY0_MUX, "combphy0_mux", hi3798cv200_comphy_mux_p, + ARRAY_SIZE(hi3798cv200_comphy_mux_p), CLK_SET_RATE_PARENT, + 0x188, 2, 2, 0, hi3798cv200_comphy_mux_table, }, + { HI3798_COMBPHY1_MUX, "combphy1_mux", hi3798cv200_comphy_mux_p, + ARRAY_SIZE(hi3798cv200_comphy_mux_p), CLK_SET_RATE_PARENT, + 0x188, 10, 2, 0, hi3798cv200_comphy_mux_table, }, + { HI3798_SDIO0_MUX, "sdio0_mux", hi3798cv200_sdio_mux_p, + ARRAY_SIZE(hi3798cv200_sdio_mux_p), CLK_SET_RATE_PARENT, + 0x9c, 8, 2, 0, hi3798cv200_sdio_mux_table, }, }; =20 static u32 mmc_phase_regvals[] =3D {0, 1, 2, 3, 4, 5, 6, 7}; @@ -253,9 +252,9 @@ static const struct hisi_gate_clock hi3798cv200_gate_cl= ks[] =3D { { HISTB_PCIE_AUX_CLK, "clk_pcie_aux", "24m", CLK_SET_RATE_PARENT, 0x18c, 3, 0, }, /* Ethernet */ - { HI3798_ETH_PUB_CLK, "clk_pub", NULL, + { HISTB_ETH_PUB_CLK, "clk_pub", NULL, CLK_SET_RATE_PARENT, 0xcc, 5, 0, }, - { HI3798_ETH_BUS_CLK, "clk_bus", "clk_pub", + { HISTB_ETH_BUS_CLK, "clk_bus", "clk_pub", CLK_SET_RATE_PARENT, 0xcc, 0, 0, }, { HI3798_ETH_BUS0_CLK, "clk_bus_m0", "clk_bus", CLK_SET_RATE_PARENT, 0xcc, 1, 0, }, diff --git a/include/dt-bindings/clock/histb-clock.h b/include/dt-bindings/= clock/histb-clock.h index e64e5770a..ed47c43c3 100644 --- a/include/dt-bindings/clock/histb-clock.h +++ b/include/dt-bindings/clock/histb-clock.h @@ -58,6 +58,8 @@ #define HISTB_USB3_UTMI_CLK1 48 #define HISTB_USB3_PIPE_CLK1 49 #define HISTB_USB3_SUSPEND_CLK1 50 +#define HISTB_ETH_PUB_CLK 51 +#define HISTB_ETH_BUS_CLK 52 =20 /* clocks provided by mcu CRG */ #define HISTB_MCE_CLK 1 --=20 2.39.1 From nobody Sat Apr 11 08:29:30 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 846E9C64EC4 for ; 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Fri, 03 Mar 2023 07:16:10 -0800 (PST) Received: from y.ha.lan ([104.28.213.199]) by smtp.gmail.com with ESMTPSA id p4-20020aa78604000000b005a8bdc18453sm1739721pfn.35.2023.03.03.07.16.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 03 Mar 2023 07:16:09 -0800 (PST) From: David Yang To: mmyangfl@gmail.com Cc: Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 4/5] clk: hisilicon: Add inner clocks for Hi3798MV100 Date: Fri, 3 Mar 2023 23:14:12 +0800 Message-Id: <20230303151417.104321-5-mmyangfl@gmail.com> X-Mailer: git-send-email 2.39.1 In-Reply-To: <20230303151417.104321-1-mmyangfl@gmail.com> References: <20230303151417.104321-1-mmyangfl@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" These are inner clocks for Hi3798MV100, but not exist on Hi3798CV200. Signed-off-by: David Yang --- drivers/clk/hisilicon/crg-hi3798.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/drivers/clk/hisilicon/crg-hi3798.c b/drivers/clk/hisilicon/crg= -hi3798.c index f834805d7..791d39e6a 100644 --- a/drivers/clk/hisilicon/crg-hi3798.c +++ b/drivers/clk/hisilicon/crg-hi3798.c @@ -36,6 +36,9 @@ #define HI3798_FIXED_166P5M 84 #define HI3798_SDIO0_MUX 85 #define HI3798_COMBPHY0_MUX 86 +#define HI3798_FIXED_3M 87 +#define HI3798_FIXED_15M 88 +#define HI3798_FIXED_83P3M 89 =20 #define HI3798_CRG_NR_CLKS 128 =20 @@ -43,13 +46,16 @@ static const struct hisi_fixed_rate_clock hi3798_fixed_= rate_clks[] =3D { { HISTB_OSC_CLK, "clk_osc", NULL, 0, 24000000, }, { HISTB_APB_CLK, "clk_apb", NULL, 0, 100000000, }, { HISTB_AHB_CLK, "clk_ahb", NULL, 0, 200000000, }, + { HI3798_FIXED_3M, "3m", NULL, 0, 3000000, }, { HI3798_FIXED_12M, "12m", NULL, 0, 12000000, }, + { HI3798_FIXED_15M, "15m", NULL, 0, 15000000, }, { HI3798_FIXED_24M, "24m", NULL, 0, 24000000, }, { HI3798_FIXED_25M, "25m", NULL, 0, 25000000, }, { HI3798_FIXED_48M, "48m", NULL, 0, 48000000, }, { HI3798_FIXED_50M, "50m", NULL, 0, 50000000, }, { HI3798_FIXED_60M, "60m", NULL, 0, 60000000, }, { HI3798_FIXED_75M, "75m", NULL, 0, 75000000, }, + { HI3798_FIXED_83P3M, "83p3m", NULL, 0, 83333333, }, { HI3798_FIXED_100M, "100m", NULL, 0, 100000000, }, { HI3798_FIXED_150M, "150m", NULL, 0, 150000000, }, { HI3798_FIXED_166P5M, "166p5m", NULL, 0, 165000000, }, --=20 2.39.1 From nobody Sat Apr 11 08:29:30 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 765DAC64EC4 for ; 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Fri, 03 Mar 2023 07:16:21 -0800 (PST) From: David Yang To: mmyangfl@gmail.com Cc: Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 5/5] clk: hisilicon: Add CRG driver for Hi3798MV100 SoC Date: Fri, 3 Mar 2023 23:14:13 +0800 Message-Id: <20230303151417.104321-6-mmyangfl@gmail.com> X-Mailer: git-send-email 2.39.1 In-Reply-To: <20230303151417.104321-1-mmyangfl@gmail.com> References: <20230303151417.104321-1-mmyangfl@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add CRG driver for Hi3798MV100 SoC. CRG (Clock and Reset Generator) module generates clock and reset signals used by other module blocks on SoC. Signed-off-by: David Yang --- .../devicetree/bindings/clock/hisi-crg.txt | 2 + drivers/clk/hisilicon/crg-hi3798.c | 193 ++++++++++++++++-- include/dt-bindings/clock/histb-clock.h | 11 + 3 files changed, 192 insertions(+), 14 deletions(-) diff --git a/Documentation/devicetree/bindings/clock/hisi-crg.txt b/Documen= tation/devicetree/bindings/clock/hisi-crg.txt index cc60b3d42..972c038c8 100644 --- a/Documentation/devicetree/bindings/clock/hisi-crg.txt +++ b/Documentation/devicetree/bindings/clock/hisi-crg.txt @@ -13,6 +13,8 @@ Required Properties: - "hisilicon,hi3516cv300-crg" - "hisilicon,hi3516cv300-sysctrl" - "hisilicon,hi3519-crg" + - "hisilicon,hi3798mv100-crg" + - "hisilicon,hi3798mv100-sysctrl" - "hisilicon,hi3798cv200-crg" - "hisilicon,hi3798cv200-sysctrl" =20 diff --git a/drivers/clk/hisilicon/crg-hi3798.c b/drivers/clk/hisilicon/crg= -hi3798.c index 791d39e6a..095009c91 100644 --- a/drivers/clk/hisilicon/crg-hi3798.c +++ b/drivers/clk/hisilicon/crg-hi3798.c @@ -27,6 +27,7 @@ #define HI3798_FIXED_300M 73 #define HI3798_FIXED_400M 74 #define HI3798_MMC_MUX 75 +#define HI3798_ETH_MUX 77 #define HI3798_ETH_BUS0_CLK 78 #define HI3798_ETH_BUS1_CLK 79 #define HI3798_COMBPHY1_MUX 80 @@ -179,6 +180,178 @@ static void hi3798_sysctrl_clk_unregister( hisi_clk_unregister_gate(clks->gate_clks, clks->gate_clks_nums, crg->clk_= data); } =20 +/* hi3798MV100 */ + +static const char *const hi3798mv100_mmc_mux_p[] =3D { + "75m", "100m", "50m", "15m" }; +static u32 hi3798mv100_mmc_mux_table[] =3D {0, 1, 2, 3}; + +static const char *const hi3798mv100_eth_mux_p[] =3D { + "83p3m" }; +static u32 hi3798mv100_eth_mux_table[] =3D {2}; + +static struct hisi_mux_clock hi3798mv100_mux_clks[] =3D { + { HI3798_MMC_MUX, "mmc_mux", hi3798mv100_mmc_mux_p, + ARRAY_SIZE(hi3798mv100_mmc_mux_p), CLK_SET_RATE_PARENT, + 0xa0, 8, 2, 0, hi3798mv100_mmc_mux_table, }, + { HI3798_SDIO0_MUX, "sdio0_mux", hi3798mv100_mmc_mux_p, + ARRAY_SIZE(hi3798mv100_mmc_mux_p), CLK_SET_RATE_PARENT, + 0x9c, 8, 2, 0, hi3798mv100_mmc_mux_table, }, + { HI3798_ETH_MUX, "eth_mux", hi3798mv100_eth_mux_p, + ARRAY_SIZE(hi3798mv100_eth_mux_p), CLK_SET_RATE_PARENT, + 0xcc, 2, 2, 0, hi3798mv100_eth_mux_table, }, +}; + +static u32 mmc_phase_regvals[] =3D {0, 1, 2, 3, 4, 5, 6, 7}; +static u32 mmc_phase_degrees[] =3D {0, 45, 90, 135, 180, 225, 270, 315}; + +static struct hisi_phase_clock hi3798mv100_phase_clks[] =3D { + { HISTB_MMC_SAMPLE_CLK, "mmc_sample", "clk_mmc_ciu", + CLK_SET_RATE_PARENT, 0xa0, 12, 3, mmc_phase_degrees, + mmc_phase_regvals, ARRAY_SIZE(mmc_phase_regvals) }, + { HISTB_MMC_DRV_CLK, "mmc_drive", "clk_mmc_ciu", + CLK_SET_RATE_PARENT, 0xa0, 16, 3, mmc_phase_degrees, + mmc_phase_regvals, ARRAY_SIZE(mmc_phase_regvals) }, +}; + +static const struct hisi_gate_clock hi3798mv100_gate_clks[] =3D { + /* NAND */ + { HISTB_NAND_CLK, "clk_nand", "clk_apb", + CLK_SET_RATE_PARENT, 0x60, 0, 0, }, + /* UART */ + { HISTB_UART1_CLK, "clk_uart1", "3m", + CLK_SET_RATE_PARENT, 0x68, 0, 0, }, + { HISTB_UART2_CLK, "clk_uart2", "83p3m", + CLK_SET_RATE_PARENT, 0x68, 4, 0, }, + /* I2C */ + { HISTB_I2C0_CLK, "clk_i2c0", "clk_apb", + CLK_SET_RATE_PARENT, 0x6C, 4, 0, }, + { HISTB_I2C1_CLK, "clk_i2c1", "clk_apb", + CLK_SET_RATE_PARENT, 0x6C, 8, 0, }, + { HISTB_I2C2_CLK, "clk_i2c2", "clk_apb", + CLK_SET_RATE_PARENT, 0x6C, 12, 0, }, + /* SPI */ + { HISTB_SPI0_CLK, "clk_spi0", "clk_apb", + CLK_SET_RATE_PARENT, 0x70, 0, 0, }, + /* SDIO */ + { HISTB_SDIO0_BIU_CLK, "clk_sdio0_biu", "200m", + CLK_SET_RATE_PARENT, 0x9c, 0, 0, }, + { HISTB_SDIO0_CIU_CLK, "clk_sdio0_ciu", "sdio0_mux", + CLK_SET_RATE_PARENT, 0x9c, 1, 0, }, + /* EMMC */ + { HISTB_MMC_BIU_CLK, "clk_mmc_biu", "200m", + CLK_SET_RATE_PARENT, 0xa0, 0, 0, }, + { HISTB_MMC_CIU_CLK, "clk_mmc_ciu", "mmc_mux", + CLK_SET_RATE_PARENT, 0xa0, 1, 0, }, + /* Ethernet */ + { HISTB_ETH_BUS_CLK, "clk_bus", NULL, + CLK_SET_RATE_PARENT, 0xcc, 0, 0, }, + { HISTB_ETH_PUB_CLK, "clk_pub", "eth_mux", + CLK_SET_RATE_PARENT, 0xcc, 1, 0, }, + /* USB2 */ + { HISTB_USB2_BUS_CLK, "clk_u2_bus", "clk_ahb", + CLK_SET_RATE_PARENT, 0xb8, 0, 0, }, + { HISTB_USB2_PHY_CLK, "clk_u2_phy", "60m", + CLK_SET_RATE_PARENT, 0xb8, 4, 0, }, + { HISTB_USB2_12M_CLK, "clk_u2_12m", "12m", + CLK_SET_RATE_PARENT, 0xb8, 2, 0 }, + { HISTB_USB2_48M_CLK, "clk_u2_48m", "48m", + CLK_SET_RATE_PARENT, 0xb8, 1, 0 }, + { HISTB_USB2_UTMI_CLK, "clk_u2_utmi", "60m", + CLK_SET_RATE_PARENT, 0xb8, 5, 0 }, + { HISTB_USB2_UTMI_CLK1, "clk_u2_utmi1", "60m", + CLK_SET_RATE_PARENT, 0xb8, 6, 0 }, + { HISTB_USB2_OTG_UTMI_CLK, "clk_u2_otg_utmi", "60m", + CLK_SET_RATE_PARENT, 0xb8, 3, 0 }, + { HISTB_USB2_PHY1_REF_CLK, "clk_u2_phy1_ref", "24m", + CLK_SET_RATE_PARENT, 0xbc, 0, 0 }, + { HISTB_USB2_PHY2_REF_CLK, "clk_u2_phy2_ref", "24m", + CLK_SET_RATE_PARENT, 0xbc, 2, 0 }, + /* USB2 2 */ + { HISTB_USB2_2_BUS_CLK, "clk_u2_2_bus", "clk_ahb", + CLK_SET_RATE_PARENT, 0x198, 0, 0, }, + { HISTB_USB2_2_PHY_CLK, "clk_u2_2_phy", "60m", + CLK_SET_RATE_PARENT, 0x198, 4, 0, }, + { HISTB_USB2_2_12M_CLK, "clk_u2_2_12m", "12m", + CLK_SET_RATE_PARENT, 0x198, 2, 0 }, + { HISTB_USB2_2_48M_CLK, "clk_u2_2_48m", "48m", + CLK_SET_RATE_PARENT, 0x198, 1, 0 }, + { HISTB_USB2_2_UTMI_CLK, "clk_u2_2_utmi", "60m", + CLK_SET_RATE_PARENT, 0x198, 5, 0 }, + { HISTB_USB2_2_UTMI_CLK1, "clk_u2_2_utmi1", "60m", + CLK_SET_RATE_PARENT, 0x198, 6, 0 }, + { HISTB_USB2_2_OTG_UTMI_CLK, "clk_u2_2_otg_utmi", "60m", + CLK_SET_RATE_PARENT, 0x198, 3, 0 }, + { HISTB_USB2_2_PHY1_REF_CLK, "clk_u2_2_phy1_ref", "24m", + CLK_SET_RATE_PARENT, 0x190, 0, 0 }, + { HISTB_USB2_2_PHY2_REF_CLK, "clk_u2_2_phy2_ref", "24m", + CLK_SET_RATE_PARENT, 0x190, 2, 0 }, + /* USB3 */ + { HISTB_USB3_BUS_CLK, "clk_u3_bus", NULL, + CLK_SET_RATE_PARENT, 0xb0, 0, 0 }, + { HISTB_USB3_UTMI_CLK, "clk_u3_utmi", NULL, + CLK_SET_RATE_PARENT, 0xb0, 4, 0 }, + { HISTB_USB3_PIPE_CLK, "clk_u3_pipe", NULL, + CLK_SET_RATE_PARENT, 0xb0, 3, 0 }, + { HISTB_USB3_SUSPEND_CLK, "clk_u3_suspend", NULL, + CLK_SET_RATE_PARENT, 0xb0, 2, 0 }, +}; + +static const struct hi3798_crg_clks hi3798mv100_crg_clks_data =3D { + .phase_clks =3D hi3798mv100_phase_clks, + .phase_clks_nums =3D ARRAY_SIZE(hi3798mv100_phase_clks), + .mux_clks =3D hi3798mv100_mux_clks, + .mux_clks_nums =3D ARRAY_SIZE(hi3798mv100_mux_clks), + .gate_clks =3D hi3798mv100_gate_clks, + .gate_clks_nums =3D ARRAY_SIZE(hi3798mv100_gate_clks), +}; + +static struct hisi_clock_data *hi3798mv100_clk_register( + struct platform_device *pdev) +{ + return hi3798_clk_register(pdev, &hi3798mv100_crg_clks_data); +} + +static void hi3798mv100_clk_unregister(struct platform_device *pdev) +{ + hi3798_clk_unregister(pdev, &hi3798mv100_crg_clks_data); +} + +static const struct hisi_crg_funcs hi3798mv100_crg_funcs =3D { + .register_clks =3D hi3798mv100_clk_register, + .unregister_clks =3D hi3798mv100_clk_unregister, +}; + +static const struct hisi_gate_clock hi3798mv100_sysctrl_gate_clks[] =3D { + { HISTB_IR_CLK, "clk_ir", "24m", + CLK_SET_RATE_PARENT, 0x48, 4, 0, }, + { HISTB_TIMER01_CLK, "clk_timer01", "24m", + CLK_SET_RATE_PARENT, 0x48, 6, 0, }, + { HISTB_UART0_CLK, "clk_uart0", "83p3m", + CLK_SET_RATE_PARENT, 0x48, 12, 0, }, +}; + +static const struct hi3798_sysctrl_clks hi3798mv100_sysctrl_clks_data =3D { + .gate_clks =3D hi3798mv100_sysctrl_gate_clks, + .gate_clks_nums =3D ARRAY_SIZE(hi3798mv100_sysctrl_gate_clks), +}; + +static struct hisi_clock_data *hi3798mv100_sysctrl_clk_register( + struct platform_device *pdev) +{ + return hi3798_sysctrl_clk_register(pdev, &hi3798mv100_sysctrl_clks_data); +} + +static void hi3798mv100_sysctrl_clk_unregister(struct platform_device *pde= v) +{ + hi3798_sysctrl_clk_unregister(pdev, &hi3798mv100_sysctrl_clks_data); +} + +static const struct hisi_crg_funcs hi3798mv100_sysctrl_funcs =3D { + .register_clks =3D hi3798mv100_sysctrl_clk_register, + .unregister_clks =3D hi3798mv100_sysctrl_clk_unregister, +}; + /* hi3798CV200 */ =20 static const char *const hi3798cv200_mmc_mux_p[] =3D { @@ -208,18 +381,6 @@ static struct hisi_mux_clock hi3798cv200_mux_clks[] = =3D { 0x9c, 8, 2, 0, hi3798cv200_sdio_mux_table, }, }; =20 -static u32 mmc_phase_regvals[] =3D {0, 1, 2, 3, 4, 5, 6, 7}; -static u32 mmc_phase_degrees[] =3D {0, 45, 90, 135, 180, 225, 270, 315}; - -static struct hisi_phase_clock hi3798cv200_phase_clks[] =3D { - { HISTB_MMC_SAMPLE_CLK, "mmc_sample", "clk_mmc_ciu", - CLK_SET_RATE_PARENT, 0xa0, 12, 3, mmc_phase_degrees, - mmc_phase_regvals, ARRAY_SIZE(mmc_phase_regvals) }, - { HISTB_MMC_DRV_CLK, "mmc_drive", "clk_mmc_ciu", - CLK_SET_RATE_PARENT, 0xa0, 16, 3, mmc_phase_degrees, - mmc_phase_regvals, ARRAY_SIZE(mmc_phase_regvals) }, -}; - static const struct hisi_gate_clock hi3798cv200_gate_clks[] =3D { /* UART */ { HISTB_UART2_CLK, "clk_uart2", "75m", @@ -317,8 +478,8 @@ static const struct hisi_gate_clock hi3798cv200_gate_cl= ks[] =3D { }; =20 static const struct hi3798_crg_clks hi3798cv200_crg_clks_data =3D { - .phase_clks =3D hi3798cv200_phase_clks, - .phase_clks_nums =3D ARRAY_SIZE(hi3798cv200_phase_clks), + .phase_clks =3D hi3798mv100_phase_clks, + .phase_clks_nums =3D ARRAY_SIZE(hi3798mv100_phase_clks), .mux_clks =3D hi3798cv200_mux_clks, .mux_clks_nums =3D ARRAY_SIZE(hi3798cv200_mux_clks), .gate_clks =3D hi3798cv200_gate_clks, @@ -372,6 +533,10 @@ static const struct hisi_crg_funcs hi3798cv200_sysctrl= _funcs =3D { }; =20 static const struct of_device_id hi3798_crg_match_table[] =3D { + { .compatible =3D "hisilicon,hi3798mv100-crg", + .data =3D &hi3798mv100_crg_funcs }, + { .compatible =3D "hisilicon,hi3798mv100-sysctrl", + .data =3D &hi3798mv100_sysctrl_funcs }, { .compatible =3D "hisilicon,hi3798cv200-crg", .data =3D &hi3798cv200_crg_funcs }, { .compatible =3D "hisilicon,hi3798cv200-sysctrl", diff --git a/include/dt-bindings/clock/histb-clock.h b/include/dt-bindings/= clock/histb-clock.h index ed47c43c3..4fbf86e75 100644 --- a/include/dt-bindings/clock/histb-clock.h +++ b/include/dt-bindings/clock/histb-clock.h @@ -60,6 +60,17 @@ #define HISTB_USB3_SUSPEND_CLK1 50 #define HISTB_ETH_PUB_CLK 51 #define HISTB_ETH_BUS_CLK 52 +#define HISTB_USB2_UTMI_CLK1 53 +#define HISTB_NAND_CLK 54 +#define HISTB_USB2_2_BUS_CLK 55 +#define HISTB_USB2_2_PHY_CLK 56 +#define HISTB_USB2_2_UTMI_CLK 57 +#define HISTB_USB2_2_UTMI_CLK1 58 +#define HISTB_USB2_2_12M_CLK 59 +#define HISTB_USB2_2_48M_CLK 60 +#define HISTB_USB2_2_OTG_UTMI_CLK 61 +#define HISTB_USB2_2_PHY1_REF_CLK 62 +#define HISTB_USB2_2_PHY2_REF_CLK 63 =20 /* clocks provided by mcu CRG */ #define HISTB_MCE_CLK 1 --=20 2.39.1