From nobody Sat Sep 21 02:38:30 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id E084FC7EE32 for ; Fri, 3 Mar 2023 03:17:45 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229861AbjCCDRo (ORCPT ); Thu, 2 Mar 2023 22:17:44 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:36734 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229455AbjCCDRj (ORCPT ); Thu, 2 Mar 2023 22:17:39 -0500 Received: from mailgw02.mediatek.com (unknown [210.61.82.184]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 358A414E89; Thu, 2 Mar 2023 19:17:35 -0800 (PST) X-UUID: ef320d66b97111ed945fc101203acc17-20230303 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=zIlJ7NybosfQq5qKIS3xQ+78hBjmgkGkVjNteGRkKmo=; b=E50r4WW2doidIVpBONyCS326BLm3tgiJVzhXgTZGRSe30mQDBjedESnN4W0xLe05W3n1KrwdQThIC18YMS0o28KLqbb16nnMrEi4qYzC7dEus7aCnPTyHe9DxU6RsXLIa20OfB3JNF1q46emUrbTLNLWR+iXkLkt7pnSgvcAt/0=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.20,REQID:f592460b-2aa3-4d94-afc9-67ecb8a47a5d,IP:0,U RL:0,TC:0,Content:0,EDM:0,RT:0,SF:0,FILE:0,BULK:0,RULE:Release_Ham,ACTION: release,TS:0 X-CID-META: VersionHash:25b5999,CLOUDID:64b13027-564d-42d9-9875-7c868ee415ec,B ulkID:nil,BulkQuantity:0,Recheck:0,SF:102,TC:nil,Content:0,EDM:-3,IP:nil,U RL:0,File:nil,Bulk:nil,QS:nil,BEC:nil,COL:0,OSI:0,OSA:0,AV:0 X-CID-BVR: 0,NGT X-UUID: ef320d66b97111ed945fc101203acc17-20230303 Received: from mtkmbs11n1.mediatek.inc [(172.21.101.185)] by mailgw02.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 262018460; Fri, 03 Mar 2023 11:17:31 +0800 Received: from mtkmbs11n1.mediatek.inc (172.21.101.185) by mtkmbs11n1.mediatek.inc (172.21.101.185) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.25; Fri, 3 Mar 2023 11:17:30 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkmbs11n1.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.1118.25 via Frontend Transport; Fri, 3 Mar 2023 11:17:29 +0800 From: Allen-KH Cheng To: Matthias Brugger , Rob Herring , Krzysztof Kozlowski , Stephen Boyd , AngeloGioacchino Del Regno CC: , , , , , , Allen-KH Cheng Subject: [PATCH v3 1/7] arm64: dts: mediatek: mt8186: Add MTU3 nodes Date: Fri, 3 Mar 2023 11:17:22 +0800 Message-ID: <20230303031728.24251-2-allen-kh.cheng@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20230303031728.24251-1-allen-kh.cheng@mediatek.com> References: <20230303031728.24251-1-allen-kh.cheng@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add MTU3 nodes for MT8186 SoC. Signed-off-by: Allen-KH Cheng Tested-by: Chen-Yu Tsai Reviewed-by: AngeloGioacchino Del Regno --- arch/arm64/boot/dts/mediatek/mt8186.dtsi | 68 ++++++++++++++++++++++++ 1 file changed, 68 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8186.dtsi b/arch/arm64/boot/dts= /mediatek/mt8186.dtsi index a0d3e1f731bd..178421fd8380 100644 --- a/arch/arm64/boot/dts/mediatek/mt8186.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8186.dtsi @@ -981,6 +981,40 @@ status =3D "disabled"; }; =20 + ssusb0: usb@11201000 { + compatible =3D "mediatek,mt8186-mtu3", "mediatek,mtu3"; + reg =3D <0 0x11201000 0 0x2dff>, <0 0x11203e00 0 0x0100>; + reg-names =3D "mac", "ippc"; + clocks =3D <&topckgen CLK_TOP_USB_TOP>, + <&infracfg_ao CLK_INFRA_AO_SSUSB_TOP_REF>, + <&infracfg_ao CLK_INFRA_AO_SSUSB_TOP_HCLK>, + <&infracfg_ao CLK_INFRA_AO_ICUSB>; + clock-names =3D "sys_ck", "ref_ck", "mcu_ck", "dma_ck"; + interrupts =3D ; + phys =3D <&u2port0 PHY_TYPE_USB2>; + power-domains =3D <&spm MT8186_POWER_DOMAIN_SSUSB>; + #address-cells =3D <2>; + #size-cells =3D <2>; + ranges; + status =3D "disabled"; + + usb_host0: usb@11200000 { + compatible =3D "mediatek,mt8186-xhci", "mediatek,mtk-xhci"; + reg =3D <0 0x11200000 0 0x1000>; + reg-names =3D "mac"; + clocks =3D <&topckgen CLK_TOP_USB_TOP>, + <&infracfg_ao CLK_INFRA_AO_SSUSB_TOP_REF>, + <&infracfg_ao CLK_INFRA_AO_SSUSB_TOP_HCLK>, + <&infracfg_ao CLK_INFRA_AO_ICUSB>, + <&infracfg_ao CLK_INFRA_AO_SSUSB_TOP_XHCI>; + clock-names =3D "sys_ck", "ref_ck", "mcu_ck", "dma_ck", "xhci_ck"; + interrupts =3D ; + mediatek,syscon-wakeup =3D <&pericfg 0x420 2>; + wakeup-source; + status =3D "disabled"; + }; + }; + mmc0: mmc@11230000 { compatible =3D "mediatek,mt8186-mmc", "mediatek,mt8183-mmc"; @@ -1012,6 +1046,40 @@ status =3D "disabled"; }; =20 + ssusb1: usb@11281000 { + compatible =3D "mediatek,mt8186-mtu3", "mediatek,mtu3"; + reg =3D <0 0x11281000 0 0x2dff>, <0 0x11283e00 0 0x0100>; + reg-names =3D "mac", "ippc"; + clocks =3D <&infracfg_ao CLK_INFRA_AO_SSUSB_TOP_P1_SYS>, + <&infracfg_ao CLK_INFRA_AO_SSUSB_TOP_P1_REF>, + <&infracfg_ao CLK_INFRA_AO_SSUSB_TOP_P1_HCLK>, + <&clk26m>; + clock-names =3D "sys_ck", "ref_ck", "mcu_ck", "dma_ck"; + interrupts =3D ; + phys =3D <&u2port1 PHY_TYPE_USB2>, <&u3port1 PHY_TYPE_USB3>; + power-domains =3D <&spm MT8186_POWER_DOMAIN_SSUSB_P1>; + #address-cells =3D <2>; + #size-cells =3D <2>; + ranges; + status =3D "disabled"; + + usb_host1: usb@11280000 { + compatible =3D "mediatek,mt8186-xhci", "mediatek,mtk-xhci"; + reg =3D <0 0x11280000 0 0x1000>; + reg-names =3D "mac"; + clocks =3D <&infracfg_ao CLK_INFRA_AO_SSUSB_TOP_P1_SYS>, + <&infracfg_ao CLK_INFRA_AO_SSUSB_TOP_P1_REF>, + <&infracfg_ao CLK_INFRA_AO_SSUSB_TOP_P1_HCLK>, + <&clk26m>, + <&infracfg_ao CLK_INFRA_AO_SSUSB_TOP_P1_XHCI>; + clock-names =3D "sys_ck", "ref_ck", "mcu_ck", "dma_ck","xhci_ck"; + interrupts =3D ; + mediatek,syscon-wakeup =3D <&pericfg 0x424 2>; + wakeup-source; + status =3D "disabled"; + }; + }; + u3phy0: t-phy@11c80000 { compatible =3D "mediatek,mt8186-tphy", "mediatek,generic-tphy-v2"; --=20 2.18.0 From nobody Sat Sep 21 02:38:30 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8C875C678D4 for ; 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Fri, 03 Mar 2023 11:17:32 +0800 Received: from mtkmbs11n1.mediatek.inc (172.21.101.186) by mtkmbs13n2.mediatek.inc (172.21.101.108) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.25; Fri, 3 Mar 2023 11:17:30 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkmbs11n1.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.1118.25 via Frontend Transport; Fri, 3 Mar 2023 11:17:30 +0800 From: Allen-KH Cheng To: Matthias Brugger , Rob Herring , Krzysztof Kozlowski , Stephen Boyd , AngeloGioacchino Del Regno CC: , , , , , , Allen-KH Cheng Subject: [PATCH v3 2/7] dt-bindings: spmi: spmi-mtk-pmif: Document mediatek,mt8195-spmi as fallback of mediatek,mt8186-spmi Date: Fri, 3 Mar 2023 11:17:23 +0800 Message-ID: <20230303031728.24251-3-allen-kh.cheng@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20230303031728.24251-1-allen-kh.cheng@mediatek.com> References: <20230303031728.24251-1-allen-kh.cheng@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The mt8186-spmi is used as compatible with mt8195-spmi on the MT8186, document this situation. Signed-off-by: Allen-KH Cheng Reviewed-by: Rob Herring Reviewed-by: AngeloGioacchino Del Regno Reviewed-by: Matthias Brugger --- .../devicetree/bindings/spmi/mtk,spmi-mtk-pmif.yaml | 11 ++++++++--- 1 file changed, 8 insertions(+), 3 deletions(-) diff --git a/Documentation/devicetree/bindings/spmi/mtk,spmi-mtk-pmif.yaml = b/Documentation/devicetree/bindings/spmi/mtk,spmi-mtk-pmif.yaml index abcbbe13723f..e4f465abcfe9 100644 --- a/Documentation/devicetree/bindings/spmi/mtk,spmi-mtk-pmif.yaml +++ b/Documentation/devicetree/bindings/spmi/mtk,spmi-mtk-pmif.yaml @@ -18,9 +18,14 @@ allOf: =20 properties: compatible: - enum: - - mediatek,mt6873-spmi - - mediatek,mt8195-spmi + oneOf: + - enum: + - mediatek,mt6873-spmi + - mediatek,mt8195-spmi + - items: + - enum: + - mediatek,mt8186-spmi + - const: mediatek,mt8195-spmi =20 reg: maxItems: 2 --=20 2.18.0 From nobody Sat Sep 21 02:38:30 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5BEB2C6FA8E for ; Fri, 3 Mar 2023 03:17:48 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229748AbjCCDRq (ORCPT ); Thu, 2 Mar 2023 22:17:46 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:36746 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229484AbjCCDRk (ORCPT ); Thu, 2 Mar 2023 22:17:40 -0500 Received: from mailgw01.mediatek.com (unknown [60.244.123.138]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 667402BEF6; Thu, 2 Mar 2023 19:17:37 -0800 (PST) X-UUID: eff136fab97111eda06fc9ecc4dadd91-20230303 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=qvEI8FN3wBwu6ZlVwOeje29yYcekRLOHCPmieBrV1IY=; b=U5KMhvsEgDTojVdUFqcCGZdg9Q59hOTo6RU1y0CEnNJO/zx+o4wuHPpUbcn2Azo6WBYvupcoSD8ulwjLsGiEvk5rHwk4tzcJEr4XjQbVcyd+2JpTt7xReB/sr8uuxQVNouBP9sm2ftu2KG5WhIM8X+er6nuXjZU8rStHQ7IRttU=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.20,REQID:98863a7d-22d3-41ce-ae6b-8b72676557cb,IP:0,U RL:0,TC:0,Content:-5,EDM:0,RT:0,SF:95,FILE:0,BULK:0,RULE:Release_Ham,ACTIO N:release,TS:90 X-CID-INFO: VERSION:1.1.20,REQID:98863a7d-22d3-41ce-ae6b-8b72676557cb,IP:0,URL :0,TC:0,Content:-5,EDM:0,RT:0,SF:95,FILE:0,BULK:0,RULE:Spam_GS981B3D,ACTIO N:quarantine,TS:90 X-CID-META: VersionHash:25b5999,CLOUDID:b9b13027-564d-42d9-9875-7c868ee415ec,B ulkID:230303111733W4RWXYOR,BulkQuantity:0,Recheck:0,SF:38|29|28|17|19|48,T C:nil,Content:0,EDM:-3,IP:nil,URL:0,File:nil,Bulk:nil,QS:nil,BEC:nil,COL:0 ,OSI:0,OSA:0,AV:0 X-CID-BVR: 0,NGT X-UUID: eff136fab97111eda06fc9ecc4dadd91-20230303 Received: from mtkmbs13n1.mediatek.inc [(172.21.101.193)] by mailgw01.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 36588692; Fri, 03 Mar 2023 11:17:32 +0800 Received: from mtkmbs11n1.mediatek.inc (172.21.101.185) by mtkmbs11n1.mediatek.inc (172.21.101.185) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.25; Fri, 3 Mar 2023 11:17:31 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkmbs11n1.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.1118.25 via Frontend Transport; Fri, 3 Mar 2023 11:17:31 +0800 From: Allen-KH Cheng To: Matthias Brugger , Rob Herring , Krzysztof Kozlowski , Stephen Boyd , AngeloGioacchino Del Regno CC: , , , , , , Allen-KH Cheng Subject: [PATCH v3 3/7] arm64: dts: mediatek: mt8186: Add SPMI node Date: Fri, 3 Mar 2023 11:17:24 +0800 Message-ID: <20230303031728.24251-4-allen-kh.cheng@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20230303031728.24251-1-allen-kh.cheng@mediatek.com> References: <20230303031728.24251-1-allen-kh.cheng@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add SPMI node for MT8186 SoC. Signed-off-by: Allen-KH Cheng Reviewed-by: AngeloGioacchino Del Regno --- arch/arm64/boot/dts/mediatek/mt8186.dtsi | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8186.dtsi b/arch/arm64/boot/dts= /mediatek/mt8186.dtsi index 178421fd8380..0e42bdbd2cb6 100644 --- a/arch/arm64/boot/dts/mediatek/mt8186.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8186.dtsi @@ -602,6 +602,21 @@ clock-names =3D "spi", "wrap"; }; =20 + spmi: spmi@10015000 { + compatible =3D "mediatek,mt8186-spmi", "mediatek,mt8195-spmi"; + reg =3D <0 0x10015000 0 0x000e00>, <0 0x1001B000 0 0x000100>; + reg-names =3D "pmif", "spmimst"; + clocks =3D <&infracfg_ao CLK_INFRA_AO_PMIC_AP>, + <&infracfg_ao CLK_INFRA_AO_PMIC_TMR>, + <&topckgen CLK_TOP_SPMI_MST>; + clock-names =3D "pmif_sys_ck", "pmif_tmr_ck", "spmimst_clk_mux"; + assigned-clocks =3D <&topckgen CLK_TOP_SPMI_MST>; + assigned-clock-parents =3D <&topckgen CLK_TOP_ULPOSC1_D10>; + interrupts =3D , + ; + status =3D "disabled"; + }; + systimer: timer@10017000 { compatible =3D "mediatek,mt8186-timer", "mediatek,mt6765-timer"; --=20 2.18.0 From nobody Sat Sep 21 02:38:30 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4C46FC678D4 for ; Fri, 3 Mar 2023 03:17:50 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229885AbjCCDRs (ORCPT ); Thu, 2 Mar 2023 22:17:48 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:36762 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229644AbjCCDRk (ORCPT ); Thu, 2 Mar 2023 22:17:40 -0500 Received: from mailgw02.mediatek.com (unknown [210.61.82.184]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id EF36E57D0B; Thu, 2 Mar 2023 19:17:38 -0800 (PST) X-UUID: f0a2e3b4b97111ed945fc101203acc17-20230303 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=oaloW61vYsYhb9woC0pGOBCyeLOtwht+oMl/dWqapWk=; b=glsV0qyltodDN1H7Hc4nHPJnafy87ifaNCK70NIgIIgvDQ6eLqi3VCo/PHGDgUvwNuyw3+pj1zr/K2L62BOf/hiaMM55SVaWNmbXSCDtmS3c199bge5/LITgMEjqR2n3IBi5Feh4am7UHTBC1eYixIr3e7xVeRylN0LHkRqlcjQ=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.20,REQID:7e66b9e1-ce1b-48b5-8685-9df117c0e00a,IP:0,U RL:0,TC:0,Content:-5,EDM:0,RT:0,SF:95,FILE:0,BULK:0,RULE:Release_Ham,ACTIO N:release,TS:90 X-CID-INFO: VERSION:1.1.20,REQID:7e66b9e1-ce1b-48b5-8685-9df117c0e00a,IP:0,URL :0,TC:0,Content:-5,EDM:0,RT:0,SF:95,FILE:0,BULK:0,RULE:Spam_GS981B3D,ACTIO N:quarantine,TS:90 X-CID-META: VersionHash:25b5999,CLOUDID:9af59ef4-ddba-41c3-91d9-10eeade8eac7,B ulkID:230303111735DBDLI1P1,BulkQuantity:0,Recheck:0,SF:38|29|28|17|19|48,T C:nil,Content:0,EDM:-3,IP:nil,URL:0,File:nil,Bulk:nil,QS:nil,BEC:nil,COL:0 ,OSI:0,OSA:0,AV:0 X-CID-BVR: 0,NGT X-UUID: f0a2e3b4b97111ed945fc101203acc17-20230303 Received: from mtkmbs13n1.mediatek.inc [(172.21.101.193)] by mailgw02.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 1106794499; Fri, 03 Mar 2023 11:17:33 +0800 Received: from mtkmbs11n1.mediatek.inc (172.21.101.185) by mtkmbs11n1.mediatek.inc (172.21.101.185) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.25; Fri, 3 Mar 2023 11:17:32 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkmbs11n1.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.1118.25 via Frontend Transport; Fri, 3 Mar 2023 11:17:32 +0800 From: Allen-KH Cheng To: Matthias Brugger , Rob Herring , Krzysztof Kozlowski , Stephen Boyd , AngeloGioacchino Del Regno CC: , , , , , , Allen-KH Cheng Subject: [PATCH v3 4/7] arm64: dts: mediatek: mt8186: Add ADSP node Date: Fri, 3 Mar 2023 11:17:25 +0800 Message-ID: <20230303031728.24251-5-allen-kh.cheng@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20230303031728.24251-1-allen-kh.cheng@mediatek.com> References: <20230303031728.24251-1-allen-kh.cheng@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add ADSP node for MT8186 SoC. Signed-off-by: Allen-KH Cheng --- arch/arm64/boot/dts/mediatek/mt8186.dtsi | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8186.dtsi b/arch/arm64/boot/dts= /mediatek/mt8186.dtsi index 0e42bdbd2cb6..337bcf3c1571 100644 --- a/arch/arm64/boot/dts/mediatek/mt8186.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8186.dtsi @@ -633,6 +633,22 @@ interrupts =3D ; }; =20 + adsp: adsp@10680000 { + compatible =3D "mediatek,mt8186-dsp"; + reg =3D <0 0x10680000 0 0x2000>, <0 0x10800000 0 0x100000>, + <0 0x1068b000 0 0x100>, <0 0x1068f000 0 0x1000>; + reg-names =3D "cfg", "sram", "sec", "bus"; + clocks =3D <&topckgen CLK_TOP_AUDIODSP>, <&topckgen CLK_TOP_ADSP_BUS>; + clock-names =3D "audiodsp", "adsp_bus"; + assigned-clocks =3D <&topckgen CLK_TOP_AUDIODSP>, + <&topckgen CLK_TOP_ADSP_BUS>; + assigned-clock-parents =3D <&clk26m>, <&topckgen CLK_TOP_MAINPLL_D2_D2>; + mbox-names =3D "rx", "tx"; + mboxes =3D <&adsp_mailbox0>, <&adsp_mailbox1>; + power-domains =3D <&spm MT8186_POWER_DOMAIN_ADSP_TOP>; + status =3D "disabled"; + }; + adsp_mailbox0: mailbox@10686000 { compatible =3D "mediatek,mt8186-adsp-mbox"; #mbox-cells =3D <0>; --=20 2.18.0 From nobody Sat Sep 21 02:38:30 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id CC8D4C678D4 for ; Fri, 3 Mar 2023 03:17:54 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229894AbjCCDRx (ORCPT ); Thu, 2 Mar 2023 22:17:53 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:36762 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229714AbjCCDRl (ORCPT ); Thu, 2 Mar 2023 22:17:41 -0500 Received: from mailgw01.mediatek.com (unknown [60.244.123.138]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 23C9014E89; Thu, 2 Mar 2023 19:17:40 -0800 (PST) X-UUID: f1316a62b97111eda06fc9ecc4dadd91-20230303 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=D94WFA3SndeHGVIdcLs2oaCrSr2lE/+uRTmXDF6D3iM=; b=eJman8+H9rJwAqisCIedJ60Ud0yQCxTh+5gr2lgdy5OwnKHrlETBkYiGFgQc3rtHEHpnR280XQxj3HEFOcYUyvEYqstjO8N/GueAi2Jxma+lMWrN94MV/bG/PDmVqYlJDEhwRrmWajLKNpu0m/1KZ0Hgg68iCIgRz/Wtpv/Jo5M=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.20,REQID:03969ae1-dc0e-47c0-acc3-c13c484eb405,IP:0,U RL:0,TC:0,Content:-5,EDM:0,RT:0,SF:0,FILE:0,BULK:0,RULE:Release_Ham,ACTION :release,TS:-5 X-CID-META: VersionHash:25b5999,CLOUDID:ce4511b2-beed-4dfc-bd9c-e1b22fa6ccc4,B ulkID:nil,BulkQuantity:0,Recheck:0,SF:102,TC:nil,Content:0,EDM:-3,IP:nil,U RL:0,File:nil,Bulk:nil,QS:nil,BEC:nil,COL:0,OSI:0,OSA:0,AV:0 X-CID-BVR: 0 X-UUID: f1316a62b97111eda06fc9ecc4dadd91-20230303 Received: from mtkmbs10n2.mediatek.inc [(172.21.101.183)] by mailgw01.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 631483533; Fri, 03 Mar 2023 11:17:34 +0800 Received: from mtkmbs11n1.mediatek.inc (172.21.101.186) by mtkmbs13n1.mediatek.inc (172.21.101.193) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.25; Fri, 3 Mar 2023 11:17:33 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkmbs11n1.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.1118.25 via Frontend Transport; Fri, 3 Mar 2023 11:17:33 +0800 From: Allen-KH Cheng To: Matthias Brugger , Rob Herring , Krzysztof Kozlowski , Stephen Boyd , AngeloGioacchino Del Regno CC: , , , , , , Allen-KH Cheng Subject: [PATCH v3 5/7] arm64: dts: mediatek: mt8186: Add audio controller node Date: Fri, 3 Mar 2023 11:17:26 +0800 Message-ID: <20230303031728.24251-6-allen-kh.cheng@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20230303031728.24251-1-allen-kh.cheng@mediatek.com> References: <20230303031728.24251-1-allen-kh.cheng@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add audio controller node for MT8186 SoC. Signed-off-by: Allen-KH Cheng Reviewed-by: AngeloGioacchino Del Regno --- arch/arm64/boot/dts/mediatek/mt8186.dtsi | 62 ++++++++++++++++++++++++ 1 file changed, 62 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8186.dtsi b/arch/arm64/boot/dts= /mediatek/mt8186.dtsi index 337bcf3c1571..f198fd8abc1d 100644 --- a/arch/arm64/boot/dts/mediatek/mt8186.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8186.dtsi @@ -1046,6 +1046,68 @@ }; }; =20 + afe: audio-controller@11210000 { + compatible =3D "mediatek,mt8186-sound"; + reg =3D <0 0x11210000 0 0x2000>; + clocks =3D <&infracfg_ao CLK_INFRA_AO_AUDIO>, + <&infracfg_ao CLK_INFRA_AO_AUDIO_26M_BCLK>, + <&topckgen CLK_TOP_AUDIO>, + <&topckgen CLK_TOP_AUD_INTBUS>, + <&topckgen CLK_TOP_MAINPLL_D2_D4>, + <&topckgen CLK_TOP_AUD_1>, + <&apmixedsys CLK_APMIXED_APLL1>, + <&topckgen CLK_TOP_AUD_2>, + <&apmixedsys CLK_APMIXED_APLL2>, + <&topckgen CLK_TOP_AUD_ENGEN1>, + <&topckgen CLK_TOP_APLL1_D8>, + <&topckgen CLK_TOP_AUD_ENGEN2>, + <&topckgen CLK_TOP_APLL2_D8>, + <&topckgen CLK_TOP_APLL_I2S0_MCK_SEL>, + <&topckgen CLK_TOP_APLL_I2S1_MCK_SEL>, + <&topckgen CLK_TOP_APLL_I2S2_MCK_SEL>, + <&topckgen CLK_TOP_APLL_I2S4_MCK_SEL>, + <&topckgen CLK_TOP_APLL_TDMOUT_MCK_SEL>, + <&topckgen CLK_TOP_APLL12_CK_DIV0>, + <&topckgen CLK_TOP_APLL12_CK_DIV1>, + <&topckgen CLK_TOP_APLL12_CK_DIV2>, + <&topckgen CLK_TOP_APLL12_CK_DIV4>, + <&topckgen CLK_TOP_APLL12_CK_DIV_TDMOUT_M>, + <&topckgen CLK_TOP_AUDIO_H>, + <&clk26m>; + clock-names =3D "aud_infra_clk", + "mtkaif_26m_clk", + "top_mux_audio", + "top_mux_audio_int", + "top_mainpll_d2_d4", + "top_mux_aud_1", + "top_apll1_ck", + "top_mux_aud_2", + "top_apll2_ck", + "top_mux_aud_eng1", + "top_apll1_d8", + "top_mux_aud_eng2", + "top_apll2_d8", + "top_i2s0_m_sel", + "top_i2s1_m_sel", + "top_i2s2_m_sel", + "top_i2s4_m_sel", + "top_tdm_m_sel", + "top_apll12_div0", + "top_apll12_div1", + "top_apll12_div2", + "top_apll12_div4", + "top_apll12_div_tdm", + "top_mux_audio_h", + "top_clk26m_clk"; + interrupts =3D ; + mediatek,apmixedsys =3D <&apmixedsys>; + mediatek,infracfg =3D <&infracfg_ao>; + mediatek,topckgen =3D <&topckgen>; + resets =3D <&watchdog MT8186_TOPRGU_AUDIO_SW_RST>; + reset-names =3D "audiosys"; + status =3D "disabled"; + }; + mmc0: mmc@11230000 { compatible =3D "mediatek,mt8186-mmc", "mediatek,mt8183-mmc"; --=20 2.18.0 From nobody Sat Sep 21 02:38:30 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 39AABC678D4 for ; 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Fri, 03 Mar 2023 11:17:35 +0800 Received: from mtkmbs11n1.mediatek.inc (172.21.101.185) by mtkmbs11n1.mediatek.inc (172.21.101.185) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.25; Fri, 3 Mar 2023 11:17:34 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkmbs11n1.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.1118.25 via Frontend Transport; Fri, 3 Mar 2023 11:17:34 +0800 From: Allen-KH Cheng To: Matthias Brugger , Rob Herring , Krzysztof Kozlowski , Stephen Boyd , AngeloGioacchino Del Regno CC: , , , , , , Allen-KH Cheng Subject: [PATCH v3 6/7] arm64: dts: mediatek: mt8186: Add GCE node Date: Fri, 3 Mar 2023 11:17:27 +0800 Message-ID: <20230303031728.24251-7-allen-kh.cheng@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20230303031728.24251-1-allen-kh.cheng@mediatek.com> References: <20230303031728.24251-1-allen-kh.cheng@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add the Global Command Engine (GCE) node for MT8186 SoC Signed-off-by: Allen-KH Cheng Reviewed-by: AngeloGioacchino Del Regno --- arch/arm64/boot/dts/mediatek/mt8186.dtsi | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8186.dtsi b/arch/arm64/boot/dts= /mediatek/mt8186.dtsi index f198fd8abc1d..b9d5af26771e 100644 --- a/arch/arm64/boot/dts/mediatek/mt8186.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8186.dtsi @@ -5,6 +5,7 @@ */ /dts-v1/; #include +#include #include #include #include @@ -625,6 +626,15 @@ clocks =3D <&clk13m>; }; =20 + gce: mailbox@1022c000 { + compatible =3D "mediatek,mt8186-gce"; + reg =3D <0 0X1022c000 0 0x4000>; + clocks =3D <&infracfg_ao CLK_INFRA_AO_GCE>; + clock-names =3D "gce"; + interrupts =3D ; + #mbox-cells =3D <2>; + }; + scp: scp@10500000 { compatible =3D "mediatek,mt8186-scp"; reg =3D <0 0x10500000 0 0x40000>, --=20 2.18.0 From nobody Sat Sep 21 02:38:30 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id AA4A0C6FA8E for ; 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Fri, 03 Mar 2023 11:17:36 +0800 Received: from mtkmbs11n1.mediatek.inc (172.21.101.186) by mtkmbs13n2.mediatek.inc (172.21.101.108) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.25; Fri, 3 Mar 2023 11:17:34 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkmbs11n1.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.1118.25 via Frontend Transport; Fri, 3 Mar 2023 11:17:34 +0800 From: Allen-KH Cheng To: Matthias Brugger , Rob Herring , Krzysztof Kozlowski , Stephen Boyd , AngeloGioacchino Del Regno CC: , , , , , , Allen-KH Cheng Subject: [PATCH v3 7/7] arm64: dts: mediatek: mt8186: Add display nodes Date: Fri, 3 Mar 2023 11:17:28 +0800 Message-ID: <20230303031728.24251-8-allen-kh.cheng@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20230303031728.24251-1-allen-kh.cheng@mediatek.com> References: <20230303031728.24251-1-allen-kh.cheng@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add display nodes and the GCE (Global Command Engine) properties to the display nodes in order to enable the usage of the CMDQ (Command Queue), which is required for operating the display. Signed-off-by: Allen-KH Cheng --- arch/arm64/boot/dts/mediatek/mt8186.dtsi | 125 +++++++++++++++++++++++ 1 file changed, 125 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8186.dtsi b/arch/arm64/boot/dts= /mediatek/mt8186.dtsi index b9d5af26771e..909f1a6ae108 100644 --- a/arch/arm64/boot/dts/mediatek/mt8186.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8186.dtsi @@ -20,6 +20,13 @@ #address-cells =3D <2>; #size-cells =3D <2>; =20 + aliases { + ovl =3D &ovl; + ovl_2l=3D &ovl_2l; + rdma0 =3D &rdma0; + rdma1 =3D &rdma1; + }; + cpus { #address-cells =3D <1>; #size-cells =3D <0>; @@ -1251,6 +1258,20 @@ reg =3D <0 0x14000000 0 0x1000>; #clock-cells =3D <1>; #reset-cells =3D <1>; + mboxes =3D <&gce 0 CMDQ_THR_PRIO_HIGHEST>, + <&gce 1 CMDQ_THR_PRIO_HIGHEST>; + mediatek,gce-client-reg =3D <&gce SUBSYS_1400XXXX 0 0x1000>; + }; + + mutex: mutex@14001000 { + compatible =3D "mediatek,mt8186-disp-mutex"; + reg =3D <0 0x14001000 0 0x1000>; + clocks =3D <&mmsys CLK_MM_DISP_MUTEX0>; + interrupts =3D ; + mediatek,gce-client-reg =3D <&gce SUBSYS_1401XXXX 0x1000 0x1000>; + mediatek,gce-events =3D , + ; + power-domains =3D <&spm MT8186_POWER_DOMAIN_DIS>; }; =20 smi_common: smi@14002000 { @@ -1284,6 +1305,49 @@ power-domains =3D <&spm MT8186_POWER_DOMAIN_DIS>; }; =20 + ovl: ovl@14005000 { + compatible =3D "mediatek,mt8186-disp-ovl", + "mediatek,mt8192-disp-ovl"; + reg =3D <0 0x14005000 0 0x1000>; + clocks =3D <&mmsys CLK_MM_DISP_OVL0>; + interrupts =3D ; + iommus =3D <&iommu_mm IOMMU_PORT_L0_OVL_RDMA0>; + mediatek,gce-client-reg =3D <&gce SUBSYS_1400XXXX 0x5000 0x1000>; + power-domains =3D <&spm MT8186_POWER_DOMAIN_DIS>; + }; + + ovl_2l: ovl@14006000 { + compatible =3D "mediatek,mt8186-disp-ovl-2l", + "mediatek,mt8192-disp-ovl-2l"; + reg =3D <0 0x14006000 0 0x1000>; + clocks =3D <&mmsys CLK_MM_DISP_OVL0_2L>; + interrupts =3D ; + iommus =3D <&iommu_mm IOMMU_PORT_L1_OVL_2L_RDMA0>; + mediatek,gce-client-reg =3D <&gce SUBSYS_1400XXXX 0x6000 0x1000>; + power-domains =3D <&spm MT8186_POWER_DOMAIN_DIS>; + }; + + rdma0: rdma@14007000 { + compatible =3D "mediatek,mt8186-disp-rdma", + "mediatek,mt8183-disp-rdma"; + reg =3D <0 0x14007000 0 0x1000>; + clocks =3D <&mmsys CLK_MM_DISP_RDMA0>; + interrupts =3D ; + iommus =3D <&iommu_mm IOMMU_PORT_L1_DISP_RDMA0>; + mediatek,gce-client-reg =3D <&gce SUBSYS_1400XXXX 0x7000 0x1000>; + power-domains =3D <&spm MT8186_POWER_DOMAIN_DIS>; + }; + + color: color@14009000 { + compatible =3D "mediatek,mt8186-disp-color", + "mediatek,mt8173-disp-color"; + reg =3D <0 0x14009000 0 0x1000>; + clocks =3D <&mmsys CLK_MM_DISP_COLOR0>; + interrupts =3D ; + mediatek,gce-client-reg =3D <&gce SUBSYS_1400XXXX 0x8000 0x1000>; + power-domains =3D <&spm MT8186_POWER_DOMAIN_DIS>; + }; + dpi: dpi@1400a000 { compatible =3D "mediatek,mt8186-dpi"; reg =3D <0 0x1400a000 0 0x1000>; @@ -1301,6 +1365,56 @@ }; }; =20 + ccorr: ccorr@1400b000 { + compatible =3D "mediatek,mt8186-disp-ccorr", + "mediatek,mt8192-disp-ccorr"; + reg =3D <0 0x1400b000 0 0x1000>; + clocks =3D <&mmsys CLK_MM_DISP_CCORR0>; + interrupts =3D ; + mediatek,gce-client-reg =3D <&gce SUBSYS_1400XXXX 0xb000 0x1000>; + power-domains =3D <&spm MT8186_POWER_DOMAIN_DIS>; + }; + + aal: aal@1400c000 { + compatible =3D "mediatek,mt8186-disp-aal", + "mediatek,mt8183-disp-aal"; + reg =3D <0 0x1400c000 0 0x1000>; + clocks =3D <&mmsys CLK_MM_DISP_AAL0>; + interrupts =3D ; + mediatek,gce-client-reg =3D <&gce SUBSYS_1400XXXX 0xc000 0x1000>; + power-domains =3D <&spm MT8186_POWER_DOMAIN_DIS>; + }; + + gamma: gamma@1400d000 { + compatible =3D "mediatek,mt8186-disp-gamma", + "mediatek,mt8183-disp-gamma"; + reg =3D <0 0x1400d000 0 0x1000>; + clocks =3D <&mmsys CLK_MM_DISP_GAMMA0>; + interrupts =3D ; + mediatek,gce-client-reg =3D <&gce SUBSYS_1400XXXX 0xd000 0x1000>; + power-domains =3D <&spm MT8186_POWER_DOMAIN_DIS>; + }; + + postmask: postmask@1400e000 { + compatible =3D "mediatek,mt8186-disp-postmask", + "mediatek,mt8192-disp-postmask"; + reg =3D <0 0x1400e000 0 0x1000>; + clocks =3D <&mmsys CLK_MM_DISP_POSTMASK0>; + interrupts =3D ; + mediatek,gce-client-reg =3D <&gce SUBSYS_1400XXXX 0xe000 0x1000>; + power-domains =3D <&spm MT8186_POWER_DOMAIN_DIS>; + }; + + dither: dither@1400f000 { + compatible =3D "mediatek,mt8186-disp-dither", + "mediatek,mt8183-disp-dither"; + reg =3D <0 0x1400f000 0 0x1000>; + clocks =3D <&mmsys CLK_MM_DISP_DITHER0>; + interrupts =3D ; + mediatek,gce-client-reg =3D <&gce SUBSYS_1400XXXX 0xf000 0x1000>; + power-domains =3D <&spm MT8186_POWER_DOMAIN_DIS>; + }; + dsi0: dsi@14013000 { compatible =3D "mediatek,mt8186-dsi"; reg =3D <0 0x14013000 0 0x1000>; @@ -1334,6 +1448,17 @@ #iommu-cells =3D <1>; }; =20 + rdma1: rdma@1401f000 { + compatible =3D "mediatek,mt8186-disp-rdma", + "mediatek,mt8183-disp-rdma"; + reg =3D <0 0x1401f000 0 0x1000>; + clocks =3D <&mmsys CLK_MM_DISP_RDMA1>; + interrupts =3D ; + iommus =3D <&iommu_mm IOMMU_PORT_L1_DISP_RDMA1>; + mediatek,gce-client-reg =3D <&gce SUBSYS_1401XXXX 0xf000 0x1000>; + power-domains =3D <&spm MT8186_POWER_DOMAIN_DIS>; + }; + wpesys: clock-controller@14020000 { compatible =3D "mediatek,mt8186-wpesys"; reg =3D <0 0x14020000 0 0x1000>; --=20 2.18.0