From nobody Thu Nov 14 17:48:33 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id A673FC678D4 for ; Fri, 3 Mar 2023 01:39:18 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229596AbjCCBjR (ORCPT ); Thu, 2 Mar 2023 20:39:17 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:47124 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229984AbjCCBjB (ORCPT ); Thu, 2 Mar 2023 20:39:01 -0500 Received: from mailgw02.mediatek.com (unknown [210.61.82.184]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id DD7D1559D8; Thu, 2 Mar 2023 17:38:57 -0800 (PST) X-UUID: 25291206b96411ed945fc101203acc17-20230303 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=3HkB48symoODIC8ECiB6Yao0itYaQt3zHYaMGMx88ZQ=; b=mrxGYG7Y2lXppKl09xo80tPDHY+IMvvhUQPe2Vfd1Zqo71qa4RimY6rmdzzF8nZsVB+9O5yhRVNZLXHYluuHo/orH4oytKcRLYv2WfG2IYP6FYwiwuH6DDaFbHYGcvR9rIeDIxkWa8g8Y6PyH6LdJgZH3lRuXwKXpNvt+Z6NX8g=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.20,REQID:c1e6ca7e-5709-4ba1-8dc4-5f8bdbbd6202,IP:0,U RL:0,TC:0,Content:-25,EDM:0,RT:0,SF:0,FILE:0,BULK:0,RULE:Release_Ham,ACTIO N:release,TS:-25 X-CID-META: VersionHash:25b5999,CLOUDID:20389bf4-ddba-41c3-91d9-10eeade8eac7,B ulkID:nil,BulkQuantity:0,Recheck:0,SF:102,TC:nil,Content:0,EDM:-3,IP:nil,U RL:0,File:nil,Bulk:nil,QS:nil,BEC:nil,COL:0,OSI:0,OSA:0,AV:0 X-CID-BVR: 0 X-UUID: 25291206b96411ed945fc101203acc17-20230303 Received: from mtkmbs10n2.mediatek.inc [(172.21.101.183)] by mailgw02.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 1501646870; Fri, 03 Mar 2023 09:38:48 +0800 Received: from mtkmbs13n1.mediatek.inc (172.21.101.193) by mtkmbs10n2.mediatek.inc (172.21.101.183) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.25; Fri, 3 Mar 2023 09:38:48 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkmbs13n1.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.1118.25 via Frontend Transport; Fri, 3 Mar 2023 09:38:48 +0800 From: Allen-KH Cheng To: Mauro Carvalho Chehab , Matthias Brugger , Rob Herring , "Krzysztof Kozlowski" CC: , , , , , , , "Allen-KH Cheng" Subject: [RESEND 6/6] arm64: dts: mt8195: Add video decoder node Date: Fri, 3 Mar 2023 09:38:42 +0800 Message-ID: <20230303013842.23259-7-allen-kh.cheng@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20230303013842.23259-1-allen-kh.cheng@mediatek.com> References: <20230303013842.23259-1-allen-kh.cheng@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Yunfei Dong Add video decoder node to mt8195 device tree. Signed-off-by: Yunfei Dong Signed-off-by: Allen-KH Cheng Reviewed-by: AngeloGioacchino Del Regno Reviewed-by: Chen-Yu Tsai Tested-by: Chen-Yu Tsai --- arch/arm64/boot/dts/mediatek/mt8195.dtsi | 70 ++++++++++++++++++++++++ 1 file changed, 70 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi b/arch/arm64/boot/dts= /mediatek/mt8195.dtsi index 8fc527570791..d0d53e0bfbfc 100644 --- a/arch/arm64/boot/dts/mediatek/mt8195.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi @@ -2211,6 +2211,76 @@ power-domains =3D <&spm MT8195_POWER_DOMAIN_CAM>; }; =20 + video-codec@18000000 { + compatible =3D "mediatek,mt8195-vcodec-dec"; + mediatek,scp =3D <&scp>; + iommus =3D <&iommu_vdo M4U_PORT_L21_VDEC_MC_EXT>; + #address-cells =3D <2>; + #size-cells =3D <2>; + reg =3D <0 0x18000000 0 0x1000>, + <0 0x18004000 0 0x1000>; + ranges =3D <0 0 0 0x18000000 0 0x26000>; + + video-codec@2000 { + compatible =3D "mediatek,mtk-vcodec-lat-soc"; + reg =3D <0 0x2000 0 0x800>; + iommus =3D <&iommu_vpp M4U_PORT_L23_VDEC_UFO_ENC_EXT>, + <&iommu_vpp M4U_PORT_L23_VDEC_RDMA_EXT>; + clocks =3D <&topckgen CLK_TOP_VDEC>, + <&vdecsys_soc CLK_VDEC_SOC_VDEC>, + <&vdecsys_soc CLK_VDEC_SOC_LAT>, + <&topckgen CLK_TOP_UNIVPLL_D4>; + clock-names =3D "sel", "vdec", "lat", "top"; + assigned-clocks =3D <&topckgen CLK_TOP_VDEC>; + assigned-clock-parents =3D <&topckgen CLK_TOP_UNIVPLL_D4>; + power-domains =3D <&spm MT8195_POWER_DOMAIN_VDEC0>; + }; + + video-codec@10000 { + compatible =3D "mediatek,mtk-vcodec-lat"; + reg =3D <0 0x10000 0 0x800>; + interrupts =3D ; + iommus =3D <&iommu_vdo M4U_PORT_L24_VDEC_LAT0_VLD_EXT>, + <&iommu_vdo M4U_PORT_L24_VDEC_LAT0_VLD2_EXT>, + <&iommu_vdo M4U_PORT_L24_VDEC_LAT0_AVC_MC_EXT>, + <&iommu_vdo M4U_PORT_L24_VDEC_LAT0_PRED_RD_EXT>, + <&iommu_vdo M4U_PORT_L24_VDEC_LAT0_TILE_EXT>, + <&iommu_vdo M4U_PORT_L24_VDEC_LAT0_WDMA_EXT>; + clocks =3D <&topckgen CLK_TOP_VDEC>, + <&vdecsys_soc CLK_VDEC_SOC_VDEC>, + <&vdecsys_soc CLK_VDEC_SOC_LAT>, + <&topckgen CLK_TOP_UNIVPLL_D4>; + clock-names =3D "sel", "vdec", "lat", "top"; + assigned-clocks =3D <&topckgen CLK_TOP_VDEC>; + assigned-clock-parents =3D <&topckgen CLK_TOP_UNIVPLL_D4>; + power-domains =3D <&spm MT8195_POWER_DOMAIN_VDEC0>; + }; + + video-codec@25000 { + compatible =3D "mediatek,mtk-vcodec-core"; + reg =3D <0 0x25000 0 0x1000>; /* VDEC_CORE_MISC */ + interrupts =3D ; + iommus =3D <&iommu_vdo M4U_PORT_L21_VDEC_MC_EXT>, + <&iommu_vdo M4U_PORT_L21_VDEC_UFO_EXT>, + <&iommu_vdo M4U_PORT_L21_VDEC_PP_EXT>, + <&iommu_vdo M4U_PORT_L21_VDEC_PRED_RD_EXT>, + <&iommu_vdo M4U_PORT_L21_VDEC_PRED_WR_EXT>, + <&iommu_vdo M4U_PORT_L21_VDEC_PPWRAP_EXT>, + <&iommu_vdo M4U_PORT_L21_VDEC_TILE_EXT>, + <&iommu_vdo M4U_PORT_L21_VDEC_VLD_EXT>, + <&iommu_vdo M4U_PORT_L21_VDEC_VLD2_EXT>, + <&iommu_vdo M4U_PORT_L21_VDEC_AVC_MV_EXT>; + clocks =3D <&topckgen CLK_TOP_VDEC>, + <&vdecsys CLK_VDEC_VDEC>, + <&vdecsys CLK_VDEC_LAT>, + <&topckgen CLK_TOP_UNIVPLL_D4>; + clock-names =3D "sel", "vdec", "lat", "top"; + assigned-clocks =3D <&topckgen CLK_TOP_VDEC>; + assigned-clock-parents =3D <&topckgen CLK_TOP_UNIVPLL_D4>; + power-domains =3D <&spm MT8195_POWER_DOMAIN_VDEC1>; + }; + }; + larb24: larb@1800d000 { compatible =3D "mediatek,mt8195-smi-larb"; reg =3D <0 0x1800d000 0 0x1000>; --=20 2.18.0