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[83.9.32.99]) by smtp.gmail.com with ESMTPSA id e27-20020ac2547b000000b004cafa01ebbfsm552670lfn.101.2023.03.03.13.58.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 03 Mar 2023 13:58:31 -0800 (PST) From: Konrad Dybcio Date: Fri, 03 Mar 2023 22:58:14 +0100 Subject: [PATCH 14/15] arm64: dts: qcom: sm6375: Introduce C3 power state for both ARM clusters MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20230303-topic-sm6375_features0_dts-v1-14-8c8d94fba6f0@linaro.org> References: <20230303-topic-sm6375_features0_dts-v1-0-8c8d94fba6f0@linaro.org> In-Reply-To: <20230303-topic-sm6375_features0_dts-v1-0-8c8d94fba6f0@linaro.org> To: Amit Kucheria , Thara Gopinath , Andy Gross , Bjorn Andersson , "Rafael J. Wysocki" , Daniel Lezcano , Zhang Rui , Rob Herring , Krzysztof Kozlowski , Georgi Djakov , Sibi Sankar Cc: linux-arm-msm@vger.kernel.org, linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Konrad Dybcio X-Mailer: b4 0.12.1 X-Developer-Signature: v=1; a=ed25519-sha256; t=1677880689; l=3486; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=BoPm/b3+zv1C9oti+VeDmiDfZTtPEFlzg5/g/B0wkuM=; b=r1bhNl8KZSXM0Ex+wdQb5ZfkteY5xsSugf2fNelDZMgFcAYPBGdoIDJjokE8XJrDiDxGTrPSn3KA Wcb7o/30AXeoYYWSE+v6cDp0kLjcR1KnXuNsyGhet+Wv4Rlrcf9s X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Introduce the C3 power state, which - to the best of my understanding - gates the CPU clock, but does not shut off the power rail. Signed-off-by: Konrad Dybcio --- arch/arm64/boot/dts/qcom/sm6375.dtsi | 36 ++++++++++++++++++++++++++++----= ---- 1 file changed, 28 insertions(+), 8 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm6375.dtsi b/arch/arm64/boot/dts/qco= m/sm6375.dtsi index 05d8d6a012b6..5a6661dbde08 100644 --- a/arch/arm64/boot/dts/qcom/sm6375.dtsi +++ b/arch/arm64/boot/dts/qcom/sm6375.dtsi @@ -207,6 +207,16 @@ core7 { idle-states { entry-method =3D "psci"; =20 + LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 { + compatible =3D "arm,idle-state"; + idle-state-name =3D "silver-power-collapse"; + arm,psci-suspend-param =3D <0x40000003>; + entry-latency-us =3D <549>; + exit-latency-us =3D <901>; + min-residency-us =3D <1774>; + local-timer-stop; + }; + LITTLE_CPU_SLEEP_1: cpu-sleep-0-1 { compatible =3D "arm,idle-state"; idle-state-name =3D "silver-rail-power-collapse"; @@ -217,6 +227,16 @@ LITTLE_CPU_SLEEP_1: cpu-sleep-0-1 { local-timer-stop; }; =20 + BIG_CPU_SLEEP_0: cpu-sleep-1-0 { + compatible =3D "arm,idle-state"; + idle-state-name =3D "gold-power-collapse"; + arm,psci-suspend-param =3D <0x40000003>; + entry-latency-us =3D <523>; + exit-latency-us =3D <1244>; + min-residency-us =3D <2207>; + local-timer-stop; + }; + BIG_CPU_SLEEP_1: cpu-sleep-1-1 { compatible =3D "arm,idle-state"; idle-state-name =3D "gold-rail-power-collapse"; @@ -268,49 +288,49 @@ psci { CPU_PD0: power-domain-cpu0 { #power-domain-cells =3D <0>; power-domains =3D <&CLUSTER_PD>; - domain-idle-states =3D <&LITTLE_CPU_SLEEP_1>; + domain-idle-states =3D <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>; }; =20 CPU_PD1: power-domain-cpu1 { #power-domain-cells =3D <0>; power-domains =3D <&CLUSTER_PD>; - domain-idle-states =3D <&LITTLE_CPU_SLEEP_1>; + domain-idle-states =3D <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>; }; =20 CPU_PD2: power-domain-cpu2 { #power-domain-cells =3D <0>; power-domains =3D <&CLUSTER_PD>; - domain-idle-states =3D <&LITTLE_CPU_SLEEP_1>; + domain-idle-states =3D <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>; }; =20 CPU_PD3: power-domain-cpu3 { #power-domain-cells =3D <0>; power-domains =3D <&CLUSTER_PD>; - domain-idle-states =3D <&LITTLE_CPU_SLEEP_1>; + domain-idle-states =3D <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>; }; =20 CPU_PD4: power-domain-cpu4 { #power-domain-cells =3D <0>; power-domains =3D <&CLUSTER_PD>; - domain-idle-states =3D <&LITTLE_CPU_SLEEP_1>; + domain-idle-states =3D <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>; }; =20 CPU_PD5: power-domain-cpu5 { #power-domain-cells =3D <0>; power-domains =3D <&CLUSTER_PD>; - domain-idle-states =3D <&LITTLE_CPU_SLEEP_1>; + domain-idle-states =3D <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>; }; =20 CPU_PD6: power-domain-cpu6 { #power-domain-cells =3D <0>; power-domains =3D <&CLUSTER_PD>; - domain-idle-states =3D <&BIG_CPU_SLEEP_1>; + domain-idle-states =3D <&BIG_CPU_SLEEP_0 &BIG_CPU_SLEEP_1>; }; =20 CPU_PD7: power-domain-cpu7 { #power-domain-cells =3D <0>; power-domains =3D <&CLUSTER_PD>; - domain-idle-states =3D <&BIG_CPU_SLEEP_1>; + domain-idle-states =3D <&BIG_CPU_SLEEP_0 &BIG_CPU_SLEEP_1>; }; =20 CLUSTER_PD: power-domain-cpu-cluster0 { --=20 2.39.2