From nobody Thu Feb 12 00:28:56 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id CBE12C77B6E for ; Wed, 12 Apr 2023 17:14:33 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230409AbjDLROc (ORCPT ); Wed, 12 Apr 2023 13:14:32 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:52758 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230116AbjDLRO0 (ORCPT ); Wed, 12 Apr 2023 13:14:26 -0400 Received: from dfw.source.kernel.org (dfw.source.kernel.org [IPv6:2604:1380:4641:c500::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 1D0E193D6 for ; Wed, 12 Apr 2023 10:14:09 -0700 (PDT) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id 87A6F637B9 for ; Wed, 12 Apr 2023 17:14:08 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 764DDC433A0; Wed, 12 Apr 2023 17:14:06 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1681319648; bh=vMkVXc4lbvz4uyuWt0yemZ/hAK+0RVCA8X8YUjPhV2s=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=O3RP2OJnwLtxQ623xfXkbUkYXDE98YGA4NQo9aWjTY1WFFxJBvUyNcuQ31n0vbz9T cmGlJFMgirOUljZPGSlGcMK2QTnCyQt8WueM974xjGlryZ/vs5Cr5sA82b6FeHLZBP 7jrxrfkvTisDhO6YZhWNxSiTP6epc2CiGwQjU+EjMH99dkOEHNqTf6sRySvVA3OhPh XrcGZodv5XrG4X1bY93a+nSivJZcvmVts3lGn0CD/hVZW4ycRjoSc3aVVRgoHYqADa a6jFc/OfJiHINqf/UUWx0B85w4w2foQaWrmWR8DhfUM+Cvvi5nvsYqqojv9BWSuoGs ZnOr4e//81VgA== From: Mark Brown Date: Wed, 12 Apr 2023 18:13:31 +0100 Subject: [PATCH v2 3/3] arm64/cpufeature: Use helper macro to specify ID register for capabilites MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20230303-arm64-cpufeature-helpers-v2-3-4c8f28a6f203@kernel.org> References: <20230303-arm64-cpufeature-helpers-v2-0-4c8f28a6f203@kernel.org> In-Reply-To: <20230303-arm64-cpufeature-helpers-v2-0-4c8f28a6f203@kernel.org> To: Catalin Marinas , Will Deacon Cc: Suzuki K Poulose , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Mark Brown X-Mailer: b4 0.13-dev-00303 X-Developer-Signature: v=1; a=openpgp-sha256; l=20045; i=broonie@kernel.org; h=from:subject:message-id; bh=vMkVXc4lbvz4uyuWt0yemZ/hAK+0RVCA8X8YUjPhV2s=; b=owEBbQGS/pANAwAKASTWi3JdVIfQAcsmYgBkNubY0jF+hoxJpjGK8TY4Vb0dc9XdCkemwURZhgVk Qvb0L0+JATMEAAEKAB0WIQSt5miqZ1cYtZ/in+ok1otyXVSH0AUCZDbm2AAKCRAk1otyXVSH0NoVB/ 4/LL7nATtjcCZHabPptk0lqMcwYevMYMTN7OhvI5TZDnCUA0vKCelgBO1vOVrv8j8GVuFvWU+KXBDy zdhhaQLAN3b8brHqFQ+B35fQzrgIJfD5ajL3pet2bj80q/5/qM+gshCl1Mtomljeeh1PqFVtjuJlA5 xj1mMpLmtnlws3rkbTSA7+YcyT8gKirXSaINTSgpHZMalEPpIqS5Zgb9rM5rsqS52kegZBLhaQlpO+ AoXrsIfsTPvJn+Dxi0SldrT4JCL0fQE69TUQCqoH/TNcFjDJgic9TYtGqs/Tm0Fh9uzxvmLN7VlFD8 58YyMHfFBodxTKNW8Akuy43vX+Mh9g X-Developer-Key: i=broonie@kernel.org; a=openpgp; fpr=3F2568AAC26998F9E813A1C5C3F436CA30F5D8EB Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org When defining which value to look for in a system register field we currently manually specify the register, field shift, width and sign and the value to look for. This opens the potential for error with for example the wrong field width or sign being specified, an enumeration value for a different similarly named field or letting something be initialised to 0. Since we now generate defines for all the ID registers we now have named constants for all of these things generated from the system register description, meaning that we can generate initialisation for all the fields used in matching from a minimal specification of register, field and match value. This is both shorter and eliminates or makes build failures several potential errors. No change in the generated binary. Signed-off-by: Mark Brown --- arch/arm64/kernel/cpufeature.c | 244 ++++++++-----------------------------= ---- 1 file changed, 44 insertions(+), 200 deletions(-) diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c index 1002ac437e8b..f7bba88bf75f 100644 --- a/arch/arm64/kernel/cpufeature.c +++ b/arch/arm64/kernel/cpufeature.c @@ -2213,22 +2213,14 @@ static const struct arm64_cpu_capabilities arm64_fe= atures[] =3D { .capability =3D ARM64_HAS_GIC_CPUIF_SYSREGS, .type =3D ARM64_CPUCAP_STRICT_BOOT_CPU_FEATURE, .matches =3D has_useable_gicv3_cpuif, - .sys_reg =3D SYS_ID_AA64PFR0_EL1, - .field_pos =3D ID_AA64PFR0_EL1_GIC_SHIFT, - .field_width =3D 4, - .sign =3D FTR_UNSIGNED, - .min_field_value =3D ID_AA64PFR0_EL1_GIC_IMP, + ARM64_CPUID_FIELDS(ID_AA64PFR0_EL1, GIC, IMP) }, { .desc =3D "Enhanced Counter Virtualization", .capability =3D ARM64_HAS_ECV, .type =3D ARM64_CPUCAP_SYSTEM_FEATURE, .matches =3D has_cpuid_feature, - .sys_reg =3D SYS_ID_AA64MMFR0_EL1, - .field_pos =3D ID_AA64MMFR0_EL1_ECV_SHIFT, - .field_width =3D 4, - .sign =3D FTR_UNSIGNED, - .min_field_value =3D ID_AA64MMFR0_EL1_ECV_IMP, + ARM64_CPUID_FIELDS(ID_AA64MMFR0_EL1, ECV, IMP) }, #ifdef CONFIG_ARM64_PAN { @@ -2236,12 +2228,8 @@ static const struct arm64_cpu_capabilities arm64_fea= tures[] =3D { .capability =3D ARM64_HAS_PAN, .type =3D ARM64_CPUCAP_SYSTEM_FEATURE, .matches =3D has_cpuid_feature, - .sys_reg =3D SYS_ID_AA64MMFR1_EL1, - .field_pos =3D ID_AA64MMFR1_EL1_PAN_SHIFT, - .field_width =3D 4, - .sign =3D FTR_UNSIGNED, - .min_field_value =3D ID_AA64MMFR1_EL1_PAN_IMP, .cpu_enable =3D cpu_enable_pan, + ARM64_CPUID_FIELDS(ID_AA64MMFR1_EL1, PAN, IMP) }, #endif /* CONFIG_ARM64_PAN */ #ifdef CONFIG_ARM64_EPAN @@ -2250,11 +2238,7 @@ static const struct arm64_cpu_capabilities arm64_fea= tures[] =3D { .capability =3D ARM64_HAS_EPAN, .type =3D ARM64_CPUCAP_SYSTEM_FEATURE, .matches =3D has_cpuid_feature, - .sys_reg =3D SYS_ID_AA64MMFR1_EL1, - .field_pos =3D ID_AA64MMFR1_EL1_PAN_SHIFT, - .field_width =3D 4, - .sign =3D FTR_UNSIGNED, - .min_field_value =3D ID_AA64MMFR1_EL1_PAN_PAN3, + ARM64_CPUID_FIELDS(ID_AA64MMFR1_EL1, PAN, PAN3) }, #endif /* CONFIG_ARM64_EPAN */ #ifdef CONFIG_ARM64_LSE_ATOMICS @@ -2263,11 +2247,7 @@ static const struct arm64_cpu_capabilities arm64_fea= tures[] =3D { .capability =3D ARM64_HAS_LSE_ATOMICS, .type =3D ARM64_CPUCAP_SYSTEM_FEATURE, .matches =3D has_cpuid_feature, - .sys_reg =3D SYS_ID_AA64ISAR0_EL1, - .field_pos =3D ID_AA64ISAR0_EL1_ATOMIC_SHIFT, - .field_width =3D 4, - .sign =3D FTR_UNSIGNED, - .min_field_value =3D ID_AA64ISAR0_EL1_ATOMIC_IMP, + ARM64_CPUID_FIELDS(ID_AA64ISAR0_EL1, ATOMIC, IMP) }, #endif /* CONFIG_ARM64_LSE_ATOMICS */ { @@ -2288,21 +2268,13 @@ static const struct arm64_cpu_capabilities arm64_fe= atures[] =3D { .capability =3D ARM64_HAS_NESTED_VIRT, .type =3D ARM64_CPUCAP_SYSTEM_FEATURE, .matches =3D has_nested_virt_support, - .sys_reg =3D SYS_ID_AA64MMFR2_EL1, - .sign =3D FTR_UNSIGNED, - .field_pos =3D ID_AA64MMFR2_EL1_NV_SHIFT, - .field_width =3D 4, - .min_field_value =3D ID_AA64MMFR2_EL1_NV_IMP, + ARM64_CPUID_FIELDS(ID_AA64MMFR2_EL1, NV, IMP) }, { .capability =3D ARM64_HAS_32BIT_EL0_DO_NOT_USE, .type =3D ARM64_CPUCAP_SYSTEM_FEATURE, .matches =3D has_32bit_el0, - .sys_reg =3D SYS_ID_AA64PFR0_EL1, - .sign =3D FTR_UNSIGNED, - .field_pos =3D ID_AA64PFR0_EL1_EL0_SHIFT, - .field_width =3D 4, - .min_field_value =3D ID_AA64PFR0_EL1_ELx_32BIT_64BIT, + ARM64_CPUID_FIELDS(ID_AA64PFR0_EL1, EL0, AARCH32) }, #ifdef CONFIG_KVM { @@ -2310,11 +2282,7 @@ static const struct arm64_cpu_capabilities arm64_fea= tures[] =3D { .capability =3D ARM64_HAS_32BIT_EL1, .type =3D ARM64_CPUCAP_SYSTEM_FEATURE, .matches =3D has_cpuid_feature, - .sys_reg =3D SYS_ID_AA64PFR0_EL1, - .sign =3D FTR_UNSIGNED, - .field_pos =3D ID_AA64PFR0_EL1_EL1_SHIFT, - .field_width =3D 4, - .min_field_value =3D ID_AA64PFR0_EL1_ELx_32BIT_64BIT, + ARM64_CPUID_FIELDS(ID_AA64PFR0_EL1, EL1, AARCH32) }, { .desc =3D "Protected KVM", @@ -2327,17 +2295,14 @@ static const struct arm64_cpu_capabilities arm64_fe= atures[] =3D { .desc =3D "Kernel page table isolation (KPTI)", .capability =3D ARM64_UNMAP_KERNEL_AT_EL0, .type =3D ARM64_CPUCAP_BOOT_RESTRICTED_CPU_LOCAL_FEATURE, + .cpu_enable =3D kpti_install_ng_mappings, + .matches =3D unmap_kernel_at_el0, /* * The ID feature fields below are used to indicate that * the CPU doesn't need KPTI. See unmap_kernel_at_el0 for * more details. */ - .sys_reg =3D SYS_ID_AA64PFR0_EL1, - .field_pos =3D ID_AA64PFR0_EL1_CSV3_SHIFT, - .field_width =3D 4, - .min_field_value =3D ID_AA64PFR0_EL1_CSV3_IMP, - .matches =3D unmap_kernel_at_el0, - .cpu_enable =3D kpti_install_ng_mappings, + ARM64_CPUID_FIELDS(ID_AA64PFR0_EL1, CSV3, IMP) }, { /* FP/SIMD is not implemented */ @@ -2352,21 +2317,14 @@ static const struct arm64_cpu_capabilities arm64_fe= atures[] =3D { .capability =3D ARM64_HAS_DCPOP, .type =3D ARM64_CPUCAP_SYSTEM_FEATURE, .matches =3D has_cpuid_feature, - .sys_reg =3D SYS_ID_AA64ISAR1_EL1, - .field_pos =3D ID_AA64ISAR1_EL1_DPB_SHIFT, - .field_width =3D 4, - .min_field_value =3D ID_AA64ISAR1_EL1_DPB_IMP, + ARM64_CPUID_FIELDS(ID_AA64ISAR1_EL1, DPB, IMP) }, { .desc =3D "Data cache clean to Point of Deep Persistence", .capability =3D ARM64_HAS_DCPODP, .type =3D ARM64_CPUCAP_SYSTEM_FEATURE, .matches =3D has_cpuid_feature, - .sys_reg =3D SYS_ID_AA64ISAR1_EL1, - .sign =3D FTR_UNSIGNED, - .field_pos =3D ID_AA64ISAR1_EL1_DPB_SHIFT, - .field_width =3D 4, - .min_field_value =3D ID_AA64ISAR1_EL1_DPB_DPB2, + ARM64_CPUID_FIELDS(ID_AA64ISAR1_EL1, DPB, DPB2) }, #endif #ifdef CONFIG_ARM64_SVE @@ -2374,13 +2332,9 @@ static const struct arm64_cpu_capabilities arm64_fea= tures[] =3D { .desc =3D "Scalable Vector Extension", .type =3D ARM64_CPUCAP_SYSTEM_FEATURE, .capability =3D ARM64_SVE, - .sys_reg =3D SYS_ID_AA64PFR0_EL1, - .sign =3D FTR_UNSIGNED, - .field_pos =3D ID_AA64PFR0_EL1_SVE_SHIFT, - .field_width =3D 4, - .min_field_value =3D ID_AA64PFR0_EL1_SVE_IMP, - .matches =3D has_cpuid_feature, .cpu_enable =3D sve_kernel_enable, + .matches =3D has_cpuid_feature, + ARM64_CPUID_FIELDS(ID_AA64PFR0_EL1, SVE, IMP) }, #endif /* CONFIG_ARM64_SVE */ #ifdef CONFIG_ARM64_RAS_EXTN @@ -2389,12 +2343,8 @@ static const struct arm64_cpu_capabilities arm64_fea= tures[] =3D { .capability =3D ARM64_HAS_RAS_EXTN, .type =3D ARM64_CPUCAP_SYSTEM_FEATURE, .matches =3D has_cpuid_feature, - .sys_reg =3D SYS_ID_AA64PFR0_EL1, - .sign =3D FTR_UNSIGNED, - .field_pos =3D ID_AA64PFR0_EL1_RAS_SHIFT, - .field_width =3D 4, - .min_field_value =3D ID_AA64PFR0_EL1_RAS_IMP, .cpu_enable =3D cpu_clear_disr, + ARM64_CPUID_FIELDS(ID_AA64PFR0_EL1, RAS, IMP) }, #endif /* CONFIG_ARM64_RAS_EXTN */ #ifdef CONFIG_ARM64_AMU_EXTN @@ -2408,12 +2358,8 @@ static const struct arm64_cpu_capabilities arm64_fea= tures[] =3D { .capability =3D ARM64_HAS_AMU_EXTN, .type =3D ARM64_CPUCAP_WEAK_LOCAL_CPU_FEATURE, .matches =3D has_amu, - .sys_reg =3D SYS_ID_AA64PFR0_EL1, - .sign =3D FTR_UNSIGNED, - .field_pos =3D ID_AA64PFR0_EL1_AMU_SHIFT, - .field_width =3D 4, - .min_field_value =3D ID_AA64PFR0_EL1_AMU_IMP, .cpu_enable =3D cpu_amu_enable, + ARM64_CPUID_FIELDS(ID_AA64PFR0_EL1, AMU, IMP) }, #endif /* CONFIG_ARM64_AMU_EXTN */ { @@ -2433,34 +2379,22 @@ static const struct arm64_cpu_capabilities arm64_fe= atures[] =3D { .desc =3D "Stage-2 Force Write-Back", .type =3D ARM64_CPUCAP_SYSTEM_FEATURE, .capability =3D ARM64_HAS_STAGE2_FWB, - .sys_reg =3D SYS_ID_AA64MMFR2_EL1, - .sign =3D FTR_UNSIGNED, - .field_pos =3D ID_AA64MMFR2_EL1_FWB_SHIFT, - .field_width =3D 4, - .min_field_value =3D ID_AA64MMFR2_EL1_FWB_IMP, .matches =3D has_cpuid_feature, + ARM64_CPUID_FIELDS(ID_AA64MMFR2_EL1, FWB, IMP) }, { .desc =3D "ARMv8.4 Translation Table Level", .type =3D ARM64_CPUCAP_SYSTEM_FEATURE, .capability =3D ARM64_HAS_ARMv8_4_TTL, - .sys_reg =3D SYS_ID_AA64MMFR2_EL1, - .sign =3D FTR_UNSIGNED, - .field_pos =3D ID_AA64MMFR2_EL1_TTL_SHIFT, - .field_width =3D 4, - .min_field_value =3D ID_AA64MMFR2_EL1_TTL_IMP, .matches =3D has_cpuid_feature, + ARM64_CPUID_FIELDS(ID_AA64MMFR2_EL1, TTL, IMP) }, { .desc =3D "TLB range maintenance instructions", .capability =3D ARM64_HAS_TLB_RANGE, .type =3D ARM64_CPUCAP_SYSTEM_FEATURE, .matches =3D has_cpuid_feature, - .sys_reg =3D SYS_ID_AA64ISAR0_EL1, - .field_pos =3D ID_AA64ISAR0_EL1_TLB_SHIFT, - .field_width =3D 4, - .sign =3D FTR_UNSIGNED, - .min_field_value =3D ID_AA64ISAR0_EL1_TLB_RANGE, + ARM64_CPUID_FIELDS(ID_AA64ISAR0_EL1, TLB, RANGE) }, #ifdef CONFIG_ARM64_HW_AFDBM { @@ -2474,13 +2408,9 @@ static const struct arm64_cpu_capabilities arm64_fea= tures[] =3D { */ .type =3D ARM64_CPUCAP_WEAK_LOCAL_CPU_FEATURE, .capability =3D ARM64_HW_DBM, - .sys_reg =3D SYS_ID_AA64MMFR1_EL1, - .sign =3D FTR_UNSIGNED, - .field_pos =3D ID_AA64MMFR1_EL1_HAFDBS_SHIFT, - .field_width =3D 4, - .min_field_value =3D ID_AA64MMFR1_EL1_HAFDBS_DBM, .matches =3D has_hw_dbm, .cpu_enable =3D cpu_enable_hw_dbm, + ARM64_CPUID_FIELDS(ID_AA64MMFR1_EL1, HAFDBS, DBM) }, #endif { @@ -2488,21 +2418,14 @@ static const struct arm64_cpu_capabilities arm64_fe= atures[] =3D { .capability =3D ARM64_HAS_CRC32, .type =3D ARM64_CPUCAP_SYSTEM_FEATURE, .matches =3D has_cpuid_feature, - .sys_reg =3D SYS_ID_AA64ISAR0_EL1, - .field_pos =3D ID_AA64ISAR0_EL1_CRC32_SHIFT, - .field_width =3D 4, - .min_field_value =3D ID_AA64ISAR0_EL1_CRC32_IMP, + ARM64_CPUID_FIELDS(ID_AA64ISAR0_EL1, CRC32, IMP) }, { .desc =3D "Speculative Store Bypassing Safe (SSBS)", .capability =3D ARM64_SSBS, .type =3D ARM64_CPUCAP_SYSTEM_FEATURE, .matches =3D has_cpuid_feature, - .sys_reg =3D SYS_ID_AA64PFR1_EL1, - .field_pos =3D ID_AA64PFR1_EL1_SSBS_SHIFT, - .field_width =3D 4, - .sign =3D FTR_UNSIGNED, - .min_field_value =3D ID_AA64PFR1_EL1_SSBS_IMP, + ARM64_CPUID_FIELDS(ID_AA64PFR1_EL1, SSBS, IMP) }, #ifdef CONFIG_ARM64_CNP { @@ -2510,12 +2433,8 @@ static const struct arm64_cpu_capabilities arm64_fea= tures[] =3D { .capability =3D ARM64_HAS_CNP, .type =3D ARM64_CPUCAP_SYSTEM_FEATURE, .matches =3D has_useable_cnp, - .sys_reg =3D SYS_ID_AA64MMFR2_EL1, - .sign =3D FTR_UNSIGNED, - .field_pos =3D ID_AA64MMFR2_EL1_CnP_SHIFT, - .field_width =3D 4, - .min_field_value =3D ID_AA64MMFR2_EL1_CnP_IMP, .cpu_enable =3D cpu_enable_cnp, + ARM64_CPUID_FIELDS(ID_AA64MMFR2_EL1, CnP, IMP) }, #endif { @@ -2523,45 +2442,29 @@ static const struct arm64_cpu_capabilities arm64_fe= atures[] =3D { .capability =3D ARM64_HAS_SB, .type =3D ARM64_CPUCAP_SYSTEM_FEATURE, .matches =3D has_cpuid_feature, - .sys_reg =3D SYS_ID_AA64ISAR1_EL1, - .field_pos =3D ID_AA64ISAR1_EL1_SB_SHIFT, - .field_width =3D 4, - .sign =3D FTR_UNSIGNED, - .min_field_value =3D ID_AA64ISAR1_EL1_SB_IMP, + ARM64_CPUID_FIELDS(ID_AA64ISAR1_EL1, SB, IMP) }, #ifdef CONFIG_ARM64_PTR_AUTH { .desc =3D "Address authentication (architected QARMA5 algorithm)", .capability =3D ARM64_HAS_ADDRESS_AUTH_ARCH_QARMA5, .type =3D ARM64_CPUCAP_BOOT_CPU_FEATURE, - .sys_reg =3D SYS_ID_AA64ISAR1_EL1, - .sign =3D FTR_UNSIGNED, - .field_pos =3D ID_AA64ISAR1_EL1_APA_SHIFT, - .field_width =3D 4, - .min_field_value =3D ID_AA64ISAR1_EL1_APA_PAuth, .matches =3D has_address_auth_cpucap, + ARM64_CPUID_FIELDS(ID_AA64ISAR1_EL1, APA, PAuth) }, { .desc =3D "Address authentication (architected QARMA3 algorithm)", .capability =3D ARM64_HAS_ADDRESS_AUTH_ARCH_QARMA3, .type =3D ARM64_CPUCAP_BOOT_CPU_FEATURE, - .sys_reg =3D SYS_ID_AA64ISAR2_EL1, - .sign =3D FTR_UNSIGNED, - .field_pos =3D ID_AA64ISAR2_EL1_APA3_SHIFT, - .field_width =3D 4, - .min_field_value =3D ID_AA64ISAR2_EL1_APA3_PAuth, .matches =3D has_address_auth_cpucap, + ARM64_CPUID_FIELDS(ID_AA64ISAR2_EL1, APA3, PAuth) }, { .desc =3D "Address authentication (IMP DEF algorithm)", .capability =3D ARM64_HAS_ADDRESS_AUTH_IMP_DEF, .type =3D ARM64_CPUCAP_BOOT_CPU_FEATURE, - .sys_reg =3D SYS_ID_AA64ISAR1_EL1, - .sign =3D FTR_UNSIGNED, - .field_pos =3D ID_AA64ISAR1_EL1_API_SHIFT, - .field_width =3D 4, - .min_field_value =3D ID_AA64ISAR1_EL1_API_PAuth, .matches =3D has_address_auth_cpucap, + ARM64_CPUID_FIELDS(ID_AA64ISAR1_EL1, API, PAuth) }, { .capability =3D ARM64_HAS_ADDRESS_AUTH, @@ -2572,34 +2475,22 @@ static const struct arm64_cpu_capabilities arm64_fe= atures[] =3D { .desc =3D "Generic authentication (architected QARMA5 algorithm)", .capability =3D ARM64_HAS_GENERIC_AUTH_ARCH_QARMA5, .type =3D ARM64_CPUCAP_SYSTEM_FEATURE, - .sys_reg =3D SYS_ID_AA64ISAR1_EL1, - .sign =3D FTR_UNSIGNED, - .field_pos =3D ID_AA64ISAR1_EL1_GPA_SHIFT, - .field_width =3D 4, - .min_field_value =3D ID_AA64ISAR1_EL1_GPA_IMP, .matches =3D has_cpuid_feature, + ARM64_CPUID_FIELDS(ID_AA64ISAR1_EL1, GPA, IMP) }, { .desc =3D "Generic authentication (architected QARMA3 algorithm)", .capability =3D ARM64_HAS_GENERIC_AUTH_ARCH_QARMA3, .type =3D ARM64_CPUCAP_SYSTEM_FEATURE, - .sys_reg =3D SYS_ID_AA64ISAR2_EL1, - .sign =3D FTR_UNSIGNED, - .field_pos =3D ID_AA64ISAR2_EL1_GPA3_SHIFT, - .field_width =3D 4, - .min_field_value =3D ID_AA64ISAR2_EL1_GPA3_IMP, .matches =3D has_cpuid_feature, + ARM64_CPUID_FIELDS(ID_AA64ISAR2_EL1, GPA3, IMP) }, { .desc =3D "Generic authentication (IMP DEF algorithm)", .capability =3D ARM64_HAS_GENERIC_AUTH_IMP_DEF, .type =3D ARM64_CPUCAP_SYSTEM_FEATURE, - .sys_reg =3D SYS_ID_AA64ISAR1_EL1, - .sign =3D FTR_UNSIGNED, - .field_pos =3D ID_AA64ISAR1_EL1_GPI_SHIFT, - .field_width =3D 4, - .min_field_value =3D ID_AA64ISAR1_EL1_GPI_IMP, .matches =3D has_cpuid_feature, + ARM64_CPUID_FIELDS(ID_AA64ISAR1_EL1, GPI, IMP) }, { .capability =3D ARM64_HAS_GENERIC_AUTH, @@ -2631,13 +2522,9 @@ static const struct arm64_cpu_capabilities arm64_fea= tures[] =3D { .desc =3D "E0PD", .capability =3D ARM64_HAS_E0PD, .type =3D ARM64_CPUCAP_SYSTEM_FEATURE, - .sys_reg =3D SYS_ID_AA64MMFR2_EL1, - .sign =3D FTR_UNSIGNED, - .field_width =3D 4, - .field_pos =3D ID_AA64MMFR2_EL1_E0PD_SHIFT, - .matches =3D has_cpuid_feature, - .min_field_value =3D ID_AA64MMFR2_EL1_E0PD_IMP, .cpu_enable =3D cpu_enable_e0pd, + .matches =3D has_cpuid_feature, + ARM64_CPUID_FIELDS(ID_AA64MMFR2_EL1, E0PD, IMP) }, #endif { @@ -2645,11 +2532,7 @@ static const struct arm64_cpu_capabilities arm64_fea= tures[] =3D { .capability =3D ARM64_HAS_RNG, .type =3D ARM64_CPUCAP_SYSTEM_FEATURE, .matches =3D has_cpuid_feature, - .sys_reg =3D SYS_ID_AA64ISAR0_EL1, - .field_pos =3D ID_AA64ISAR0_EL1_RNDR_SHIFT, - .field_width =3D 4, - .sign =3D FTR_UNSIGNED, - .min_field_value =3D ID_AA64ISAR0_EL1_RNDR_IMP, + ARM64_CPUID_FIELDS(ID_AA64ISAR0_EL1, RNDR, IMP) }, #ifdef CONFIG_ARM64_BTI { @@ -2662,10 +2545,7 @@ static const struct arm64_cpu_capabilities arm64_fea= tures[] =3D { #endif .matches =3D has_cpuid_feature, .cpu_enable =3D bti_enable, - .sys_reg =3D SYS_ID_AA64PFR1_EL1, - .field_pos =3D ID_AA64PFR1_EL1_BT_SHIFT, - .field_width =3D 4, - .min_field_value =3D ID_AA64PFR1_EL1_BT_IMP, + ARM64_CPUID_FIELDS(ID_AA64PFR1_EL1, BT, IMP) .sign =3D FTR_UNSIGNED, }, #endif @@ -2675,109 +2555,73 @@ static const struct arm64_cpu_capabilities arm64_f= eatures[] =3D { .capability =3D ARM64_MTE, .type =3D ARM64_CPUCAP_STRICT_BOOT_CPU_FEATURE, .matches =3D has_cpuid_feature, - .sys_reg =3D SYS_ID_AA64PFR1_EL1, - .field_pos =3D ID_AA64PFR1_EL1_MTE_SHIFT, - .field_width =3D 4, - .min_field_value =3D ID_AA64PFR1_EL1_MTE_MTE2, - .sign =3D FTR_UNSIGNED, .cpu_enable =3D cpu_enable_mte, + ARM64_CPUID_FIELDS(ID_AA64PFR1_EL1, MTE, MTE2) }, { .desc =3D "Asymmetric MTE Tag Check Fault", .capability =3D ARM64_MTE_ASYMM, .type =3D ARM64_CPUCAP_BOOT_CPU_FEATURE, .matches =3D has_cpuid_feature, - .sys_reg =3D SYS_ID_AA64PFR1_EL1, - .field_pos =3D ID_AA64PFR1_EL1_MTE_SHIFT, - .field_width =3D 4, - .min_field_value =3D ID_AA64PFR1_EL1_MTE_MTE3, - .sign =3D FTR_UNSIGNED, + ARM64_CPUID_FIELDS(ID_AA64PFR1_EL1, MTE, MTE3) }, #endif /* CONFIG_ARM64_MTE */ { .desc =3D "RCpc load-acquire (LDAPR)", .capability =3D ARM64_HAS_LDAPR, .type =3D ARM64_CPUCAP_SYSTEM_FEATURE, - .sys_reg =3D SYS_ID_AA64ISAR1_EL1, - .sign =3D FTR_UNSIGNED, - .field_pos =3D ID_AA64ISAR1_EL1_LRCPC_SHIFT, - .field_width =3D 4, .matches =3D has_cpuid_feature, - .min_field_value =3D ID_AA64ISAR1_EL1_LRCPC_IMP, + ARM64_CPUID_FIELDS(ID_AA64ISAR1_EL1, LRCPC, IMP) }, #ifdef CONFIG_ARM64_SME { .desc =3D "Scalable Matrix Extension", .type =3D ARM64_CPUCAP_SYSTEM_FEATURE, .capability =3D ARM64_SME, - .sys_reg =3D SYS_ID_AA64PFR1_EL1, - .sign =3D FTR_UNSIGNED, - .field_pos =3D ID_AA64PFR1_EL1_SME_SHIFT, - .field_width =3D 4, - .min_field_value =3D ID_AA64PFR1_EL1_SME_IMP, .matches =3D has_cpuid_feature, .cpu_enable =3D sme_kernel_enable, + ARM64_CPUID_FIELDS(ID_AA64PFR1_EL1, SME, IMP) }, /* FA64 should be sorted after the base SME capability */ { .desc =3D "FA64", .type =3D ARM64_CPUCAP_SYSTEM_FEATURE, .capability =3D ARM64_SME_FA64, - .sys_reg =3D SYS_ID_AA64SMFR0_EL1, - .sign =3D FTR_UNSIGNED, - .field_pos =3D ID_AA64SMFR0_EL1_FA64_SHIFT, - .field_width =3D 1, - .min_field_value =3D ID_AA64SMFR0_EL1_FA64_IMP, .matches =3D has_cpuid_feature, .cpu_enable =3D fa64_kernel_enable, + ARM64_CPUID_FIELDS(ID_AA64SMFR0_EL1, FA64, IMP) }, { .desc =3D "SME2", .type =3D ARM64_CPUCAP_SYSTEM_FEATURE, .capability =3D ARM64_SME2, - .sys_reg =3D SYS_ID_AA64PFR1_EL1, - .sign =3D FTR_UNSIGNED, - .field_pos =3D ID_AA64PFR1_EL1_SME_SHIFT, - .field_width =3D ID_AA64PFR1_EL1_SME_WIDTH, - .min_field_value =3D ID_AA64PFR1_EL1_SME_SME2, .matches =3D has_cpuid_feature, .cpu_enable =3D sme2_kernel_enable, + ARM64_CPUID_FIELDS(ID_AA64PFR1_EL1, SME, SME2) }, #endif /* CONFIG_ARM64_SME */ { .desc =3D "WFx with timeout", .capability =3D ARM64_HAS_WFXT, .type =3D ARM64_CPUCAP_SYSTEM_FEATURE, - .sys_reg =3D SYS_ID_AA64ISAR2_EL1, - .sign =3D FTR_UNSIGNED, - .field_pos =3D ID_AA64ISAR2_EL1_WFxT_SHIFT, - .field_width =3D 4, .matches =3D has_cpuid_feature, - .min_field_value =3D ID_AA64ISAR2_EL1_WFxT_IMP, + ARM64_CPUID_FIELDS(ID_AA64ISAR2_EL1, WFxT, IMP) }, { .desc =3D "Trap EL0 IMPLEMENTATION DEFINED functionality", .capability =3D ARM64_HAS_TIDCP1, .type =3D ARM64_CPUCAP_SYSTEM_FEATURE, - .sys_reg =3D SYS_ID_AA64MMFR1_EL1, - .sign =3D FTR_UNSIGNED, - .field_pos =3D ID_AA64MMFR1_EL1_TIDCP1_SHIFT, - .field_width =3D 4, - .min_field_value =3D ID_AA64MMFR1_EL1_TIDCP1_IMP, .matches =3D has_cpuid_feature, .cpu_enable =3D cpu_trap_el0_impdef, + ARM64_CPUID_FIELDS(ID_AA64MMFR1_EL1, TIDCP1, IMP) }, { .desc =3D "Data independent timing control (DIT)", .capability =3D ARM64_HAS_DIT, .type =3D ARM64_CPUCAP_SYSTEM_FEATURE, - .sys_reg =3D SYS_ID_AA64PFR0_EL1, - .sign =3D FTR_UNSIGNED, - .field_pos =3D ID_AA64PFR0_EL1_DIT_SHIFT, - .field_width =3D 4, - .min_field_value =3D ID_AA64PFR0_EL1_DIT_IMP, .matches =3D has_cpuid_feature, .cpu_enable =3D cpu_enable_dit, + ARM64_CPUID_FIELDS(ID_AA64PFR0_EL1, DIT, IMP) }, {}, }; --=20 2.30.2