From nobody Sat Apr 11 13:07:33 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 06A85C64EC4 for ; Mon, 6 Mar 2023 22:20:49 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230051AbjCFWUr (ORCPT ); Mon, 6 Mar 2023 17:20:47 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:47276 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230035AbjCFWUn (ORCPT ); Mon, 6 Mar 2023 17:20:43 -0500 Received: from ams.source.kernel.org (ams.source.kernel.org [145.40.68.75]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 14EEE5D476 for ; Mon, 6 Mar 2023 14:20:42 -0800 (PST) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ams.source.kernel.org (Postfix) with ESMTPS id C20B7B81141 for ; Mon, 6 Mar 2023 22:20:40 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 30B7AC433A0; Mon, 6 Mar 2023 22:20:38 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1678141239; bh=VTfNMr9L+OZD61fr7gdaYm/jVX8qzkby7YMcuXZ9mFU=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=JAg71P6ctiIsp3OinvUbuklYSbxEQNHCJaI/ZeYXIB8NoTMsEmlyMkkwvmmRqoEFY E3m7LuMxCfHN9MhDjpolb5APS/kcKsaZmEMHdKQyruQPMvZ/7/EmtNf7NSuCTIwE3J 9fnRiAYO6eAaQ3J7znBejZKC8UudnzkTYtOj8WDeY0bTUs4xD6pTUUVge9pTC1l/Nj lbWS0XSJPjspt92Z28comwlS/tOVi7Br+ZzNPkH9ouFs5ur/P8cp4hSKQMYGjWXdoo AF2qutd3rFc0k+Meu1ziqVDJFsswMZquodLMj7QGQsAlgQEbYE/OqopiJhXRtmCBSx +ll9DngBkjrtQ== From: Mark Brown Date: Mon, 06 Mar 2023 22:20:23 +0000 Subject: [PATCH 1/3] arm64/cpufeature: Pull out helper for CPUID register definitions MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20230303-arm64-cpufeature-helpers-v1-1-b16cf36acaea@kernel.org> References: <20230303-arm64-cpufeature-helpers-v1-0-b16cf36acaea@kernel.org> In-Reply-To: <20230303-arm64-cpufeature-helpers-v1-0-b16cf36acaea@kernel.org> To: Catalin Marinas , Will Deacon Cc: Suzuki K Poulose , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Mark Brown X-Mailer: b4 0.13-dev-bd1bf X-Developer-Signature: v=1; a=openpgp-sha256; l=2794; i=broonie@kernel.org; h=from:subject:message-id; bh=VTfNMr9L+OZD61fr7gdaYm/jVX8qzkby7YMcuXZ9mFU=; b=owEBbQGS/pANAwAKASTWi3JdVIfQAcsmYgBkBmcx2Y5IxiHuDp4hea7brk355PUmvzDhPhmF8Ym6 zQik5RyJATMEAAEKAB0WIQSt5miqZ1cYtZ/in+ok1otyXVSH0AUCZAZnMQAKCRAk1otyXVSH0G8SB/ 9/oeM1uv8BJc13DrXGX31mWlPAc13MPIZtUQqHVCGbSaBn9FhFf2KiNeTUEiLFgJ7ELv6vtat5sxvX 6sCPSPUASguAku2QrOpqPvsOTYRSZZbgutHwo3QiCgeXAh3AoHNRRxv0aqz18XXWetLBbcC/yW8uAz viwoR6jhD9kThahXuXeHqfwpifLxGxFCW99N7kC4Y51VVJlUSfRIUzxpEcWbByxifOE03B77EGT29b HUtBY+leSgaFW/CCr2+Lr6LVgH4PNrhlxcH6E6ykpCoZCKgA5/SZdUmwOW4vWceSQUfy2i9aErOD3E P4UeeXBXyg8M4WfXF0IKxcKAFqM+H5 X-Developer-Key: i=broonie@kernel.org; a=openpgp; fpr=3F2568AAC26998F9E813A1C5C3F436CA30F5D8EB Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org We use the same structure to match hwcaps and CPU features so we can use the same helper to generate the fields required. Pull the portion of the current hwcaps helper that initialises the fields out into a separate define placed earlier in the file so we can use it for cpufeatures. No functional change. Signed-off-by: Mark Brown --- arch/arm64/kernel/cpufeature.c | 27 +++++++++++++++------------ 1 file changed, 15 insertions(+), 12 deletions(-) diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c index 2e3e55139777..77862b7c8908 100644 --- a/arch/arm64/kernel/cpufeature.c +++ b/arch/arm64/kernel/cpufeature.c @@ -140,6 +140,13 @@ void dump_cpu_features(void) pr_emerg("0x%*pb\n", ARM64_NCAPS, &cpu_hwcaps); } =20 +#define ARM64_CPUID_FIELDS(reg, field, min_value) \ + .sys_reg =3D SYS_##reg, \ + .field_pos =3D reg##_##field##_SHIFT, \ + .field_width =3D reg##_##field##_WIDTH, \ + .sign =3D reg##_##field##_SIGNED, \ + .min_field_value =3D reg##_##field##_##min_value, + #define __ARM64_FTR_BITS(SIGNED, VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE= _VAL) \ { \ .sign =3D SIGNED, \ @@ -2776,12 +2783,8 @@ static const struct arm64_cpu_capabilities arm64_fea= tures[] =3D { }; =20 #define HWCAP_CPUID_MATCH(reg, field, min_value) \ - .matches =3D has_user_cpuid_feature, \ - .sys_reg =3D SYS_##reg, \ - .field_pos =3D reg##_##field##_SHIFT, \ - .field_width =3D reg##_##field##_WIDTH, \ - .sign =3D reg##_##field##_SIGNED, \ - .min_field_value =3D reg##_##field##_##min_value, + .matches =3D has_user_cpuid_feature, \ + ARM64_CPUID_FIELDS(reg, field, min_value) =20 #define __HWCAP_CAP(name, cap_type, cap) \ .desc =3D name, \ @@ -2811,26 +2814,26 @@ static const struct arm64_cpu_capabilities arm64_fe= atures[] =3D { #ifdef CONFIG_ARM64_PTR_AUTH static const struct arm64_cpu_capabilities ptr_auth_hwcap_addr_matches[] = =3D { { - HWCAP_CPUID_MATCH(ID_AA64ISAR1_EL1, APA, PAuth) + ARM64_CPUID_FIELDS(ID_AA64ISAR1_EL1, APA, PAuth) }, { - HWCAP_CPUID_MATCH(ID_AA64ISAR2_EL1, APA3, PAuth) + ARM64_CPUID_FIELDS(ID_AA64ISAR2_EL1, APA3, PAuth) }, { - HWCAP_CPUID_MATCH(ID_AA64ISAR1_EL1, API, PAuth) + ARM64_CPUID_FIELDS(ID_AA64ISAR1_EL1, API, PAuth) }, {}, }; =20 static const struct arm64_cpu_capabilities ptr_auth_hwcap_gen_matches[] = =3D { { - HWCAP_CPUID_MATCH(ID_AA64ISAR1_EL1, GPA, IMP) + ARM64_CPUID_FIELDS(ID_AA64ISAR1_EL1, GPA, IMP) }, { - HWCAP_CPUID_MATCH(ID_AA64ISAR2_EL1, GPA3, IMP) + ARM64_CPUID_FIELDS(ID_AA64ISAR2_EL1, GPA3, IMP) }, { - HWCAP_CPUID_MATCH(ID_AA64ISAR1_EL1, GPI, IMP) + ARM64_CPUID_FIELDS(ID_AA64ISAR1_EL1, GPI, IMP) }, {}, }; --=20 2.30.2 From nobody Sat Apr 11 13:07:33 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 24793C61DA4 for ; Mon, 6 Mar 2023 22:20:52 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230057AbjCFWUu (ORCPT ); Mon, 6 Mar 2023 17:20:50 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:47280 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230033AbjCFWUn (ORCPT ); Mon, 6 Mar 2023 17:20:43 -0500 Received: from dfw.source.kernel.org (dfw.source.kernel.org [139.178.84.217]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 2578E5D8AC for ; Mon, 6 Mar 2023 14:20:42 -0800 (PST) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id A7D7C60F63 for ; Mon, 6 Mar 2023 22:20:41 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id D8AACC433EF; Mon, 6 Mar 2023 22:20:39 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1678141241; bh=0Hr13Ki+m63iSYR2fR5Lo1Ctqag6JX+98ae54h0hx9Q=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=PUI+sAkbsyaCSqxa1GTfdjBU5ila6ir+VpxFBvPVyNpAXPMtYGzeQ+0t/VYlV+vIT 2t1sm8UFkFc94KzZ+lyql3+tDfFdVpi+911jqihG3+hELuwwGFvUUtV3dhCDqvYpEv yZBxT0W6xatJIE2ORerO0vgRQ+6i9/AGSCTx0poykDvr0mRAqXYfNciTnaDGrGWTBO kK7tUvVN5ALb0rAHMqSCtjLIGZwHSCCxy/NmDMnyKLYq4iap6CUB+zpBStbRW9uZo7 /71a3U4yg2TysIkRYGr292YcCOnxkCc3fBeov3iWV0nLDHdqeC8VaH8HOv3LPJxm98 JubMHKMaRwyOQ== From: Mark Brown Date: Mon, 06 Mar 2023 22:20:24 +0000 Subject: [PATCH 2/3] arm64/cpufeature: Consistently use symbolic constants for min_field_value MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20230303-arm64-cpufeature-helpers-v1-2-b16cf36acaea@kernel.org> References: <20230303-arm64-cpufeature-helpers-v1-0-b16cf36acaea@kernel.org> In-Reply-To: <20230303-arm64-cpufeature-helpers-v1-0-b16cf36acaea@kernel.org> To: Catalin Marinas , Will Deacon Cc: Suzuki K Poulose , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Mark Brown X-Mailer: b4 0.13-dev-bd1bf X-Developer-Signature: v=1; a=openpgp-sha256; l=5978; i=broonie@kernel.org; h=from:subject:message-id; bh=0Hr13Ki+m63iSYR2fR5Lo1Ctqag6JX+98ae54h0hx9Q=; b=owEBbQGS/pANAwAKASTWi3JdVIfQAcsmYgBkBmcygVTlhWtSWpA78GWaDC3BCrsYJ5c59DjGY4OX M+3mgceJATMEAAEKAB0WIQSt5miqZ1cYtZ/in+ok1otyXVSH0AUCZAZnMgAKCRAk1otyXVSH0EwiB/ 9lGRVToZ4N5Fj7SCc6p4z3/97PND32a2YFKWrO643WRwhpaq6YZbItpNJ8ZP1kt9s/OD6tKimauRH+ 7tTiexRoxpQ5O7Rbkv6W5RPgSXiKkT0XYnVpVcjsGOJLb6jisu2sZHrKpnvzZ/DMMib2cQFD9ld0j/ yw0mGUd+YHUp9fgKCoq9SjJit5UitR/Xe3daci1Y8RtXJ/kovEATvwHIgFLyKVxx8N+XQVgDa4rFNZ d1I60SbhtfuJZ40TG5RM1d61KUOr2r5DoRR99NJccoCccfIIfs1AoTr7BYsXszw/E0nUNI3ywz8vFI nSdgA1tvJ+mA1WnwiHs4IgiEBCBKwp X-Developer-Key: i=broonie@kernel.org; a=openpgp; fpr=3F2568AAC26998F9E813A1C5C3F436CA30F5D8EB Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org A number of the cpufeatures use raw numbers for the minimum field values specified rather than symbolic constants. In preparation for the use of helper macros replace all these with the appropriate constants. No change in the generated binary. Signed-off-by: Mark Brown --- arch/arm64/kernel/cpufeature.c | 34 +++++++++++++++++----------------- 1 file changed, 17 insertions(+), 17 deletions(-) diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c index 77862b7c8908..1002ac437e8b 100644 --- a/arch/arm64/kernel/cpufeature.c +++ b/arch/arm64/kernel/cpufeature.c @@ -2217,7 +2217,7 @@ static const struct arm64_cpu_capabilities arm64_feat= ures[] =3D { .field_pos =3D ID_AA64PFR0_EL1_GIC_SHIFT, .field_width =3D 4, .sign =3D FTR_UNSIGNED, - .min_field_value =3D 1, + .min_field_value =3D ID_AA64PFR0_EL1_GIC_IMP, }, { .desc =3D "Enhanced Counter Virtualization", @@ -2228,7 +2228,7 @@ static const struct arm64_cpu_capabilities arm64_feat= ures[] =3D { .field_pos =3D ID_AA64MMFR0_EL1_ECV_SHIFT, .field_width =3D 4, .sign =3D FTR_UNSIGNED, - .min_field_value =3D 1, + .min_field_value =3D ID_AA64MMFR0_EL1_ECV_IMP, }, #ifdef CONFIG_ARM64_PAN { @@ -2240,7 +2240,7 @@ static const struct arm64_cpu_capabilities arm64_feat= ures[] =3D { .field_pos =3D ID_AA64MMFR1_EL1_PAN_SHIFT, .field_width =3D 4, .sign =3D FTR_UNSIGNED, - .min_field_value =3D 1, + .min_field_value =3D ID_AA64MMFR1_EL1_PAN_IMP, .cpu_enable =3D cpu_enable_pan, }, #endif /* CONFIG_ARM64_PAN */ @@ -2254,7 +2254,7 @@ static const struct arm64_cpu_capabilities arm64_feat= ures[] =3D { .field_pos =3D ID_AA64MMFR1_EL1_PAN_SHIFT, .field_width =3D 4, .sign =3D FTR_UNSIGNED, - .min_field_value =3D 3, + .min_field_value =3D ID_AA64MMFR1_EL1_PAN_PAN3, }, #endif /* CONFIG_ARM64_EPAN */ #ifdef CONFIG_ARM64_LSE_ATOMICS @@ -2267,7 +2267,7 @@ static const struct arm64_cpu_capabilities arm64_feat= ures[] =3D { .field_pos =3D ID_AA64ISAR0_EL1_ATOMIC_SHIFT, .field_width =3D 4, .sign =3D FTR_UNSIGNED, - .min_field_value =3D 2, + .min_field_value =3D ID_AA64ISAR0_EL1_ATOMIC_IMP, }, #endif /* CONFIG_ARM64_LSE_ATOMICS */ { @@ -2335,7 +2335,7 @@ static const struct arm64_cpu_capabilities arm64_feat= ures[] =3D { .sys_reg =3D SYS_ID_AA64PFR0_EL1, .field_pos =3D ID_AA64PFR0_EL1_CSV3_SHIFT, .field_width =3D 4, - .min_field_value =3D 1, + .min_field_value =3D ID_AA64PFR0_EL1_CSV3_IMP, .matches =3D unmap_kernel_at_el0, .cpu_enable =3D kpti_install_ng_mappings, }, @@ -2355,7 +2355,7 @@ static const struct arm64_cpu_capabilities arm64_feat= ures[] =3D { .sys_reg =3D SYS_ID_AA64ISAR1_EL1, .field_pos =3D ID_AA64ISAR1_EL1_DPB_SHIFT, .field_width =3D 4, - .min_field_value =3D 1, + .min_field_value =3D ID_AA64ISAR1_EL1_DPB_IMP, }, { .desc =3D "Data cache clean to Point of Deep Persistence", @@ -2366,7 +2366,7 @@ static const struct arm64_cpu_capabilities arm64_feat= ures[] =3D { .sign =3D FTR_UNSIGNED, .field_pos =3D ID_AA64ISAR1_EL1_DPB_SHIFT, .field_width =3D 4, - .min_field_value =3D 2, + .min_field_value =3D ID_AA64ISAR1_EL1_DPB_DPB2, }, #endif #ifdef CONFIG_ARM64_SVE @@ -2437,7 +2437,7 @@ static const struct arm64_cpu_capabilities arm64_feat= ures[] =3D { .sign =3D FTR_UNSIGNED, .field_pos =3D ID_AA64MMFR2_EL1_FWB_SHIFT, .field_width =3D 4, - .min_field_value =3D 1, + .min_field_value =3D ID_AA64MMFR2_EL1_FWB_IMP, .matches =3D has_cpuid_feature, }, { @@ -2448,7 +2448,7 @@ static const struct arm64_cpu_capabilities arm64_feat= ures[] =3D { .sign =3D FTR_UNSIGNED, .field_pos =3D ID_AA64MMFR2_EL1_TTL_SHIFT, .field_width =3D 4, - .min_field_value =3D 1, + .min_field_value =3D ID_AA64MMFR2_EL1_TTL_IMP, .matches =3D has_cpuid_feature, }, { @@ -2478,7 +2478,7 @@ static const struct arm64_cpu_capabilities arm64_feat= ures[] =3D { .sign =3D FTR_UNSIGNED, .field_pos =3D ID_AA64MMFR1_EL1_HAFDBS_SHIFT, .field_width =3D 4, - .min_field_value =3D 2, + .min_field_value =3D ID_AA64MMFR1_EL1_HAFDBS_DBM, .matches =3D has_hw_dbm, .cpu_enable =3D cpu_enable_hw_dbm, }, @@ -2491,7 +2491,7 @@ static const struct arm64_cpu_capabilities arm64_feat= ures[] =3D { .sys_reg =3D SYS_ID_AA64ISAR0_EL1, .field_pos =3D ID_AA64ISAR0_EL1_CRC32_SHIFT, .field_width =3D 4, - .min_field_value =3D 1, + .min_field_value =3D ID_AA64ISAR0_EL1_CRC32_IMP, }, { .desc =3D "Speculative Store Bypassing Safe (SSBS)", @@ -2514,7 +2514,7 @@ static const struct arm64_cpu_capabilities arm64_feat= ures[] =3D { .sign =3D FTR_UNSIGNED, .field_pos =3D ID_AA64MMFR2_EL1_CnP_SHIFT, .field_width =3D 4, - .min_field_value =3D 1, + .min_field_value =3D ID_AA64MMFR2_EL1_CnP_IMP, .cpu_enable =3D cpu_enable_cnp, }, #endif @@ -2527,7 +2527,7 @@ static const struct arm64_cpu_capabilities arm64_feat= ures[] =3D { .field_pos =3D ID_AA64ISAR1_EL1_SB_SHIFT, .field_width =3D 4, .sign =3D FTR_UNSIGNED, - .min_field_value =3D 1, + .min_field_value =3D ID_AA64ISAR1_EL1_SB_IMP, }, #ifdef CONFIG_ARM64_PTR_AUTH { @@ -2636,7 +2636,7 @@ static const struct arm64_cpu_capabilities arm64_feat= ures[] =3D { .field_width =3D 4, .field_pos =3D ID_AA64MMFR2_EL1_E0PD_SHIFT, .matches =3D has_cpuid_feature, - .min_field_value =3D 1, + .min_field_value =3D ID_AA64MMFR2_EL1_E0PD_IMP, .cpu_enable =3D cpu_enable_e0pd, }, #endif @@ -2649,7 +2649,7 @@ static const struct arm64_cpu_capabilities arm64_feat= ures[] =3D { .field_pos =3D ID_AA64ISAR0_EL1_RNDR_SHIFT, .field_width =3D 4, .sign =3D FTR_UNSIGNED, - .min_field_value =3D 1, + .min_field_value =3D ID_AA64ISAR0_EL1_RNDR_IMP, }, #ifdef CONFIG_ARM64_BTI { @@ -2703,7 +2703,7 @@ static const struct arm64_cpu_capabilities arm64_feat= ures[] =3D { .field_pos =3D ID_AA64ISAR1_EL1_LRCPC_SHIFT, .field_width =3D 4, .matches =3D has_cpuid_feature, - .min_field_value =3D 1, + .min_field_value =3D ID_AA64ISAR1_EL1_LRCPC_IMP, }, #ifdef CONFIG_ARM64_SME { --=20 2.30.2 From nobody Sat Apr 11 13:07:33 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id EF5CAC6FD1A for ; Mon, 6 Mar 2023 22:20:54 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230075AbjCFWUx (ORCPT ); Mon, 6 Mar 2023 17:20:53 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:47420 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229638AbjCFWUq (ORCPT ); Mon, 6 Mar 2023 17:20:46 -0500 Received: from dfw.source.kernel.org (dfw.source.kernel.org [IPv6:2604:1380:4641:c500::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 069756C88F for ; Mon, 6 Mar 2023 14:20:44 -0800 (PST) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id 892D060F60 for ; Mon, 6 Mar 2023 22:20:43 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 8B32AC433A0; Mon, 6 Mar 2023 22:20:41 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1678141243; bh=E+3ApSAAjKRZFTXy1lr7SjpFnM5CKJ2ooFUGc9JA2I4=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=B/9hOsCJWR/uyCEQQv6g3cKBuIGYjYniv6beVPtycKXs86sBl9kZ+U7SNQSTMBIaP /lsc3o5UMTZ/V47Rrw6B42X9cWVak9ounlf0mhnk9Ksbh5ddf/ShPgV6M+mTse0lOM 3UrxV/RqSoEQpWbQUc6RTUtL61j0GVSXbIVfFWSQyByihmJmu2qQkm4zWhGxEEx643 OVjiH1GDZTK8PTsT9nUsSmthqec3hurSaRNStE43gQhmAHQ/66Hs9HWwnN+Y/RHQUg 2vXbvurCk2E87nRQzjiDQpzhgsRB1OcEqgwu84wsH6luxbiELeKhvP/c6+lIHPHHER MnSV4LwMVu3Ug== From: Mark Brown Date: Mon, 06 Mar 2023 22:20:25 +0000 Subject: [PATCH 3/3] arm64/cpufeature: Use helper macro to specify ID register for capabilites MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20230303-arm64-cpufeature-helpers-v1-3-b16cf36acaea@kernel.org> References: <20230303-arm64-cpufeature-helpers-v1-0-b16cf36acaea@kernel.org> In-Reply-To: <20230303-arm64-cpufeature-helpers-v1-0-b16cf36acaea@kernel.org> To: Catalin Marinas , Will Deacon Cc: Suzuki K Poulose , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Mark Brown X-Mailer: b4 0.13-dev-bd1bf X-Developer-Signature: v=1; a=openpgp-sha256; l=20045; i=broonie@kernel.org; h=from:subject:message-id; bh=E+3ApSAAjKRZFTXy1lr7SjpFnM5CKJ2ooFUGc9JA2I4=; b=owEBbQGS/pANAwAKASTWi3JdVIfQAcsmYgBkBmczkdKkDFkpRR7COVvyz6rGXQ/Q+ufifxOqIm1C z14UUuKJATMEAAEKAB0WIQSt5miqZ1cYtZ/in+ok1otyXVSH0AUCZAZnMwAKCRAk1otyXVSH0ITdB/ 43cSSO0ASBGU8p1XcaLwIEPMUl+zrDjVQoxjXH8G30G6BRSzGGwJgvVFwwKThUNN+oYBgUO1Xh+vDp JD0yNwkLMKCx3/EB3Us9K/Oft9wrkR1qKrVEkhGw2OISJbJk1Qr2JNYGlK0kUa3xut0yAYErmAmHSp t6L2qjk+YAJmrQovF3cPrpE+ebPcyrA6XC4nexoxqY3uX5Je3/Ln7/Fwlo7gfKxh7i4njX2lxf+RvR EYOURHPh4qgrxMFuyhALDPhPB20QryZcH5+RycVJF2sTVqmsVk0NcF7XrTh97XbDnHk6ltpPbMz49B Jjkra32aScvjZPuxovcP3EdkC0mVIn X-Developer-Key: i=broonie@kernel.org; a=openpgp; fpr=3F2568AAC26998F9E813A1C5C3F436CA30F5D8EB Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org When defining which value to look for in a system register field we currently manually specify the register, field shift, width and sign and the value to look for. This opens the potential for error with for example the wrong field width or sign being specified, an enumeration value for a different similarly named field or letting something be initialised to 0. Since we now generate defines for all the ID registers we now have named constants for all of these things generated from the system register description, meaning that we can generate initialisation for all the fields used in matching from a minimal specification of register, field and match value. This is both shorter and eliminates or makes build failures several potential errors. No change in the generated binary. Signed-off-by: Mark Brown --- arch/arm64/kernel/cpufeature.c | 245 ++++++++-----------------------------= ---- 1 file changed, 44 insertions(+), 201 deletions(-) diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c index 1002ac437e8b..e25cb8bc60f6 100644 --- a/arch/arm64/kernel/cpufeature.c +++ b/arch/arm64/kernel/cpufeature.c @@ -2213,22 +2213,14 @@ static const struct arm64_cpu_capabilities arm64_fe= atures[] =3D { .capability =3D ARM64_HAS_GIC_CPUIF_SYSREGS, .type =3D ARM64_CPUCAP_STRICT_BOOT_CPU_FEATURE, .matches =3D has_useable_gicv3_cpuif, - .sys_reg =3D SYS_ID_AA64PFR0_EL1, - .field_pos =3D ID_AA64PFR0_EL1_GIC_SHIFT, - .field_width =3D 4, - .sign =3D FTR_UNSIGNED, - .min_field_value =3D ID_AA64PFR0_EL1_GIC_IMP, + ARM64_CPUID_FIELDS(ID_AA64PFR0_EL1, GIC, IMP) }, { .desc =3D "Enhanced Counter Virtualization", .capability =3D ARM64_HAS_ECV, .type =3D ARM64_CPUCAP_SYSTEM_FEATURE, .matches =3D has_cpuid_feature, - .sys_reg =3D SYS_ID_AA64MMFR0_EL1, - .field_pos =3D ID_AA64MMFR0_EL1_ECV_SHIFT, - .field_width =3D 4, - .sign =3D FTR_UNSIGNED, - .min_field_value =3D ID_AA64MMFR0_EL1_ECV_IMP, + ARM64_CPUID_FIELDS(ID_AA64MMFR0_EL1, ECV, IMP) }, #ifdef CONFIG_ARM64_PAN { @@ -2236,12 +2228,8 @@ static const struct arm64_cpu_capabilities arm64_fea= tures[] =3D { .capability =3D ARM64_HAS_PAN, .type =3D ARM64_CPUCAP_SYSTEM_FEATURE, .matches =3D has_cpuid_feature, - .sys_reg =3D SYS_ID_AA64MMFR1_EL1, - .field_pos =3D ID_AA64MMFR1_EL1_PAN_SHIFT, - .field_width =3D 4, - .sign =3D FTR_UNSIGNED, - .min_field_value =3D ID_AA64MMFR1_EL1_PAN_IMP, .cpu_enable =3D cpu_enable_pan, + ARM64_CPUID_FIELDS(ID_AA64MMFR1_EL1, PAN, IMP) }, #endif /* CONFIG_ARM64_PAN */ #ifdef CONFIG_ARM64_EPAN @@ -2250,11 +2238,7 @@ static const struct arm64_cpu_capabilities arm64_fea= tures[] =3D { .capability =3D ARM64_HAS_EPAN, .type =3D ARM64_CPUCAP_SYSTEM_FEATURE, .matches =3D has_cpuid_feature, - .sys_reg =3D SYS_ID_AA64MMFR1_EL1, - .field_pos =3D ID_AA64MMFR1_EL1_PAN_SHIFT, - .field_width =3D 4, - .sign =3D FTR_UNSIGNED, - .min_field_value =3D ID_AA64MMFR1_EL1_PAN_PAN3, + ARM64_CPUID_FIELDS(ID_AA64MMFR1_EL1, PAN, PAN3) }, #endif /* CONFIG_ARM64_EPAN */ #ifdef CONFIG_ARM64_LSE_ATOMICS @@ -2263,11 +2247,7 @@ static const struct arm64_cpu_capabilities arm64_fea= tures[] =3D { .capability =3D ARM64_HAS_LSE_ATOMICS, .type =3D ARM64_CPUCAP_SYSTEM_FEATURE, .matches =3D has_cpuid_feature, - .sys_reg =3D SYS_ID_AA64ISAR0_EL1, - .field_pos =3D ID_AA64ISAR0_EL1_ATOMIC_SHIFT, - .field_width =3D 4, - .sign =3D FTR_UNSIGNED, - .min_field_value =3D ID_AA64ISAR0_EL1_ATOMIC_IMP, + ARM64_CPUID_FIELDS(ID_AA64ISAR0_EL1, ATOMIC, IMP) }, #endif /* CONFIG_ARM64_LSE_ATOMICS */ { @@ -2288,21 +2268,13 @@ static const struct arm64_cpu_capabilities arm64_fe= atures[] =3D { .capability =3D ARM64_HAS_NESTED_VIRT, .type =3D ARM64_CPUCAP_SYSTEM_FEATURE, .matches =3D has_nested_virt_support, - .sys_reg =3D SYS_ID_AA64MMFR2_EL1, - .sign =3D FTR_UNSIGNED, - .field_pos =3D ID_AA64MMFR2_EL1_NV_SHIFT, - .field_width =3D 4, - .min_field_value =3D ID_AA64MMFR2_EL1_NV_IMP, + ARM64_CPUID_FIELDS(ID_AA64MMFR2_EL1, NV, IMP) }, { .capability =3D ARM64_HAS_32BIT_EL0_DO_NOT_USE, .type =3D ARM64_CPUCAP_SYSTEM_FEATURE, .matches =3D has_32bit_el0, - .sys_reg =3D SYS_ID_AA64PFR0_EL1, - .sign =3D FTR_UNSIGNED, - .field_pos =3D ID_AA64PFR0_EL1_EL0_SHIFT, - .field_width =3D 4, - .min_field_value =3D ID_AA64PFR0_EL1_ELx_32BIT_64BIT, + ARM64_CPUID_FIELDS(ID_AA64PFR0_EL1, EL0, AARCH32) }, #ifdef CONFIG_KVM { @@ -2310,11 +2282,7 @@ static const struct arm64_cpu_capabilities arm64_fea= tures[] =3D { .capability =3D ARM64_HAS_32BIT_EL1, .type =3D ARM64_CPUCAP_SYSTEM_FEATURE, .matches =3D has_cpuid_feature, - .sys_reg =3D SYS_ID_AA64PFR0_EL1, - .sign =3D FTR_UNSIGNED, - .field_pos =3D ID_AA64PFR0_EL1_EL1_SHIFT, - .field_width =3D 4, - .min_field_value =3D ID_AA64PFR0_EL1_ELx_32BIT_64BIT, + ARM64_CPUID_FIELDS(ID_AA64PFR0_EL1, EL1, AARCH32) }, { .desc =3D "Protected KVM", @@ -2327,17 +2295,14 @@ static const struct arm64_cpu_capabilities arm64_fe= atures[] =3D { .desc =3D "Kernel page table isolation (KPTI)", .capability =3D ARM64_UNMAP_KERNEL_AT_EL0, .type =3D ARM64_CPUCAP_BOOT_RESTRICTED_CPU_LOCAL_FEATURE, + .cpu_enable =3D kpti_install_ng_mappings, + .matches =3D unmap_kernel_at_el0, /* * The ID feature fields below are used to indicate that * the CPU doesn't need KPTI. See unmap_kernel_at_el0 for * more details. */ - .sys_reg =3D SYS_ID_AA64PFR0_EL1, - .field_pos =3D ID_AA64PFR0_EL1_CSV3_SHIFT, - .field_width =3D 4, - .min_field_value =3D ID_AA64PFR0_EL1_CSV3_IMP, - .matches =3D unmap_kernel_at_el0, - .cpu_enable =3D kpti_install_ng_mappings, + ARM64_CPUID_FIELDS(ID_AA64PFR0_EL1, CSV3, IMP) }, { /* FP/SIMD is not implemented */ @@ -2352,21 +2317,14 @@ static const struct arm64_cpu_capabilities arm64_fe= atures[] =3D { .capability =3D ARM64_HAS_DCPOP, .type =3D ARM64_CPUCAP_SYSTEM_FEATURE, .matches =3D has_cpuid_feature, - .sys_reg =3D SYS_ID_AA64ISAR1_EL1, - .field_pos =3D ID_AA64ISAR1_EL1_DPB_SHIFT, - .field_width =3D 4, - .min_field_value =3D ID_AA64ISAR1_EL1_DPB_IMP, + ARM64_CPUID_FIELDS(ID_AA64ISAR1_EL1, DPB, IMP) }, { .desc =3D "Data cache clean to Point of Deep Persistence", .capability =3D ARM64_HAS_DCPODP, .type =3D ARM64_CPUCAP_SYSTEM_FEATURE, .matches =3D has_cpuid_feature, - .sys_reg =3D SYS_ID_AA64ISAR1_EL1, - .sign =3D FTR_UNSIGNED, - .field_pos =3D ID_AA64ISAR1_EL1_DPB_SHIFT, - .field_width =3D 4, - .min_field_value =3D ID_AA64ISAR1_EL1_DPB_DPB2, + ARM64_CPUID_FIELDS(ID_AA64ISAR1_EL1, DPB, DPB2) }, #endif #ifdef CONFIG_ARM64_SVE @@ -2374,13 +2332,9 @@ static const struct arm64_cpu_capabilities arm64_fea= tures[] =3D { .desc =3D "Scalable Vector Extension", .type =3D ARM64_CPUCAP_SYSTEM_FEATURE, .capability =3D ARM64_SVE, - .sys_reg =3D SYS_ID_AA64PFR0_EL1, - .sign =3D FTR_UNSIGNED, - .field_pos =3D ID_AA64PFR0_EL1_SVE_SHIFT, - .field_width =3D 4, - .min_field_value =3D ID_AA64PFR0_EL1_SVE_IMP, - .matches =3D has_cpuid_feature, .cpu_enable =3D sve_kernel_enable, + .matches =3D has_cpuid_feature, + ARM64_CPUID_FIELDS(ID_AA64PFR0_EL1, SVE, IMP) }, #endif /* CONFIG_ARM64_SVE */ #ifdef CONFIG_ARM64_RAS_EXTN @@ -2389,12 +2343,8 @@ static const struct arm64_cpu_capabilities arm64_fea= tures[] =3D { .capability =3D ARM64_HAS_RAS_EXTN, .type =3D ARM64_CPUCAP_SYSTEM_FEATURE, .matches =3D has_cpuid_feature, - .sys_reg =3D SYS_ID_AA64PFR0_EL1, - .sign =3D FTR_UNSIGNED, - .field_pos =3D ID_AA64PFR0_EL1_RAS_SHIFT, - .field_width =3D 4, - .min_field_value =3D ID_AA64PFR0_EL1_RAS_IMP, .cpu_enable =3D cpu_clear_disr, + ARM64_CPUID_FIELDS(ID_AA64PFR0_EL1, RAS, IMP) }, #endif /* CONFIG_ARM64_RAS_EXTN */ #ifdef CONFIG_ARM64_AMU_EXTN @@ -2408,12 +2358,8 @@ static const struct arm64_cpu_capabilities arm64_fea= tures[] =3D { .capability =3D ARM64_HAS_AMU_EXTN, .type =3D ARM64_CPUCAP_WEAK_LOCAL_CPU_FEATURE, .matches =3D has_amu, - .sys_reg =3D SYS_ID_AA64PFR0_EL1, - .sign =3D FTR_UNSIGNED, - .field_pos =3D ID_AA64PFR0_EL1_AMU_SHIFT, - .field_width =3D 4, - .min_field_value =3D ID_AA64PFR0_EL1_AMU_IMP, .cpu_enable =3D cpu_amu_enable, + ARM64_CPUID_FIELDS(ID_AA64PFR0_EL1, AMU, IMP) }, #endif /* CONFIG_ARM64_AMU_EXTN */ { @@ -2433,34 +2379,22 @@ static const struct arm64_cpu_capabilities arm64_fe= atures[] =3D { .desc =3D "Stage-2 Force Write-Back", .type =3D ARM64_CPUCAP_SYSTEM_FEATURE, .capability =3D ARM64_HAS_STAGE2_FWB, - .sys_reg =3D SYS_ID_AA64MMFR2_EL1, - .sign =3D FTR_UNSIGNED, - .field_pos =3D ID_AA64MMFR2_EL1_FWB_SHIFT, - .field_width =3D 4, - .min_field_value =3D ID_AA64MMFR2_EL1_FWB_IMP, .matches =3D has_cpuid_feature, + ARM64_CPUID_FIELDS(ID_AA64MMFR2_EL1, FWB, IMP) }, { .desc =3D "ARMv8.4 Translation Table Level", .type =3D ARM64_CPUCAP_SYSTEM_FEATURE, .capability =3D ARM64_HAS_ARMv8_4_TTL, - .sys_reg =3D SYS_ID_AA64MMFR2_EL1, - .sign =3D FTR_UNSIGNED, - .field_pos =3D ID_AA64MMFR2_EL1_TTL_SHIFT, - .field_width =3D 4, - .min_field_value =3D ID_AA64MMFR2_EL1_TTL_IMP, .matches =3D has_cpuid_feature, + ARM64_CPUID_FIELDS(ID_AA64MMFR2_EL1, TTL, IMP) }, { .desc =3D "TLB range maintenance instructions", .capability =3D ARM64_HAS_TLB_RANGE, .type =3D ARM64_CPUCAP_SYSTEM_FEATURE, .matches =3D has_cpuid_feature, - .sys_reg =3D SYS_ID_AA64ISAR0_EL1, - .field_pos =3D ID_AA64ISAR0_EL1_TLB_SHIFT, - .field_width =3D 4, - .sign =3D FTR_UNSIGNED, - .min_field_value =3D ID_AA64ISAR0_EL1_TLB_RANGE, + ARM64_CPUID_FIELDS(ID_AA64ISAR0_EL1, TLB, RANGE) }, #ifdef CONFIG_ARM64_HW_AFDBM { @@ -2474,13 +2408,9 @@ static const struct arm64_cpu_capabilities arm64_fea= tures[] =3D { */ .type =3D ARM64_CPUCAP_WEAK_LOCAL_CPU_FEATURE, .capability =3D ARM64_HW_DBM, - .sys_reg =3D SYS_ID_AA64MMFR1_EL1, - .sign =3D FTR_UNSIGNED, - .field_pos =3D ID_AA64MMFR1_EL1_HAFDBS_SHIFT, - .field_width =3D 4, - .min_field_value =3D ID_AA64MMFR1_EL1_HAFDBS_DBM, .matches =3D has_hw_dbm, .cpu_enable =3D cpu_enable_hw_dbm, + ARM64_CPUID_FIELDS(ID_AA64MMFR1_EL1, HAFDBS, DBM) }, #endif { @@ -2488,21 +2418,14 @@ static const struct arm64_cpu_capabilities arm64_fe= atures[] =3D { .capability =3D ARM64_HAS_CRC32, .type =3D ARM64_CPUCAP_SYSTEM_FEATURE, .matches =3D has_cpuid_feature, - .sys_reg =3D SYS_ID_AA64ISAR0_EL1, - .field_pos =3D ID_AA64ISAR0_EL1_CRC32_SHIFT, - .field_width =3D 4, - .min_field_value =3D ID_AA64ISAR0_EL1_CRC32_IMP, + ARM64_CPUID_FIELDS(ID_AA64ISAR0_EL1, CRC32, IMP) }, { .desc =3D "Speculative Store Bypassing Safe (SSBS)", .capability =3D ARM64_SSBS, .type =3D ARM64_CPUCAP_SYSTEM_FEATURE, .matches =3D has_cpuid_feature, - .sys_reg =3D SYS_ID_AA64PFR1_EL1, - .field_pos =3D ID_AA64PFR1_EL1_SSBS_SHIFT, - .field_width =3D 4, - .sign =3D FTR_UNSIGNED, - .min_field_value =3D ID_AA64PFR1_EL1_SSBS_IMP, + ARM64_CPUID_FIELDS(ID_AA64PFR1_EL1, SSBS, IMP) }, #ifdef CONFIG_ARM64_CNP { @@ -2510,12 +2433,8 @@ static const struct arm64_cpu_capabilities arm64_fea= tures[] =3D { .capability =3D ARM64_HAS_CNP, .type =3D ARM64_CPUCAP_SYSTEM_FEATURE, .matches =3D has_useable_cnp, - .sys_reg =3D SYS_ID_AA64MMFR2_EL1, - .sign =3D FTR_UNSIGNED, - .field_pos =3D ID_AA64MMFR2_EL1_CnP_SHIFT, - .field_width =3D 4, - .min_field_value =3D ID_AA64MMFR2_EL1_CnP_IMP, .cpu_enable =3D cpu_enable_cnp, + ARM64_CPUID_FIELDS(ID_AA64MMFR2_EL1, CnP, IMP) }, #endif { @@ -2523,45 +2442,29 @@ static const struct arm64_cpu_capabilities arm64_fe= atures[] =3D { .capability =3D ARM64_HAS_SB, .type =3D ARM64_CPUCAP_SYSTEM_FEATURE, .matches =3D has_cpuid_feature, - .sys_reg =3D SYS_ID_AA64ISAR1_EL1, - .field_pos =3D ID_AA64ISAR1_EL1_SB_SHIFT, - .field_width =3D 4, - .sign =3D FTR_UNSIGNED, - .min_field_value =3D ID_AA64ISAR1_EL1_SB_IMP, + ARM64_CPUID_FIELDS(ID_AA64ISAR1_EL1, SB, IMP) }, #ifdef CONFIG_ARM64_PTR_AUTH { .desc =3D "Address authentication (architected QARMA5 algorithm)", .capability =3D ARM64_HAS_ADDRESS_AUTH_ARCH_QARMA5, .type =3D ARM64_CPUCAP_BOOT_CPU_FEATURE, - .sys_reg =3D SYS_ID_AA64ISAR1_EL1, - .sign =3D FTR_UNSIGNED, - .field_pos =3D ID_AA64ISAR1_EL1_APA_SHIFT, - .field_width =3D 4, - .min_field_value =3D ID_AA64ISAR1_EL1_APA_PAuth, .matches =3D has_address_auth_cpucap, + ARM64_CPUID_FIELDS(ID_AA64ISAR1_EL1, APA, PAuth) }, { .desc =3D "Address authentication (architected QARMA3 algorithm)", .capability =3D ARM64_HAS_ADDRESS_AUTH_ARCH_QARMA3, .type =3D ARM64_CPUCAP_BOOT_CPU_FEATURE, - .sys_reg =3D SYS_ID_AA64ISAR2_EL1, - .sign =3D FTR_UNSIGNED, - .field_pos =3D ID_AA64ISAR2_EL1_APA3_SHIFT, - .field_width =3D 4, - .min_field_value =3D ID_AA64ISAR2_EL1_APA3_PAuth, .matches =3D has_address_auth_cpucap, + ARM64_CPUID_FIELDS(ID_AA64ISAR2_EL1, APA3, PAuth) }, { .desc =3D "Address authentication (IMP DEF algorithm)", .capability =3D ARM64_HAS_ADDRESS_AUTH_IMP_DEF, .type =3D ARM64_CPUCAP_BOOT_CPU_FEATURE, - .sys_reg =3D SYS_ID_AA64ISAR1_EL1, - .sign =3D FTR_UNSIGNED, - .field_pos =3D ID_AA64ISAR1_EL1_API_SHIFT, - .field_width =3D 4, - .min_field_value =3D ID_AA64ISAR1_EL1_API_PAuth, .matches =3D has_address_auth_cpucap, + ARM64_CPUID_FIELDS(ID_AA64ISAR1_EL1, API, PAuth) }, { .capability =3D ARM64_HAS_ADDRESS_AUTH, @@ -2572,34 +2475,22 @@ static const struct arm64_cpu_capabilities arm64_fe= atures[] =3D { .desc =3D "Generic authentication (architected QARMA5 algorithm)", .capability =3D ARM64_HAS_GENERIC_AUTH_ARCH_QARMA5, .type =3D ARM64_CPUCAP_SYSTEM_FEATURE, - .sys_reg =3D SYS_ID_AA64ISAR1_EL1, - .sign =3D FTR_UNSIGNED, - .field_pos =3D ID_AA64ISAR1_EL1_GPA_SHIFT, - .field_width =3D 4, - .min_field_value =3D ID_AA64ISAR1_EL1_GPA_IMP, .matches =3D has_cpuid_feature, + ARM64_CPUID_FIELDS(ID_AA64ISAR1_EL1, GPA, IMP) }, { .desc =3D "Generic authentication (architected QARMA3 algorithm)", .capability =3D ARM64_HAS_GENERIC_AUTH_ARCH_QARMA3, .type =3D ARM64_CPUCAP_SYSTEM_FEATURE, - .sys_reg =3D SYS_ID_AA64ISAR2_EL1, - .sign =3D FTR_UNSIGNED, - .field_pos =3D ID_AA64ISAR2_EL1_GPA3_SHIFT, - .field_width =3D 4, - .min_field_value =3D ID_AA64ISAR2_EL1_GPA3_IMP, .matches =3D has_cpuid_feature, + ARM64_CPUID_FIELDS(ID_AA64ISAR2_EL1, GPA3, IMP) }, { .desc =3D "Generic authentication (IMP DEF algorithm)", .capability =3D ARM64_HAS_GENERIC_AUTH_IMP_DEF, .type =3D ARM64_CPUCAP_SYSTEM_FEATURE, - .sys_reg =3D SYS_ID_AA64ISAR1_EL1, - .sign =3D FTR_UNSIGNED, - .field_pos =3D ID_AA64ISAR1_EL1_GPI_SHIFT, - .field_width =3D 4, - .min_field_value =3D ID_AA64ISAR1_EL1_GPI_IMP, .matches =3D has_cpuid_feature, + ARM64_CPUID_FIELDS(ID_AA64ISAR1_EL1, GPI, IMP) }, { .capability =3D ARM64_HAS_GENERIC_AUTH, @@ -2631,13 +2522,9 @@ static const struct arm64_cpu_capabilities arm64_fea= tures[] =3D { .desc =3D "E0PD", .capability =3D ARM64_HAS_E0PD, .type =3D ARM64_CPUCAP_SYSTEM_FEATURE, - .sys_reg =3D SYS_ID_AA64MMFR2_EL1, - .sign =3D FTR_UNSIGNED, - .field_width =3D 4, - .field_pos =3D ID_AA64MMFR2_EL1_E0PD_SHIFT, - .matches =3D has_cpuid_feature, - .min_field_value =3D ID_AA64MMFR2_EL1_E0PD_IMP, .cpu_enable =3D cpu_enable_e0pd, + .matches =3D has_cpuid_feature, + ARM64_CPUID_FIELDS(ID_AA64MMFR2_EL1, E0PD, IMP) }, #endif { @@ -2645,11 +2532,7 @@ static const struct arm64_cpu_capabilities arm64_fea= tures[] =3D { .capability =3D ARM64_HAS_RNG, .type =3D ARM64_CPUCAP_SYSTEM_FEATURE, .matches =3D has_cpuid_feature, - .sys_reg =3D SYS_ID_AA64ISAR0_EL1, - .field_pos =3D ID_AA64ISAR0_EL1_RNDR_SHIFT, - .field_width =3D 4, - .sign =3D FTR_UNSIGNED, - .min_field_value =3D ID_AA64ISAR0_EL1_RNDR_IMP, + ARM64_CPUID_FIELDS(ID_AA64ISAR0_EL1, RNDR, IMP) }, #ifdef CONFIG_ARM64_BTI { @@ -2662,10 +2545,7 @@ static const struct arm64_cpu_capabilities arm64_fea= tures[] =3D { #endif .matches =3D has_cpuid_feature, .cpu_enable =3D bti_enable, - .sys_reg =3D SYS_ID_AA64PFR1_EL1, - .field_pos =3D ID_AA64PFR1_EL1_BT_SHIFT, - .field_width =3D 4, - .min_field_value =3D ID_AA64PFR1_EL1_BT_IMP, + ARM64_CPUID_FIELDS(ID_AA64PFR1_EL1, BT, IMP) .sign =3D FTR_UNSIGNED, }, #endif @@ -2675,109 +2555,72 @@ static const struct arm64_cpu_capabilities arm64_f= eatures[] =3D { .capability =3D ARM64_MTE, .type =3D ARM64_CPUCAP_STRICT_BOOT_CPU_FEATURE, .matches =3D has_cpuid_feature, - .sys_reg =3D SYS_ID_AA64PFR1_EL1, - .field_pos =3D ID_AA64PFR1_EL1_MTE_SHIFT, - .field_width =3D 4, - .min_field_value =3D ID_AA64PFR1_EL1_MTE_MTE2, - .sign =3D FTR_UNSIGNED, .cpu_enable =3D cpu_enable_mte, + ARM64_CPUID_FIELDS(ID_AA64PFR1_EL1, MTE, MTE2) }, { .desc =3D "Asymmetric MTE Tag Check Fault", .capability =3D ARM64_MTE_ASYMM, .type =3D ARM64_CPUCAP_BOOT_CPU_FEATURE, .matches =3D has_cpuid_feature, - .sys_reg =3D SYS_ID_AA64PFR1_EL1, - .field_pos =3D ID_AA64PFR1_EL1_MTE_SHIFT, - .field_width =3D 4, - .min_field_value =3D ID_AA64PFR1_EL1_MTE_MTE3, - .sign =3D FTR_UNSIGNED, + ARM64_CPUID_FIELDS(ID_AA64PFR1_EL1, MTE, MTE3) }, #endif /* CONFIG_ARM64_MTE */ { .desc =3D "RCpc load-acquire (LDAPR)", .capability =3D ARM64_HAS_LDAPR, .type =3D ARM64_CPUCAP_SYSTEM_FEATURE, - .sys_reg =3D SYS_ID_AA64ISAR1_EL1, - .sign =3D FTR_UNSIGNED, - .field_pos =3D ID_AA64ISAR1_EL1_LRCPC_SHIFT, - .field_width =3D 4, .matches =3D has_cpuid_feature, - .min_field_value =3D ID_AA64ISAR1_EL1_LRCPC_IMP, + ARM64_CPUID_FIELDS(ID_AA64ISAR1_EL1, LRCPC, IMP) }, #ifdef CONFIG_ARM64_SME { .desc =3D "Scalable Matrix Extension", .type =3D ARM64_CPUCAP_SYSTEM_FEATURE, .capability =3D ARM64_SME, - .sys_reg =3D SYS_ID_AA64PFR1_EL1, - .sign =3D FTR_UNSIGNED, - .field_pos =3D ID_AA64PFR1_EL1_SME_SHIFT, - .field_width =3D 4, - .min_field_value =3D ID_AA64PFR1_EL1_SME_IMP, .matches =3D has_cpuid_feature, .cpu_enable =3D sme_kernel_enable, + ARM64_CPUID_FIELDS(ID_AA64PFR1_EL1, SME, IMP) }, /* FA64 should be sorted after the base SME capability */ { .desc =3D "FA64", .type =3D ARM64_CPUCAP_SYSTEM_FEATURE, .capability =3D ARM64_SME_FA64, - .sys_reg =3D SYS_ID_AA64SMFR0_EL1, - .sign =3D FTR_UNSIGNED, - .field_pos =3D ID_AA64SMFR0_EL1_FA64_SHIFT, - .field_width =3D 1, - .min_field_value =3D ID_AA64SMFR0_EL1_FA64_IMP, .matches =3D has_cpuid_feature, .cpu_enable =3D fa64_kernel_enable, + ARM64_CPUID_FIELDS(ID_AA64SMFR0_EL1, FA64, IMP) }, { .desc =3D "SME2", .type =3D ARM64_CPUCAP_SYSTEM_FEATURE, .capability =3D ARM64_SME2, - .sys_reg =3D SYS_ID_AA64PFR1_EL1, - .sign =3D FTR_UNSIGNED, - .field_pos =3D ID_AA64PFR1_EL1_SME_SHIFT, - .field_width =3D ID_AA64PFR1_EL1_SME_WIDTH, - .min_field_value =3D ID_AA64PFR1_EL1_SME_SME2, .matches =3D has_cpuid_feature, .cpu_enable =3D sme2_kernel_enable, + ARM64_CPUID_FIELDS(ID_AA64PFR1_EL1, SME, SME2) }, #endif /* CONFIG_ARM64_SME */ { .desc =3D "WFx with timeout", .capability =3D ARM64_HAS_WFXT, .type =3D ARM64_CPUCAP_SYSTEM_FEATURE, - .sys_reg =3D SYS_ID_AA64ISAR2_EL1, - .sign =3D FTR_UNSIGNED, - .field_pos =3D ID_AA64ISAR2_EL1_WFxT_SHIFT, - .field_width =3D 4, - .matches =3D has_cpuid_feature, - .min_field_value =3D ID_AA64ISAR2_EL1_WFxT_IMP, + ARM64_CPUID_FIELDS(ID_AA64ISAR2_EL1, WFxT, IMP) }, { .desc =3D "Trap EL0 IMPLEMENTATION DEFINED functionality", .capability =3D ARM64_HAS_TIDCP1, .type =3D ARM64_CPUCAP_SYSTEM_FEATURE, - .sys_reg =3D SYS_ID_AA64MMFR1_EL1, - .sign =3D FTR_UNSIGNED, - .field_pos =3D ID_AA64MMFR1_EL1_TIDCP1_SHIFT, - .field_width =3D 4, - .min_field_value =3D ID_AA64MMFR1_EL1_TIDCP1_IMP, .matches =3D has_cpuid_feature, .cpu_enable =3D cpu_trap_el0_impdef, + ARM64_CPUID_FIELDS(ID_AA64MMFR1_EL1, TIDCP1, IMP) }, { .desc =3D "Data independent timing control (DIT)", .capability =3D ARM64_HAS_DIT, .type =3D ARM64_CPUCAP_SYSTEM_FEATURE, - .sys_reg =3D SYS_ID_AA64PFR0_EL1, - .sign =3D FTR_UNSIGNED, - .field_pos =3D ID_AA64PFR0_EL1_DIT_SHIFT, - .field_width =3D 4, - .min_field_value =3D ID_AA64PFR0_EL1_DIT_IMP, .matches =3D has_cpuid_feature, .cpu_enable =3D cpu_enable_dit, + ARM64_CPUID_FIELDS(ID_AA64PFR0_EL1, DIT, IMP) }, {}, }; --=20 2.30.2