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([172.25.112.68]) by fmsmga006.fm.intel.com with ESMTP; 01 Mar 2023 21:50:50 -0800 From: Xin Li To: linux-kernel@vger.kernel.org, x86@kernel.org, kvm@vger.kernel.org Cc: tglx@linutronix.de, mingo@redhat.com, bp@alien8.de, dave.hansen@linux.intel.com, hpa@zytor.com, peterz@infradead.org, andrew.cooper3@citrix.com, seanjc@google.com, pbonzini@redhat.com, ravi.v.shankar@intel.com Subject: [PATCH v4 27/34] x86/fred: allow single-step trap and NMI when starting a new thread Date: Wed, 1 Mar 2023 21:25:04 -0800 Message-Id: <20230302052511.1918-28-xin3.li@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230302052511.1918-1-xin3.li@intel.com> References: <20230302052511.1918-1-xin3.li@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: "H. Peter Anvin (Intel)" Allow single-step trap and NMI when starting a new thread, thus once the new thread returns to ring3, single-step trap and NMI are both enabled immediately. High-order 48 bits above the lowest 16 bit CS are discarded by the legacy IRET instruction, thus can be set unconditionally, even when FRED is not enabled. Signed-off-by: H. Peter Anvin (Intel) Tested-by: Shan Kang Signed-off-by: Xin Li --- arch/x86/include/asm/fred.h | 11 +++++++++++ arch/x86/kernel/process_64.c | 13 +++++++------ 2 files changed, 18 insertions(+), 6 deletions(-) diff --git a/arch/x86/include/asm/fred.h b/arch/x86/include/asm/fred.h index cd974edc8e8a..12449448e9bf 100644 --- a/arch/x86/include/asm/fred.h +++ b/arch/x86/include/asm/fred.h @@ -52,6 +52,14 @@ #define FRED_CSL_ALLOW_SINGLE_STEP _BITUL(25) #define FRED_CSL_INTERRUPT_SHADOW _BITUL(24) =20 +/* + * High-order 48 bits above the lowest 16 bit CS are discarded by the + * legacy IRET instruction, thus can be set unconditionally, even when + * FRED is not enabled. + */ +#define CSL_PROCESS_START \ + (FRED_CSL_ENABLE_NMI | FRED_CSL_ALLOW_SINGLE_STEP) + #ifndef __ASSEMBLY__ =20 #include @@ -115,6 +123,9 @@ void fred_setup_apic(void); #else #define cpu_init_fred_exceptions() BUG() #define fred_setup_apic() BUG() + +#define CSL_PROCESS_START 0 + #endif /* CONFIG_X86_FRED */ =20 #endif /* ASM_X86_FRED_H */ diff --git a/arch/x86/kernel/process_64.c b/arch/x86/kernel/process_64.c index ff6594dbea4a..b23850352e7d 100644 --- a/arch/x86/kernel/process_64.c +++ b/arch/x86/kernel/process_64.c @@ -55,6 +55,7 @@ #include #include #include +#include #ifdef CONFIG_IA32_EMULATION /* Not included via unistd.h */ #include @@ -506,7 +507,7 @@ void x86_gsbase_write_task(struct task_struct *task, un= signed long gsbase) static void start_thread_common(struct pt_regs *regs, unsigned long new_ip, unsigned long new_sp, - unsigned int _cs, unsigned int _ss, unsigned int _ds) + u16 _cs, u16 _ss, u16 _ds) { WARN_ON_ONCE(regs !=3D current_pt_regs()); =20 @@ -521,11 +522,11 @@ start_thread_common(struct pt_regs *regs, unsigned lo= ng new_ip, loadsegment(ds, _ds); load_gs_index(0); =20 - regs->ip =3D new_ip; - regs->sp =3D new_sp; - regs->cs =3D _cs; - regs->ss =3D _ss; - regs->flags =3D X86_EFLAGS_IF; + regs->ip =3D new_ip; + regs->sp =3D new_sp; + regs->csx =3D _cs | CSL_PROCESS_START; + regs->ssx =3D _ss; + regs->flags =3D X86_EFLAGS_IF | X86_EFLAGS_FIXED; } =20 void --=20 2.34.1