From nobody Sat Apr 11 07:07:34 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id F3BCFC7EE2F for ; Thu, 2 Mar 2023 05:51:29 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229952AbjCBFv1 (ORCPT ); Thu, 2 Mar 2023 00:51:27 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:44720 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229836AbjCBFu5 (ORCPT ); Thu, 2 Mar 2023 00:50:57 -0500 Received: from mga05.intel.com (mga05.intel.com [192.55.52.43]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 4C3D438EBF; Wed, 1 Mar 2023 21:50:54 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1677736255; x=1709272255; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=xePdNXHU682aUfMVCFmcmPRxw9pVvyjrZ2d9bkzRB0U=; b=CLzNobftOYhJIANZjkSdArN2/BUj79100PuNwX4FfDu8NNR4kxGLVrG1 7VLjyUn9C58UGE4eEzTk6URP+pkmaN8bQJFMOIsC17eeAjqRfCxOQE4Ey pHvLj0kTKonz7YPD1I/2xdVPm+/jxQVhi6lInv/GfbEX3pMN1rzBYW/lF 8QOYwVxzAPHODuynw9CzAPLxXrViMmGLmINM1FVnF/mQ5UVMRu018tUUb swq2sIPsa+iHlvIPELVmDJpFWNasxGWdPie47p9OvJU2SzNjrIl/1J1cU mTWZ4SVy8A2ASembyY+DXBodfYYPxkpWqk2lNBNJ/BiaqznB4LlWyhVTs A==; X-IronPort-AV: E=McAfee;i="6500,9779,10636"; a="420887123" X-IronPort-AV: E=Sophos;i="5.98,226,1673942400"; d="scan'208";a="420887123" Received: from fmsmga006.fm.intel.com ([10.253.24.20]) by fmsmga105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 01 Mar 2023 21:50:51 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10636"; a="920530896" X-IronPort-AV: E=Sophos;i="5.98,226,1673942400"; d="scan'208";a="920530896" Received: from unknown (HELO fred..) ([172.25.112.68]) by fmsmga006.fm.intel.com with ESMTP; 01 Mar 2023 21:50:47 -0800 From: Xin Li To: linux-kernel@vger.kernel.org, x86@kernel.org, kvm@vger.kernel.org Cc: tglx@linutronix.de, mingo@redhat.com, bp@alien8.de, dave.hansen@linux.intel.com, hpa@zytor.com, peterz@infradead.org, andrew.cooper3@citrix.com, seanjc@google.com, pbonzini@redhat.com, ravi.v.shankar@intel.com Subject: [PATCH v4 09/34] x86/cpu: add X86_CR4_FRED macro Date: Wed, 1 Mar 2023 21:24:46 -0800 Message-Id: <20230302052511.1918-10-xin3.li@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230302052511.1918-1-xin3.li@intel.com> References: <20230302052511.1918-1-xin3.li@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: "H. Peter Anvin (Intel)" Add X86_CR4_FRED macro for the FRED bit in %cr4. This bit should be a pinned bit, not to be changed after initialization. Signed-off-by: H. Peter Anvin (Intel) Tested-by: Shan Kang Signed-off-by: Xin Li --- arch/x86/include/uapi/asm/processor-flags.h | 2 ++ arch/x86/kernel/cpu/common.c | 11 ++++++++--- 2 files changed, 10 insertions(+), 3 deletions(-) diff --git a/arch/x86/include/uapi/asm/processor-flags.h b/arch/x86/include= /uapi/asm/processor-flags.h index c47cc7f2feeb..a90933f1ff41 100644 --- a/arch/x86/include/uapi/asm/processor-flags.h +++ b/arch/x86/include/uapi/asm/processor-flags.h @@ -132,6 +132,8 @@ #define X86_CR4_PKE _BITUL(X86_CR4_PKE_BIT) #define X86_CR4_CET_BIT 23 /* enable Control-flow Enforcement Technology = */ #define X86_CR4_CET _BITUL(X86_CR4_CET_BIT) +#define X86_CR4_FRED_BIT 32 /* enable FRED kernel entry */ +#define X86_CR4_FRED _BITULL(X86_CR4_FRED_BIT) =20 /* * x86-64 Task Priority Register, CR8 diff --git a/arch/x86/kernel/cpu/common.c b/arch/x86/kernel/cpu/common.c index 8cd4126d8253..e8cf6f4cfb52 100644 --- a/arch/x86/kernel/cpu/common.c +++ b/arch/x86/kernel/cpu/common.c @@ -412,10 +412,15 @@ static __always_inline void setup_umip(struct cpuinfo= _x86 *c) cr4_clear_bits(X86_CR4_UMIP); } =20 -/* These bits should not change their value after CPU init is finished. */ +/* + * These bits should not change their value after CPU init is finished. + * The explicit cast to unsigned long suppresses a warning on i386 for + * x86-64 only feature bits >=3D 32. + */ static const unsigned long cr4_pinned_mask =3D - X86_CR4_SMEP | X86_CR4_SMAP | X86_CR4_UMIP | - X86_CR4_FSGSBASE | X86_CR4_CET; + (unsigned long) + (X86_CR4_SMEP | X86_CR4_SMAP | X86_CR4_UMIP | + X86_CR4_FSGSBASE | X86_CR4_CET | X86_CR4_FRED); static DEFINE_STATIC_KEY_FALSE_RO(cr_pinning); static unsigned long cr4_pinned_bits __ro_after_init; =20 --=20 2.34.1