From nobody Wed Sep 10 02:01:35 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 68A1AC64ED6 for ; Wed, 1 Mar 2023 18:38:39 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230075AbjCASii (ORCPT ); Wed, 1 Mar 2023 13:38:38 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:45296 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229951AbjCASi0 (ORCPT ); Wed, 1 Mar 2023 13:38:26 -0500 Received: from mx.sberdevices.ru (mx.sberdevices.ru [45.89.227.171]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id DBAD27AA6; Wed, 1 Mar 2023 10:38:22 -0800 (PST) Received: from s-lin-edge02.sberdevices.ru (localhost [127.0.0.1]) by mx.sberdevices.ru (Postfix) with ESMTP id 86D815FD7A; Wed, 1 Mar 2023 21:38:20 +0300 (MSK) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sberdevices.ru; s=mail; t=1677695900; bh=Y1ClNeO/IfzDilO46T9zQGovTdnLJV+fYPRRx9cgGF0=; h=From:To:Subject:Date:Message-ID:MIME-Version:Content-Type; b=jvclV50n1aa0ob36vu2bBz8+7aTSjPGFmU0cT+kGnK/Jr4wcM2o9sJsfTv0LUh8Dk d7B0JnhsZuxu68Y4VN4zAPhhw2nVxiM4vVr7EG6naMPQZDcBeI8PQg6NBTGczTnNFw aYiJkOFACM5lUbVmlYfDMUWS8XtIi+tQDD8vcUjL8DggL7wBVtEhKP0xsOREUQ2ZoO ezSL0zuicDDt7nAPb1MHB/gfEb+47vAnCVXh91opTXEySGRUT7969oPPQLgIZBNCuW u9FeFZxu4CZyFeEZ6LDWixdlJAodz5L8NVIhPNf0nD8zj6ErKvBnQW/yJj4B2HQfwN DmJFM0jm3fLHQ== Received: from S-MS-EXCH01.sberdevices.ru (S-MS-EXCH01.sberdevices.ru [172.16.1.4]) by mx.sberdevices.ru (Postfix) with ESMTP; Wed, 1 Mar 2023 21:38:20 +0300 (MSK) From: Dmitry Rokosov To: , , , , , , , CC: , , , , , , , , Dmitry Rokosov Subject: [PATCH v9 2/5] clk: meson: a1: add Amlogic A1 PLL clock controller driver Date: Wed, 1 Mar 2023 21:37:56 +0300 Message-ID: <20230301183759.16163-3-ddrokosov@sberdevices.ru> X-Mailer: git-send-email 2.36.0 In-Reply-To: <20230301183759.16163-1-ddrokosov@sberdevices.ru> References: <20230301183759.16163-1-ddrokosov@sberdevices.ru> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Originating-IP: [172.16.1.6] X-ClientProxiedBy: S-MS-EXCH01.sberdevices.ru (172.16.1.4) To S-MS-EXCH01.sberdevices.ru (172.16.1.4) X-KSMG-Rule-ID: 4 X-KSMG-Message-Action: clean X-KSMG-AntiSpam-Status: not scanned, disabled by settings X-KSMG-AntiSpam-Interceptor-Info: not scanned X-KSMG-AntiPhishing: not scanned, disabled by settings X-KSMG-AntiVirus: Kaspersky Secure Mail Gateway, version 1.1.2.30, bases: 2023/03/01 14:15:00 #20905952 X-KSMG-AntiVirus-Status: Clean, skipped Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Introduce PLL clock controller for Amlogic A1 SoC family. Signed-off-by: Jian Hu Signed-off-by: Dmitry Rokosov --- drivers/clk/meson/Kconfig | 10 + drivers/clk/meson/Makefile | 1 + drivers/clk/meson/a1-pll.c | 365 +++++++++++++++++++++++++++++++++++++ drivers/clk/meson/a1-pll.h | 47 +++++ 4 files changed, 423 insertions(+) create mode 100644 drivers/clk/meson/a1-pll.c create mode 100644 drivers/clk/meson/a1-pll.h diff --git a/drivers/clk/meson/Kconfig b/drivers/clk/meson/Kconfig index fc002c155bc3..f56da2a4b000 100644 --- a/drivers/clk/meson/Kconfig +++ b/drivers/clk/meson/Kconfig @@ -99,6 +99,16 @@ config COMMON_CLK_AXG_AUDIO Support for the audio clock controller on AmLogic A113D devices, aka axg, Say Y if you want audio subsystem to work. =20 +config COMMON_CLK_A1_PLL + tristate "Meson A1 SoC PLL controller support" + depends on ARM64 + select COMMON_CLK_MESON_REGMAP + select COMMON_CLK_MESON_PLL + help + Support for the PLL clock controller on Amlogic A113L based + device, A1 SoC Family. Say Y if you want A1 PLL clock controller + to work. + config COMMON_CLK_G12A tristate "G12 and SM1 SoC clock controllers support" depends on ARM64 diff --git a/drivers/clk/meson/Makefile b/drivers/clk/meson/Makefile index 6eca2a406ee3..2f17f475a48f 100644 --- a/drivers/clk/meson/Makefile +++ b/drivers/clk/meson/Makefile @@ -16,6 +16,7 @@ obj-$(CONFIG_COMMON_CLK_MESON_VID_PLL_DIV) +=3D vid-pll-d= iv.o =20 obj-$(CONFIG_COMMON_CLK_AXG) +=3D axg.o axg-aoclk.o obj-$(CONFIG_COMMON_CLK_AXG_AUDIO) +=3D axg-audio.o +obj-$(CONFIG_COMMON_CLK_A1_PLL) +=3D a1-pll.o obj-$(CONFIG_COMMON_CLK_GXBB) +=3D gxbb.o gxbb-aoclk.o obj-$(CONFIG_COMMON_CLK_G12A) +=3D g12a.o g12a-aoclk.o obj-$(CONFIG_COMMON_CLK_MESON8B) +=3D meson8b.o meson8-ddr.o diff --git a/drivers/clk/meson/a1-pll.c b/drivers/clk/meson/a1-pll.c new file mode 100644 index 000000000000..c565f9b2a8dd --- /dev/null +++ b/drivers/clk/meson/a1-pll.c @@ -0,0 +1,365 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2019 Amlogic, Inc. All rights reserved. + * Author: Jian Hu + * + * Copyright (c) 2023, SberDevices. All Rights Reserved. + * Author: Dmitry Rokosov + */ + +#include +#include +#include +#include "meson-a1-clkc.h" +#include "a1-pll.h" +#include "clk-regmap.h" + +static struct clk_regmap fixed_pll_dco =3D { + .data =3D &(struct meson_clk_pll_data){ + .en =3D { + .reg_off =3D ANACTRL_FIXPLL_CTRL0, + .shift =3D 28, + .width =3D 1, + }, + .m =3D { + .reg_off =3D ANACTRL_FIXPLL_CTRL0, + .shift =3D 0, + .width =3D 8, + }, + .n =3D { + .reg_off =3D ANACTRL_FIXPLL_CTRL0, + .shift =3D 10, + .width =3D 5, + }, + .frac =3D { + .reg_off =3D ANACTRL_FIXPLL_CTRL1, + .shift =3D 0, + .width =3D 19, + }, + .l =3D { + .reg_off =3D ANACTRL_FIXPLL_STS, + .shift =3D 31, + .width =3D 1, + }, + .rst =3D { + .reg_off =3D ANACTRL_FIXPLL_CTRL0, + .shift =3D 29, + .width =3D 1, + }, + }, + .hw.init =3D &(struct clk_init_data){ + .name =3D "fixed_pll_dco", + .ops =3D &meson_clk_pll_ro_ops, + .parent_data =3D &(const struct clk_parent_data) { + .fw_name =3D "fixpll_in", + }, + .num_parents =3D 1, + }, +}; + +static struct clk_regmap fixed_pll =3D { + .data =3D &(struct clk_regmap_gate_data){ + .offset =3D ANACTRL_FIXPLL_CTRL0, + .bit_idx =3D 20, + }, + .hw.init =3D &(struct clk_init_data) { + .name =3D "fixed_pll", + .ops =3D &clk_regmap_gate_ops, + .parent_hws =3D (const struct clk_hw *[]) { + &fixed_pll_dco.hw + }, + .num_parents =3D 1, + /* + * It is enough that the fdiv leaf has critical flag, + * No critical or unused flag here. + */ + }, +}; + +static const struct pll_mult_range hifi_pll_mult_range =3D { + .min =3D 32, + .max =3D 64, +}; + +static const struct reg_sequence hifi_init_regs[] =3D { + { .reg =3D ANACTRL_HIFIPLL_CTRL1, .def =3D 0x01800000 }, + { .reg =3D ANACTRL_HIFIPLL_CTRL2, .def =3D 0x00001100 }, + { .reg =3D ANACTRL_HIFIPLL_CTRL3, .def =3D 0x100a1100 }, + { .reg =3D ANACTRL_HIFIPLL_CTRL4, .def =3D 0x00302000 }, + { .reg =3D ANACTRL_HIFIPLL_CTRL0, .def =3D 0x01f18440 }, +}; + +static struct clk_regmap hifi_pll =3D { + .data =3D &(struct meson_clk_pll_data){ + .en =3D { + .reg_off =3D ANACTRL_HIFIPLL_CTRL0, + .shift =3D 28, + .width =3D 1, + }, + .m =3D { + .reg_off =3D ANACTRL_HIFIPLL_CTRL0, + .shift =3D 0, + .width =3D 8, + }, + .n =3D { + .reg_off =3D ANACTRL_HIFIPLL_CTRL0, + .shift =3D 10, + .width =3D 5, + }, + .frac =3D { + .reg_off =3D ANACTRL_HIFIPLL_CTRL1, + .shift =3D 0, + .width =3D 19, + }, + .l =3D { + .reg_off =3D ANACTRL_HIFIPLL_STS, + .shift =3D 31, + .width =3D 1, + }, + .current_en =3D { + .reg_off =3D ANACTRL_HIFIPLL_CTRL0, + .shift =3D 26, + .width =3D 1, + }, + .l_detect =3D { + .reg_off =3D ANACTRL_HIFIPLL_CTRL2, + .shift =3D 6, + .width =3D 1, + }, + .range =3D &hifi_pll_mult_range, + .init_regs =3D hifi_init_regs, + .init_count =3D ARRAY_SIZE(hifi_init_regs), + }, + .hw.init =3D &(struct clk_init_data){ + .name =3D "hifi_pll", + .ops =3D &meson_clk_pll_ops, + .parent_data =3D &(const struct clk_parent_data) { + .fw_name =3D "hifipll_in", + }, + .num_parents =3D 1, + }, +}; + +static struct clk_fixed_factor fclk_div2_div =3D { + .mult =3D 1, + .div =3D 2, + .hw.init =3D &(struct clk_init_data){ + .name =3D "fclk_div2_div", + .ops =3D &clk_fixed_factor_ops, + .parent_hws =3D (const struct clk_hw *[]) { + &fixed_pll.hw + }, + .num_parents =3D 1, + }, +}; + +static struct clk_regmap fclk_div2 =3D { + .data =3D &(struct clk_regmap_gate_data){ + .offset =3D ANACTRL_FIXPLL_CTRL0, + .bit_idx =3D 21, + }, + .hw.init =3D &(struct clk_init_data){ + .name =3D "fclk_div2", + .ops =3D &clk_regmap_gate_ops, + .parent_hws =3D (const struct clk_hw *[]) { + &fclk_div2_div.hw + }, + .num_parents =3D 1, + /* + * This clock is used by DDR clock in BL2 firmware + * and is required by the platform to operate correctly. + * Until the following condition are met, we need this clock to + * be marked as critical: + * a) Mark the clock used by a firmware resource, if possible + * b) CCF has a clock hand-off mechanism to make the sure the + * clock stays on until the proper driver comes along + */ + .flags =3D CLK_IS_CRITICAL, + }, +}; + +static struct clk_fixed_factor fclk_div3_div =3D { + .mult =3D 1, + .div =3D 3, + .hw.init =3D &(struct clk_init_data){ + .name =3D "fclk_div3_div", + .ops =3D &clk_fixed_factor_ops, + .parent_hws =3D (const struct clk_hw *[]) { + &fixed_pll.hw + }, + .num_parents =3D 1, + }, +}; + +static struct clk_regmap fclk_div3 =3D { + .data =3D &(struct clk_regmap_gate_data){ + .offset =3D ANACTRL_FIXPLL_CTRL0, + .bit_idx =3D 22, + }, + .hw.init =3D &(struct clk_init_data){ + .name =3D "fclk_div3", + .ops =3D &clk_regmap_gate_ops, + .parent_hws =3D (const struct clk_hw *[]) { + &fclk_div3_div.hw + }, + .num_parents =3D 1, + /* + * This clock is used by APB bus which is set in boot ROM code + * and is required by the platform to operate correctly. + * About critical, refer to fclk_div2. + */ + .flags =3D CLK_IS_CRITICAL, + }, +}; + +static struct clk_fixed_factor fclk_div5_div =3D { + .mult =3D 1, + .div =3D 5, + .hw.init =3D &(struct clk_init_data){ + .name =3D "fclk_div5_div", + .ops =3D &clk_fixed_factor_ops, + .parent_hws =3D (const struct clk_hw *[]) { + &fixed_pll.hw + }, + .num_parents =3D 1, + }, +}; + +static struct clk_regmap fclk_div5 =3D { + .data =3D &(struct clk_regmap_gate_data){ + .offset =3D ANACTRL_FIXPLL_CTRL0, + .bit_idx =3D 23, + }, + .hw.init =3D &(struct clk_init_data){ + .name =3D "fclk_div5", + .ops =3D &clk_regmap_gate_ops, + .parent_hws =3D (const struct clk_hw *[]) { + &fclk_div5_div.hw + }, + .num_parents =3D 1, + /* + * This clock is used by AXI bus which setted in Romcode + * and is required by the platform to operate correctly. + * About critical, refer to fclk_div2. + */ + .flags =3D CLK_IS_CRITICAL, + }, +}; + +static struct clk_fixed_factor fclk_div7_div =3D { + .mult =3D 1, + .div =3D 7, + .hw.init =3D &(struct clk_init_data){ + .name =3D "fclk_div7_div", + .ops =3D &clk_fixed_factor_ops, + .parent_hws =3D (const struct clk_hw *[]) { + &fixed_pll.hw + }, + .num_parents =3D 1, + }, +}; + +static struct clk_regmap fclk_div7 =3D { + .data =3D &(struct clk_regmap_gate_data){ + .offset =3D ANACTRL_FIXPLL_CTRL0, + .bit_idx =3D 24, + }, + .hw.init =3D &(struct clk_init_data){ + .name =3D "fclk_div7", + .ops =3D &clk_regmap_gate_ops, + .parent_hws =3D (const struct clk_hw *[]) { + &fclk_div7_div.hw + }, + .num_parents =3D 1, + }, +}; + +/* Array of all clocks provided by this provider */ +static struct clk_hw_onecell_data a1_pll_hw_onecell_data =3D { + .hws =3D { + [CLKID_FIXED_PLL_DCO] =3D &fixed_pll_dco.hw, + [CLKID_FIXED_PLL] =3D &fixed_pll.hw, + [CLKID_FCLK_DIV2_DIV] =3D &fclk_div2_div.hw, + [CLKID_FCLK_DIV3_DIV] =3D &fclk_div3_div.hw, + [CLKID_FCLK_DIV5_DIV] =3D &fclk_div5_div.hw, + [CLKID_FCLK_DIV7_DIV] =3D &fclk_div7_div.hw, + [CLKID_FCLK_DIV2] =3D &fclk_div2.hw, + [CLKID_FCLK_DIV3] =3D &fclk_div3.hw, + [CLKID_FCLK_DIV5] =3D &fclk_div5.hw, + [CLKID_FCLK_DIV7] =3D &fclk_div7.hw, + [CLKID_HIFI_PLL] =3D &hifi_pll.hw, + [NR_PLL_CLKS] =3D NULL, + }, + .num =3D NR_PLL_CLKS, +}; + +static struct clk_regmap *const a1_pll_regmaps[] =3D { + &fixed_pll_dco, + &fixed_pll, + &fclk_div2, + &fclk_div3, + &fclk_div5, + &fclk_div7, + &hifi_pll, +}; + +static struct regmap_config a1_pll_regmap_cfg =3D { + .reg_bits =3D 32, + .val_bits =3D 32, + .reg_stride =3D 4, +}; + +static int meson_a1_pll_probe(struct platform_device *pdev) +{ + struct device *dev =3D &pdev->dev; + struct clk_hw *hw; + void __iomem *base; + struct regmap *map; + int clkid, i, err; + + base =3D devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(base)) + return dev_err_probe(dev, PTR_ERR(base), + "can't ioremap resource\n"); + + map =3D devm_regmap_init_mmio(dev, base, &a1_pll_regmap_cfg); + if (IS_ERR(map)) + return dev_err_probe(dev, PTR_ERR(map), + "can't init regmap mmio region\n"); + + /* Populate regmap for the regmap backed clocks */ + for (i =3D 0; i < ARRAY_SIZE(a1_pll_regmaps); i++) + a1_pll_regmaps[i]->map =3D map; + + for (clkid =3D 0; clkid < a1_pll_hw_onecell_data.num; clkid++) { + hw =3D a1_pll_hw_onecell_data.hws[clkid]; + err =3D devm_clk_hw_register(dev, hw); + if (err) + return dev_err_probe(dev, err, + "clock registration failed\n"); + } + + return devm_of_clk_add_hw_provider(dev, of_clk_hw_onecell_get, + &a1_pll_hw_onecell_data); +} + +#ifdef CONFIG_OF +static const struct of_device_id a1_pll_clkc_match_table[] =3D { + { .compatible =3D "amlogic,a1-pll-clkc", }, + {}, +}; +MODULE_DEVICE_TABLE(of, a1_pll_clkc_match_table); +#endif /* CONFIG_OF */ + +static struct platform_driver a1_pll_clkc_driver =3D { + .probe =3D meson_a1_pll_probe, + .driver =3D { + .name =3D "a1-pll-clkc", + .of_match_table =3D of_match_ptr(a1_pll_clkc_match_table), + }, +}; + +module_platform_driver(a1_pll_clkc_driver); +MODULE_AUTHOR("Jian Hu "); +MODULE_AUTHOR("Dmitry Rokosov "); +MODULE_LICENSE("GPL"); diff --git a/drivers/clk/meson/a1-pll.h b/drivers/clk/meson/a1-pll.h new file mode 100644 index 000000000000..de2eebce98af --- /dev/null +++ b/drivers/clk/meson/a1-pll.h @@ -0,0 +1,47 @@ +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ +/* + * Amlogic Meson-A1 PLL Clock Controller internals + * + * Copyright (c) 2019 Amlogic, Inc. All rights reserved. + * Author: Jian Hu + * + * Copyright (c) 2023, SberDevices. All Rights Reserved. + * Author: Dmitry Rokosov + */ + +#ifndef __A1_PLL_H +#define __A1_PLL_H + +#include "clk-pll.h" + +/* PLL register offset */ +#define ANACTRL_FIXPLL_CTRL0 0x0 +#define ANACTRL_FIXPLL_CTRL1 0x4 +#define ANACTRL_FIXPLL_STS 0x14 +#define ANACTRL_HIFIPLL_CTRL0 0xc0 +#define ANACTRL_HIFIPLL_CTRL1 0xc4 +#define ANACTRL_HIFIPLL_CTRL2 0xc8 +#define ANACTRL_HIFIPLL_CTRL3 0xcc +#define ANACTRL_HIFIPLL_CTRL4 0xd0 +#define ANACTRL_HIFIPLL_STS 0xd4 + +/* + * CLKID index values + * + * These indices are entirely contrived and do not map onto the hardware. + * It has now been decided to expose everything by default in the DT heade= r: + * include/dt-bindings/clock/a1-pll-clkc.h. Only the clocks ids we don't w= ant + * to expose, such as the internal muxes and dividers of composite clocks, + * will remain defined here. + */ +#define CLKID_FIXED_PLL_DCO 0 +#define CLKID_FCLK_DIV2_DIV 2 +#define CLKID_FCLK_DIV3_DIV 3 +#define CLKID_FCLK_DIV5_DIV 4 +#define CLKID_FCLK_DIV7_DIV 5 +#define NR_PLL_CLKS 11 + +/* include the CLKIDs that have been made part of the DT binding */ +#include + +#endif /* __A1_PLL_H */ --=20 2.36.0