From nobody Sat Apr 11 04:15:22 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6B5B9C64EC7 for ; Wed, 1 Mar 2023 09:12:00 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229600AbjCAJL6 (ORCPT ); Wed, 1 Mar 2023 04:11:58 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:34028 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229501AbjCAJL4 (ORCPT ); Wed, 1 Mar 2023 04:11:56 -0500 Received: from lelv0142.ext.ti.com (lelv0142.ext.ti.com [198.47.23.249]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 81D2B2A6C0; Wed, 1 Mar 2023 01:11:54 -0800 (PST) Received: from lelv0266.itg.ti.com ([10.180.67.225]) by lelv0142.ext.ti.com (8.15.2/8.15.2) with ESMTP id 3219Bj81057476; Wed, 1 Mar 2023 03:11:45 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1677661905; bh=K9AnTQyEviIHTEIq+dOWg4AD6zLxyl+k+1/TD/19yq0=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=KakJh4FI483VYXChwENsW0+aD7XFSeTavxHse26kWN9k1+aO/NkVWEiGvlkbAmRh8 kOt5UaQZqxM6skAqqFLj1StpvY4bKJ7OjK9GbMzksF1AkjE9WWudXxhJTUEhljr+c7 fhGpWnhk8dEdlzsVx8LR5pNxGF79W/Cy1aqlyITs= Received: from DFLE111.ent.ti.com (dfle111.ent.ti.com [10.64.6.32]) by lelv0266.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 3219BjP2055764 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Wed, 1 Mar 2023 03:11:45 -0600 Received: from DFLE108.ent.ti.com (10.64.6.29) by DFLE111.ent.ti.com (10.64.6.32) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.16; Wed, 1 Mar 2023 03:11:45 -0600 Received: from lelv0327.itg.ti.com (10.180.67.183) by DFLE108.ent.ti.com (10.64.6.29) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.16 via Frontend Transport; Wed, 1 Mar 2023 03:11:45 -0600 Received: from uda0500640.dal.design.ti.com (ileaxei01-snat2.itg.ti.com [10.180.69.6]) by lelv0327.itg.ti.com (8.15.2/8.15.2) with ESMTP id 3219BbbA088843; Wed, 1 Mar 2023 03:11:41 -0600 From: Ravi Gunasekaran To: , , , , , , , , CC: , , Subject: [PATCH v12 1/8] arm64: dts: ti: k3-j721s2-main: Add support for USB Date: Wed, 1 Mar 2023 14:41:29 +0530 Message-ID: <20230301091136.17862-2-r-gunasekaran@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230301091136.17862-1-r-gunasekaran@ti.com> References: <20230301091136.17862-1-r-gunasekaran@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Aswath Govindraju Add support for single instance of USB 3.0 controller in J721S2 SoC. Signed-off-by: Aswath Govindraju Signed-off-by: Matt Ranostay Signed-off-by: Ravi Gunasekaran Reviewed-by tag. --- I had reviewed this patch in the v5 series [0]. Since I'm taking over upstreaming this series, I removed the self Reviewed-by tag. [0] - https://lore.kernel.org/all/134c28a0-2d49-549c-dc8d-0887d8fd29c3@ti.c= om/ Changes from v11: * Cleaned up comments Changes from v10: * Fixed dtbs warnings by adding "reg" property to the mux-controller nodes. * Documented the reason for disabling the nodes by default. * Removed Link tag from commit message Changes from v9: * Disabled USB nodes by default in common DT file. Changes from v8: * Updated mux-controller node name to fix dtbs warnings. Changes from v7: * No change Changes from v6: * No change Changes from v5: * No change Changes from v4: * Removed Cc tags from commit message Changes from v3: * No change Changes from v2: * No change Changes from v1: * Updated mux-controller node name. arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi | 47 ++++++++++++++++++++++ 1 file changed, 47 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi b/arch/arm64/boot/d= ts/ti/k3-j721s2-main.dtsi index 8915132efcc1..37beaebc94bf 100644 --- a/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi @@ -26,6 +26,21 @@ }; }; =20 + scm_conf: syscon@104000 { + compatible =3D "ti,j721e-system-controller", "syscon", "simple-mfd"; + reg =3D <0x00 0x00104000 0x00 0x18000>; + #address-cells =3D <1>; + #size-cells =3D <1>; + ranges =3D <0x00 0x00 0x00104000 0x18000>; + + usb_serdes_mux: mux-controller@0 { + compatible =3D "mmio-mux"; + reg =3D <0x0 0x4>; + #mux-control-cells =3D <1>; + mux-reg-masks =3D <0x0 0x8000000>; /* USB0 to SERDES0 lane 1/3 mux */ + }; + }; + gic500: interrupt-controller@1800000 { compatible =3D "arm,gic-v3"; #address-cells =3D <2>; @@ -745,6 +760,38 @@ }; }; =20 + usbss0: cdns-usb@4104000 { + compatible =3D "ti,j721e-usb"; + reg =3D <0x00 0x04104000 0x00 0x100>; + clocks =3D <&k3_clks 360 16>, <&k3_clks 360 15>; + clock-names =3D "ref", "lpm"; + assigned-clocks =3D <&k3_clks 360 16>; /* USB2_REFCLK */ + assigned-clock-parents =3D <&k3_clks 360 17>; + power-domains =3D <&k3_pds 360 TI_SCI_PD_EXCLUSIVE>; + #address-cells =3D <2>; + #size-cells =3D <2>; + ranges; + dma-coherent; + + status =3D "disabled"; /* Needs pinmux */ + + usb0: usb@6000000 { + compatible =3D "cdns,usb3"; + reg =3D <0x00 0x06000000 0x00 0x10000>, + <0x00 0x06010000 0x00 0x10000>, + <0x00 0x06020000 0x00 0x10000>; + reg-names =3D "otg", "xhci", "dev"; + interrupts =3D , + , + ; + interrupt-names =3D "host", "peripheral", "otg"; + maximum-speed =3D "super-speed"; + dr_mode =3D "otg"; + + status =3D "disabled"; + }; + }; + main_mcan0: can@2701000 { compatible =3D "bosch,m_can"; reg =3D <0x00 0x02701000 0x00 0x200>, --=20 2.17.1 From nobody Sat Apr 11 04:15:22 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4039FC7EE30 for ; Wed, 1 Mar 2023 09:12:07 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229715AbjCAJMF (ORCPT ); Wed, 1 Mar 2023 04:12:05 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:34090 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229623AbjCAJMA (ORCPT ); Wed, 1 Mar 2023 04:12:00 -0500 Received: from fllv0015.ext.ti.com (fllv0015.ext.ti.com [198.47.19.141]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id B920A2A6F1; Wed, 1 Mar 2023 01:11:58 -0800 (PST) Received: from fllv0035.itg.ti.com ([10.64.41.0]) by fllv0015.ext.ti.com (8.15.2/8.15.2) with ESMTP id 3219BomX101953; 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Wed, 1 Mar 2023 03:11:49 -0600 Received: from uda0500640.dal.design.ti.com (ileaxei01-snat2.itg.ti.com [10.180.69.6]) by lelv0327.itg.ti.com (8.15.2/8.15.2) with ESMTP id 3219BbbB088843; Wed, 1 Mar 2023 03:11:45 -0600 From: Ravi Gunasekaran To: , , , , , , , , CC: , , Subject: [PATCH v12 2/8] arm64: dts: ti: k3-j721s2-main: Add SERDES and WIZ device tree node Date: Wed, 1 Mar 2023 14:41:30 +0530 Message-ID: <20230301091136.17862-3-r-gunasekaran@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230301091136.17862-1-r-gunasekaran@ti.com> References: <20230301091136.17862-1-r-gunasekaran@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Matt Ranostay Add dt node for the single instance of WIZ (SERDES wrapper) and SERDES module shared by PCIe, eDP and USB. Signed-off-by: Matt Ranostay Signed-off-by: Ravi Gunasekaran Reviewed-by tag. --- I had reviewed this patch in the v7 series [0]. Since I'm taking over upstreaming this series, I removed the self Reviewed-by tag. [0] - https://lore.kernel.org/lkml/4173e0c6-61d9-5b79-44ec-317870de070b@ti.= com/ Changes from v11: * Cleaned up comments Changes from v10: * Fixed dtbs warnings by adding "reg" property to the mux-controller nodes * Documented the reason for disabling the nodes by default * Removed Link tag from commit message Changes from v9: * Disabled serdes related nodes by default in common DT file Changes from v8: * No change Changes from v7: * Updated mux-controller node name Changes from v6: * Fixed the incorrect "compatible" property Changes from v5: * Removed Cc tag from commit message Changes from v4: * No change Changes from v3: * No change Changes from v2: * Reworked SERDES + WIZ enablement patchset to use properies for clocks defines versus entire devicetree nodes. Results in cleaner code that doesn't break dt-schema or the driver functionality. Changes from v1: * Update mux-controller node name arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi | 59 ++++++++++++++++++++++ 1 file changed, 59 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi b/arch/arm64/boot/d= ts/ti/k3-j721s2-main.dtsi index 37beaebc94bf..96e7dcc5ebad 100644 --- a/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi @@ -5,6 +5,17 @@ * Copyright (C) 2021 Texas Instruments Incorporated - https://www.ti.com/ */ =20 +#include +#include + +/ { + serdes_refclk: clock-cmnrefclk { + #clock-cells =3D <0>; + compatible =3D "fixed-clock"; + clock-frequency =3D <0>; + }; +}; + &cbass_main { msmc_ram: sram@70000000 { compatible =3D "mmio-sram"; @@ -39,6 +50,14 @@ #mux-control-cells =3D <1>; mux-reg-masks =3D <0x0 0x8000000>; /* USB0 to SERDES0 lane 1/3 mux */ }; + + serdes_ln_ctrl: mux-controller@80 { + compatible =3D "mmio-mux"; + reg =3D <0x80 0x10>; + #mux-control-cells =3D <1>; + mux-reg-masks =3D <0x80 0x3>, <0x84 0x3>, /* SERDES0 lane0/1 select */ + <0x88 0x3>, <0x8c 0x3>; /* SERDES0 lane2/3 select */ + }; }; =20 gic500: interrupt-controller@1800000 { @@ -792,6 +811,46 @@ }; }; =20 + serdes_wiz0: wiz@5060000 { + compatible =3D "ti,j721s2-wiz-10g"; + #address-cells =3D <1>; + #size-cells =3D <1>; + power-domains =3D <&k3_pds 365 TI_SCI_PD_EXCLUSIVE>; + clocks =3D <&k3_clks 365 0>, <&k3_clks 365 3>, <&serdes_refclk>; + clock-names =3D "fck", "core_ref_clk", "ext_ref_clk"; + num-lanes =3D <4>; + #reset-cells =3D <1>; + #clock-cells =3D <1>; + ranges =3D <0x5060000 0x0 0x5060000 0x10000>; + + assigned-clocks =3D <&k3_clks 365 3>; + assigned-clock-parents =3D <&k3_clks 365 7>; + + status =3D "disabled"; + + serdes0: serdes@5060000 { + compatible =3D "ti,j721e-serdes-10g"; + reg =3D <0x05060000 0x00010000>; + reg-names =3D "torrent_phy"; + resets =3D <&serdes_wiz0 0>; + reset-names =3D "torrent_reset"; + clocks =3D <&serdes_wiz0 TI_WIZ_PLL0_REFCLK>, + <&serdes_wiz0 TI_WIZ_PHY_EN_REFCLK>; + clock-names =3D "refclk", "phy_en_refclk"; + assigned-clocks =3D <&serdes_wiz0 TI_WIZ_PLL0_REFCLK>, + <&serdes_wiz0 TI_WIZ_PLL1_REFCLK>, + <&serdes_wiz0 TI_WIZ_REFCLK_DIG>; + assigned-clock-parents =3D <&k3_clks 365 3>, + <&k3_clks 365 3>, + <&k3_clks 365 3>; + #address-cells =3D <1>; + #size-cells =3D <0>; + #clock-cells =3D <1>; + + status =3D "disabled"; /* Needs lane config */ + }; + }; + main_mcan0: can@2701000 { compatible =3D "bosch,m_can"; reg =3D <0x00 0x02701000 0x00 0x200>, --=20 2.17.1 From nobody Sat Apr 11 04:15:22 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8798EC64ED6 for ; Wed, 1 Mar 2023 09:12:10 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229775AbjCAJMI (ORCPT ); Wed, 1 Mar 2023 04:12:08 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:34120 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229673AbjCAJMB (ORCPT ); Wed, 1 Mar 2023 04:12:01 -0500 Received: from lelv0142.ext.ti.com (lelv0142.ext.ti.com [198.47.23.249]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 7AA0030B3E; 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Wed, 1 Mar 2023 03:11:53 -0600 Received: from uda0500640.dal.design.ti.com (ileaxei01-snat2.itg.ti.com [10.180.69.6]) by lelv0327.itg.ti.com (8.15.2/8.15.2) with ESMTP id 3219BbbC088843; Wed, 1 Mar 2023 03:11:49 -0600 From: Ravi Gunasekaran To: , , , , , , , , CC: , , Subject: [PATCH v12 3/8] arm64: dts: ti: k3-j721s2-mcu-wakeup: Add support of OSPI Date: Wed, 1 Mar 2023 14:41:31 +0530 Message-ID: <20230301091136.17862-4-r-gunasekaran@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230301091136.17862-1-r-gunasekaran@ti.com> References: <20230301091136.17862-1-r-gunasekaran@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Aswath Govindraju Add support for two instance of OSPI in J721S2 SoC. Reviewed-by: Vaishnav Achath Signed-off-by: Aswath Govindraju Signed-off-by: Matt Ranostay Signed-off-by: Ravi Gunasekaran --- Changes from v11: * Cleaned up comments Changes from v10: * Documented the reason for disabling the nodes by default. * Removed Link tag from commmit message Changes from v9: * Disabled fss, ospi nodes by default in common DT file Changes from v8: * Updated "ranges" property to fix dtbs warnings Changes from v7: * Removed "reg" property from syscon node * Renamed the "syscon" node to "bus" to after change in compatible property Changes from v6: * Fixed the syscon node's compatible property Changes from v5: * Updated the syscon node's compatible property * Removed Cc tags from commit message Changes from v4: * No change Changes from v3: * No change Changes from v2: * No change Changes from v1: * No change .../boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi | 46 +++++++++++++++++++ 1 file changed, 46 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi b/arch/arm64/= boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi index 0af242aa9816..ab3ce8be7216 100644 --- a/arch/arm64/boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi @@ -306,4 +306,50 @@ ti,cpts-periodic-outputs =3D <2>; }; }; + + fss: bus@47000000 { + compatible =3D "simple-bus"; + #address-cells =3D <2>; + #size-cells =3D <2>; + ranges =3D <0x00 0x47000000 0x00 0x47000000 0x00 0x00068400>, + <0x05 0x00000000 0x05 0x00000000 0x01 0x00000000>, + <0x07 0x00000000 0x07 0x00000000 0x01 0x00000000>; + + status =3D "disabled"; + + ospi0: spi@47040000 { + compatible =3D "ti,am654-ospi", "cdns,qspi-nor"; + reg =3D <0x00 0x47040000 0x00 0x100>, + <0x05 0x00000000 0x01 0x00000000>; + interrupts =3D ; + cdns,fifo-depth =3D <256>; + cdns,fifo-width =3D <4>; + cdns,trigger-address =3D <0x0>; + clocks =3D <&k3_clks 109 5>; + assigned-clocks =3D <&k3_clks 109 5>; + assigned-clock-parents =3D <&k3_clks 109 7>; + assigned-clock-rates =3D <166666666>; + power-domains =3D <&k3_pds 109 TI_SCI_PD_EXCLUSIVE>; + #address-cells =3D <1>; + #size-cells =3D <0>; + + status =3D "disabled"; /* Needs pinmux */ + }; + + ospi1: spi@47050000 { + compatible =3D "ti,am654-ospi", "cdns,qspi-nor"; + reg =3D <0x00 0x47050000 0x00 0x100>, + <0x07 0x00000000 0x01 0x00000000>; + interrupts =3D ; + cdns,fifo-depth =3D <256>; + cdns,fifo-width =3D <4>; + cdns,trigger-address =3D <0x0>; + clocks =3D <&k3_clks 110 5>; + power-domains =3D <&k3_pds 110 TI_SCI_PD_EXCLUSIVE>; + #address-cells =3D <1>; + #size-cells =3D <0>; + + status =3D "disabled"; /* Needs pinmux */ + }; + }; }; --=20 2.17.1 From nobody Sat Apr 11 04:15:22 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 01443C64ED6 for ; Wed, 1 Mar 2023 09:12:21 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229934AbjCAJMS (ORCPT ); Wed, 1 Mar 2023 04:12:18 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:34870 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229815AbjCAJMO (ORCPT ); Wed, 1 Mar 2023 04:12:14 -0500 Received: from fllv0016.ext.ti.com (fllv0016.ext.ti.com [198.47.19.142]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 7A3EA301BA; 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Wed, 1 Mar 2023 03:11:58 -0600 Received: from uda0500640.dal.design.ti.com (ileaxei01-snat2.itg.ti.com [10.180.69.6]) by lelv0327.itg.ti.com (8.15.2/8.15.2) with ESMTP id 3219BbbD088843; Wed, 1 Mar 2023 03:11:54 -0600 From: Ravi Gunasekaran To: , , , , , , , , CC: , , Subject: [PATCH v12 4/8] arm64: dts: ti: k3-j721s2-common-proc-board: Enable SERDES0 Date: Wed, 1 Mar 2023 14:41:32 +0530 Message-ID: <20230301091136.17862-5-r-gunasekaran@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230301091136.17862-1-r-gunasekaran@ti.com> References: <20230301091136.17862-1-r-gunasekaran@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Aswath Govindraju Configure first lane to PCIe, the second lane to USB and the last two lanes to eDP. Also, add sub-nodes to SERDES0 DT node to represent SERDES0 is connected to PCIe. Signed-off-by: Aswath Govindraju Signed-off-by: Matt Ranostay Signed-off-by: Ravi Gunasekaran Reviewed-by tag. --- I had reviewed this patch in the v5 series [0]. Since I'm taking over upstreaming this series, I removed the self Reviewed-by tag. [0] - https://lore.kernel.org/all/71ce4ecd-2a50-c69d-28be-f1a8d769970e@ti.c= om/ Changes from v11: * No change Changes from v10: * Removed Link tag from commit message Changes from v9: * Enabled serdes related nodes Changes from v8: * No change Changes from v7: * No change Changes from v6: * No change Changes from v5: * Removed Cc tags from commit message Changes from v4: * No change Changes from v3: * No change Changes from v2: * No change Changes from v1: * No change .../dts/ti/k3-j721s2-common-proc-board.dts | 27 +++++++++++++++++++ 1 file changed, 27 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts b/arch/= arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts index a7aa6cf08acd..907f34ff22a5 100644 --- a/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts +++ b/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts @@ -9,6 +9,9 @@ =20 #include "k3-j721s2-som-p0.dtsi" #include +#include +#include +#include =20 / { compatible =3D "ti,j721s2-evm", "ti,j721s2"; @@ -296,6 +299,30 @@ phy-handle =3D <&phy0>; }; =20 +&serdes_ln_ctrl { + idle-states =3D , , + , ; +}; + +&serdes_refclk { + clock-frequency =3D <100000000>; +}; + +&serdes_wiz0 { + status =3D "okay"; +}; + +&serdes0 { + status =3D "okay"; + serdes0_pcie_link: phy@0 { + reg =3D <0>; + cdns,num-lanes =3D <1>; + #phy-cells =3D <0>; + cdns,phy-type =3D ; + resets =3D <&serdes_wiz0 1>; + }; +}; + &mcu_mcan0 { status =3D "okay"; pinctrl-names =3D "default"; --=20 2.17.1 From nobody Sat Apr 11 04:15:22 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id DD83CC64EC7 for ; Wed, 1 Mar 2023 09:12:35 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229935AbjCAJMe (ORCPT ); Wed, 1 Mar 2023 04:12:34 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:34912 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229926AbjCAJMR (ORCPT ); Wed, 1 Mar 2023 04:12:17 -0500 Received: from fllv0015.ext.ti.com (fllv0015.ext.ti.com [198.47.19.141]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 0FB153B3ED; Wed, 1 Mar 2023 01:12:08 -0800 (PST) Received: from fllv0035.itg.ti.com ([10.64.41.0]) by fllv0015.ext.ti.com (8.15.2/8.15.2) with ESMTP id 3219C2aC101991; Wed, 1 Mar 2023 03:12:02 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1677661922; bh=z8CHtWLyHnQ4Vunc/xsEnmTsPPNCiHLOqJwkdjCSlgY=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=v2wB+IHHYf8FOJJugnEvWHMkUJ1O9uGAhu12ufRw/WwQkw7xVs+OqIZLAL5+lnAiS nDZnJEwz69DjOT5wFvF4lVKv5OUqj02K0YP85xC7r+gjuFfCC9mysMvcdIDoSD1Ncc uIeY8T5zOVGkR4IYmMINsPc5ZE6E3S6x/nTJtGec= Received: from DFLE111.ent.ti.com (dfle111.ent.ti.com [10.64.6.32]) by fllv0035.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 3219C2JF009188 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Wed, 1 Mar 2023 03:12:02 -0600 Received: from DFLE114.ent.ti.com (10.64.6.35) by DFLE111.ent.ti.com (10.64.6.32) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.16; Wed, 1 Mar 2023 03:12:01 -0600 Received: from lelv0327.itg.ti.com (10.180.67.183) by DFLE114.ent.ti.com (10.64.6.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.16 via Frontend Transport; Wed, 1 Mar 2023 03:12:01 -0600 Received: from uda0500640.dal.design.ti.com (ileaxei01-snat2.itg.ti.com [10.180.69.6]) by lelv0327.itg.ti.com (8.15.2/8.15.2) with ESMTP id 3219BbbE088843; Wed, 1 Mar 2023 03:11:58 -0600 From: Ravi Gunasekaran To: , , , , , , , , CC: , , Subject: [PATCH v12 5/8] arm64: dts: ti: k3-j721s2-common-proc-board: Add USB support Date: Wed, 1 Mar 2023 14:41:33 +0530 Message-ID: <20230301091136.17862-6-r-gunasekaran@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230301091136.17862-1-r-gunasekaran@ti.com> References: <20230301091136.17862-1-r-gunasekaran@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Aswath Govindraju The board uses lane 1 of SERDES for USB. Set the mux accordingly. The USB controller and EVM supports super-speed for USB0 on the Type-C port. However, the SERDES has a limitation that up to 2 protocols can be used at a time. The SERDES is wired for PCIe, eDP and USB super-speed. It has been chosen to use PCIe and eDP as default. So restrict USB0 to high-speed mode. Signed-off-by: Aswath Govindraju Signed-off-by: Matt Ranostay Signed-off-by: Ravi Gunasekaran Reviewed-by tag. --- I had reviewed this patch in the v5 series [0]. Since I'm taking over upstreaming this series, I removed the self Reviewed-by tag. [0] - https://lore.kernel.org/all/96058a13-4903-2b8c-8de2-f37fdfd3672b@ti.c= om/ Changes from v11: * No change Changes from v10: * Removed Link tag from commit message Changes from v9: * Enabled USB nodes Changes from v8: * No change Changes from v7: * No change Changes from v6: * No change Changes from v5: * Removed Cc tags from commit message Changes from v4: * No change Changes from v3: * No change Changes from v2: * No change Changes from v1: * No change .../dts/ti/k3-j721s2-common-proc-board.dts | 24 +++++++++++++++++++ 1 file changed, 24 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts b/arch/= arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts index 907f34ff22a5..fa38940fe6cd 100644 --- a/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts +++ b/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts @@ -147,6 +147,12 @@ J721S2_IOPAD(0x020, PIN_INPUT, 7) /* (AA23) MCAN15_RX.GPIO0_8 */ >; }; + + main_usbss0_pins_default: main-usbss0-pins-default { + pinctrl-single,pins =3D < + J721S2_IOPAD(0x0ec, PIN_OUTPUT, 6) /* (AG25) TIMER_IO1.USB0_DRVVBUS */ + >; + }; }; =20 &wkup_pmx0 { @@ -323,6 +329,24 @@ }; }; =20 +&usb_serdes_mux { + idle-states =3D <1>; /* USB0 to SERDES lane 1 */ +}; + +&usbss0 { + status =3D "okay"; + pinctrl-0 =3D <&main_usbss0_pins_default>; + pinctrl-names =3D "default"; + ti,vbus-divider; + ti,usb2-only; +}; + +&usb0 { + status =3D "okay"; + dr_mode =3D "otg"; + maximum-speed =3D "high-speed"; +}; + &mcu_mcan0 { status =3D "okay"; pinctrl-names =3D "default"; --=20 2.17.1 From nobody Sat Apr 11 04:15:22 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4FBD0C64EC7 for ; Wed, 1 Mar 2023 09:12:46 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229910AbjCAJMo (ORCPT ); Wed, 1 Mar 2023 04:12:44 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:34986 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229842AbjCAJMZ (ORCPT ); Wed, 1 Mar 2023 04:12:25 -0500 Received: from lelv0142.ext.ti.com (lelv0142.ext.ti.com [198.47.23.249]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id C68323B3D8; Wed, 1 Mar 2023 01:12:11 -0800 (PST) Received: from lelv0265.itg.ti.com ([10.180.67.224]) by lelv0142.ext.ti.com (8.15.2/8.15.2) with ESMTP id 3219C66l057556; Wed, 1 Mar 2023 03:12:06 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1677661926; bh=XBXdoeWbMZe4ja6FSXFOGeIeOpckrselaphCWGMiA3s=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=iuIA5+pyixtVKGkTlAonSG73tVLp+aXrS+MY+p1ySyzoqqggmNPpTXkfAlj++sCyy Zd7TAucHQGbmId+nss0ziga9o5aTMerLDwEmB+WAt3apF0L+Kb3+iMngU/BSURQ/eQ C84Io5aEx3tTg+MvHuZ1Ny/feGYBoGXkYW7pszls= Received: from DFLE114.ent.ti.com (dfle114.ent.ti.com [10.64.6.35]) by lelv0265.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 3219C6lk026480 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Wed, 1 Mar 2023 03:12:06 -0600 Received: from DFLE105.ent.ti.com (10.64.6.26) by DFLE114.ent.ti.com (10.64.6.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.16; Wed, 1 Mar 2023 03:12:05 -0600 Received: from lelv0327.itg.ti.com (10.180.67.183) by DFLE105.ent.ti.com (10.64.6.26) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.16 via Frontend Transport; Wed, 1 Mar 2023 03:12:05 -0600 Received: from uda0500640.dal.design.ti.com (ileaxei01-snat2.itg.ti.com [10.180.69.6]) by lelv0327.itg.ti.com (8.15.2/8.15.2) with ESMTP id 3219BbbF088843; Wed, 1 Mar 2023 03:12:02 -0600 From: Ravi Gunasekaran To: , , , , , , , , CC: , , Subject: [PATCH v12 6/8] arm64: dts: ti: k3-j721s2: Add support for OSPI Flashes Date: Wed, 1 Mar 2023 14:41:34 +0530 Message-ID: <20230301091136.17862-7-r-gunasekaran@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230301091136.17862-1-r-gunasekaran@ti.com> References: <20230301091136.17862-1-r-gunasekaran@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Aswath Govindraju J721S2 has an OSPI NOR flash on its SOM connected the OSPI0 instance and a QSPI NOR flash on the common processor board connected to the OSPI1 instance. Add support for the same Reviewed-by: Vaishnav Achath Signed-off-by: Aswath Govindraju Signed-off-by: Matt Ranostay Signed-off-by: Ravi Gunasekaran --- Changes from v11: * Remove deprecated properties Changes from v10: * Removed Link tag from commit message Changes from v9: * Enabled fss and ospi nodes Changes from v8: * No change Changes from v7: * No change Changes from v6: * No change Changes from v5: * Removed Cc tags from commit message Changes from v4: * No change Changes from v3: * No change Changes from v2: * No change Changes from v1: * No change .../dts/ti/k3-j721s2-common-proc-board.dts | 37 +++++++++++++++++ arch/arm64/boot/dts/ti/k3-j721s2-som-p0.dtsi | 41 +++++++++++++++++++ 2 files changed, 78 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts b/arch/= arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts index fa38940fe6cd..6bd6370e5bae 100644 --- a/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts +++ b/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts @@ -206,6 +206,20 @@ J721S2_WKUP_IOPAD(0x0c8, PIN_INPUT, 7) /* (C28) WKUP_GPIO0_2 */ >; }; + + mcu_fss0_ospi1_pins_default: mcu-fss0-ospi1-pins-default { + pinctrl-single,pins =3D < + J721S2_WKUP_IOPAD(0x040, PIN_OUTPUT, 0) /* (A19) MCU_OSPI1_CLK */ + J721S2_WKUP_IOPAD(0x05c, PIN_OUTPUT, 0) /* (D20) MCU_OSPI1_CSn0 */ + J721S2_WKUP_IOPAD(0x060, PIN_OUTPUT, 0) /* (C21) MCU_OSPI1_CSn1 */ + J721S2_WKUP_IOPAD(0x04c, PIN_INPUT, 0) /* (D21) MCU_OSPI1_D0 */ + J721S2_WKUP_IOPAD(0x050, PIN_INPUT, 0) /* (G20) MCU_OSPI1_D1 */ + J721S2_WKUP_IOPAD(0x054, PIN_INPUT, 0) /* (C20) MCU_OSPI1_D2 */ + J721S2_WKUP_IOPAD(0x058, PIN_INPUT, 0) /* (A20) MCU_OSPI1_D3 */ + J721S2_WKUP_IOPAD(0x048, PIN_INPUT, 0) /* (B19) MCU_OSPI1_DQS */ + J721S2_WKUP_IOPAD(0x044, PIN_INPUT, 0) /* (B20) MCU_OSPI1_LBCLKO */ + >; + }; }; =20 &main_gpio2 { @@ -347,6 +361,29 @@ maximum-speed =3D "high-speed"; }; =20 +&fss { + status =3D "okay"; +}; + +&ospi1 { + status =3D "okay"; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&mcu_fss0_ospi1_pins_default>; + + flash@0{ + compatible =3D "jedec,spi-nor"; + reg =3D <0x0>; + spi-tx-bus-width =3D <1>; + spi-rx-bus-width =3D <4>; + spi-max-frequency =3D <40000000>; + cdns,tshsl-ns =3D <60>; + cdns,tsd2d-ns =3D <60>; + cdns,tchsh-ns =3D <60>; + cdns,tslch-ns =3D <60>; + cdns,read-delay =3D <2>; + }; +}; + &mcu_mcan0 { status =3D "okay"; pinctrl-names =3D "default"; diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-som-p0.dtsi b/arch/arm64/boot= /dts/ti/k3-j721s2-som-p0.dtsi index 6930efff8a5a..d473d79c2757 100644 --- a/arch/arm64/boot/dts/ti/k3-j721s2-som-p0.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j721s2-som-p0.dtsi @@ -39,6 +39,28 @@ }; }; =20 +&wkup_pmx0 { + mcu_fss0_ospi0_pins_default: mcu-fss0-ospi0-pins-default { + pinctrl-single,pins =3D < + J721S2_WKUP_IOPAD(0x000, PIN_OUTPUT, 0) /* (D19) MCU_OSPI0_CLK */ + J721S2_WKUP_IOPAD(0x02c, PIN_OUTPUT, 0) /* (F15) MCU_OSPI0_CSn0 */ + J721S2_WKUP_IOPAD(0x030, PIN_OUTPUT, 0) /* (G17) MCU_OSPI0_CSn1 */ + J721S2_WKUP_IOPAD(0x038, PIN_OUTPUT, 0) /* (F14) MCU_OSPI0_CSn2 */ + J721S2_WKUP_IOPAD(0x03c, PIN_OUTPUT, 0) /* (F17) MCU_OSPI0_CSn3 */ + J721S2_WKUP_IOPAD(0x00c, PIN_INPUT, 0) /* (C19) MCU_OSPI0_D0 */ + J721S2_WKUP_IOPAD(0x010, PIN_INPUT, 0) /* (F16) MCU_OSPI0_D1 */ + J721S2_WKUP_IOPAD(0x014, PIN_INPUT, 0) /* (G15) MCU_OSPI0_D2 */ + J721S2_WKUP_IOPAD(0x018, PIN_INPUT, 0) /* (F18) MCU_OSPI0_D3 */ + J721S2_WKUP_IOPAD(0x01c, PIN_INPUT, 0) /* (E19) MCU_OSPI0_D4 */ + J721S2_WKUP_IOPAD(0x020, PIN_INPUT, 0) /* (G19) MCU_OSPI0_D5 */ + J721S2_WKUP_IOPAD(0x024, PIN_INPUT, 0) /* (F19) MCU_OSPI0_D6 */ + J721S2_WKUP_IOPAD(0x028, PIN_INPUT, 0) /* (F20) MCU_OSPI0_D7 */ + J721S2_WKUP_IOPAD(0x008, PIN_INPUT, 0) /* (E18) MCU_OSPI0_DQS */ + J721S2_WKUP_IOPAD(0x004, PIN_INPUT, 0) /* (E20) MCU_OSPI0_LBCLKO */ + >; + }; +}; + &main_pmx0 { main_i2c0_pins_default: main-i2c0-pins-default { pinctrl-single,pins =3D < @@ -79,3 +101,22 @@ pinctrl-names =3D "default"; phys =3D <&transceiver0>; }; + +&ospi0 { + status =3D "okay"; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&mcu_fss0_ospi0_pins_default>; + + flash@0 { + compatible =3D "jedec,spi-nor"; + reg =3D <0x0>; + spi-tx-bus-width =3D <8>; + spi-rx-bus-width =3D <8>; + spi-max-frequency =3D <25000000>; + cdns,tshsl-ns =3D <60>; + cdns,tsd2d-ns =3D <60>; + cdns,tchsh-ns =3D <60>; + cdns,tslch-ns =3D <60>; + cdns,read-delay =3D <4>; + }; +}; --=20 2.17.1 From nobody Sat Apr 11 04:15:22 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9D273C64ED6 for ; Wed, 1 Mar 2023 09:13:03 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229716AbjCAJNB (ORCPT ); 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charset="utf-8" From: Aswath Govindraju Add PCIe1 RC device tree node for the single PCIe instance present on the J721S2. Reviewed-by: Siddharth Vadapalli Signed-off-by: Aswath Govindraju Signed-off-by: Vignesh Raghavendra Signed-off-by: Matt Ranostay Signed-off-by: Ravi Gunasekaran --- Changes from v11: * Cleaned up comments Changes from v10: * Removed Link tag from commit message Changes from v9: * No change Changes from v8: * No change Changes from v7: * No change Changes from v6: * Remove the pcie_ep node as device cannot act as RC and EP at the same time Changes from v5: * No change Changes from v4: * No change Changes from v3: * No change Changes from v2: * Patch newly added to the series arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi | 43 ++++++++++++++++++++++ 1 file changed, 43 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi b/arch/arm64/boot/d= ts/ti/k3-j721s2-main.dtsi index 96e7dcc5ebad..8184391647d5 100644 --- a/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi @@ -851,6 +851,49 @@ }; }; =20 + pcie1_rc: pcie@2910000 { + compatible =3D "ti,j7200-pcie-host", "ti,j721e-pcie-host"; + reg =3D <0x00 0x02910000 0x00 0x1000>, + <0x00 0x02917000 0x00 0x400>, + <0x00 0x0d800000 0x00 0x00800000>, + <0x00 0x18000000 0x00 0x00001000>; + reg-names =3D "intd_cfg", "user_cfg", "reg", "cfg"; + interrupt-names =3D "link_state"; + interrupts =3D ; + device_type =3D "pci"; + ti,syscon-pcie-ctrl =3D <&scm_conf 0x074>; + max-link-speed =3D <3>; + num-lanes =3D <4>; + power-domains =3D <&k3_pds 276 TI_SCI_PD_EXCLUSIVE>; + clocks =3D <&k3_clks 276 41>; + clock-names =3D "fck"; + #address-cells =3D <3>; + #size-cells =3D <2>; + bus-range =3D <0x0 0xff>; + vendor-id =3D <0x104c>; + device-id =3D <0xb013>; + msi-map =3D <0x0 &gic_its 0x0 0x10000>; + dma-coherent; + ranges =3D <0x01000000 0x0 0x18001000 0x00 0x18001000 0x0 0x0010000>, + <0x02000000 0x0 0x18011000 0x00 0x18011000 0x0 0x7fef000>; + dma-ranges =3D <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>; + #interrupt-cells =3D <1>; + interrupt-map-mask =3D <0 0 0 7>; + interrupt-map =3D <0 0 0 1 &pcie1_intc 0>, /* INT A */ + <0 0 0 2 &pcie1_intc 0>, /* INT B */ + <0 0 0 3 &pcie1_intc 0>, /* INT C */ + <0 0 0 4 &pcie1_intc 0>; /* INT D */ + + status =3D "disabled"; + + pcie1_intc: interrupt-controller { + interrupt-controller; + #interrupt-cells =3D <1>; + interrupt-parent =3D <&gic500>; + interrupts =3D ; + }; + }; + main_mcan0: can@2701000 { compatible =3D "bosch,m_can"; reg =3D <0x00 0x02701000 0x00 0x200>, --=20 2.17.1 From nobody Sat Apr 11 04:15:22 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id A7411C7EE30 for ; Wed, 1 Mar 2023 09:13:24 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229818AbjCAJNX (ORCPT ); Wed, 1 Mar 2023 04:13:23 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:35366 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229777AbjCAJNI (ORCPT ); Wed, 1 Mar 2023 04:13:08 -0500 Received: from fllv0016.ext.ti.com (fllv0016.ext.ti.com [198.47.19.142]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 1BA833B65B; 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Wed, 1 Mar 2023 03:12:14 -0600 Received: from uda0500640.dal.design.ti.com (ileaxei01-snat2.itg.ti.com [10.180.69.6]) by lelv0327.itg.ti.com (8.15.2/8.15.2) with ESMTP id 3219BbbH088843; Wed, 1 Mar 2023 03:12:10 -0600 From: Ravi Gunasekaran To: , , , , , , , , CC: , , Subject: [PATCH v12 8/8] arm64: dts: ti: k3-j721s2-common-proc-board: Enable PCIe Date: Wed, 1 Mar 2023 14:41:36 +0530 Message-ID: <20230301091136.17862-9-r-gunasekaran@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230301091136.17862-1-r-gunasekaran@ti.com> References: <20230301091136.17862-1-r-gunasekaran@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Aswath Govindraju x1 lane PCIe slot in the common processor board is enabled and connected to J721S2 SOM. Add PCIe DT node in common processor board to reflect the same. Reviewed-by: Siddharth Vadapalli Signed-off-by: Aswath Govindraju Signed-off-by: Vignesh Raghavendra Signed-off-by: Matt Ranostay Signed-off-by: Ravi Gunasekaran --- Changes from v11: * No change Changes from v10: * Removed Link tag from commit message Changes from v9: * No change Changes from v8: * No change Changes from v7: * No change Changes from v6: * Removed pcie_ep node update Changes from v5: * No change Changes from v4: * No change Changes from v3: * No change Changes from v2: * Patch newly added to the series arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts b/arch/= arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts index 6bd6370e5bae..83be4a1b61cb 100644 --- a/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts +++ b/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts @@ -384,6 +384,14 @@ }; }; =20 +&pcie1_rc { + status =3D "okay"; + reset-gpios =3D <&exp1 2 GPIO_ACTIVE_HIGH>; + phys =3D <&serdes0_pcie_link>; + phy-names =3D "pcie-phy"; + num-lanes =3D <1>; +}; + &mcu_mcan0 { status =3D "okay"; pinctrl-names =3D "default"; --=20 2.17.1