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[90.112.194.32]) by smtp.gmail.com with ESMTPSA id p25-20020a05600c1d9900b003e71a6be279sm13272391wms.37.2023.02.28.07.47.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 28 Feb 2023 07:47:33 -0800 (PST) From: Alexandre Ghiti To: Jonathan Corbet , Paul Walmsley , Palmer Dabbelt , Albert Ou , Conor Dooley , Ard Biesheuvel , =?UTF-8?q?Bj=C3=B6rn=20T=C3=B6pel?= , linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org Cc: Alexandre Ghiti , =?UTF-8?q?Bj=C3=B6rn=20T=C3=B6pel?= Subject: [PATCH v8 1/1] riscv: Allow to downgrade paging mode from the command line Date: Tue, 28 Feb 2023 16:46:29 +0100 Message-Id: <20230228154629.240541-2-alexghiti@rivosinc.com> X-Mailer: git-send-email 2.37.2 In-Reply-To: <20230228154629.240541-1-alexghiti@rivosinc.com> References: <20230228154629.240541-1-alexghiti@rivosinc.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add 2 early command line parameters that allow to downgrade satp mode (using the same naming as x86): - "no5lvl": use a 4-level page table (down from sv57 to sv48) - "no4lvl": use a 3-level page table (down from sv57/sv48 to sv39) Note that going through the device tree to get the kernel command line works with ACPI too since the efi stub creates a device tree anyway with the command line. In KASAN kernels, we can't use the libfdt that early in the boot process since we are not ready to execute instrumented functions. So instead of using the "generic" libfdt, we compile our own versions of those functions that are not instrumented and that are prefixed so that they do not conflict with the generic ones. We also need the non-instrumented versions of the string functions and the prefixed versions of memcpy/memmove. This is largely inspired by commit aacd149b6238 ("arm64: head: avoid relocating the kernel twice for KASLR") from which I removed compilation flags that were not relevant to RISC-V at the moment (LTO, SCS, pie). Signed-off-by: Alexandre Ghiti Tested-by: Bj=C3=B6rn T=C3=B6pel Reviewed-by: Bj=C3=B6rn T=C3=B6pel --- .../admin-guide/kernel-parameters.txt | 5 +- arch/riscv/kernel/Makefile | 2 + arch/riscv/kernel/pi/Makefile | 37 +++++++++++ arch/riscv/kernel/pi/cmdline_early.c | 62 +++++++++++++++++++ arch/riscv/kernel/vmlinux.lds.S | 8 +++ arch/riscv/lib/memcpy.S | 2 + arch/riscv/lib/memmove.S | 2 + arch/riscv/lib/strlen.S | 1 + arch/riscv/mm/init.c | 36 +++++++++-- 9 files changed, 148 insertions(+), 7 deletions(-) create mode 100644 arch/riscv/kernel/pi/Makefile create mode 100644 arch/riscv/kernel/pi/cmdline_early.c diff --git a/Documentation/admin-guide/kernel-parameters.txt b/Documentatio= n/admin-guide/kernel-parameters.txt index 6cfa6e3996cf..1d8fc66d2b0d 100644 --- a/Documentation/admin-guide/kernel-parameters.txt +++ b/Documentation/admin-guide/kernel-parameters.txt @@ -3578,7 +3578,10 @@ emulation library even if a 387 maths coprocessor is present. =20 - no5lvl [X86-64] Disable 5-level paging mode. Forces + no4lvl [RISCV] Disable 4-level and 5-level paging modes. Forces + kernel to use 3-level paging instead. + + no5lvl [X86-64,RISCV] Disable 5-level paging mode. Forces kernel to use 4-level paging instead. =20 nofsgsbase [X86] Disables FSGSBASE instructions. diff --git a/arch/riscv/kernel/Makefile b/arch/riscv/kernel/Makefile index 4cf303a779ab..aa22f87faeae 100644 --- a/arch/riscv/kernel/Makefile +++ b/arch/riscv/kernel/Makefile @@ -89,3 +89,5 @@ obj-$(CONFIG_EFI) +=3D efi.o obj-$(CONFIG_COMPAT) +=3D compat_syscall_table.o obj-$(CONFIG_COMPAT) +=3D compat_signal.o obj-$(CONFIG_COMPAT) +=3D compat_vdso/ + +obj-$(CONFIG_64BIT) +=3D pi/ diff --git a/arch/riscv/kernel/pi/Makefile b/arch/riscv/kernel/pi/Makefile new file mode 100644 index 000000000000..4002ed94b6d3 --- /dev/null +++ b/arch/riscv/kernel/pi/Makefile @@ -0,0 +1,37 @@ +# SPDX-License-Identifier: GPL-2.0 +# This file was copied from arm64/kernel/pi/Makefile. + +KBUILD_CFLAGS :=3D $(subst $(CC_FLAGS_FTRACE),,$(KBUILD_CFLAGS)) \ + -Os -DDISABLE_BRANCH_PROFILING $(DISABLE_STACKLEAK_PLUGIN) \ + $(call cc-option,-mbranch-protection=3Dnone) \ + -I$(srctree)/scripts/dtc/libfdt -fno-stack-protector \ + -D__DISABLE_EXPORTS -ffreestanding \ + -fno-asynchronous-unwind-tables -fno-unwind-tables \ + $(call cc-option,-fno-addrsig) + +CFLAGS_cmdline_early.o +=3D -D__NO_FORTIFY +CFLAGS_lib-fdt_ro.o +=3D -D__NO_FORTIFY + +GCOV_PROFILE :=3D n +KASAN_SANITIZE :=3D n +KCSAN_SANITIZE :=3D n +UBSAN_SANITIZE :=3D n +KCOV_INSTRUMENT :=3D n + +$(obj)/%.pi.o: OBJCOPYFLAGS :=3D --prefix-symbols=3D__pi_ \ + --remove-section=3D.note.gnu.property \ + --prefix-alloc-sections=3D.init +$(obj)/%.pi.o: $(obj)/%.o FORCE + $(call if_changed,objcopy) + +$(obj)/lib-%.o: $(srctree)/lib/%.c FORCE + $(call if_changed_rule,cc_o_c) + +$(obj)/string.o: $(srctree)/lib/string.c FORCE + $(call if_changed_rule,cc_o_c) + +$(obj)/ctype.o: $(srctree)/lib/ctype.c FORCE + $(call if_changed_rule,cc_o_c) + +obj-y :=3D cmdline_early.pi.o string.pi.o ctype.pi.o lib-fdt.pi.o lib-fdt= _ro.pi.o +extra-y :=3D $(patsubst %.pi.o,%.o,$(obj-y)) diff --git a/arch/riscv/kernel/pi/cmdline_early.c b/arch/riscv/kernel/pi/cm= dline_early.c new file mode 100644 index 000000000000..05652d13c746 --- /dev/null +++ b/arch/riscv/kernel/pi/cmdline_early.c @@ -0,0 +1,62 @@ +// SPDX-License-Identifier: GPL-2.0-only +#include +#include +#include +#include +#include +#include + +static char early_cmdline[COMMAND_LINE_SIZE]; + +/* + * Declare the functions that are exported (but prefixed) here so that LLVM + * does not complain it lacks the 'static' keyword (which, if added, makes + * LLVM complain because the function is actually unused in this file). + */ +u64 set_satp_mode_from_cmdline(uintptr_t dtb_pa); + +static char *get_early_cmdline(uintptr_t dtb_pa) +{ + const char *fdt_cmdline =3D NULL; + unsigned int fdt_cmdline_size =3D 0; + int chosen_node; + + if (!IS_ENABLED(CONFIG_CMDLINE_FORCE)) { + chosen_node =3D fdt_path_offset((void *)dtb_pa, "/chosen"); + if (chosen_node >=3D 0) { + fdt_cmdline =3D fdt_getprop((void *)dtb_pa, chosen_node, + "bootargs", NULL); + if (fdt_cmdline) { + fdt_cmdline_size =3D strlen(fdt_cmdline); + strscpy(early_cmdline, fdt_cmdline, + COMMAND_LINE_SIZE); + } + } + } + + if (IS_ENABLED(CONFIG_CMDLINE_EXTEND) || + IS_ENABLED(CONFIG_CMDLINE_FORCE) || + fdt_cmdline_size =3D=3D 0 /* CONFIG_CMDLINE_FALLBACK */) { + strncat(early_cmdline, CONFIG_CMDLINE, + COMMAND_LINE_SIZE - fdt_cmdline_size); + } + + return early_cmdline; +} + +static u64 match_noXlvl(char *cmdline) +{ + if (strstr(cmdline, "no4lvl")) + return SATP_MODE_48; + else if (strstr(cmdline, "no5lvl")) + return SATP_MODE_57; + + return 0; +} + +u64 set_satp_mode_from_cmdline(uintptr_t dtb_pa) +{ + char *cmdline =3D get_early_cmdline(dtb_pa); + + return match_noXlvl(cmdline); +} diff --git a/arch/riscv/kernel/vmlinux.lds.S b/arch/riscv/kernel/vmlinux.ld= s.S index b2813b5e47a0..21d402e65e26 100644 --- a/arch/riscv/kernel/vmlinux.lds.S +++ b/arch/riscv/kernel/vmlinux.lds.S @@ -87,6 +87,14 @@ SECTIONS /* Start of init data section */ __init_data_begin =3D .; INIT_DATA_SECTION(16) + + /* Those sections result from the compilation of kernel/pi/string.c */ + .init.pidata : { + *(.init.srodata.cst8*) + *(.init__bug_table*) + *(.init.sdata*) + } + .init.bss : { *(.init.bss) /* from the EFI stub */ } diff --git a/arch/riscv/lib/memcpy.S b/arch/riscv/lib/memcpy.S index 51ab716253fa..1a40d01a9543 100644 --- a/arch/riscv/lib/memcpy.S +++ b/arch/riscv/lib/memcpy.S @@ -106,3 +106,5 @@ WEAK(memcpy) 6: ret END(__memcpy) +SYM_FUNC_ALIAS(__pi_memcpy, __memcpy) +SYM_FUNC_ALIAS(__pi___memcpy, __memcpy) diff --git a/arch/riscv/lib/memmove.S b/arch/riscv/lib/memmove.S index e0609e1f0864..838ff2022fe3 100644 --- a/arch/riscv/lib/memmove.S +++ b/arch/riscv/lib/memmove.S @@ -314,3 +314,5 @@ return_from_memmove: =20 SYM_FUNC_END(memmove) SYM_FUNC_END(__memmove) +SYM_FUNC_ALIAS(__pi_memmove, __memmove) +SYM_FUNC_ALIAS(__pi___memmove, __memmove) diff --git a/arch/riscv/lib/strlen.S b/arch/riscv/lib/strlen.S index 8345ceeee3f6..ed43be976134 100644 --- a/arch/riscv/lib/strlen.S +++ b/arch/riscv/lib/strlen.S @@ -131,3 +131,4 @@ strlen_zbb: .option pop #endif SYM_FUNC_END(strlen) +SYM_FUNC_ALIAS(__pi_strlen, strlen) diff --git a/arch/riscv/mm/init.c b/arch/riscv/mm/init.c index 478d6763a01a..70c7fc566f63 100644 --- a/arch/riscv/mm/init.c +++ b/arch/riscv/mm/init.c @@ -732,6 +732,8 @@ static __init pgprot_t pgprot_from_va(uintptr_t va) #endif /* CONFIG_STRICT_KERNEL_RWX */ =20 #if defined(CONFIG_64BIT) && !defined(CONFIG_XIP_KERNEL) +u64 __pi_set_satp_mode_from_cmdline(uintptr_t dtb_pa); + static void __init disable_pgtable_l5(void) { pgtable_l5_enabled =3D false; @@ -746,17 +748,39 @@ static void __init disable_pgtable_l4(void) satp_mode =3D SATP_MODE_39; } =20 +static int __init print_no4lvl(char *p) +{ + pr_info("Disabled 4-level and 5-level paging"); + return 0; +} +early_param("no4lvl", print_no4lvl); + +static int __init print_no5lvl(char *p) +{ + pr_info("Disabled 5-level paging"); + return 0; +} +early_param("no5lvl", print_no5lvl); + /* * There is a simple way to determine if 4-level is supported by the * underlying hardware: establish 1:1 mapping in 4-level page table mode * then read SATP to see if the configuration was taken into account * meaning sv48 is supported. */ -static __init void set_satp_mode(void) +static __init void set_satp_mode(uintptr_t dtb_pa) { u64 identity_satp, hw_satp; uintptr_t set_satp_mode_pmd =3D ((unsigned long)set_satp_mode) & PMD_MASK; - bool check_l4 =3D false; + u64 satp_mode_cmdline =3D __pi_set_satp_mode_from_cmdline(dtb_pa); + + if (satp_mode_cmdline =3D=3D SATP_MODE_57) { + disable_pgtable_l5(); + } else if (satp_mode_cmdline =3D=3D SATP_MODE_48) { + disable_pgtable_l5(); + disable_pgtable_l4(); + return; + } =20 create_p4d_mapping(early_p4d, set_satp_mode_pmd, (uintptr_t)early_pud, @@ -775,7 +799,8 @@ static __init void set_satp_mode(void) retry: create_pgd_mapping(early_pg_dir, set_satp_mode_pmd, - check_l4 ? (uintptr_t)early_pud : (uintptr_t)early_p4d, + pgtable_l5_enabled ? + (uintptr_t)early_p4d : (uintptr_t)early_pud, PGDIR_SIZE, PAGE_TABLE); =20 identity_satp =3D PFN_DOWN((uintptr_t)&early_pg_dir) | satp_mode; @@ -786,9 +811,8 @@ static __init void set_satp_mode(void) local_flush_tlb_all(); =20 if (hw_satp !=3D identity_satp) { - if (!check_l4) { + if (pgtable_l5_enabled) { disable_pgtable_l5(); - check_l4 =3D true; memset(early_pg_dir, 0, PAGE_SIZE); goto retry; } @@ -979,7 +1003,7 @@ asmlinkage void __init setup_vm(uintptr_t dtb_pa) #endif =20 #if defined(CONFIG_64BIT) && !defined(CONFIG_XIP_KERNEL) - set_satp_mode(); + set_satp_mode(dtb_pa); #endif =20 kernel_map.va_pa_offset =3D PAGE_OFFSET - kernel_map.phys_addr; --=20 2.37.2