From nobody Sat Sep 21 04:40:00 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id AC788C64ED6 for ; Tue, 28 Feb 2023 10:48:06 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229797AbjB1KsF (ORCPT ); Tue, 28 Feb 2023 05:48:05 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:60874 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230220AbjB1Krx (ORCPT ); Tue, 28 Feb 2023 05:47:53 -0500 Received: from madras.collabora.co.uk (madras.collabora.co.uk [46.235.227.172]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 8C49F2108; Tue, 28 Feb 2023 02:47:52 -0800 (PST) Received: from IcarusMOD.eternityproject.eu (2-237-20-237.ip236.fastwebnet.it [2.237.20.237]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: kholk11) by madras.collabora.co.uk (Postfix) with ESMTPSA id E106E6602FDA; Tue, 28 Feb 2023 10:47:50 +0000 (GMT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1677581271; bh=lArSKCx17mh1O30bNJ4tPf+I/p5uXQpXGMq90jh0j/I=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=OWM8GNat2cxz2dHig+YugKoL+OwAddx+1YznjJbNxnFhTFXspLxH6Dy8FDq+jOA+K xtgtptCoLnOc3iLfGHxYuTQEBIbgLRsBCg0+QxL9KmQ8NPZq47vcKMNz8glpon+/bj dKalxWeJIqHFmg/dtfgl3NY1gYcxP4VpAgFZAwvgCykLjxSdelXoqZE0QpZdJZnbX/ YIPUJqXJYiCZLPPYoXgJO0/4mGr4CIURa8oX6q0Ar9ImBiy5AlMxFLsMe4RvVH1OiT 38mD8GR5LzccWvMr9szI6SNtknO51dwE5D/Qn1HmViPM9snCYMWgOxkY6NR2K9RSIm WwwWJotS+u4+Q== From: AngeloGioacchino Del Regno To: matthias.bgg@gmail.com Cc: robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, angelogioacchino.delregno@collabora.com, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, wenst@chromium.org Subject: [PATCH v3 03/18] arm64: dts: mediatek: mt8183: Remove second opp-microvolt entries from gpu table Date: Tue, 28 Feb 2023 11:47:26 +0100 Message-Id: <20230228104741.717819-4-angelogioacchino.delregno@collabora.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230228104741.717819-1-angelogioacchino.delregno@collabora.com> References: <20230228104741.717819-1-angelogioacchino.delregno@collabora.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" This was done to keep a strict relation between VSRAM and VGPU, but it never worked: now we're doing it transparently with the new mediatek-regulator-coupler driver. Signed-off-by: AngeloGioacchino Del Regno Reviewed-by: Chen-Yu Tsai --- arch/arm64/boot/dts/mediatek/mt8183.dtsi | 32 ++++++++++++------------ 1 file changed, 16 insertions(+), 16 deletions(-) diff --git a/arch/arm64/boot/dts/mediatek/mt8183.dtsi b/arch/arm64/boot/dts= /mediatek/mt8183.dtsi index 3d1d7870a5f1..e01b96adef02 100644 --- a/arch/arm64/boot/dts/mediatek/mt8183.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8183.dtsi @@ -563,82 +563,82 @@ gpu_opp_table: opp-table-0 { =20 opp-300000000 { opp-hz =3D /bits/ 64 <300000000>; - opp-microvolt =3D <625000>, <850000>; + opp-microvolt =3D <625000>; }; =20 opp-320000000 { opp-hz =3D /bits/ 64 <320000000>; - opp-microvolt =3D <631250>, <850000>; + opp-microvolt =3D <631250>; }; =20 opp-340000000 { opp-hz =3D /bits/ 64 <340000000>; - opp-microvolt =3D <637500>, <850000>; + opp-microvolt =3D <637500>; }; =20 opp-360000000 { opp-hz =3D /bits/ 64 <360000000>; - opp-microvolt =3D <643750>, <850000>; + opp-microvolt =3D <643750>; }; =20 opp-380000000 { opp-hz =3D /bits/ 64 <380000000>; - opp-microvolt =3D <650000>, <850000>; + opp-microvolt =3D <650000>; }; =20 opp-400000000 { opp-hz =3D /bits/ 64 <400000000>; - opp-microvolt =3D <656250>, <850000>; + opp-microvolt =3D <656250>; }; =20 opp-420000000 { opp-hz =3D /bits/ 64 <420000000>; - opp-microvolt =3D <662500>, <850000>; + opp-microvolt =3D <662500>; }; =20 opp-460000000 { opp-hz =3D /bits/ 64 <460000000>; - opp-microvolt =3D <675000>, <850000>; + opp-microvolt =3D <675000>; }; =20 opp-500000000 { opp-hz =3D /bits/ 64 <500000000>; - opp-microvolt =3D <687500>, <850000>; + opp-microvolt =3D <687500>; }; =20 opp-540000000 { opp-hz =3D /bits/ 64 <540000000>; - opp-microvolt =3D <700000>, <850000>; + opp-microvolt =3D <700000>; }; =20 opp-580000000 { opp-hz =3D /bits/ 64 <580000000>; - opp-microvolt =3D <712500>, <850000>; + opp-microvolt =3D <712500>; }; =20 opp-620000000 { opp-hz =3D /bits/ 64 <620000000>; - opp-microvolt =3D <725000>, <850000>; + opp-microvolt =3D <725000>; }; =20 opp-653000000 { opp-hz =3D /bits/ 64 <653000000>; - opp-microvolt =3D <743750>, <850000>; + opp-microvolt =3D <743750>; }; =20 opp-698000000 { opp-hz =3D /bits/ 64 <698000000>; - opp-microvolt =3D <768750>, <868750>; + opp-microvolt =3D <768750>; }; =20 opp-743000000 { opp-hz =3D /bits/ 64 <743000000>; - opp-microvolt =3D <793750>, <893750>; + opp-microvolt =3D <793750>; }; =20 opp-800000000 { opp-hz =3D /bits/ 64 <800000000>; - opp-microvolt =3D <825000>, <925000>; + opp-microvolt =3D <825000>; }; }; =20 --=20 2.39.2