From nobody Sat Sep 21 03:08:52 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id EFDA2C64EC7 for ; Tue, 28 Feb 2023 07:30:04 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229981AbjB1HaD (ORCPT ); Tue, 28 Feb 2023 02:30:03 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:50618 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229835AbjB1H3u (ORCPT ); Tue, 28 Feb 2023 02:29:50 -0500 Received: from mail-lf1-x12c.google.com (mail-lf1-x12c.google.com [IPv6:2a00:1450:4864:20::12c]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 49D96EFAC; Mon, 27 Feb 2023 23:29:48 -0800 (PST) Received: by mail-lf1-x12c.google.com with SMTP id k14so11885364lfj.7; Mon, 27 Feb 2023 23:29:48 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=anJfvBlE+shc2bmOxourHefmds/BtxwdudHBi4fTMDE=; b=EJeNyNiEouLJCSo+lYCJumat2GRI7N0vyjv8gKfz5S/MY6+HDt6Sh5XFI1LczHt3oV X1jKFx3jWBMjMIJJmSe4+pF73SGPCR4t3n/DQmb7XpDsQJt7V4YywVYSHV2bpn4fgIef w35lEOCB1eeUBYKpsjlbUtjBvceAB7+sgHaOHs3WqLIrdQ4Xx6XfscB0G6d5MFDgqZEi RLDJnDfPsaLqDq10l1EHb/c4XEgrORIJ+WnLIiCb/WdGCobFNM5tghacSO7jXxSiOuw5 hIcpqxXeoZ6HkP/HY1YdRx5P2EMtTwXJnlb5r3ZIF29YHB1KRrff4r2KnvwwKXgnEHse xPaw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=anJfvBlE+shc2bmOxourHefmds/BtxwdudHBi4fTMDE=; b=e+HqO/FxUGSzyH5xV2mbyJsukeM1KSYpIwjXNkLzf7T4qYNnYM56a+xmWucSkZDo0k L7JAWyQqezysXxPD2hpKopWKd69c01q4mW2lbIaoQBz4YSYrRmv6YD+HsERAGHNxyHet fuzT78TbijYqItPHrDU2Ds1iKEz0iVx8MPGSxuEkwXYbSVoCFhjTDhTdL1bTT09soTwi Gx/Eq9gnNmxmlHpvTvruEvATut1gS1D60O+rhq8QPAxZUkq231kVia5ePdrp1RvpyumY /CFBfpudabe4Hc6PhVRiChLrvtXJF4y6DjL+doWsGO4/1O5CMrziZoolRcFVne71rO4m m9qA== X-Gm-Message-State: AO0yUKUCyfY84g8x4V2lbDd+/i/ni2wsfdFVi7SO/xvjQqBjemu3TX+N gR4QgTedwvld5fUgN/sjgzw= X-Google-Smtp-Source: AK7set/QtguLI5ukTkiUykG2VdzDxDgGFtQnX9xt1e+GexfGmgk3wXArPR+umYOM4/Qgy/igZSM+Sg== X-Received: by 2002:ac2:5215:0:b0:4e1:7209:c09f with SMTP id a21-20020ac25215000000b004e17209c09fmr476595lfl.66.1677569386447; Mon, 27 Feb 2023 23:29:46 -0800 (PST) Received: from localhost.lan (ip-194-187-74-233.konfederacka.maverick.com.pl. [194.187.74.233]) by smtp.gmail.com with ESMTPSA id l2-20020ac25542000000b004d85a7e8b17sm1229550lfk.269.2023.02.27.23.29.45 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 27 Feb 2023 23:29:46 -0800 (PST) From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= To: Srinivas Kandagatla , Rob Herring , Krzysztof Kozlowski Cc: Matthias Brugger , Kunihiko Hayashi , Masami Hiramatsu , linux-mediatek@lists.infradead.org, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= , Rob Herring Subject: [PATCH V4 1/2] dt-bindings: nvmem: mmio: new binding for MMIO accessible NVMEM devices Date: Tue, 28 Feb 2023 08:29:35 +0100 Message-Id: <20230228072936.1108-2-zajec5@gmail.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230228072936.1108-1-zajec5@gmail.com> References: <20230228072936.1108-1-zajec5@gmail.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Rafa=C5=82 Mi=C5=82ecki Content of some NVMEM devices can be read using MMIO. Some of them (probably very few though) may be also programmable that way. Add generic binding to allow describing such hardware. This *doesn't* apply to any more complicated devices that need more complex interface e.g. for writing. While such devices could be supported for reading purposes by the same driver - they should get their own binding. This binding will gain even more usability once we fully support NVMEM layouts (describing content of NVMEM devices in an independent way). Signed-off-by: Rafa=C5=82 Mi=C5=82ecki Reviewed-by: Rob Herring --- V3: Make it clear this binding should NOT be used for more complex devices --- .../devicetree/bindings/nvmem/mmio.yaml | 50 +++++++++++++++++++ 1 file changed, 50 insertions(+) create mode 100644 Documentation/devicetree/bindings/nvmem/mmio.yaml diff --git a/Documentation/devicetree/bindings/nvmem/mmio.yaml b/Documentat= ion/devicetree/bindings/nvmem/mmio.yaml new file mode 100644 index 000000000000..9ca96b7a4856 --- /dev/null +++ b/Documentation/devicetree/bindings/nvmem/mmio.yaml @@ -0,0 +1,50 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/nvmem/mmio.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: MMIO access based NVMEM + +description: | + This binding describes simple NVMEM devices with content that can be acc= essed + using MMIO (memory-mapped I/O access). + + More complex devices that support any other access than a simple memory + mapping should use a custom binding. In such cases this binding's compat= ible + should NOT be used even as a fallback. + + This binding is designed to describe just an NVMEM content access method= . The + way of handling actual content should be described independently (on top= of + this binding). + +maintainers: + - Rafa=C5=82 Mi=C5=82ecki + +allOf: + - $ref: nvmem.yaml# + +properties: + compatible: + const: mmio-nvmem + + reg: + maxItems: 1 + + reg-io-width: + description: | + The size (in bytes) of the IO accesses that should be performed + on the device. + enum: [1, 2, 4, 8] + +required: + - reg + +unevaluatedProperties: false + +examples: + - | + nvmem@10000 { + compatible =3D "mmio-nvmem"; + reg =3D <0x10000000 0x10000>; + }; --=20 2.34.1 From nobody Sat Sep 21 03:08:52 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6839AC64ED6 for ; Tue, 28 Feb 2023 07:30:08 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229931AbjB1HaG (ORCPT ); Tue, 28 Feb 2023 02:30:06 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:50640 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229841AbjB1H3v (ORCPT ); Tue, 28 Feb 2023 02:29:51 -0500 Received: from mail-lf1-x130.google.com (mail-lf1-x130.google.com [IPv6:2a00:1450:4864:20::130]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 0BA6CC677; Mon, 27 Feb 2023 23:29:50 -0800 (PST) Received: by mail-lf1-x130.google.com with SMTP id m7so11896433lfj.8; Mon, 27 Feb 2023 23:29:49 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=IsqApEBQlKEPGyVsiuZgMJvp51SjT+jXo8h7J6aTlqU=; b=DBHZA2u5l6sYOQBXU/2/qGXgWNfm4q9o6T31R/JnTWDO8+FcoSjDjHBXuWpemTIAJ2 zZnTHkzXpgOcUctUStUU7PVZpT45yuNXpJjl9/QvKceCBhaN5wDdBpWNxfKAl09oI14X 3+M3Q2qL3o0bj/0SBM4rca658rXwm18o+nxUHCLvSgGwWtqnnxK7UsLOn4+EQCzLZPEt ZJ10IHLfgOWy9SHq4uqPd8X4t9WhlQ/X/MYiVW2LfGLwdznLxMeo3E32a6gmxjVSLwdA fuw50Xk3ahyQ9LaKxVQkfTfdfOc0mIb1Q70ZL0FYsdkbHsF+jPPLKWLm0vaETbpt3c3u PcKQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=IsqApEBQlKEPGyVsiuZgMJvp51SjT+jXo8h7J6aTlqU=; b=rhakyfkN3IWXNr0uma+JReRBTpdCw0/kK+GBy0yej71s8yGsa2x0GqHSxuYCmSukqO nYMI7oDgVGiLDWnQm0SPoBsPhCc6Y2ByQ3Qk0ptqK6sYGlc3H9AdRoyiQ/GOy0Mcwod6 QsNJ6KxpG4L9FgkUm8NKkCbNv+pslhzIPQ+xT0eN0+tPF0OsQm/m8eREv5XGTc8B9b3T etPKlF3ibonPxP3BlNnu1LK+skgoiiGd0216ILShneVa0Z71kkNid6CjSgLxdJhm0qJJ DkZBDdngRQ8YHeBgYGZXhsOJ4ku9GZcMmSbhj3ZC2l1gZARuMCDrH0YmsyT7p7Upkw9h D+1A== X-Gm-Message-State: AO0yUKV4Ad3sugVWHrqi9/61VccDuPfdBLs0op4Me0PjgKW7A111EkTp K3pUNXqS4FuGTJ79ZYf0BEA= X-Google-Smtp-Source: AK7set/BRw5MnHT0rZU7iDo8+O3cRX17DDUeYCp+iZHDDfDmN9WEg14Yor2SJOus5mnaGa3ZPRsN2A== X-Received: by 2002:ac2:4117:0:b0:4db:4b7a:d6de with SMTP id b23-20020ac24117000000b004db4b7ad6demr410780lfi.63.1677569388255; Mon, 27 Feb 2023 23:29:48 -0800 (PST) Received: from localhost.lan (ip-194-187-74-233.konfederacka.maverick.com.pl. [194.187.74.233]) by smtp.gmail.com with ESMTPSA id l2-20020ac25542000000b004d85a7e8b17sm1229550lfk.269.2023.02.27.23.29.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 27 Feb 2023 23:29:47 -0800 (PST) From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= To: Srinivas Kandagatla , Rob Herring , Krzysztof Kozlowski Cc: Matthias Brugger , Kunihiko Hayashi , Masami Hiramatsu , linux-mediatek@lists.infradead.org, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= Subject: [PATCH V4 2/2] nvmem: add generic driver for devices with MMIO access Date: Tue, 28 Feb 2023 08:29:36 +0100 Message-Id: <20230228072936.1108-3-zajec5@gmail.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230228072936.1108-1-zajec5@gmail.com> References: <20230228072936.1108-1-zajec5@gmail.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Rafa=C5=82 Mi=C5=82ecki Some NVMEM devices can be accessed by simply mapping memory and reading from / writing to it. This driver adds support for a generic "mmio-nvmem" DT binding used by such devices. One of such devices is Broadcom's NVRAM. It's already supported (see NVMEM_BRCM_NVRAM) but existing driver covers both: 1. NVMEM device access 2. NVMEM content parsing Once we get support for NVMEM layouts then existing NVRAM driver will get converted into a layout and generic driver will take over responsibility for data access. Signed-off-by: Rafa=C5=82 Mi=C5=82ecki --- V3: Support "reg-io-width", basic writing & "brcm,nvram" string V3: Don't duplicate core checks, add 64 b support, complete writing support, don't add confusing conditional "brcm,nvram" support (it will be handled with layouts migration) --- drivers/nvmem/Kconfig | 10 +++ drivers/nvmem/Makefile | 2 + drivers/nvmem/mmio.c | 148 +++++++++++++++++++++++++++++++++++++++++ 3 files changed, 160 insertions(+) create mode 100644 drivers/nvmem/mmio.c diff --git a/drivers/nvmem/Kconfig b/drivers/nvmem/Kconfig index 6dec38805041..189ea85bd67d 100644 --- a/drivers/nvmem/Kconfig +++ b/drivers/nvmem/Kconfig @@ -166,6 +166,16 @@ config NVMEM_MICROCHIP_OTPC This driver enable the OTP controller available on Microchip SAMA7G5 SoCs. It controls the access to the OTP memory connected to it. =20 +config NVMEM_MMIO + tristate "MMIO access based NVMEM support" + depends on HAS_IOMEM + help + This driver provides support for NVMEM devices that can be accessed + using MMIO. + + This driver can also be built as a module. If so, the module + will be called nvmem-mmio. + config NVMEM_MTK_EFUSE tristate "Mediatek SoCs EFUSE support" depends on ARCH_MEDIATEK || COMPILE_TEST diff --git a/drivers/nvmem/Makefile b/drivers/nvmem/Makefile index 6a1efffa88f0..767a9db2bfc1 100644 --- a/drivers/nvmem/Makefile +++ b/drivers/nvmem/Makefile @@ -35,6 +35,8 @@ obj-$(CONFIG_NVMEM_MESON_MX_EFUSE) +=3D nvmem_meson_mx_ef= use.o nvmem_meson_mx_efuse-y :=3D meson-mx-efuse.o obj-$(CONFIG_NVMEM_MICROCHIP_OTPC) +=3D nvmem-microchip-otpc.o nvmem-microchip-otpc-y :=3D microchip-otpc.o +obj-$(CONFIG_NVMEM_MMIO) +=3D nvmem-mmio.o +nvmem-mmio-y :=3D mmio.o obj-$(CONFIG_NVMEM_MTK_EFUSE) +=3D nvmem_mtk-efuse.o nvmem_mtk-efuse-y :=3D mtk-efuse.o obj-$(CONFIG_NVMEM_MXS_OCOTP) +=3D nvmem-mxs-ocotp.o diff --git a/drivers/nvmem/mmio.c b/drivers/nvmem/mmio.c new file mode 100644 index 000000000000..ce51648bb321 --- /dev/null +++ b/drivers/nvmem/mmio.c @@ -0,0 +1,148 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2023 Rafa=C5=82 Mi=C5=82ecki + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +struct mmio_nvmem { + void __iomem *base; + u32 io_width; +}; + +static int mmio_nvmem_read(void *context, unsigned int offset, void *val, = size_t bytes) +{ + struct mmio_nvmem *priv =3D context; + u64 __maybe_unused *dst64; + u32 *dst32; + u16 *dst16; + u8 *dst8; + + switch (priv->io_width) { + case 0: + memcpy_fromio(val, priv->base + offset, bytes); + break; + case 1: + for (dst8 =3D val; bytes; bytes -=3D 1, offset +=3D 1) + *dst8++ =3D readb(priv->base + offset); + break; + case 2: + for (dst16 =3D val; bytes; bytes -=3D 2, offset +=3D 2) + *dst16++ =3D readw(priv->base + offset); + break; + case 4: + for (dst32 =3D val; bytes; bytes -=3D 4, offset +=3D 4) + *dst32++ =3D readl(priv->base + offset); + break; +#ifdef CONFIG_64BIT + case 8: + for (dst64 =3D val; bytes; bytes -=3D 8, offset +=3D 8) + *dst64++ =3D readq(priv->base + offset); + break; +#endif + default: + return -EINVAL; + } + + return 0; +} + +static int mmio_nvmem_write(void *context, unsigned int offset, void *val,= size_t bytes) +{ + struct mmio_nvmem *priv =3D context; + u64 __maybe_unused *dst64; + u32 *dst32; + u16 *dst16; + u8 *dst8; + + switch (priv->io_width) { + case 0: + memcpy_toio(priv->base + offset, val, bytes); + break; + case 1: + for (dst8 =3D val; bytes; bytes -=3D 1, offset +=3D 1) + writeb(*dst8++, priv->base + offset); + break; + case 2: + for (dst16 =3D val; bytes; bytes -=3D 2, offset +=3D 2) + writew(*dst16++, priv->base + offset); + break; + case 4: + for (dst32 =3D val; bytes; bytes -=3D 4, offset +=3D 4) + writel(*dst32++, priv->base + offset); + break; +#ifdef CONFIG_64BIT + case 8: + for (dst64 =3D val; bytes; bytes -=3D 8, offset +=3D 8) + writeq(*dst64++, priv->base + offset); + break; +#endif + default: + return -EINVAL; + } + + return 0; +} + +static int mmio_nvmem_probe(struct platform_device *pdev) +{ + struct nvmem_config config =3D { + .name =3D "mmio-nvmem", + .id =3D NVMEM_DEVID_AUTO, + .read_only =3D true, + .reg_read =3D mmio_nvmem_read, + .reg_write =3D mmio_nvmem_write, + }; + struct device *dev =3D &pdev->dev; + struct mmio_nvmem *priv; + struct resource *res; + + priv =3D devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); + if (!priv) + return -ENOMEM; + + priv->base =3D devm_platform_get_and_ioremap_resource(pdev, 0, &res); + if (IS_ERR(priv->base)) + return PTR_ERR(priv->base); + + of_property_read_u32(dev->of_node, "reg-io-width", &priv->io_width); + + config.dev =3D dev; + config.size =3D resource_size(res); + config.word_size =3D priv->io_width; + config.stride =3D priv->io_width; + config.priv =3D priv; + + return PTR_ERR_OR_ZERO(devm_nvmem_register(dev, &config)); +} + +static const struct of_device_id mmio_nvmem_of_match_table[] =3D { + { .compatible =3D "mmio-nvmem", }, + {}, +}; + +static struct platform_driver mmio_nvmem_driver =3D { + .probe =3D mmio_nvmem_probe, + .driver =3D { + .name =3D "mmio_nvmem", + .of_match_table =3D mmio_nvmem_of_match_table, + }, +}; + +static int __init mmio_nvmem_init(void) +{ + return platform_driver_register(&mmio_nvmem_driver); +} + +subsys_initcall_sync(mmio_nvmem_init); + +MODULE_AUTHOR("Rafa=C5=82 Mi=C5=82ecki"); +MODULE_LICENSE("GPL"); +MODULE_DEVICE_TABLE(of, mmio_nvmem_of_match_table); --=20 2.34.1