From nobody Mon Sep 8 19:06:39 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id F136EC7EE2D for ; Sun, 26 Feb 2023 03:15:24 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229504AbjBZDPX (ORCPT ); Sat, 25 Feb 2023 22:15:23 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:38996 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229489AbjBZDPV (ORCPT ); Sat, 25 Feb 2023 22:15:21 -0500 Received: from twspam01.aspeedtech.com (twspam01.aspeedtech.com [211.20.114.71]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id E5CF4FF28; Sat, 25 Feb 2023 19:15:19 -0800 (PST) Received: from mail.aspeedtech.com ([192.168.0.24]) by twspam01.aspeedtech.com with ESMTP id 31Q30CKT025216; Sun, 26 Feb 2023 11:00:12 +0800 (GMT-8) (envelope-from ryan_chen@aspeedtech.com) Received: from aspeedtech.com (192.168.10.13) by TWMBX02.aspeed.com (192.168.0.24) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Sun, 26 Feb 2023 11:13:25 +0800 From: Ryan Chen To: Ryan Chen , Andrew Jeffery , Brendan Higgins , Benjamin Herrenschmidt , Joel Stanley , Rob Herring , Krzysztof Kozlowski , Philipp Zabel , , , , , , Subject: [PATCH v6 1/2] dt-bindings: i2c: aspeed: support for AST2600-i2cv2 Date: Sun, 26 Feb 2023 11:13:20 +0800 Message-ID: <20230226031321.3126756-2-ryan_chen@aspeedtech.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230226031321.3126756-1-ryan_chen@aspeedtech.com> References: <20230226031321.3126756-1-ryan_chen@aspeedtech.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Originating-IP: [192.168.10.13] X-ClientProxiedBy: TWMBX02.aspeed.com (192.168.0.24) To TWMBX02.aspeed.com (192.168.0.24) X-DNSRBL: X-MAIL: twspam01.aspeedtech.com 31Q30CKT025216 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add ast2600-i2cv2 compatible and aspeed,global-regs, aspeed,timeout aspeed,xfer-mode description for ast2600-i2cv2. Signed-off-by: Ryan Chen --- .../devicetree/bindings/i2c/aspeed,i2c.yaml | 44 +++++++++++++++++++ 1 file changed, 44 insertions(+) diff --git a/Documentation/devicetree/bindings/i2c/aspeed,i2c.yaml b/Docume= ntation/devicetree/bindings/i2c/aspeed,i2c.yaml index f597f73ccd87..75de3ce41cf5 100644 --- a/Documentation/devicetree/bindings/i2c/aspeed,i2c.yaml +++ b/Documentation/devicetree/bindings/i2c/aspeed,i2c.yaml @@ -49,6 +49,25 @@ properties: description: states that there is another master active on this bus =20 + aspeed,timeout: + type: boolean + description: I2C bus timeout enable for master/slave mode + + aspeed,xfer-mode: + description: | + I2C bus transfer mode selection. + - "byte": I2C bus byte transfer mode. + - "buffered": I2C bus buffer register transfer mode. + - "dma": I2C bus dma transfer mode (default) + items: + enum: [byte, buffered, dma] + maxItems: 1 + $ref: /schemas/types.yaml#/definitions/non-unique-string-array + + aspeed,global-regs: + $ref: /schemas/types.yaml#/definitions/phandle + description: The phandle of i2c global register node. + required: - reg - compatible @@ -57,6 +76,19 @@ required: =20 unevaluatedProperties: false =20 +if: + properties: + compatible: + contains: + const: aspeed,ast2600-i2cv2 + +then: + properties: + reg: + minItems: 2 + required: + - aspeed,global-regs + examples: - | #include @@ -71,3 +103,15 @@ examples: interrupts =3D <0>; interrupt-parent =3D <&i2c_ic>; }; + - | + #include + i2c1: i2c@80 { + #address-cells =3D <1>; + #size-cells =3D <0>; + compatible =3D "aspeed,ast2600-i2cv2"; + reg =3D <0x80 0x80>, <0xc00 0x20>; + interrupts =3D ; + aspeed,global-regs =3D <&i2c_global>; + clocks =3D <&syscon ASPEED_CLK_APB>; + resets =3D <&syscon ASPEED_RESET_I2C>; + }; --=20 2.34.1 From nobody Mon Sep 8 19:06:39 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9F85EC7EE2D for ; Sun, 26 Feb 2023 03:15:35 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229679AbjBZDPe (ORCPT ); Sat, 25 Feb 2023 22:15:34 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:39104 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229659AbjBZDPZ (ORCPT ); Sat, 25 Feb 2023 22:15:25 -0500 Received: from twspam01.aspeedtech.com (twspam01.aspeedtech.com [211.20.114.71]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 8FAF7FF2C; Sat, 25 Feb 2023 19:15:20 -0800 (PST) Received: from mail.aspeedtech.com ([192.168.0.24]) by twspam01.aspeedtech.com with ESMTP id 31Q30DSD025218; Sun, 26 Feb 2023 11:00:13 +0800 (GMT-8) (envelope-from ryan_chen@aspeedtech.com) Received: from aspeedtech.com (192.168.10.13) by TWMBX02.aspeed.com (192.168.0.24) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Sun, 26 Feb 2023 11:13:25 +0800 From: Ryan Chen To: Ryan Chen , Andrew Jeffery , Brendan Higgins , Benjamin Herrenschmidt , Joel Stanley , Rob Herring , Krzysztof Kozlowski , Philipp Zabel , , , , , , Subject: [PATCH v6 2/2] i2c: aspeed: support ast2600 i2cv new register mode driver Date: Sun, 26 Feb 2023 11:13:21 +0800 Message-ID: <20230226031321.3126756-3-ryan_chen@aspeedtech.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230226031321.3126756-1-ryan_chen@aspeedtech.com> References: <20230226031321.3126756-1-ryan_chen@aspeedtech.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Originating-IP: [192.168.10.13] X-ClientProxiedBy: TWMBX02.aspeed.com (192.168.0.24) To TWMBX02.aspeed.com (192.168.0.24) X-DNSRBL: X-MAIL: twspam01.aspeedtech.com 31Q30DSD025218 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add i2c new register mode driver to support AST2600 i2c new register mode. AST2600 i2c controller have legacy and new register mode. The new register mode have global register support 4 base clock for scl clock selection, and new clock divider mode. The i2c new register mode have separate register set to control i2c master and slave. Signed-off-by: Ryan Chen --- MAINTAINERS | 9 + drivers/i2c/busses/Kconfig | 11 + drivers/i2c/busses/Makefile | 1 + drivers/i2c/busses/i2c-ast2600.c | 1630 ++++++++++++++++++++++++++++++ 4 files changed, 1651 insertions(+) create mode 100644 drivers/i2c/busses/i2c-ast2600.c diff --git a/MAINTAINERS b/MAINTAINERS index 749710e22b4d..433ec2309441 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -1924,6 +1924,15 @@ F: Documentation/devicetree/bindings/interrupt-contr= oller/aspeed,ast2400-i2c-ic. F: drivers/i2c/busses/i2c-aspeed.c F: drivers/irqchip/irq-aspeed-i2c-ic.c =20 +ARM/ASPEED I2CV2 DRIVER +M: Ryan Chen +R: Andrew Jeffery +L: linux-i2c@vger.kernel.org +L: openbmc@lists.ozlabs.org (moderated for non-subscribers) +S: Maintained +F: Documentation/devicetree/bindings/i2c/aspeed,i2c.yaml +F: drivers/i2c/busses/i2c-ast2600.c + ARM/ASPEED MACHINE SUPPORT M: Joel Stanley R: Andrew Jeffery diff --git a/drivers/i2c/busses/Kconfig b/drivers/i2c/busses/Kconfig index 7284206b278b..4f6935866257 100644 --- a/drivers/i2c/busses/Kconfig +++ b/drivers/i2c/busses/Kconfig @@ -389,6 +389,17 @@ config I2C_ALTERA This driver can also be built as a module. If so, the module will be called i2c-altera. =20 +config I2C_AST2600 + tristate "Aspeed I2C v2 Controller" + depends on ARCH_ASPEED || COMPILE_TEST + select I2C_SMBUS + help + If you say yes to this option, support will be included for the + Aspeed I2C controller with new register set. + + This driver can also be built as a module. If so, the module + will be called i2c-ast2600. + config I2C_ASPEED tristate "Aspeed I2C Controller" depends on ARCH_ASPEED || COMPILE_TEST diff --git a/drivers/i2c/busses/Makefile b/drivers/i2c/busses/Makefile index c5cac15f075c..d0ab4d45781c 100644 --- a/drivers/i2c/busses/Makefile +++ b/drivers/i2c/busses/Makefile @@ -38,6 +38,7 @@ obj-$(CONFIG_I2C_POWERMAC) +=3D i2c-powermac.o obj-$(CONFIG_I2C_ALTERA) +=3D i2c-altera.o obj-$(CONFIG_I2C_AMD_MP2) +=3D i2c-amd-mp2-pci.o i2c-amd-mp2-plat.o obj-$(CONFIG_I2C_ASPEED) +=3D i2c-aspeed.o +obj-$(CONFIG_I2C_AST2600) +=3D i2c-ast2600.o obj-$(CONFIG_I2C_AT91) +=3D i2c-at91.o i2c-at91-objs :=3D i2c-at91-core.o i2c-at91-master.o ifeq ($(CONFIG_I2C_AT91_SLAVE_EXPERIMENTAL),y) diff --git a/drivers/i2c/busses/i2c-ast2600.c b/drivers/i2c/busses/i2c-ast2= 600.c new file mode 100644 index 000000000000..419e9050481a --- /dev/null +++ b/drivers/i2c/busses/i2c-ast2600.c @@ -0,0 +1,1630 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * ASPEED AST2600 new register set I2C controller driver + * + * Copyright (C) ASPEED Technology Inc. + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* + * APB clk : 100Mhz + * div : scl : baseclk [APB/((div/2) + 1)] : tBuf [1/bclk * 16] + * I2CG10[31:24] base clk4 for i2c auto recovery timeout counter (0xC6) + * I2CG10[23:16] base clk3 for Standard-mode (100Khz) min tBuf 4.7us + * 0x3c : 100.8Khz : 3.225Mhz : 4.96us + * 0x3d : 99.2Khz : 3.174Mhz : 5.04us + * 0x3e : 97.65Khz : 3.125Mhz : 5.12us + * 0x40 : 97.75Khz : 3.03Mhz : 5.28us + * 0x41 : 99.5Khz : 2.98Mhz : 5.36us (default) + * I2CG10[15:8] base clk2 for Fast-mode (400Khz) min tBuf 1.3us + * 0x12 : 400Khz : 10Mhz : 1.6us + * I2CG10[7:0] base clk1 for Fast-mode Plus (1Mhz) min tBuf 0.5us + * 0x08 : 1Mhz : 20Mhz : 0.8us + */ +#define AST2600_I2CG_ISR 0x00 +#define AST2600_I2CG_SLAVE_ISR 0x04 +#define AST2600_I2CG_OWNER 0x08 +#define AST2600_I2CG_CTRL 0x0C +#define AST2600_I2CG_CLK_DIV_CTRL 0x10 + +#define AST2600_I2CG_SLAVE_PKT_NAK BIT(4) +#define AST2600_I2CG_M_S_SEPARATE_INTR BIT(3) +#define AST2600_I2CG_CTRL_NEW_REG BIT(2) +#define AST2600_I2CG_CTRL_NEW_CLK_DIV BIT(1) + +#define AST2600_GLOBAL_INIT \ + (AST2600_I2CG_CTRL_NEW_REG | \ + AST2600_I2CG_CTRL_NEW_CLK_DIV) +#define I2CCG_DIV_CTRL 0xC6411208 + +/* 0x00 : I2CC Master/Slave Function Control Register */ +#define AST2600_I2CC_FUN_CTRL 0x00 +#define AST2600_I2CC_SLAVE_ADDR_RX_EN BIT(20) +#define AST2600_I2CC_MASTER_RETRY_MASK GENMASK(19, 18) +#define AST2600_I2CC_MASTER_RETRY(x) (((x) & GENMASK(1, 0)) << 18) +#define AST2600_I2CC_BUS_AUTO_RELEASE BIT(17) +#define AST2600_I2CC_M_SDA_LOCK_EN BIT(16) +#define AST2600_I2CC_MULTI_MASTER_DIS BIT(15) +#define AST2600_I2CC_M_SCL_DRIVE_EN BIT(14) +#define AST2600_I2CC_MSB_STS BIT(9) +#define AST2600_I2CC_SDA_DRIVE_1T_EN BIT(8) +#define AST2600_I2CC_M_SDA_DRIVE_1T_EN BIT(7) +#define AST2600_I2CC_M_HIGH_SPEED_EN BIT(6) +/* reserver 5 : 2 */ +#define AST2600_I2CC_SLAVE_EN BIT(1) +#define AST2600_I2CC_MASTER_EN BIT(0) + +/* 0x04 : I2CC Master/Slave Clock and AC Timing Control Register #1 */ +#define AST2600_I2CC_AC_TIMING 0x04 +#define AST2600_I2CC_TTIMEOUT(x) (((x) & GENMASK(4, 0)) << 24) +#define AST2600_I2CC_TCKHIGHMIN(x) (((x) & GENMASK(3, 0)) << 20) +#define AST2600_I2CC_TCKHIGH(x) (((x) & GENMASK(3, 0)) << 16) +#define AST2600_I2CC_TCKLOW(x) (((x) & GENMASK(3, 0)) << 12) +#define AST2600_I2CC_THDDAT(x) (((x) & GENMASK(1, 0)) << 10) +#define AST2600_I2CC_TOUTBASECLK(x) (((x) & GENMASK(1, 0)) << 8) +#define AST2600_I2CC_TBASECLK(x) ((x) & GENMASK(3, 0)) + +/* 0x08 : I2CC Master/Slave Transmit/Receive Byte Buffer Register */ +#define AST2600_I2CC_STS_AND_BUFF 0x08 +#define AST2600_I2CC_TX_DIR_MASK GENMASK(31, 29) +#define AST2600_I2CC_SDA_OE BIT(28) +#define AST2600_I2CC_SDA_O BIT(27) +#define AST2600_I2CC_SCL_OE BIT(26) +#define AST2600_I2CC_SCL_O BIT(25) + +#define AST2600_I2CC_SCL_LINE_STS BIT(18) +#define AST2600_I2CC_SDA_LINE_STS BIT(17) +#define AST2600_I2CC_BUS_BUSY_STS BIT(16) + +#define AST2600_I2CC_GET_RX_BUFF(x) (((x) >> 8) & GENMASK(7, 0)) + +/* 0x0C : I2CC Master/Slave Pool Buffer Control Register */ +#define AST2600_I2CC_BUFF_CTRL 0x0C +#define AST2600_I2CC_GET_RX_BUF_LEN(x) (((x) >> 24) & GENMASK(5, 0)) +#define AST2600_I2CC_SET_RX_BUF_LEN(x) (((((x) - 1) & GENMASK(4, 0)) << 1= 6) | BIT(0)) +#define AST2600_I2CC_SET_TX_BUF_LEN(x) (((((x) - 1) & GENMASK(4, 0)) << 8= ) | BIT(0)) +#define AST2600_I2CC_GET_TX_BUF_LEN(x) ((((x) >> 8) & GENMASK(4, 0)) + 1) + +/* 0x10 : I2CM Master Interrupt Control Register */ +#define AST2600_I2CM_IER 0x10 +/* 0x14 : I2CM Master Interrupt Status Register : WC */ +#define AST2600_I2CM_ISR 0x14 + +#define AST2600_I2CM_PKT_TIMEOUT BIT(18) +#define AST2600_I2CM_PKT_ERROR BIT(17) +#define AST2600_I2CM_PKT_DONE BIT(16) + +#define AST2600_I2CM_BUS_RECOVER_FAIL BIT(15) +#define AST2600_I2CM_SDA_DL_TO BIT(14) +#define AST2600_I2CM_BUS_RECOVER BIT(13) +#define AST2600_I2CM_SMBUS_ALT BIT(12) + +#define AST2600_I2CM_SCL_LOW_TO BIT(6) +#define AST2600_I2CM_ABNORMAL BIT(5) +#define AST2600_I2CM_NORMAL_STOP BIT(4) +#define AST2600_I2CM_ARBIT_LOSS BIT(3) +#define AST2600_I2CM_RX_DONE BIT(2) +#define AST2600_I2CM_TX_NAK BIT(1) +#define AST2600_I2CM_TX_ACK BIT(0) + +/* 0x18 : I2CM Master Command/Status Register */ +#define AST2600_I2CM_CMD_STS 0x18 +#define AST2600_I2CM_PKT_ADDR(x) (((x) & GENMASK(6, 0)) << 24) +#define AST2600_I2CM_PKT_EN BIT(16) +#define AST2600_I2CM_SDA_OE_OUT_DIR BIT(15) +#define AST2600_I2CM_SDA_O_OUT_DIR BIT(14) +#define AST2600_I2CM_SCL_OE_OUT_DIR BIT(13) +#define AST2600_I2CM_SCL_O_OUT_DIR BIT(12) +#define AST2600_I2CM_RECOVER_CMD_EN BIT(11) + +#define AST2600_I2CM_RX_DMA_EN BIT(9) +#define AST2600_I2CM_TX_DMA_EN BIT(8) +/* Command Bit */ +#define AST2600_I2CM_RX_BUFF_EN BIT(7) +#define AST2600_I2CM_TX_BUFF_EN BIT(6) +#define AST2600_I2CM_STOP_CMD BIT(5) +#define AST2600_I2CM_RX_CMD_LAST BIT(4) +#define AST2600_I2CM_RX_CMD BIT(3) + +#define AST2600_I2CM_TX_CMD BIT(1) +#define AST2600_I2CM_START_CMD BIT(0) + +/* 0x1C : I2CM Master DMA Transfer Length Register */ +#define AST2600_I2CM_DMA_LEN 0x1C +/* Tx Rx support length 1 ~ 4096 */ +#define AST2600_I2CM_SET_RX_DMA_LEN(x) ((((x) & GENMASK(11, 0)) << 16) | B= IT(31)) +#define AST2600_I2CM_SET_TX_DMA_LEN(x) (((x) & GENMASK(11, 0)) | BIT(15)) + +/* 0x20 : I2CS Slave Interrupt Control Register */ +#define AST2600_I2CS_IER 0x20 +/* 0x24 : I2CS Slave Interrupt Status Register */ +#define AST2600_I2CS_ISR 0x24 + +#define AST2600_I2CS_ADDR_INDICATE_MASK GENMASK(31, 30) +#define AST2600_I2CS_SLAVE_PENDING BIT(29) + +#define AST2600_I2CS_WAIT_TX_DMA BIT(25) +#define AST2600_I2CS_WAIT_RX_DMA BIT(24) + +#define AST2600_I2CS_ADDR3_NAK BIT(22) +#define AST2600_I2CS_ADDR2_NAK BIT(21) +#define AST2600_I2CS_ADDR1_NAK BIT(20) + +#define AST2600_I2CS_ADDR_MASK GENMASK(19, 18) +#define AST2600_I2CS_PKT_ERROR BIT(17) +#define AST2600_I2CS_PKT_DONE BIT(16) +#define AST2600_I2CS_INACTIVE_TO BIT(15) + +#define AST2600_I2CS_SLAVE_MATCH BIT(7) +#define AST2600_I2CS_ABNOR_STOP BIT(5) +#define AST2600_I2CS_STOP BIT(4) +#define AST2600_I2CS_RX_DONE_NAK BIT(3) +#define AST2600_I2CS_RX_DONE BIT(2) +#define AST2600_I2CS_TX_NAK BIT(1) +#define AST2600_I2CS_TX_ACK BIT(0) + +/* 0x28 : I2CS Slave CMD/Status Register */ +#define AST2600_I2CS_CMD_STS 0x28 +#define AST2600_I2CS_ACTIVE_ALL GENMASK(18, 17) +#define AST2600_I2CS_PKT_MODE_EN BIT(16) +#define AST2600_I2CS_AUTO_NAK_NOADDR BIT(15) +#define AST2600_I2CS_AUTO_NAK_EN BIT(14) + +#define AST2600_I2CS_ALT_EN BIT(10) +#define AST2600_I2CS_RX_DMA_EN BIT(9) +#define AST2600_I2CS_TX_DMA_EN BIT(8) +#define AST2600_I2CS_RX_BUFF_EN BIT(7) +#define AST2600_I2CS_TX_BUFF_EN BIT(6) +#define AST2600_I2CS_RX_CMD_LAST BIT(4) + +#define AST2600_I2CS_TX_CMD BIT(2) + +#define AST2600_I2CS_DMA_LEN 0x2C +#define AST2600_I2CS_SET_RX_DMA_LEN(x) (((((x) - 1) & GENMASK(11, 0)) << 1= 6) | BIT(31)) +#define AST2600_I2CS_RX_DMA_LEN_MASK (GENMASK(11, 0) << 16) + +#define AST2600_I2CS_SET_TX_DMA_LEN(x) ((((x) - 1) & GENMASK(11, 0)) | BIT= (15)) +#define AST2600_I2CS_TX_DMA_LEN_MASK GENMASK(11, 0) + +/* I2CM Master DMA Tx Buffer Register */ +#define AST2600_I2CM_TX_DMA 0x30 +/* I2CM Master DMA Rx Buffer Register */ +#define AST2600_I2CM_RX_DMA 0x34 +/* I2CS Slave DMA Tx Buffer Register */ +#define AST2600_I2CS_TX_DMA 0x38 +/* I2CS Slave DMA Rx Buffer Register */ +#define AST2600_I2CS_RX_DMA 0x3C + +#define AST2600_I2CS_ADDR_CTRL 0x40 + +#define AST2600_I2CS_ADDR3_MASK GENMASK(22, 16) +#define AST2600_I2CS_ADDR2_MASK GENMASK(14, 8) +#define AST2600_I2CS_ADDR1_MASK GENMASK(6, 0) + +#define AST2600_I2CM_DMA_LEN_STS 0x48 +#define AST2600_I2CS_DMA_LEN_STS 0x4C + +#define AST2600_I2C_GET_TX_DMA_LEN(x) ((x) & GENMASK(12, 0)) +#define AST2600_I2C_GET_RX_DMA_LEN(x) (((x) >> 16) & GENMASK(12, 0)) + +/* 0x40 : Slave Device Address Register */ +#define AST2600_I2CS_ADDR3_ENABLE BIT(23) +#define AST2600_I2CS_ADDR3(x) ((x) << 16) +#define AST2600_I2CS_ADDR2_ENABLE BIT(15) +#define AST2600_I2CS_ADDR2(x) ((x) << 8) +#define AST2600_I2CS_ADDR1_ENABLE BIT(7) +#define AST2600_I2CS_ADDR1(x) (x) + +#define I2C_SLAVE_MSG_BUF_SIZE 256 + +#define AST2600_I2C_DMA_SIZE 4096 + +#define MASTER_TRIGGER_LAST_STOP (AST2600_I2CM_RX_CMD_LAST | AST2600_I2CM_= STOP_CMD) +#define SLAVE_TRIGGER_CMD (AST2600_I2CS_ACTIVE_ALL | AST2600_I2CS_PKT_MODE= _EN) + +/* i2c timeout counter: use base clk4 1Mhz + * unit: 1/(1000/4096) =3D 4.096ms * 8 =3D 32.768ms + */ +#define AST_I2C_TIMEOUT_CLK 0x2 +#define AST_I2C_TIMEOUT_COUNT 0x8 + +struct ast2600_i2c_timing_table { + u32 divisor; + u32 timing; +}; + +enum xfer_mode { + BYTE_MODE =3D 0, + BUFF_MODE, + DMA_MODE, +}; + +struct ast2600_xfer_mode_str2field { + const char *name; + enum xfer_mode mode; +}; + +static const struct ast2600_xfer_mode_str2field ast2600_xfer_mode_type[] = =3D { + { "byte", BYTE_MODE }, + { "buffered", BUFF_MODE }, + { "dma", DMA_MODE }, + {}, +}; + +struct ast2600_i2c_bus { + struct i2c_adapter adap; + struct device *dev; + void __iomem *reg_base; + struct regmap *global_regs; + struct reset_control *rst; + int irq; + enum xfer_mode mode; + struct clk *clk; + u32 apb_clk; + u32 bus_frequency; + int slave_operate; + int timeout_enable; + /* smbus alert */ + int alert_enable; + struct i2c_smbus_alert_setup alert_data; + struct i2c_client *ara; + /* Multi-master */ + bool multi_master; + /* master structure */ + int cmd_err; + struct completion cmd_complete; + struct i2c_msg *msgs; + size_t buf_index; + /* cur xfer msgs index*/ + int msgs_index; + int msgs_count; + u8 *master_safe_buf; + dma_addr_t master_dma_addr; + /*total xfer count */ + int master_xfer_cnt; + /* Buffer mode */ + void __iomem *buf_base; + size_t buf_size; + /* Slave structure */ + int slave_xfer_len; + int slave_xfer_cnt; +#ifdef CONFIG_I2C_SLAVE + unsigned char *slave_dma_buf; + dma_addr_t slave_dma_addr; + struct i2c_client *slave; +#endif +}; + +static u32 ast2600_select_i2c_clock(struct ast2600_i2c_bus *i2c_bus) +{ + unsigned long base_clk1; + unsigned long base_clk2; + unsigned long base_clk3; + unsigned long base_clk4; + int baseclk_idx; + u32 clk_div_reg; + u32 scl_low; + u32 scl_high; + int divisor; + int inc =3D 0; + u32 data; + + regmap_read(i2c_bus->global_regs, AST2600_I2CG_CLK_DIV_CTRL, &clk_div_reg= ); + base_clk1 =3D (i2c_bus->apb_clk * 10) / ((((clk_div_reg & 0xff) + 2) * 10= ) / 2); + base_clk2 =3D (i2c_bus->apb_clk * 10) / + (((((clk_div_reg >> 8) & 0xff) + 2) * 10) / 2); + base_clk3 =3D (i2c_bus->apb_clk * 10) / + (((((clk_div_reg >> 16) & 0xff) + 2) * 10) / 2); + base_clk4 =3D (i2c_bus->apb_clk * 10) / + (((((clk_div_reg >> 24) & 0xff) + 2) * 10) / 2); + + if ((i2c_bus->apb_clk / i2c_bus->bus_frequency) <=3D 32) { + baseclk_idx =3D 0; + divisor =3D DIV_ROUND_UP(i2c_bus->apb_clk, i2c_bus->bus_frequency); + } else if ((base_clk1 / i2c_bus->bus_frequency) <=3D 32) { + baseclk_idx =3D 1; + divisor =3D DIV_ROUND_UP(base_clk1, i2c_bus->bus_frequency); + } else if ((base_clk2 / i2c_bus->bus_frequency) <=3D 32) { + baseclk_idx =3D 2; + divisor =3D DIV_ROUND_UP(base_clk2, i2c_bus->bus_frequency); + } else if ((base_clk3 / i2c_bus->bus_frequency) <=3D 32) { + baseclk_idx =3D 3; + divisor =3D DIV_ROUND_UP(base_clk3, i2c_bus->bus_frequency); + } else { + baseclk_idx =3D 4; + divisor =3D DIV_ROUND_UP(base_clk4, i2c_bus->bus_frequency); + inc =3D 0; + while ((divisor + inc) > 32) { + inc |=3D divisor & 0x1; + divisor >>=3D 1; + baseclk_idx++; + } + divisor +=3D inc; + } + divisor =3D min_t(int, divisor, 32); + baseclk_idx &=3D 0xf; + scl_low =3D ((divisor * 9) / 16) - 1; + scl_low =3D min_t(u32, scl_low, 0xf); + scl_high =3D (divisor - scl_low - 2) & 0xf; + /* Divisor : Base Clock : tCKHighMin : tCK High : tCK Low */ + data =3D ((scl_high - 1) << 20) | (scl_high << 16) | (scl_low << 12) | (b= aseclk_idx); + if (i2c_bus->timeout_enable) { + data |=3D AST2600_I2CC_TOUTBASECLK(AST_I2C_TIMEOUT_CLK); + data |=3D AST2600_I2CC_TTIMEOUT(AST_I2C_TIMEOUT_COUNT); + } + + return data; +} + +static u8 ast2600_i2c_recover_bus(struct ast2600_i2c_bus *i2c_bus) +{ + int ret =3D 0; + u32 ctrl; + u32 state; + int r; + + dev_dbg(i2c_bus->dev, "%d-bus recovery bus [%x]\n", i2c_bus->adap.nr, + readl(i2c_bus->reg_base + AST2600_I2CC_STS_AND_BUFF)); + + ctrl =3D readl(i2c_bus->reg_base + AST2600_I2CC_FUN_CTRL); + + writel(ctrl & ~(AST2600_I2CC_MASTER_EN | AST2600_I2CC_SLAVE_EN), + i2c_bus->reg_base + AST2600_I2CC_FUN_CTRL); + + writel(readl(i2c_bus->reg_base + AST2600_I2CC_FUN_CTRL) | AST2600_I2CC_MA= STER_EN, + i2c_bus->reg_base + AST2600_I2CC_FUN_CTRL); + + reinit_completion(&i2c_bus->cmd_complete); + i2c_bus->cmd_err =3D 0; + + /* Check 0x14's SDA and SCL status */ + state =3D readl(i2c_bus->reg_base + AST2600_I2CC_STS_AND_BUFF); + if (!(state & AST2600_I2CC_SDA_LINE_STS) && (state & AST2600_I2CC_SCL_LIN= E_STS)) { + writel(AST2600_I2CM_RECOVER_CMD_EN, i2c_bus->reg_base + AST2600_I2CM_CMD= _STS); + r =3D wait_for_completion_timeout(&i2c_bus->cmd_complete, i2c_bus->adap.= timeout); + if (r =3D=3D 0) { + dev_dbg(i2c_bus->dev, "recovery timed out\n"); + ret =3D -ETIMEDOUT; + } else { + if (i2c_bus->cmd_err) { + dev_dbg(i2c_bus->dev, "recovery error\n"); + ret =3D -EPROTO; + } + } + } + + dev_dbg(i2c_bus->dev, "Recovery done [%x]\n", + readl(i2c_bus->reg_base + AST2600_I2CC_STS_AND_BUFF)); + if (readl(i2c_bus->reg_base + AST2600_I2CC_STS_AND_BUFF) & AST2600_I2CC_B= US_BUSY_STS) { + dev_dbg(i2c_bus->dev, "Can't recovery bus [%x]\n", + readl(i2c_bus->reg_base + AST2600_I2CC_STS_AND_BUFF)); + ret =3D -EPROTO; + } + + writel(ctrl, i2c_bus->reg_base + AST2600_I2CC_FUN_CTRL); + return ret; +} + +#ifdef CONFIG_I2C_SLAVE +static void ast2600_i2c_slave_packet_dma_irq(struct ast2600_i2c_bus *i2c_b= us, u32 sts) +{ + int slave_rx_len; + u32 cmd =3D 0; + u8 value; + int i =3D 0; + + sts &=3D ~(AST2600_I2CS_SLAVE_PENDING); + /* Handle i2c slave timeout condition */ + if (AST2600_I2CS_INACTIVE_TO & sts) { + cmd =3D SLAVE_TRIGGER_CMD; + cmd |=3D AST2600_I2CS_RX_DMA_EN; + writel(AST2600_I2CS_SET_RX_DMA_LEN(I2C_SLAVE_MSG_BUF_SIZE), + i2c_bus->reg_base + AST2600_I2CS_DMA_LEN); + writel(cmd, i2c_bus->reg_base + AST2600_I2CS_CMD_STS); + writel(AST2600_I2CS_PKT_DONE, i2c_bus->reg_base + AST2600_I2CS_ISR); + i2c_slave_event(i2c_bus->slave, I2C_SLAVE_STOP, &value); + return; + } + + sts &=3D ~(AST2600_I2CS_PKT_DONE | AST2600_I2CS_PKT_ERROR); + + switch (sts) { + case AST2600_I2CS_SLAVE_MATCH | AST2600_I2CS_RX_DONE | AST2600_I2CS_WAIT_= RX_DMA: + case AST2600_I2CS_SLAVE_MATCH | AST2600_I2CS_WAIT_RX_DMA: + i2c_slave_event(i2c_bus->slave, I2C_SLAVE_WRITE_REQUESTED, &value); + slave_rx_len =3D AST2600_I2C_GET_RX_DMA_LEN(readl(i2c_bus->reg_base + + AST2600_I2CS_DMA_LEN_STS)); + for (i =3D 0; i < slave_rx_len; i++) { + i2c_slave_event(i2c_bus->slave, I2C_SLAVE_WRITE_RECEIVED, + &i2c_bus->slave_dma_buf[i]); + } + writel(AST2600_I2CS_SET_RX_DMA_LEN(I2C_SLAVE_MSG_BUF_SIZE), + i2c_bus->reg_base + AST2600_I2CS_DMA_LEN); + cmd =3D SLAVE_TRIGGER_CMD | AST2600_I2CS_RX_DMA_EN; + break; + case AST2600_I2CS_SLAVE_MATCH | AST2600_I2CS_STOP: + i2c_slave_event(i2c_bus->slave, I2C_SLAVE_STOP, &value); + writel(AST2600_I2CS_SET_RX_DMA_LEN(I2C_SLAVE_MSG_BUF_SIZE), + i2c_bus->reg_base + AST2600_I2CS_DMA_LEN); + cmd =3D SLAVE_TRIGGER_CMD | AST2600_I2CS_RX_DMA_EN; + break; + case AST2600_I2CS_SLAVE_MATCH | AST2600_I2CS_RX_DONE_NAK | + AST2600_I2CS_RX_DONE | AST2600_I2CS_STOP: + case AST2600_I2CS_SLAVE_MATCH | AST2600_I2CS_WAIT_RX_DMA | + AST2600_I2CS_RX_DONE | AST2600_I2CS_STOP: + case AST2600_I2CS_RX_DONE_NAK | AST2600_I2CS_RX_DONE | AST2600_I2CS_STOP: + case AST2600_I2CS_RX_DONE | AST2600_I2CS_WAIT_RX_DMA | AST2600_I2CS_STOP: + case AST2600_I2CS_RX_DONE | AST2600_I2CS_STOP: + case AST2600_I2CS_RX_DONE | AST2600_I2CS_WAIT_RX_DMA: + case AST2600_I2CS_SLAVE_MATCH | AST2600_I2CS_RX_DONE | AST2600_I2CS_STOP: + if (sts & AST2600_I2CS_SLAVE_MATCH) + i2c_slave_event(i2c_bus->slave, I2C_SLAVE_WRITE_REQUESTED, &value); + + slave_rx_len =3D AST2600_I2C_GET_RX_DMA_LEN(readl(i2c_bus->reg_base + + AST2600_I2CS_DMA_LEN_STS)); + for (i =3D 0; i < slave_rx_len; i++) { + i2c_slave_event(i2c_bus->slave, I2C_SLAVE_WRITE_RECEIVED, + &i2c_bus->slave_dma_buf[i]); + } + writel(AST2600_I2CS_SET_RX_DMA_LEN(I2C_SLAVE_MSG_BUF_SIZE), + i2c_bus->reg_base + AST2600_I2CS_DMA_LEN); + if (sts & AST2600_I2CS_STOP) + i2c_slave_event(i2c_bus->slave, I2C_SLAVE_STOP, &value); + cmd =3D SLAVE_TRIGGER_CMD | AST2600_I2CS_RX_DMA_EN; + break; + + /* it is Mw data Mr coming -> it need send tx */ + case AST2600_I2CS_RX_DONE | AST2600_I2CS_WAIT_TX_DMA: + case AST2600_I2CS_SLAVE_MATCH | AST2600_I2CS_RX_DONE | AST2600_I2CS_WAIT_= TX_DMA: + /* it should be repeat start read */ + if (sts & AST2600_I2CS_SLAVE_MATCH) + i2c_slave_event(i2c_bus->slave, I2C_SLAVE_WRITE_REQUESTED, &value); + + slave_rx_len =3D AST2600_I2C_GET_RX_DMA_LEN(readl(i2c_bus->reg_base + + AST2600_I2CS_DMA_LEN_STS)); + for (i =3D 0; i < slave_rx_len; i++) { + i2c_slave_event(i2c_bus->slave, I2C_SLAVE_WRITE_RECEIVED, + &i2c_bus->slave_dma_buf[i]); + } + i2c_slave_event(i2c_bus->slave, I2C_SLAVE_READ_REQUESTED, + &i2c_bus->slave_dma_buf[0]); + writel(0, i2c_bus->reg_base + AST2600_I2CS_DMA_LEN_STS); + writel(AST2600_I2CS_SET_TX_DMA_LEN(1), + i2c_bus->reg_base + AST2600_I2CS_DMA_LEN); + cmd =3D SLAVE_TRIGGER_CMD | AST2600_I2CS_TX_DMA_EN; + break; + case AST2600_I2CS_SLAVE_MATCH | AST2600_I2CS_WAIT_TX_DMA: + /* First Start read */ + i2c_slave_event(i2c_bus->slave, I2C_SLAVE_READ_REQUESTED, + &i2c_bus->slave_dma_buf[0]); + writel(AST2600_I2CS_SET_TX_DMA_LEN(1), + i2c_bus->reg_base + AST2600_I2CS_DMA_LEN); + cmd =3D SLAVE_TRIGGER_CMD | AST2600_I2CS_TX_DMA_EN; + break; + case AST2600_I2CS_WAIT_TX_DMA: + /* it should be next start read */ + i2c_slave_event(i2c_bus->slave, I2C_SLAVE_READ_PROCESSED, + &i2c_bus->slave_dma_buf[0]); + writel(0, i2c_bus->reg_base + AST2600_I2CS_DMA_LEN_STS); + writel(AST2600_I2CS_SET_TX_DMA_LEN(1), + i2c_bus->reg_base + AST2600_I2CS_DMA_LEN); + cmd =3D SLAVE_TRIGGER_CMD | AST2600_I2CS_TX_DMA_EN; + break; + + case AST2600_I2CS_TX_NAK | AST2600_I2CS_STOP: + /* it just tx complete */ + i2c_slave_event(i2c_bus->slave, I2C_SLAVE_STOP, &value); + writel(0, i2c_bus->reg_base + AST2600_I2CS_DMA_LEN_STS); + writel(AST2600_I2CS_SET_RX_DMA_LEN(I2C_SLAVE_MSG_BUF_SIZE), + i2c_bus->reg_base + AST2600_I2CS_DMA_LEN); + cmd =3D SLAVE_TRIGGER_CMD | AST2600_I2CS_RX_DMA_EN; + break; + case AST2600_I2CS_SLAVE_MATCH | AST2600_I2CS_RX_DONE: + cmd =3D 0; + i2c_slave_event(i2c_bus->slave, I2C_SLAVE_WRITE_REQUESTED, &value); + break; + case AST2600_I2CS_STOP: + cmd =3D 0; + i2c_slave_event(i2c_bus->slave, I2C_SLAVE_STOP, &value); + break; + default: + dev_dbg(i2c_bus->dev, "unhandled slave isr case %x, sts %x\n", sts, + readl(i2c_bus->reg_base + AST2600_I2CC_STS_AND_BUFF)); + break; + } + + if (cmd) + writel(cmd, i2c_bus->reg_base + AST2600_I2CS_CMD_STS); + writel(AST2600_I2CS_PKT_DONE, i2c_bus->reg_base + AST2600_I2CS_ISR); + readl(i2c_bus->reg_base + AST2600_I2CS_ISR); +} + +static void ast2600_i2c_slave_packet_buff_irq(struct ast2600_i2c_bus *i2c_= bus, u32 sts) +{ + int slave_rx_len =3D 0; + u32 cmd =3D 0; + u8 value; + int i =3D 0; + + /* due to master slave is common buffer, so need force the master stop no= t issue */ + if (readl(i2c_bus->reg_base + AST2600_I2CM_CMD_STS) & 0xffff) { + writel(0, i2c_bus->reg_base + AST2600_I2CM_CMD_STS); + i2c_bus->cmd_err =3D -EBUSY; + writel(0, i2c_bus->reg_base + AST2600_I2CC_BUFF_CTRL); + complete(&i2c_bus->cmd_complete); + } + + /* Handle i2c slave timeout condition */ + if (AST2600_I2CS_INACTIVE_TO & sts) { + writel(SLAVE_TRIGGER_CMD, i2c_bus->reg_base + AST2600_I2CS_CMD_STS); + writel(AST2600_I2CS_PKT_DONE, i2c_bus->reg_base + AST2600_I2CS_ISR); + i2c_slave_event(i2c_bus->slave, I2C_SLAVE_STOP, &value); + i2c_bus->slave_operate =3D 0; + return; + } + + sts &=3D ~(AST2600_I2CS_PKT_DONE | AST2600_I2CS_PKT_ERROR); + + if (sts & AST2600_I2CS_SLAVE_MATCH) + i2c_bus->slave_operate =3D 1; + + switch (sts) { + case AST2600_I2CS_SLAVE_PENDING | AST2600_I2CS_WAIT_RX_DMA | + AST2600_I2CS_SLAVE_MATCH | AST2600_I2CS_RX_DONE | AST2600_I2CS_STOP: + case AST2600_I2CS_SLAVE_PENDING | + AST2600_I2CS_SLAVE_MATCH | AST2600_I2CS_RX_DONE | AST2600_I2CS_STOP: + case AST2600_I2CS_SLAVE_PENDING | + AST2600_I2CS_SLAVE_MATCH | AST2600_I2CS_STOP: + i2c_slave_event(i2c_bus->slave, I2C_SLAVE_STOP, &value); + fallthrough; + case AST2600_I2CS_SLAVE_PENDING | + AST2600_I2CS_WAIT_RX_DMA | AST2600_I2CS_SLAVE_MATCH | AST2600_I2CS_RX_D= ONE: + case AST2600_I2CS_WAIT_RX_DMA | AST2600_I2CS_SLAVE_MATCH | AST2600_I2CS_R= X_DONE: + case AST2600_I2CS_WAIT_RX_DMA | AST2600_I2CS_SLAVE_MATCH: + i2c_slave_event(i2c_bus->slave, I2C_SLAVE_WRITE_REQUESTED, &value); + cmd =3D SLAVE_TRIGGER_CMD; + if (sts & AST2600_I2CS_RX_DONE) { + slave_rx_len =3D AST2600_I2CC_GET_RX_BUF_LEN(readl(i2c_bus->reg_base + + AST2600_I2CC_BUFF_CTRL)); + for (i =3D 0; i < slave_rx_len; i++) { + value =3D readb(i2c_bus->buf_base + 0x10 + i); + i2c_slave_event(i2c_bus->slave, I2C_SLAVE_WRITE_RECEIVED, &value); + } + } + if (readl(i2c_bus->reg_base + AST2600_I2CS_CMD_STS) & AST2600_I2CS_RX_BU= FF_EN) + cmd =3D 0; + else + cmd =3D SLAVE_TRIGGER_CMD | AST2600_I2CS_RX_BUFF_EN; + + writel(AST2600_I2CC_SET_RX_BUF_LEN(i2c_bus->buf_size), + i2c_bus->reg_base + AST2600_I2CC_BUFF_CTRL); + break; + case AST2600_I2CS_WAIT_RX_DMA | AST2600_I2CS_RX_DONE: + cmd =3D SLAVE_TRIGGER_CMD; + slave_rx_len =3D AST2600_I2CC_GET_RX_BUF_LEN(readl(i2c_bus->reg_base + + AST2600_I2CC_BUFF_CTRL)); + for (i =3D 0; i < slave_rx_len; i++) { + value =3D readb(i2c_bus->buf_base + 0x10 + i); + i2c_slave_event(i2c_bus->slave, I2C_SLAVE_WRITE_RECEIVED, &value); + } + cmd |=3D AST2600_I2CS_RX_BUFF_EN; + writel(AST2600_I2CC_SET_RX_BUF_LEN(i2c_bus->buf_size), + i2c_bus->reg_base + AST2600_I2CC_BUFF_CTRL); + break; + case AST2600_I2CS_SLAVE_PENDING | AST2600_I2CS_WAIT_RX_DMA | + AST2600_I2CS_RX_DONE | AST2600_I2CS_STOP: + cmd =3D SLAVE_TRIGGER_CMD; + slave_rx_len =3D AST2600_I2CC_GET_RX_BUF_LEN(readl(i2c_bus->reg_base + + AST2600_I2CC_BUFF_CTRL)); + for (i =3D 0; i < slave_rx_len; i++) { + value =3D readb(i2c_bus->buf_base + 0x10 + i); + i2c_slave_event(i2c_bus->slave, I2C_SLAVE_WRITE_RECEIVED, &value); + } + i2c_slave_event(i2c_bus->slave, I2C_SLAVE_STOP, &value); + cmd |=3D AST2600_I2CS_RX_BUFF_EN; + writel(AST2600_I2CC_SET_RX_BUF_LEN(i2c_bus->buf_size), + i2c_bus->reg_base + AST2600_I2CC_BUFF_CTRL); + break; + + case AST2600_I2CS_SLAVE_PENDING | AST2600_I2CS_RX_DONE | AST2600_I2CS_STO= P: + cmd =3D SLAVE_TRIGGER_CMD; + slave_rx_len =3D AST2600_I2CC_GET_RX_BUF_LEN(readl(i2c_bus->reg_base + + AST2600_I2CC_BUFF_CTRL)); + for (i =3D 0; i < slave_rx_len; i++) { + value =3D readb(i2c_bus->buf_base + 0x10 + i); + i2c_slave_event(i2c_bus->slave, I2C_SLAVE_WRITE_RECEIVED, &value); + } + /* workaround for avoid next start with len !=3D 0 */ + writel(BIT(0), i2c_bus->reg_base + AST2600_I2CC_BUFF_CTRL); + i2c_slave_event(i2c_bus->slave, I2C_SLAVE_STOP, &value); + break; + + case AST2600_I2CS_RX_DONE | AST2600_I2CS_STOP: + cmd =3D SLAVE_TRIGGER_CMD; + slave_rx_len =3D AST2600_I2CC_GET_RX_BUF_LEN(readl(i2c_bus->reg_base + + AST2600_I2CC_BUFF_CTRL)); + for (i =3D 0; i < slave_rx_len; i++) { + value =3D readb(i2c_bus->buf_base + 0x10 + i); + i2c_slave_event(i2c_bus->slave, I2C_SLAVE_WRITE_RECEIVED, &value); + } + /* workaround for avoid next start with len !=3D 0 */ + writel(BIT(0), i2c_bus->reg_base + AST2600_I2CC_BUFF_CTRL); + i2c_slave_event(i2c_bus->slave, I2C_SLAVE_STOP, &value); + break; + case AST2600_I2CS_WAIT_TX_DMA | AST2600_I2CS_SLAVE_MATCH: + i2c_slave_event(i2c_bus->slave, I2C_SLAVE_READ_REQUESTED, &value); + writeb(value, i2c_bus->buf_base); + writel(AST2600_I2CC_SET_TX_BUF_LEN(1), + i2c_bus->reg_base + AST2600_I2CC_BUFF_CTRL); + cmd =3D SLAVE_TRIGGER_CMD | AST2600_I2CS_TX_BUFF_EN; + break; + case AST2600_I2CS_WAIT_TX_DMA | AST2600_I2CS_RX_DONE: + case AST2600_I2CS_WAIT_TX_DMA: + if (sts & AST2600_I2CS_RX_DONE) { + slave_rx_len =3D AST2600_I2CC_GET_RX_BUF_LEN(readl(i2c_bus->reg_base + + AST2600_I2CC_BUFF_CTRL)); + for (i =3D 0; i < slave_rx_len; i++) { + value =3D readb(i2c_bus->buf_base + 0x10 + i); + i2c_slave_event(i2c_bus->slave, I2C_SLAVE_WRITE_RECEIVED, &value); + } + i2c_slave_event(i2c_bus->slave, I2C_SLAVE_READ_REQUESTED, &value); + } else { + i2c_slave_event(i2c_bus->slave, I2C_SLAVE_READ_PROCESSED, &value); + } + writeb(value, i2c_bus->buf_base); + writel(AST2600_I2CC_SET_TX_BUF_LEN(1), + i2c_bus->reg_base + AST2600_I2CC_BUFF_CTRL); + cmd =3D SLAVE_TRIGGER_CMD | AST2600_I2CS_TX_BUFF_EN; + break; + /* workaround : trigger the cmd twice to fix next state keep 1000000 */ + case AST2600_I2CS_SLAVE_MATCH | AST2600_I2CS_RX_DONE: + i2c_slave_event(i2c_bus->slave, I2C_SLAVE_WRITE_REQUESTED, &value); + cmd =3D SLAVE_TRIGGER_CMD | AST2600_I2CS_RX_BUFF_EN; + writel(cmd, i2c_bus->reg_base + AST2600_I2CS_CMD_STS); + break; + + case AST2600_I2CS_TX_NAK | AST2600_I2CS_STOP: + case AST2600_I2CS_STOP: + cmd =3D SLAVE_TRIGGER_CMD; + i2c_slave_event(i2c_bus->slave, I2C_SLAVE_STOP, &value); + break; + default: + dev_dbg(i2c_bus->dev, "unhandled slave isr case %x, sts %x\n", sts, + readl(i2c_bus->reg_base + AST2600_I2CC_STS_AND_BUFF)); + break; + } + + if (cmd) + writel(cmd, i2c_bus->reg_base + AST2600_I2CS_CMD_STS); + writel(AST2600_I2CS_PKT_DONE, i2c_bus->reg_base + AST2600_I2CS_ISR); + readl(i2c_bus->reg_base + AST2600_I2CS_ISR); + + if ((sts & AST2600_I2CS_STOP) && !(sts & AST2600_I2CS_SLAVE_PENDING)) + i2c_bus->slave_operate =3D 0; + +} + +static void ast2600_i2c_slave_byte_irq(struct ast2600_i2c_bus *i2c_bus, u3= 2 sts) +{ + u32 i2c_buff =3D readl(i2c_bus->reg_base + AST2600_I2CC_STS_AND_BUFF); + u32 cmd =3D AST2600_I2CS_ACTIVE_ALL; + u8 byte_data; + u8 value; + + switch (sts) { + case AST2600_I2CS_SLAVE_MATCH | AST2600_I2CS_RX_DONE | AST2600_I2CS_WAIT_= RX_DMA: + i2c_slave_event(i2c_bus->slave, I2C_SLAVE_WRITE_REQUESTED, &value); + /* first address match is address */ + byte_data =3D AST2600_I2CC_GET_RX_BUFF(i2c_buff); + break; + case AST2600_I2CS_RX_DONE | AST2600_I2CS_WAIT_RX_DMA: + byte_data =3D AST2600_I2CC_GET_RX_BUFF(i2c_buff); + i2c_slave_event(i2c_bus->slave, I2C_SLAVE_WRITE_RECEIVED, &byte_data); + break; + case AST2600_I2CS_SLAVE_MATCH | AST2600_I2CS_RX_DONE | AST2600_I2CS_WAIT_= TX_DMA: + cmd |=3D AST2600_I2CS_TX_CMD; + byte_data =3D AST2600_I2CC_GET_RX_BUFF(i2c_buff); + i2c_slave_event(i2c_bus->slave, I2C_SLAVE_READ_REQUESTED, &byte_data); + writel(byte_data, i2c_bus->reg_base + AST2600_I2CC_STS_AND_BUFF); + break; + case AST2600_I2CS_TX_ACK | AST2600_I2CS_WAIT_TX_DMA: + cmd |=3D AST2600_I2CS_TX_CMD; + i2c_slave_event(i2c_bus->slave, I2C_SLAVE_READ_PROCESSED, &byte_data); + writel(byte_data, i2c_bus->reg_base + AST2600_I2CC_STS_AND_BUFF); + break; + case AST2600_I2CS_STOP: + case AST2600_I2CS_STOP | AST2600_I2CS_TX_NAK: + i2c_slave_event(i2c_bus->slave, I2C_SLAVE_STOP, &value); + break; + default: + dev_dbg(i2c_bus->dev, "unhandled pkt isr %x\n", sts); + break; + } + writel(cmd, i2c_bus->reg_base + AST2600_I2CS_CMD_STS); + writel(sts, i2c_bus->reg_base + AST2600_I2CS_ISR); + readl(i2c_bus->reg_base + AST2600_I2CS_ISR); +} + +static int ast2600_i2c_slave_irq(struct ast2600_i2c_bus *i2c_bus) +{ + u32 ier =3D readl(i2c_bus->reg_base + AST2600_I2CS_IER); + u32 isr =3D readl(i2c_bus->reg_base + AST2600_I2CS_ISR); + + if (!(isr & ier)) + return 0; + + /* Slave interrupt coming after Master package done + * So need handle master first. + */ + if (readl(i2c_bus->reg_base + AST2600_I2CM_ISR) & AST2600_I2CM_PKT_DONE) + return 0; + + isr &=3D ~(AST2600_I2CS_ADDR_INDICATE_MASK); + + if (AST2600_I2CS_ADDR1_NAK & isr) + isr &=3D ~AST2600_I2CS_ADDR1_NAK; + + if (AST2600_I2CS_ADDR2_NAK & isr) + isr &=3D ~AST2600_I2CS_ADDR2_NAK; + + if (AST2600_I2CS_ADDR3_NAK & isr) + isr &=3D ~AST2600_I2CS_ADDR3_NAK; + + if (AST2600_I2CS_ADDR_MASK & isr) + isr &=3D ~AST2600_I2CS_ADDR_MASK; + + if (AST2600_I2CS_PKT_DONE & isr) { + if (i2c_bus->mode =3D=3D DMA_MODE) + ast2600_i2c_slave_packet_dma_irq(i2c_bus, isr); + else + ast2600_i2c_slave_packet_buff_irq(i2c_bus, isr); + } else + ast2600_i2c_slave_byte_irq(i2c_bus, isr); + + return 1; +} +#endif + +static int ast2600_i2c_do_start(struct ast2600_i2c_bus *i2c_bus) +{ + struct i2c_msg *msg =3D &i2c_bus->msgs[i2c_bus->msgs_index]; + int xfer_len =3D 0; + int i =3D 0; + u32 cmd; + + cmd =3D AST2600_I2CM_PKT_EN | AST2600_I2CM_PKT_ADDR(msg->addr) | AST2600_= I2CM_START_CMD; + + /* send start */ + dev_dbg(i2c_bus->dev, "[%d] %sing %d byte%s %s 0x%02x\n", + i2c_bus->msgs_index, msg->flags & I2C_M_RD ? "read" : "write", + msg->len, msg->len > 1 ? "s" : "", + msg->flags & I2C_M_RD ? "from" : "to", msg->addr); + + i2c_bus->master_xfer_cnt =3D 0; + i2c_bus->buf_index =3D 0; + + if (msg->flags & I2C_M_RD) { + cmd |=3D AST2600_I2CM_RX_CMD; + if (i2c_bus->mode =3D=3D DMA_MODE) { + /* dma mode */ + cmd |=3D AST2600_I2CM_RX_DMA_EN; + + if (msg->flags & I2C_M_RECV_LEN) { + xfer_len =3D 1; + } else { + if (msg->len > AST2600_I2C_DMA_SIZE) { + xfer_len =3D AST2600_I2C_DMA_SIZE; + } else { + xfer_len =3D msg->len; + if (i2c_bus->msgs_index + 1 =3D=3D i2c_bus->msgs_count) + cmd |=3D MASTER_TRIGGER_LAST_STOP; + } + } + writel(AST2600_I2CM_SET_RX_DMA_LEN(xfer_len - 1), + i2c_bus->reg_base + AST2600_I2CM_DMA_LEN); + i2c_bus->master_safe_buf =3D i2c_get_dma_safe_msg_buf(msg, 1); + if (!i2c_bus->master_safe_buf) + return -ENOMEM; + i2c_bus->master_dma_addr =3D + dma_map_single(i2c_bus->dev, i2c_bus->master_safe_buf, + msg->len, DMA_FROM_DEVICE); + if (dma_mapping_error(i2c_bus->dev, i2c_bus->master_dma_addr)) { + i2c_put_dma_safe_msg_buf(i2c_bus->master_safe_buf, msg, false); + i2c_bus->master_safe_buf =3D NULL; + return -ENOMEM; + } + writel(i2c_bus->master_dma_addr, i2c_bus->reg_base + AST2600_I2CM_RX_DM= A); + } else if (i2c_bus->mode =3D=3D BUFF_MODE) { + /* buff mode */ + cmd |=3D AST2600_I2CM_RX_BUFF_EN; + if (msg->flags & I2C_M_RECV_LEN) { + dev_dbg(i2c_bus->dev, "smbus read\n"); + xfer_len =3D 1; + } else { + if (msg->len > i2c_bus->buf_size) { + xfer_len =3D i2c_bus->buf_size; + } else { + xfer_len =3D msg->len; + if (i2c_bus->msgs_index + 1 =3D=3D i2c_bus->msgs_count) + cmd |=3D MASTER_TRIGGER_LAST_STOP; + } + } + writel(AST2600_I2CC_SET_RX_BUF_LEN(xfer_len), + i2c_bus->reg_base + AST2600_I2CC_BUFF_CTRL); + } else { + /* byte mode */ + xfer_len =3D 1; + if (msg->flags & I2C_M_RECV_LEN) { + dev_dbg(i2c_bus->dev, "smbus read\n"); + } else { + if (i2c_bus->msgs_index + 1 =3D=3D i2c_bus->msgs_count) { + if (msg->len =3D=3D 1) + cmd |=3D MASTER_TRIGGER_LAST_STOP; + } + } + } + } else { + if (i2c_bus->mode =3D=3D DMA_MODE) { + /* dma mode */ + if (msg->len > AST2600_I2C_DMA_SIZE) { + xfer_len =3D AST2600_I2C_DMA_SIZE; + } else { + if (i2c_bus->msgs_index + 1 =3D=3D i2c_bus->msgs_count) + cmd |=3D AST2600_I2CM_STOP_CMD; + xfer_len =3D msg->len; + } + + if (xfer_len) { + cmd |=3D AST2600_I2CM_TX_DMA_EN | AST2600_I2CM_TX_CMD; + writel(AST2600_I2CM_SET_TX_DMA_LEN(xfer_len - 1), + i2c_bus->reg_base + AST2600_I2CM_DMA_LEN); + i2c_bus->master_safe_buf =3D i2c_get_dma_safe_msg_buf(msg, 1); + if (!i2c_bus->master_safe_buf) + return -ENOMEM; + i2c_bus->master_dma_addr =3D + dma_map_single(i2c_bus->dev, i2c_bus->master_safe_buf, + msg->len, DMA_TO_DEVICE); + if (dma_mapping_error(i2c_bus->dev, i2c_bus->master_dma_addr)) { + i2c_put_dma_safe_msg_buf(i2c_bus->master_safe_buf, + msg, false); + i2c_bus->master_safe_buf =3D NULL; + return -ENOMEM; + } + writel(i2c_bus->master_dma_addr, + i2c_bus->reg_base + AST2600_I2CM_TX_DMA); + } + } else if (i2c_bus->mode =3D=3D BUFF_MODE) { + u8 wbuf[4]; + /* buff mode */ + if (msg->len > i2c_bus->buf_size) { + xfer_len =3D i2c_bus->buf_size; + } else { + if (i2c_bus->msgs_index + 1 =3D=3D i2c_bus->msgs_count) + cmd |=3D AST2600_I2CM_STOP_CMD; + xfer_len =3D msg->len; + } + if (xfer_len) { + cmd |=3D AST2600_I2CM_TX_BUFF_EN | AST2600_I2CM_TX_CMD; + if (readl(i2c_bus->reg_base + AST2600_I2CS_ISR)) + return -ENOMEM; + writel(AST2600_I2CC_SET_TX_BUF_LEN(xfer_len), + i2c_bus->reg_base + AST2600_I2CC_BUFF_CTRL); + if (readl(i2c_bus->reg_base + AST2600_I2CS_ISR)) + return -ENOMEM; + for (i =3D 0; i < xfer_len; i++) { + wbuf[i % 4] =3D msg->buf[i]; + if (i % 4 =3D=3D 3) + writel(*(u32 *)wbuf, i2c_bus->buf_base + i - 3); + } + if (--i % 4 !=3D 3) + writel(*(u32 *)wbuf, i2c_bus->buf_base + i - (i % 4)); + } + if (readl(i2c_bus->reg_base + AST2600_I2CS_ISR)) + return -ENOMEM; + } else { + /* byte mode */ + if ((i2c_bus->msgs_index + 1 =3D=3D i2c_bus->msgs_count) && (msg->len <= =3D 1)) + cmd |=3D AST2600_I2CM_STOP_CMD; + + if (msg->len) { + cmd |=3D AST2600_I2CM_TX_CMD; + xfer_len =3D 1; + writel(msg->buf[0], i2c_bus->reg_base + AST2600_I2CC_STS_AND_BUFF); + } else { + xfer_len =3D 0; + } + } + } + writel(cmd, i2c_bus->reg_base + AST2600_I2CM_CMD_STS); + return 0; +} + +static int ast2600_i2c_is_irq_error(u32 irq_status) +{ + if (irq_status & AST2600_I2CM_ARBIT_LOSS) + return -EAGAIN; + if (irq_status & (AST2600_I2CM_SDA_DL_TO | AST2600_I2CM_SCL_LOW_TO)) + return -EBUSY; + if (irq_status & (AST2600_I2CM_ABNORMAL)) + return -EPROTO; + + return 0; +} + +static void ast2600_i2c_master_package_irq(struct ast2600_i2c_bus *i2c_bus= , u32 sts) +{ + struct i2c_msg *msg =3D &i2c_bus->msgs[i2c_bus->msgs_index]; + u32 cmd =3D AST2600_I2CM_PKT_EN; + int xfer_len; + int i; + + sts &=3D ~AST2600_I2CM_PKT_DONE; + writel(AST2600_I2CM_PKT_DONE, i2c_bus->reg_base + AST2600_I2CM_ISR); + switch (sts) { + case AST2600_I2CM_PKT_ERROR: + i2c_bus->cmd_err =3D -EAGAIN; + complete(&i2c_bus->cmd_complete); + break; + case AST2600_I2CM_PKT_ERROR | AST2600_I2CM_TX_NAK: /* a0 fix for issue */ + fallthrough; + case AST2600_I2CM_PKT_ERROR | AST2600_I2CM_TX_NAK | AST2600_I2CM_NORMAL_S= TOP: + i2c_bus->cmd_err =3D -ENXIO; + complete(&i2c_bus->cmd_complete); + break; + case AST2600_I2CM_NORMAL_STOP: + /* write 0 byte only have stop isr */ + i2c_bus->msgs_index++; + if (i2c_bus->msgs_index < i2c_bus->msgs_count) { + if (ast2600_i2c_do_start(i2c_bus)) { + i2c_bus->cmd_err =3D -ENOMEM; + complete(&i2c_bus->cmd_complete); + } + } else { + i2c_bus->cmd_err =3D i2c_bus->msgs_index; + complete(&i2c_bus->cmd_complete); + } + break; + case AST2600_I2CM_TX_ACK: + case AST2600_I2CM_TX_ACK | AST2600_I2CM_NORMAL_STOP: + if (i2c_bus->mode =3D=3D DMA_MODE) + xfer_len =3D AST2600_I2C_GET_TX_DMA_LEN(readl(i2c_bus->reg_base + + AST2600_I2CM_DMA_LEN_STS)); + else if (i2c_bus->mode =3D=3D BUFF_MODE) + xfer_len =3D AST2600_I2CC_GET_TX_BUF_LEN(readl(i2c_bus->reg_base + + AST2600_I2CC_BUFF_CTRL)); + else + xfer_len =3D 1; + + i2c_bus->master_xfer_cnt +=3D xfer_len; + + if (i2c_bus->master_xfer_cnt =3D=3D msg->len) { + if (i2c_bus->mode =3D=3D DMA_MODE) { + dma_unmap_single(i2c_bus->dev, i2c_bus->master_dma_addr, msg->len, + DMA_TO_DEVICE); + i2c_put_dma_safe_msg_buf(i2c_bus->master_safe_buf, msg, true); + i2c_bus->master_safe_buf =3D NULL; + } + i2c_bus->msgs_index++; + if (i2c_bus->msgs_index =3D=3D i2c_bus->msgs_count) { + i2c_bus->cmd_err =3D i2c_bus->msgs_index; + complete(&i2c_bus->cmd_complete); + } else { + if (ast2600_i2c_do_start(i2c_bus)) { + i2c_bus->cmd_err =3D -ENOMEM; + complete(&i2c_bus->cmd_complete); + } + } + } else { + /* do next tx */ + cmd |=3D AST2600_I2CM_TX_CMD; + if (i2c_bus->mode =3D=3D DMA_MODE) { + cmd |=3D AST2600_I2CM_TX_DMA_EN; + xfer_len =3D msg->len - i2c_bus->master_xfer_cnt; + if (xfer_len > AST2600_I2C_DMA_SIZE) { + xfer_len =3D AST2600_I2C_DMA_SIZE; + } else { + if (i2c_bus->msgs_index + 1 =3D=3D i2c_bus->msgs_count) + cmd |=3D AST2600_I2CM_STOP_CMD; + } + writel(AST2600_I2CM_SET_TX_DMA_LEN(xfer_len - 1), + i2c_bus->reg_base + AST2600_I2CM_DMA_LEN); + writel(i2c_bus->master_dma_addr + i2c_bus->master_xfer_cnt, + i2c_bus->reg_base + AST2600_I2CM_TX_DMA); + } else if (i2c_bus->mode =3D=3D BUFF_MODE) { + u8 wbuf[4]; + + cmd |=3D AST2600_I2CM_TX_BUFF_EN; + xfer_len =3D msg->len - i2c_bus->master_xfer_cnt; + if (xfer_len > i2c_bus->buf_size) { + xfer_len =3D i2c_bus->buf_size; + } else { + if (i2c_bus->msgs_index + 1 =3D=3D i2c_bus->msgs_count) + cmd |=3D AST2600_I2CM_STOP_CMD; + } + for (i =3D 0; i < xfer_len; i++) { + wbuf[i % 4] =3D msg->buf[i2c_bus->master_xfer_cnt + i]; + if (i % 4 =3D=3D 3) + writel(*(u32 *)wbuf, i2c_bus->buf_base + i - 3); + } + if (--i % 4 !=3D 3) + writel(*(u32 *)wbuf, i2c_bus->buf_base + i - (i % 4)); + writel(AST2600_I2CC_SET_TX_BUF_LEN(xfer_len), + i2c_bus->reg_base + AST2600_I2CC_BUFF_CTRL); + } else { + /* byte */ + if ((i2c_bus->msgs_index + 1 =3D=3D i2c_bus->msgs_count) && + ((i2c_bus->master_xfer_cnt + 1) =3D=3D msg->len)) { + cmd |=3D AST2600_I2CM_STOP_CMD; + } + writel(msg->buf[i2c_bus->master_xfer_cnt], + i2c_bus->reg_base + AST2600_I2CC_STS_AND_BUFF); + } + writel(cmd, i2c_bus->reg_base + AST2600_I2CM_CMD_STS); + } + break; + case AST2600_I2CM_RX_DONE: +#ifdef CONFIG_I2C_SLAVE + /* Workaround for master/slave package mode enable rx done stuck issue + * When master go for first read (RX_DONE), slave mode will also effect + * Then controller will send nack, not operate anymore. + */ + if (readl(i2c_bus->reg_base + AST2600_I2CS_CMD_STS) & AST2600_I2CS_PKT_M= ODE_EN) { + u32 slave_cmd =3D readl(i2c_bus->reg_base + AST2600_I2CS_CMD_STS); + + writel(0, i2c_bus->reg_base + AST2600_I2CS_CMD_STS); + writel(slave_cmd, i2c_bus->reg_base + AST2600_I2CS_CMD_STS); + } + fallthrough; +#endif + case AST2600_I2CM_RX_DONE | AST2600_I2CM_NORMAL_STOP: + /* do next rx */ + if (i2c_bus->mode =3D=3D DMA_MODE) { + xfer_len =3D AST2600_I2C_GET_RX_DMA_LEN(readl(i2c_bus->reg_base + + AST2600_I2CM_DMA_LEN_STS)); + } else if (i2c_bus->mode =3D=3D BUFF_MODE) { + xfer_len =3D AST2600_I2CC_GET_RX_BUF_LEN( + readl(i2c_bus->reg_base + AST2600_I2CC_BUFF_CTRL)); + for (i =3D 0; i < xfer_len; i++) + msg->buf[i2c_bus->master_xfer_cnt + i] =3D + readb(i2c_bus->buf_base + 0x10 + i); + } else { + xfer_len =3D 1; + msg->buf[i2c_bus->master_xfer_cnt] =3D + AST2600_I2CC_GET_RX_BUFF(readl(i2c_bus->reg_base + + AST2600_I2CC_STS_AND_BUFF)); + } + + if (msg->flags & I2C_M_RECV_LEN) { + msg->len =3D msg->buf[0] + ((msg->flags & I2C_CLIENT_PEC) ? 2 : 1); + msg->len =3D min_t(unsigned int, msg->len, I2C_SMBUS_BLOCK_MAX); + msg->flags &=3D ~I2C_M_RECV_LEN; + } + i2c_bus->master_xfer_cnt +=3D xfer_len; + + if (i2c_bus->master_xfer_cnt =3D=3D msg->len) { + if (i2c_bus->mode =3D=3D DMA_MODE) { + dma_unmap_single(i2c_bus->dev, i2c_bus->master_dma_addr, msg->len, + DMA_FROM_DEVICE); + i2c_put_dma_safe_msg_buf(i2c_bus->master_safe_buf, msg, true); + i2c_bus->master_safe_buf =3D NULL; + } + + i2c_bus->msgs_index++; + if (i2c_bus->msgs_index =3D=3D i2c_bus->msgs_count) { + i2c_bus->cmd_err =3D i2c_bus->msgs_index; + complete(&i2c_bus->cmd_complete); + } else { + if (ast2600_i2c_do_start(i2c_bus)) { + i2c_bus->cmd_err =3D -ENOMEM; + complete(&i2c_bus->cmd_complete); + } + } + } else { + /* next rx */ + cmd |=3D AST2600_I2CM_RX_CMD; + if (i2c_bus->mode =3D=3D DMA_MODE) { + cmd |=3D AST2600_I2CM_RX_DMA_EN; + xfer_len =3D msg->len - i2c_bus->master_xfer_cnt; + if (xfer_len > AST2600_I2C_DMA_SIZE) { + xfer_len =3D AST2600_I2C_DMA_SIZE; + } else { + if (i2c_bus->msgs_index + 1 =3D=3D i2c_bus->msgs_count) + cmd |=3D MASTER_TRIGGER_LAST_STOP; + } + writel(AST2600_I2CM_SET_RX_DMA_LEN(xfer_len - 1), + i2c_bus->reg_base + AST2600_I2CM_DMA_LEN); + writel(i2c_bus->master_dma_addr + i2c_bus->master_xfer_cnt, + i2c_bus->reg_base + AST2600_I2CM_RX_DMA); + } else if (i2c_bus->mode =3D=3D BUFF_MODE) { + cmd |=3D AST2600_I2CM_RX_BUFF_EN; + xfer_len =3D msg->len - i2c_bus->master_xfer_cnt; + if (xfer_len > i2c_bus->buf_size) + xfer_len =3D i2c_bus->buf_size; + else { + if (i2c_bus->msgs_index + 1 =3D=3D i2c_bus->msgs_count) + cmd |=3D MASTER_TRIGGER_LAST_STOP; + } + writel(AST2600_I2CC_SET_RX_BUF_LEN(xfer_len), + i2c_bus->reg_base + AST2600_I2CC_BUFF_CTRL); + } else { + if ((i2c_bus->msgs_index + 1 =3D=3D i2c_bus->msgs_count) && + ((i2c_bus->master_xfer_cnt + 1) =3D=3D msg->len)) { + cmd |=3D MASTER_TRIGGER_LAST_STOP; + } + } + writel(cmd, i2c_bus->reg_base + AST2600_I2CM_CMD_STS); + } + break; + default: + dev_dbg(i2c_bus->dev, "unhandled sts %x\n", sts); + break; + } +} + +static int ast2600_i2c_master_irq(struct ast2600_i2c_bus *i2c_bus) +{ + u32 sts =3D readl(i2c_bus->reg_base + AST2600_I2CM_ISR); + u32 ier =3D readl(i2c_bus->reg_base + AST2600_I2CM_IER); + u32 ctrl =3D 0; + + if (!i2c_bus->alert_enable) + sts &=3D ~AST2600_I2CM_SMBUS_ALT; + + if (AST2600_I2CM_BUS_RECOVER_FAIL & sts) { + writel(AST2600_I2CM_BUS_RECOVER_FAIL, i2c_bus->reg_base + AST2600_I2CM_I= SR); + ctrl =3D readl(i2c_bus->reg_base + AST2600_I2CC_FUN_CTRL); + writel(0, i2c_bus->reg_base + AST2600_I2CC_FUN_CTRL); + writel(ctrl, i2c_bus->reg_base + AST2600_I2CC_FUN_CTRL); + i2c_bus->cmd_err =3D -EPROTO; + complete(&i2c_bus->cmd_complete); + return 1; + } + + if (AST2600_I2CM_BUS_RECOVER & sts) { + writel(AST2600_I2CM_BUS_RECOVER, i2c_bus->reg_base + AST2600_I2CM_ISR); + i2c_bus->cmd_err =3D 0; + complete(&i2c_bus->cmd_complete); + return 1; + } + + if (AST2600_I2CM_SMBUS_ALT & sts) { + if (ier & AST2600_I2CM_SMBUS_ALT) { + /* Disable ALT INT */ + writel(ier & ~AST2600_I2CM_SMBUS_ALT, i2c_bus->reg_base + AST2600_I2CM_= IER); + i2c_handle_smbus_alert(i2c_bus->ara); + writel(AST2600_I2CM_SMBUS_ALT, i2c_bus->reg_base + AST2600_I2CM_ISR); + dev_err(i2c_bus->dev, + "ast2600_master_alert_recv bus id %d, Disable Alt, Please Imple\n", + i2c_bus->adap.nr); + return 1; + } + } + + i2c_bus->cmd_err =3D ast2600_i2c_is_irq_error(sts); + if (i2c_bus->cmd_err) { + writel(AST2600_I2CM_PKT_DONE, i2c_bus->reg_base + AST2600_I2CM_ISR); + complete(&i2c_bus->cmd_complete); + return 1; + } + + if (AST2600_I2CM_PKT_DONE & sts) { + ast2600_i2c_master_package_irq(i2c_bus, sts); + return 1; + } + + return 0; +} + +static irqreturn_t ast2600_i2c_bus_irq(int irq, void *dev_id) +{ + struct ast2600_i2c_bus *i2c_bus =3D dev_id; + +#ifdef CONFIG_I2C_SLAVE + if (readl(i2c_bus->reg_base + AST2600_I2CC_FUN_CTRL) & AST2600_I2CC_SLAVE= _EN) { + if (ast2600_i2c_slave_irq(i2c_bus)) + return IRQ_HANDLED; + } +#endif + return ast2600_i2c_master_irq(i2c_bus) ? IRQ_HANDLED : IRQ_NONE; +} + +static int ast2600_i2c_master_xfer(struct i2c_adapter *adap, + struct i2c_msg *msgs, int num) +{ + struct ast2600_i2c_bus *i2c_bus =3D i2c_get_adapdata(adap); + unsigned long timeout; + int ret =3D 0; + + /* If bus is busy in a single master environment, attempt recovery. */ + if (!i2c_bus->multi_master && + (readl(i2c_bus->reg_base + AST2600_I2CC_STS_AND_BUFF) & AST2600_I2CC_= BUS_BUSY_STS)) { + int ret; + + ret =3D ast2600_i2c_recover_bus(i2c_bus); + if (ret) + return ret; + } + +#ifdef CONFIG_I2C_SLAVE + if (i2c_bus->mode =3D=3D BUFF_MODE) { + if (i2c_bus->slave_operate) + return -EBUSY; + /* disable slave isr */ + writel(0, i2c_bus->reg_base + AST2600_I2CS_IER); + if (readl(i2c_bus->reg_base + AST2600_I2CS_ISR) || (i2c_bus->slave_opera= te)) { + writel(AST2600_I2CS_PKT_DONE, i2c_bus->reg_base + AST2600_I2CS_IER); + return -EBUSY; + } + } +#endif + + i2c_bus->cmd_err =3D 0; + i2c_bus->msgs =3D msgs; + i2c_bus->msgs_index =3D 0; + i2c_bus->msgs_count =3D num; + reinit_completion(&i2c_bus->cmd_complete); + ret =3D ast2600_i2c_do_start(i2c_bus); +#ifdef CONFIG_I2C_SLAVE + /* avoid race condication slave is wait and master wait 1st slave operate= */ + if (i2c_bus->mode =3D=3D BUFF_MODE) + writel(AST2600_I2CS_PKT_DONE, i2c_bus->reg_base + AST2600_I2CS_IER); +#endif + if (ret) + goto master_out; + timeout =3D wait_for_completion_timeout(&i2c_bus->cmd_complete, i2c_bus->= adap.timeout); + if (timeout =3D=3D 0) { + u32 isr =3D readl(i2c_bus->reg_base + AST2600_I2CM_ISR); + u32 i2c_status =3D readl(i2c_bus->reg_base + AST2600_I2CC_STS_AND_BUFF); + + dev_dbg(i2c_bus->dev, "timeout isr[%x], sts[%x]\n", isr, i2c_status); + if (isr || (i2c_status & AST2600_I2CC_TX_DIR_MASK)) { + u32 ctrl =3D readl(i2c_bus->reg_base + AST2600_I2CC_FUN_CTRL); + + writel(0, i2c_bus->reg_base + AST2600_I2CC_FUN_CTRL); + writel(ctrl, i2c_bus->reg_base + AST2600_I2CC_FUN_CTRL); +#ifdef CONFIG_I2C_SLAVE + if (ctrl & AST2600_I2CC_SLAVE_EN) { + u32 cmd =3D SLAVE_TRIGGER_CMD; + + if (i2c_bus->mode =3D=3D DMA_MODE) { + cmd |=3D AST2600_I2CS_RX_DMA_EN; + writel(i2c_bus->slave_dma_addr, + i2c_bus->reg_base + AST2600_I2CS_RX_DMA); + writel(i2c_bus->slave_dma_addr, + i2c_bus->reg_base + AST2600_I2CS_TX_DMA); + writel(AST2600_I2CS_SET_RX_DMA_LEN(I2C_SLAVE_MSG_BUF_SIZE), + i2c_bus->reg_base + AST2600_I2CS_DMA_LEN); + } else if (i2c_bus->mode =3D=3D BUFF_MODE) { + cmd =3D SLAVE_TRIGGER_CMD; + } else { + cmd &=3D ~AST2600_I2CS_PKT_MODE_EN; + } + writel(cmd, i2c_bus->reg_base + AST2600_I2CS_CMD_STS); + } +#endif + } + ret =3D -ETIMEDOUT; + } else { + ret =3D i2c_bus->cmd_err; + } + + dev_dbg(i2c_bus->dev, "bus%d-m: %d end\n", i2c_bus->adap.nr, i2c_bus->cmd= _err); + +master_out: + if (i2c_bus->mode =3D=3D DMA_MODE) { + kfree(i2c_bus->master_safe_buf); + i2c_bus->master_safe_buf =3D NULL; + } + + return ret; +} + +static void ast2600_i2c_init(struct ast2600_i2c_bus *i2c_bus) +{ + struct platform_device *pdev =3D to_platform_device(i2c_bus->dev); + u32 fun_ctrl =3D AST2600_I2CC_BUS_AUTO_RELEASE | AST2600_I2CC_MASTER_EN; + + /* I2C Reset */ + writel(0, i2c_bus->reg_base + AST2600_I2CC_FUN_CTRL); + + if (of_property_read_bool(pdev->dev.of_node, "multi-master")) + i2c_bus->multi_master =3D true; + else + fun_ctrl |=3D AST2600_I2CC_MULTI_MASTER_DIS; + + /* Enable Master Mode */ + writel(fun_ctrl, i2c_bus->reg_base + AST2600_I2CC_FUN_CTRL); + /* disable slave address */ + writel(0, i2c_bus->reg_base + AST2600_I2CS_ADDR_CTRL); + + /* Set AC Timing */ + writel(ast2600_select_i2c_clock(i2c_bus), i2c_bus->reg_base + AST2600_I2C= C_AC_TIMING); + + /* Clear Interrupt */ + writel(0xfffffff, i2c_bus->reg_base + AST2600_I2CM_ISR); + +#ifdef CONFIG_I2C_SLAVE + /* for memory buffer initial */ + if (i2c_bus->mode =3D=3D DMA_MODE) { + i2c_bus->slave_dma_buf =3D dma_alloc_coherent(i2c_bus->dev, I2C_SLAVE_MS= G_BUF_SIZE, + &i2c_bus->slave_dma_addr, GFP_KERNEL); + if (!i2c_bus->slave_dma_buf) + return; + } + + writel(0xfffffff, i2c_bus->reg_base + AST2600_I2CS_ISR); + + if (i2c_bus->mode =3D=3D BYTE_MODE) { + writel(0xffff, i2c_bus->reg_base + AST2600_I2CS_IER); + } else { + /* Set interrupt generation of I2C slave controller */ + writel(AST2600_I2CS_PKT_DONE, i2c_bus->reg_base + AST2600_I2CS_IER); + } +#endif +} + +#ifdef CONFIG_I2C_SLAVE +static int ast2600_i2c_reg_slave(struct i2c_client *client) +{ + struct ast2600_i2c_bus *i2c_bus =3D i2c_get_adapdata(client->adapter); + u32 cmd =3D SLAVE_TRIGGER_CMD; + + if (i2c_bus->slave) + return -EINVAL; + + dev_dbg(i2c_bus->dev, "slave addr %x\n", client->addr); + + writel(0, i2c_bus->reg_base + AST2600_I2CS_ADDR_CTRL); + writel(AST2600_I2CC_SLAVE_EN | readl(i2c_bus->reg_base + AST2600_I2CC_FUN= _CTRL), + i2c_bus->reg_base + AST2600_I2CC_FUN_CTRL); + + /* trigger rx buffer */ + if (i2c_bus->mode =3D=3D DMA_MODE) { + cmd |=3D AST2600_I2CS_RX_DMA_EN; + writel(i2c_bus->slave_dma_addr, i2c_bus->reg_base + AST2600_I2CS_RX_DMA); + writel(i2c_bus->slave_dma_addr, i2c_bus->reg_base + AST2600_I2CS_TX_DMA); + writel(AST2600_I2CS_SET_RX_DMA_LEN(I2C_SLAVE_MSG_BUF_SIZE), + i2c_bus->reg_base + AST2600_I2CS_DMA_LEN); + } else if (i2c_bus->mode =3D=3D BUFF_MODE) { + cmd =3D SLAVE_TRIGGER_CMD; + } else { + cmd &=3D ~AST2600_I2CS_PKT_MODE_EN; + } + + writel(cmd, i2c_bus->reg_base + AST2600_I2CS_CMD_STS); + i2c_bus->slave =3D client; + /* Set slave addr. */ + writel(client->addr | AST2600_I2CS_ADDR1_ENABLE, + i2c_bus->reg_base + AST2600_I2CS_ADDR_CTRL); + + return 0; +} + +static int ast2600_i2c_unreg_slave(struct i2c_client *slave) +{ + struct ast2600_i2c_bus *i2c_bus =3D i2c_get_adapdata(slave->adapter); + + WARN_ON(!i2c_bus->slave); + + /* Turn off slave mode. */ + writel(~AST2600_I2CC_SLAVE_EN & readl(i2c_bus->reg_base + AST2600_I2CC_FU= N_CTRL), + i2c_bus->reg_base + AST2600_I2CC_FUN_CTRL); + writel(readl(i2c_bus->reg_base + AST2600_I2CS_ADDR_CTRL) & ~AST2600_I2CS_= ADDR1_MASK, + i2c_bus->reg_base + AST2600_I2CS_ADDR_CTRL); + + i2c_bus->slave =3D NULL; + + return 0; +} +#endif + +static u32 ast2600_i2c_functionality(struct i2c_adapter *adap) +{ + return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL | I2C_FUNC_SMBUS_BLOCK_DATA; +} + +static const struct i2c_algorithm i2c_ast2600_algorithm =3D { + .master_xfer =3D ast2600_i2c_master_xfer, +#if IS_ENABLED(CONFIG_I2C_SLAVE) + .reg_slave =3D ast2600_i2c_reg_slave, + .unreg_slave =3D ast2600_i2c_unreg_slave, +#endif + .functionality =3D ast2600_i2c_functionality, +}; + +static const struct of_device_id ast2600_i2c_bus_of_table[] =3D { + { + .compatible =3D "aspeed,ast2600-i2cv2", + }, + {} +}; + +MODULE_DEVICE_TABLE(of, ast2600_i2c_bus_of_table); + +static int ast2600_xfer_mode_str2val(const char *str, + const struct ast2600_xfer_mode_str2field *list) +{ + const struct ast2600_xfer_mode_str2field *p =3D list; + + for (p =3D list; p && p->name; p++) + if (!strcmp(p->name, str)) + return p->mode; + + /* default dma mode */ + return DMA_MODE; +} + +static int ast2600_i2c_probe(struct platform_device *pdev) +{ + struct device_node *np =3D pdev->dev.of_node; + struct device *dev =3D &pdev->dev; + struct ast2600_i2c_bus *i2c_bus; + struct resource *res; + const char *of_str; + u32 global_ctrl; + int ret =3D 0; + + i2c_bus =3D devm_kzalloc(dev, sizeof(*i2c_bus), GFP_KERNEL); + if (!i2c_bus) + return -ENOMEM; + + i2c_bus->reg_base =3D devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(i2c_bus->reg_base)) + return PTR_ERR(i2c_bus->reg_base); + + i2c_bus->rst =3D devm_reset_control_get_shared(dev, NULL); + if (IS_ERR(i2c_bus->rst)) + return dev_err_probe(dev, PTR_ERR(i2c_bus->rst), "Missing reset ctrl\n"); + + reset_control_deassert(i2c_bus->rst); + + i2c_bus->global_regs =3D syscon_regmap_lookup_by_phandle(np, "aspeed,glob= al-regs"); + if (IS_ERR(i2c_bus->global_regs)) + return PTR_ERR(i2c_bus->global_regs); + + regmap_read(i2c_bus->global_regs, AST2600_I2CG_CTRL, &global_ctrl); + if ((global_ctrl & AST2600_GLOBAL_INIT) !=3D AST2600_GLOBAL_INIT) { + regmap_write(i2c_bus->global_regs, AST2600_I2CG_CTRL, AST2600_GLOBAL_INI= T); + regmap_write(i2c_bus->global_regs, AST2600_I2CG_CLK_DIV_CTRL, I2CCG_DIV_= CTRL); + } + + i2c_bus->timeout_enable =3D 0; + i2c_bus->slave_operate =3D 0; + i2c_bus->dev =3D dev; + + ret =3D of_property_read_string_index(dev->of_node, + "aspeed,xfer-mode", 0, + &of_str); + if (!ret) + i2c_bus->mode =3D ast2600_xfer_mode_str2val(of_str, ast2600_xfer_mode_ty= pe); + else + i2c_bus->mode =3D DMA_MODE; + + + if (i2c_bus->mode =3D=3D BUFF_MODE) { + res =3D platform_get_resource(pdev, IORESOURCE_MEM, 1); + if (res && resource_size(res) >=3D 2) + i2c_bus->buf_base =3D devm_ioremap_resource(dev, res); + + if (!IS_ERR_OR_NULL(i2c_bus->buf_base)) + i2c_bus->buf_size =3D resource_size(res)/2; + } + + if (of_property_read_bool(dev->of_node, "aspeed,timeout")) + i2c_bus->timeout_enable =3D 1; + + init_completion(&i2c_bus->cmd_complete); + + i2c_bus->irq =3D platform_get_irq(pdev, 0); + if (i2c_bus->irq < 0) + return i2c_bus->irq; + + platform_set_drvdata(pdev, i2c_bus); + + i2c_bus->clk =3D devm_clk_get(i2c_bus->dev, NULL); + if (IS_ERR(i2c_bus->clk)) + return dev_err_probe(i2c_bus->dev, PTR_ERR(i2c_bus->clk), "Can't get clo= ck\n"); + + i2c_bus->apb_clk =3D clk_get_rate(i2c_bus->clk); + + ret =3D of_property_read_u32(dev->of_node, "clock-frequency", &i2c_bus->b= us_frequency); + if (ret < 0) { + dev_warn(dev, "Could not read clock-frequency property\n"); + i2c_bus->bus_frequency =3D 100000; + } + + /* Initialize the I2C adapter */ + i2c_bus->adap.owner =3D THIS_MODULE; + i2c_bus->adap.algo =3D &i2c_ast2600_algorithm; + i2c_bus->adap.retries =3D 0; + i2c_bus->adap.dev.parent =3D i2c_bus->dev; + i2c_bus->adap.dev.of_node =3D dev->of_node; + i2c_bus->adap.algo_data =3D i2c_bus; + strscpy(i2c_bus->adap.name, pdev->name, sizeof(i2c_bus->adap.name)); + i2c_set_adapdata(&i2c_bus->adap, i2c_bus); + + ast2600_i2c_init(i2c_bus); + + ret =3D devm_request_irq(dev, i2c_bus->irq, ast2600_i2c_bus_irq, 0, + dev_name(dev), i2c_bus); + if (ret < 0) + return dev_err_probe(dev, ret, "Unable to request irq %d\n", i2c_bus->ir= q); + + if (of_property_read_bool(dev->of_node, "smbus-alert")) { + i2c_bus->alert_enable =3D 1; + i2c_bus->ara =3D i2c_new_smbus_alert_device(&i2c_bus->adap, &i2c_bus->al= ert_data); + if (!i2c_bus->ara) + dev_warn(dev, "Failed to register ARA client\n"); + + writel(AST2600_I2CM_PKT_DONE | AST2600_I2CM_BUS_RECOVER | AST2600_I2CM_S= MBUS_ALT, + i2c_bus->reg_base + AST2600_I2CM_IER); + } else { + i2c_bus->alert_enable =3D 0; + /* Set interrupt generation of I2C master controller */ + writel(AST2600_I2CM_PKT_DONE | AST2600_I2CM_BUS_RECOVER, + i2c_bus->reg_base + AST2600_I2CM_IER); + } + + ret =3D i2c_add_adapter(&i2c_bus->adap); + if (ret) + return ret; + + dev_info(dev, "%s [%d]: adapter [%d khz] mode [%d]\n", + dev->of_node->name, i2c_bus->adap.nr, i2c_bus->bus_frequency / 1000, + i2c_bus->mode); + + return 0; + + return ret; +} + +static int ast2600_i2c_remove(struct platform_device *pdev) +{ + struct ast2600_i2c_bus *i2c_bus =3D platform_get_drvdata(pdev); + + /* Disable everything. */ + writel(0, i2c_bus->reg_base + AST2600_I2CC_FUN_CTRL); + writel(0, i2c_bus->reg_base + AST2600_I2CM_IER); + + i2c_del_adapter(&i2c_bus->adap); + devm_free_irq(&pdev->dev, i2c_bus->irq, i2c_bus); + +#ifdef CONFIG_I2C_SLAVE + /* for memory buffer initial */ + if (i2c_bus->mode =3D=3D DMA_MODE) + dma_free_coherent(i2c_bus->dev, I2C_SLAVE_MSG_BUF_SIZE, + i2c_bus->slave_dma_buf, i2c_bus->slave_dma_addr); +#endif + + return 0; +} + +static struct platform_driver ast2600_i2c_bus_driver =3D { + .probe =3D ast2600_i2c_probe, + .remove =3D ast2600_i2c_remove, + .driver =3D { + .name =3D KBUILD_MODNAME, + .of_match_table =3D ast2600_i2c_bus_of_table, + }, +}; +module_platform_driver(ast2600_i2c_bus_driver); + +MODULE_AUTHOR("Ryan Chen "); +MODULE_DESCRIPTION("ASPEED AST2600 I2C Controller Driver"); +MODULE_LICENSE("GPL"); --=20 2.34.1