From nobody Wed Sep 10 11:47:37 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 65299C7EE23 for ; Fri, 24 Feb 2023 20:03:17 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229969AbjBXUDQ (ORCPT ); Fri, 24 Feb 2023 15:03:16 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:55610 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229893AbjBXUCx (ORCPT ); Fri, 24 Feb 2023 15:02:53 -0500 Received: from mail-pl1-x631.google.com (mail-pl1-x631.google.com [IPv6:2607:f8b0:4864:20::631]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 471F130EBC; Fri, 24 Feb 2023 12:02:25 -0800 (PST) Received: by mail-pl1-x631.google.com with SMTP id q11so641733plx.5; Fri, 24 Feb 2023 12:02:25 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=0EqwRq/t+KHhVrbIAD1sooBDZlG3nzxQWus7/my7j0s=; b=I1dgb0dj7Ry8pPV5H+8x0JzSkv1l7+hzkHhVpi3PsbXQFnB42V9vKdq2xVDbpR5PLd hRgi83cakLyMem1WDy0aI7vC+aluruGZsonY+66gM5xCB+nsCr9FQsmLiIt1TowgqrTO URg/RG820QIjcNRZHPH5iKv8n+NG12XkAuUbl7c8A9IJBGuGt0n1UjEI7XsSx4gGcffg VrqqOvlkj7Rqwb9btPgO1+29UhiaP4sJqD6AfwpPlx8WaMTjns9V8Ohh7ckuWNvcsJN6 rAsaDspm4YDmXPLUrNFi0pOolOQ7XRYHTaKa5i/fqTcjwHIP00Hdmij3b4u05gDgOjRG E7Aw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=0EqwRq/t+KHhVrbIAD1sooBDZlG3nzxQWus7/my7j0s=; b=F1LTSuWMBNAsmxMP/c7GqiSq/MeDYWv/peUXS9Kwf2FIdH1ScCgat+EaBneGVejY8P EnwBfrZA+a6KiuZQyLHDCyGiwGS4oa9x2uLrzBXl5bAp9R7vuDtIibBXY3Hl2qyFVqEB rTSV9vrYMaFuZF3X445F2KkX3YvUxeK3IFdjdzUbJ9H3EGpgfgr2GkUP+ANmbqQSCIpp 9XjEEm98ovowk5FF6cgURHNwTpqfM62uqh3zY6LRV0c7Dmi+nyMt3/MEmCISKrEpTO4S R3qiQxy6hR4tYWwO1RtcSgbWNf4jCPTvquSkMtdygJlXSi868kj+puFdz38rRBSf52u9 z5mQ== X-Gm-Message-State: AO0yUKUocf32phR9Epgbjj5B29l8LkiRFAH5ACFfoyGUVJuY6LuzGwoz 0MUkPDcU2wcyyeSm5YDAjrk= X-Google-Smtp-Source: AK7set+9kh3rZJdUeXwQTJFcy1but/mDwe+TzZL3CWHxMVLR9vaJ60FohE1K0k1XrEQSPrrppgCSKg== X-Received: by 2002:a17:90a:19ce:b0:22c:6d7c:c521 with SMTP id 14-20020a17090a19ce00b0022c6d7cc521mr19218117pjj.45.1677268944714; Fri, 24 Feb 2023 12:02:24 -0800 (PST) Received: from localhost ([2a00:79e1:abd:4a00:61b:48ed:72ab:435b]) by smtp.gmail.com with ESMTPSA id nh12-20020a17090b364c00b002369d3b282csm42992pjb.40.2023.02.24.12.02.23 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 24 Feb 2023 12:02:24 -0800 (PST) From: Rob Clark To: dri-devel@lists.freedesktop.org Cc: freedreno@lists.freedesktop.org, Daniel Vetter , =?UTF-8?q?Christian=20K=C3=B6nig?= , =?UTF-8?q?Michel=20D=C3=A4nzer?= , Tvrtko Ursulin , Rodrigo Vivi , Alex Deucher , Pekka Paalanen , Simon Ser , Luben Tuikov , Rob Clark , Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , David Airlie , linux-arm-msm@vger.kernel.org (open list:DRM DRIVER FOR MSM ADRENO GPU), linux-kernel@vger.kernel.org (open list) Subject: [PATCH v6 13/15] drm/msm: Add wait-boost support Date: Fri, 24 Feb 2023 12:01:41 -0800 Message-Id: <20230224200155.2510320-14-robdclark@gmail.com> X-Mailer: git-send-email 2.39.1 In-Reply-To: <20230224200155.2510320-1-robdclark@gmail.com> References: <20230224200155.2510320-1-robdclark@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Rob Clark Add a way for various userspace waits to signal urgency. Signed-off-by: Rob Clark --- drivers/gpu/drm/msm/msm_drv.c | 12 ++++++++---- drivers/gpu/drm/msm/msm_gem.c | 5 +++++ include/uapi/drm/msm_drm.h | 14 ++++++++++++-- 3 files changed, 25 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/msm/msm_drv.c b/drivers/gpu/drm/msm/msm_drv.c index aca48c868c14..f6764a86b2da 100644 --- a/drivers/gpu/drm/msm/msm_drv.c +++ b/drivers/gpu/drm/msm/msm_drv.c @@ -46,6 +46,7 @@ * - 1.8.0 - Add MSM_BO_CACHED_COHERENT for supported GPUs (a6xx) * - 1.9.0 - Add MSM_SUBMIT_FENCE_SN_IN * - 1.10.0 - Add MSM_SUBMIT_BO_NO_IMPLICIT + * - 1.11.0 - Add wait boost (MSM_WAIT_FENCE_BOOST, MSM_PREP_BOOST) */ #define MSM_VERSION_MAJOR 1 #define MSM_VERSION_MINOR 10 @@ -899,7 +900,7 @@ static int msm_ioctl_gem_info(struct drm_device *dev, v= oid *data, } =20 static int wait_fence(struct msm_gpu_submitqueue *queue, uint32_t fence_id, - ktime_t timeout) + ktime_t timeout, uint32_t flags) { struct dma_fence *fence; int ret; @@ -929,6 +930,9 @@ static int wait_fence(struct msm_gpu_submitqueue *queue= , uint32_t fence_id, if (!fence) return 0; =20 + if (flags & MSM_WAIT_FENCE_BOOST) + dma_fence_set_deadline(fence, ktime_get()); + ret =3D dma_fence_wait_timeout(fence, true, timeout_to_jiffies(&timeout)); if (ret =3D=3D 0) { ret =3D -ETIMEDOUT; @@ -949,8 +953,8 @@ static int msm_ioctl_wait_fence(struct drm_device *dev,= void *data, struct msm_gpu_submitqueue *queue; int ret; =20 - if (args->pad) { - DRM_ERROR("invalid pad: %08x\n", args->pad); + if (args->flags & ~MSM_WAIT_FENCE_FLAGS) { + DRM_ERROR("invalid flags: %08x\n", args->flags); return -EINVAL; } =20 @@ -961,7 +965,7 @@ static int msm_ioctl_wait_fence(struct drm_device *dev,= void *data, if (!queue) return -ENOENT; =20 - ret =3D wait_fence(queue, args->fence, to_ktime(args->timeout)); + ret =3D wait_fence(queue, args->fence, to_ktime(args->timeout), args->fla= gs); =20 msm_submitqueue_put(queue); =20 diff --git a/drivers/gpu/drm/msm/msm_gem.c b/drivers/gpu/drm/msm/msm_gem.c index 1dee0d18abbb..dd4a0d773f6e 100644 --- a/drivers/gpu/drm/msm/msm_gem.c +++ b/drivers/gpu/drm/msm/msm_gem.c @@ -846,6 +846,11 @@ int msm_gem_cpu_prep(struct drm_gem_object *obj, uint3= 2_t op, ktime_t *timeout) op & MSM_PREP_NOSYNC ? 0 : timeout_to_jiffies(timeout); long ret; =20 + if (op & MSM_PREP_BOOST) { + dma_resv_set_deadline(obj->resv, dma_resv_usage_rw(write), + ktime_get()); + } + ret =3D dma_resv_wait_timeout(obj->resv, dma_resv_usage_rw(write), true, remain); if (ret =3D=3D 0) diff --git a/include/uapi/drm/msm_drm.h b/include/uapi/drm/msm_drm.h index 329100016e7c..dbf0d6f43fa9 100644 --- a/include/uapi/drm/msm_drm.h +++ b/include/uapi/drm/msm_drm.h @@ -151,8 +151,13 @@ struct drm_msm_gem_info { #define MSM_PREP_READ 0x01 #define MSM_PREP_WRITE 0x02 #define MSM_PREP_NOSYNC 0x04 +#define MSM_PREP_BOOST 0x08 =20 -#define MSM_PREP_FLAGS (MSM_PREP_READ | MSM_PREP_WRITE | MSM_PREP_NO= SYNC) +#define MSM_PREP_FLAGS (MSM_PREP_READ | \ + MSM_PREP_WRITE | \ + MSM_PREP_NOSYNC | \ + MSM_PREP_BOOST | \ + 0) =20 struct drm_msm_gem_cpu_prep { __u32 handle; /* in */ @@ -286,6 +291,11 @@ struct drm_msm_gem_submit { =20 }; =20 +#define MSM_WAIT_FENCE_BOOST 0x00000001 +#define MSM_WAIT_FENCE_FLAGS ( \ + MSM_WAIT_FENCE_BOOST | \ + 0) + /* The normal way to synchronize with the GPU is just to CPU_PREP on * a buffer if you need to access it from the CPU (other cmdstream * submission from same or other contexts, PAGE_FLIP ioctl, etc, all @@ -295,7 +305,7 @@ struct drm_msm_gem_submit { */ struct drm_msm_wait_fence { __u32 fence; /* in */ - __u32 pad; + __u32 flags; /* in, bitmask of MSM_WAIT_FENCE_x */ struct drm_msm_timespec timeout; /* in */ __u32 queueid; /* in, submitqueue id */ }; --=20 2.39.1