From nobody Tue Sep 9 06:22:21 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 79A50C678D5 for ; Fri, 24 Feb 2023 15:42:51 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229657AbjBXPmr (ORCPT ); Fri, 24 Feb 2023 10:42:47 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:37130 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229452AbjBXPmo (ORCPT ); Fri, 24 Feb 2023 10:42:44 -0500 Received: from mail-qv1-xf2d.google.com (mail-qv1-xf2d.google.com [IPv6:2607:f8b0:4864:20::f2d]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 8CC2D66964 for ; Fri, 24 Feb 2023 07:42:41 -0800 (PST) Received: by mail-qv1-xf2d.google.com with SMTP id op8so14281726qvb.11 for ; Fri, 24 Feb 2023 07:42:41 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=Cjo72C8shTrqkNA3EEnWKBaKFGEmPRo9WbjcR9+Jn9I=; b=PhDTwowMUme0dsqcW825Cf4np4FW0FiS5vbXxSrx+YZNPz3MXCudsjHjKWL0YjU9/F Ipbsr9GtgGke2dc2SncWt2JIz/NUn+Z83xxc3xRJ6RM1XIRxh6wtXOW/pF1ke5+pJqx2 0fzqVauj83hdKIj/kf1MksgZTkmhwMhgw2z0LdQo5QMHTQiLMmlZPpKPHxL4vAbcx50L nC4/BulCV9mkMWOGMwMt4KAPzD8lEBOSHNrexEQnBIB76wySSbxRtqvZtmbSGZSnGlws FQ+Jjee35knKdZDnhNYS0pZ2RfDduTq0QVILiINwIyQwtkOOcW97jS10Abp+xHjTrQ1Q jz0g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Cjo72C8shTrqkNA3EEnWKBaKFGEmPRo9WbjcR9+Jn9I=; b=ea4TzvK98l9sfeum1phi13dxSBPSVz6sK+o3JvFya0OPr1ws81d3ggUNcSVgF94lP4 TCLrAZ2lO+1T1azTyub2OjGMCow9oy9SnitePj2bJl+o3PQ7AJORQHIFyDG7nR4IxOqt lWjkCaWhwXd6oAJJMdR4MxyOFI32Cixg/omLkdkko4zZwz8Ec4P5QR//j8FBQ6xLLUIn GLehNzbOaXzv7Tqa7BEU2ITJ8hxiHoKBqpnffAdVzY2UY3bKM1JnHC6LoZL6PPXnPO8A 9BfvZ3lVUP0tlQzKp/mfVebjc6oBcxKeBP/cMB200S5zwJvXOHd4o5fgt3BKM/cfdG6i mWWg== X-Gm-Message-State: AO0yUKXl08Sl9mY15Y+fnpfOJ6djR7UhzLbUsiL4bd3WEmL2POACHPmX YBBooqGC7OXlCYos5ErDYj0IQ/MD7g== X-Google-Smtp-Source: AK7set+sR8BGy70rkPlCi7+YiiY/OtXUKSyOcmJw2pOENpHzLDkwVJhu5FOH2OvOJCIEZO+CLLbo5g== X-Received: by 2002:ad4:5bef:0:b0:56e:b7a7:40e7 with SMTP id k15-20020ad45bef000000b0056eb7a740e7mr22310066qvc.24.1677253360467; Fri, 24 Feb 2023 07:42:40 -0800 (PST) Received: from citadel.. (075-129-116-198.res.spectrum.com. [75.129.116.198]) by smtp.gmail.com with ESMTPSA id e26-20020a05620a015a00b0073b399700adsm1276131qkn.3.2023.02.24.07.42.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 24 Feb 2023 07:42:39 -0800 (PST) From: Brian Gerst To: linux-kernel@vger.kernel.org, x86@kernel.org Cc: David Woodhouse , Usama Arif , Thomas Gleixner , Borislav Petkov , "H . Peter Anvin" , Peter Zijlstra , Andy Lutomirski , Ingo Molnar , Brian Gerst , David Woodhouse Subject: [PATCH v2 1/5] x86/smpboot: Remove initial_stack on 64-bit Date: Fri, 24 Feb 2023 10:42:31 -0500 Message-Id: <20230224154235.277350-2-brgerst@gmail.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230224154235.277350-1-brgerst@gmail.com> References: <20230224154235.277350-1-brgerst@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Load RSP from current_task->thread.sp instead. Signed-off-by: Brian Gerst Reviewed-by: David Woodhouse Signed-off-by: David Woodhouse Tested-by: Usama Arif Signed-off-by: Usama Arif --- arch/x86/include/asm/processor.h | 6 +++++- arch/x86/kernel/acpi/sleep.c | 2 +- arch/x86/kernel/head_64.S | 35 ++++++++++++++++++-------------- arch/x86/xen/xen-head.S | 2 +- 4 files changed, 27 insertions(+), 18 deletions(-) diff --git a/arch/x86/include/asm/processor.h b/arch/x86/include/asm/proces= sor.h index 8d73004e4cac..a1e4fa58b357 100644 --- a/arch/x86/include/asm/processor.h +++ b/arch/x86/include/asm/processor.h @@ -647,7 +647,11 @@ static inline void spin_lock_prefetch(const void *x) #define KSTK_ESP(task) (task_pt_regs(task)->sp) =20 #else -#define INIT_THREAD { } +extern unsigned long __end_init_task[]; + +#define INIT_THREAD { \ + .sp =3D (unsigned long)&__end_init_task - sizeof(struct pt_regs), \ +} =20 extern unsigned long KSTK_ESP(struct task_struct *task); =20 diff --git a/arch/x86/kernel/acpi/sleep.c b/arch/x86/kernel/acpi/sleep.c index 47e75c056cb5..008fda8b1982 100644 --- a/arch/x86/kernel/acpi/sleep.c +++ b/arch/x86/kernel/acpi/sleep.c @@ -113,7 +113,7 @@ int x86_acpi_suspend_lowlevel(void) saved_magic =3D 0x12345678; #else /* CONFIG_64BIT */ #ifdef CONFIG_SMP - initial_stack =3D (unsigned long)temp_stack + sizeof(temp_stack); + current->thread.sp =3D (unsigned long)temp_stack + sizeof(temp_stack); early_gdt_descr.address =3D (unsigned long)get_cpu_gdt_rw(smp_processor_id()); initial_gs =3D per_cpu_offset(smp_processor_id()); diff --git a/arch/x86/kernel/head_64.S b/arch/x86/kernel/head_64.S index c32e5b06a9ce..f7905ba4b992 100644 --- a/arch/x86/kernel/head_64.S +++ b/arch/x86/kernel/head_64.S @@ -62,8 +62,8 @@ SYM_CODE_START_NOALIGN(startup_64) * tables and then reload them. */ =20 - /* Set up the stack for verify_cpu(), similar to initial_stack below */ - leaq (__end_init_task - FRAME_SIZE)(%rip), %rsp + /* Set up the stack for verify_cpu() */ + leaq (__end_init_task - PTREGS_SIZE)(%rip), %rsp =20 leaq _text(%rip), %rdi =20 @@ -245,11 +245,11 @@ SYM_INNER_LABEL(secondary_startup_64_no_verify, SYM_L= _GLOBAL) #ifdef CONFIG_SMP /* * Is this the boot CPU coming up? If so everything is available - * in initial_gs, initial_stack and early_gdt_descr. + * in initial_gs and early_gdt_descr. */ movl smpboot_control(%rip), %edx testl $STARTUP_SECONDARY, %edx - jz .Lsetup_cpu + jz .Linit_cpu0_data =20 /* * For parallel boot, the APIC ID is retrieved from CPUID, and then @@ -302,6 +302,10 @@ SYM_INNER_LABEL(secondary_startup_64_no_verify, SYM_L_= GLOBAL) hlt jmp 1b =20 +.Linit_cpu0_data: + movq __per_cpu_offset(%rip), %rdx + jmp .Lsetup_cpu + .Linit_cpu_data: /* Get the per cpu offset for the given CPU# which is in ECX */ leaq __per_cpu_offset(%rip), %rbx @@ -314,13 +318,21 @@ SYM_INNER_LABEL(secondary_startup_64_no_verify, SYM_L= _GLOBAL) addq %rbx, %rcx movq %rcx, early_gdt_descr_base(%rip) =20 - /* Find the idle task stack */ - movq pcpu_hot + X86_current_task(%rbx), %rcx - movq TASK_threadsp(%rcx), %rcx - movq %rcx, initial_stack(%rip) + movq %rbx, %rdx +#else + xorl %edx, %edx #endif /* CONFIG_SMP */ =20 .Lsetup_cpu: + /* + * Setup a boot time stack - Any secondary CPU will have lost its stack + * by now because the cr3-switch above unmaps the real-mode stack + * + * RDX contains the per-cpu offset + */ + movq pcpu_hot + X86_current_task(%rdx), %rax + movq TASK_threadsp(%rax), %rsp + /* * We must switch to a new descriptor in kernel space for the GDT * because soon the kernel won't have access anymore to the userspace @@ -355,12 +367,6 @@ SYM_INNER_LABEL(secondary_startup_64_no_verify, SYM_L_= GLOBAL) movl initial_gs+4(%rip),%edx wrmsr =20 - /* - * Setup a boot time stack - Any secondary CPU will have lost its stack - * by now because the cr3-switch above unmaps the real-mode stack - */ - movq initial_stack(%rip), %rsp - /* Drop the realmode protection. For the boot CPU the pointer is NULL! */ movq trampoline_lock(%rip), %rax testq %rax, %rax @@ -517,7 +523,6 @@ SYM_DATA(initial_vc_handler, .quad handle_vc_boot_ghcb) * The FRAME_SIZE gap is a convention which helps the in-kernel unwinder * reliably detect the end of the stack. */ -SYM_DATA(initial_stack, .quad init_thread_union + THREAD_SIZE - FRAME_SIZE) SYM_DATA(trampoline_lock, .quad 0); __FINITDATA =20 diff --git a/arch/x86/xen/xen-head.S b/arch/x86/xen/xen-head.S index e36ea4268bd2..91f7a53519a7 100644 --- a/arch/x86/xen/xen-head.S +++ b/arch/x86/xen/xen-head.S @@ -49,7 +49,7 @@ SYM_CODE_START(startup_xen) ANNOTATE_NOENDBR cld =20 - mov initial_stack(%rip), %rsp + leaq (__end_init_task - PTREGS_SIZE)(%rip), %rsp =20 /* Set up %gs. * --=20 2.39.2 From nobody Tue Sep 9 06:22:21 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 89DC6C61DA3 for ; Fri, 24 Feb 2023 15:42:51 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229672AbjBXPmt (ORCPT ); Fri, 24 Feb 2023 10:42:49 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:37158 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229556AbjBXPmo (ORCPT ); Fri, 24 Feb 2023 10:42:44 -0500 Received: from mail-qv1-xf2b.google.com (mail-qv1-xf2b.google.com [IPv6:2607:f8b0:4864:20::f2b]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id A8F71671F7 for ; Fri, 24 Feb 2023 07:42:42 -0800 (PST) Received: by mail-qv1-xf2b.google.com with SMTP id o3so13338206qvr.1 for ; Fri, 24 Feb 2023 07:42:42 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=BgwqEMh4NVAV5/z+1kf0xdWoVrFjbHnXgTZ0UxK4U+A=; b=A/qW8aPHMfBwwIk8xwVvReYCkRKJt3Wkfuk+H+kesyi8qO3eKXbjhqYBM3PHlxX2TJ J85Q2mjlchuUDRJu31HjMA9/59M19PXwu/J05kHydivGztJiMNPYROVpPBFn7I8+FJYr 4xniQn2dgmRPA9y5Zg6wbMq+BitsGD5OiQOXFYJ2Uq+vFeQ2K5ZkITvG1ZS/cMhqy3ye 4+x+KWLnJD+FhhPOvoeFpFlTrvKHIf/+MzKN7yCjBZQj98Lb5PGrXPwcVpcJMF4IxjOd H7m6TZsGPXVZF1nrZxXKvwNuNPSLrB+O53YbM1+bsKqyPRLMCG8al/QWuktYmiiiPhEp b98Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=BgwqEMh4NVAV5/z+1kf0xdWoVrFjbHnXgTZ0UxK4U+A=; b=Fq7Kg1EELjVP59mpJXHmxd2YeKJ9XJxaLo48AtcIWJCHMtBQVt/SdngMwXOJHeIA/8 xXp0egps3rxGemlYf/z50VOBc5l4PFyIGqj+MONi81nZu//Fs4B05Vhl8CqfjNAw8KTS wlGpqkHQvBvUoJgMcYvzRqxYFddq5ysRoilrGmGp1ymkoNX6Agl04gIIP+JEiW3rjVfY 3WF6llKEUOzLS/hTBJbgM3Vp2bnNRVlJuaHRcA3rekEddFX6YPiFdNdBZjEg8MWRfkQ1 hbZ+nQnAaewdLMQJKWxYyJRsjk1Kpg+Q6D5mYOP/r66+hkQYJLlxAL3Sy/FH6jWOlXnz 8Hwg== X-Gm-Message-State: AO0yUKXLefh1jwAyQe1+dH5etjploafVb7ltnLp5VZjjQ3Ih3q+jxYIb bOEUqVwOxK3qfv7cFSpgJiP+ywKhlQ== X-Google-Smtp-Source: AK7set9eMLORCaRWXMiWW4eSdJsvRF9ubgz4as0YXJRNTFFEllaZ+CBvlglmO+cXoOepdnt2ju/3GA== X-Received: by 2002:ad4:5748:0:b0:571:314:d725 with SMTP id q8-20020ad45748000000b005710314d725mr33296502qvx.49.1677253361626; Fri, 24 Feb 2023 07:42:41 -0800 (PST) Received: from citadel.. (075-129-116-198.res.spectrum.com. [75.129.116.198]) by smtp.gmail.com with ESMTPSA id e26-20020a05620a015a00b0073b399700adsm1276131qkn.3.2023.02.24.07.42.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 24 Feb 2023 07:42:41 -0800 (PST) From: Brian Gerst To: linux-kernel@vger.kernel.org, x86@kernel.org Cc: David Woodhouse , Usama Arif , Thomas Gleixner , Borislav Petkov , "H . Peter Anvin" , Peter Zijlstra , Andy Lutomirski , Ingo Molnar , Brian Gerst , David Woodhouse Subject: [PATCH v2 2/5] x86/smpboot: Remove early_gdt_descr on 64-bit Date: Fri, 24 Feb 2023 10:42:32 -0500 Message-Id: <20230224154235.277350-3-brgerst@gmail.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230224154235.277350-1-brgerst@gmail.com> References: <20230224154235.277350-1-brgerst@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Build the GDT descriptor on the stack instead. Signed-off-by: Brian Gerst Reviewed-by: David Woodhouse Signed-off-by: David Woodhouse Tested-by: Usama Arif Signed-off-by: Usama Arif --- arch/x86/kernel/acpi/sleep.c | 2 -- arch/x86/kernel/head_64.S | 19 +++++++------------ 2 files changed, 7 insertions(+), 14 deletions(-) diff --git a/arch/x86/kernel/acpi/sleep.c b/arch/x86/kernel/acpi/sleep.c index 008fda8b1982..6538ddb55f28 100644 --- a/arch/x86/kernel/acpi/sleep.c +++ b/arch/x86/kernel/acpi/sleep.c @@ -114,8 +114,6 @@ int x86_acpi_suspend_lowlevel(void) #else /* CONFIG_64BIT */ #ifdef CONFIG_SMP current->thread.sp =3D (unsigned long)temp_stack + sizeof(temp_stack); - early_gdt_descr.address =3D - (unsigned long)get_cpu_gdt_rw(smp_processor_id()); initial_gs =3D per_cpu_offset(smp_processor_id()); /* Force the startup into boot mode */ saved_smpboot_ctrl =3D xchg(&smpboot_control, 0); diff --git a/arch/x86/kernel/head_64.S b/arch/x86/kernel/head_64.S index f7905ba4b992..0dd57d573a0e 100644 --- a/arch/x86/kernel/head_64.S +++ b/arch/x86/kernel/head_64.S @@ -245,7 +245,7 @@ SYM_INNER_LABEL(secondary_startup_64_no_verify, SYM_L_G= LOBAL) #ifdef CONFIG_SMP /* * Is this the boot CPU coming up? If so everything is available - * in initial_gs and early_gdt_descr. + * in initial_gs. */ movl smpboot_control(%rip), %edx testl $STARTUP_SECONDARY, %edx @@ -313,11 +313,6 @@ SYM_INNER_LABEL(secondary_startup_64_no_verify, SYM_L_= GLOBAL) /* Save it for GS BASE setup */ movq %rbx, initial_gs(%rip) =20 - /* Calculate the GDT address */ - movq $gdt_page, %rcx - addq %rbx, %rcx - movq %rcx, early_gdt_descr_base(%rip) - movq %rbx, %rdx #else xorl %edx, %edx @@ -339,7 +334,12 @@ SYM_INNER_LABEL(secondary_startup_64_no_verify, SYM_L_= GLOBAL) * addresses where we're currently running on. We have to do that here * because in 32bit we couldn't load a 64bit linear address. */ - lgdt early_gdt_descr(%rip) + subq $16, %rsp + movw $(GDT_SIZE-1), (%rsp) + leaq gdt_page(%rdx), %rax + movq %rax, 2(%rsp) + lgdt (%rsp) + addq $16, %rsp =20 /* set up data segments */ xorl %eax,%eax @@ -754,11 +754,6 @@ SYM_DATA_END(level1_fixmap_pgt) =20 .data .align 16 - -SYM_DATA(early_gdt_descr, .word GDT_ENTRIES*8-1) -SYM_DATA_LOCAL(early_gdt_descr_base, .quad INIT_PER_CPU_VAR(gdt_page)) - - .align 16 SYM_DATA(smpboot_control, .long 0) =20 .align 16 --=20 2.39.2 From nobody Tue Sep 9 06:22:21 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id DB392C678DB for ; Fri, 24 Feb 2023 15:42:53 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229689AbjBXPmw (ORCPT ); Fri, 24 Feb 2023 10:42:52 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:37154 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229585AbjBXPmq (ORCPT ); Fri, 24 Feb 2023 10:42:46 -0500 Received: from mail-qt1-x82c.google.com (mail-qt1-x82c.google.com [IPv6:2607:f8b0:4864:20::82c]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 00CDE6A9CD for ; Fri, 24 Feb 2023 07:42:43 -0800 (PST) Received: by mail-qt1-x82c.google.com with SMTP id cf14so4657299qtb.10 for ; Fri, 24 Feb 2023 07:42:43 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=kkpL2g7L2sQ+6ZxUM2vC2iNXW2IcArehGjgvwIpbvEw=; b=Xhb7nQliM0PER/Dw9ahi/hPKBHv/E6io/C+U0Omq1Ib5xL2ZrelvvLuQB7ZktxhFPc r9CsY9S01DXv+SmTttclUjHJuOc2bVKe6wSdIIkoNLEhFk3mpSrhGOWo0lmck88atSVM OCcMGV9DV7og10HrnvCQqia3ybm6vi4zVjea0QMBjTH0/caexqkXwVyXm2llf2mfXiGR 7XgMtLIydlaLS5Ir8fmEbdx4VMumQK9v7+vyCAo+4iJUgcFWkB0j30FcVW7W5bAUSvKv etwkIM+1qmZt5cMzQYG2M5nQmaqxSlaPcPWTpi/Wq8KoVXwvQ9pXg/sAvdGPgWBe1SFW H2nw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=kkpL2g7L2sQ+6ZxUM2vC2iNXW2IcArehGjgvwIpbvEw=; b=X0d+5wkNAJoDOoOmQ+P5gNdidhL4pcBXMac/lqS2duUmfGThQW0TWMt5/oRIr6YhN6 Nnun6IKA4RSiKA7gtXMrbekHi/Ofo6vLdV95xnX52PKsnMafhk85U1F38I3M4i+nRCpg idU+AMawKM8uv2iPizwlyeJGoMJaeKTPS3ggwxPpPP30Wjv+nAEJu7ywGfdw/1NYqIrs gNs/zo+9DbNAb2FLXp87Yu/8G6AgrtiEH+ZcNC2IwkLoUL5JXHR/lOpVJK8zXFyGc1G4 PDgExi2k/Neq0l4Ww07/vSIVpc3YV9ght6ZNeSD9KhJsCqkj9D7cSQalZdQUatisbS+w +J/A== X-Gm-Message-State: AO0yUKXDu6UD7rq4oBxYyFQa2hB+L6sL4P9+6Rj13OH68q9ga3emR/Q0 Z714z486te/u2GfSDI0Rp4DLzd94sA== X-Google-Smtp-Source: AK7set+cmIv0LaIQRYRGTGGFQorfxHDYOT5+6QbE/5lz3if5/FqHTkBT5gAoKJNdKwZDPkUCImvw0Q== X-Received: by 2002:ac8:598c:0:b0:3bd:efa:baf with SMTP id e12-20020ac8598c000000b003bd0efa0bafmr30729870qte.19.1677253362756; Fri, 24 Feb 2023 07:42:42 -0800 (PST) Received: from citadel.. (075-129-116-198.res.spectrum.com. [75.129.116.198]) by smtp.gmail.com with ESMTPSA id e26-20020a05620a015a00b0073b399700adsm1276131qkn.3.2023.02.24.07.42.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 24 Feb 2023 07:42:42 -0800 (PST) From: Brian Gerst To: linux-kernel@vger.kernel.org, x86@kernel.org Cc: David Woodhouse , Usama Arif , Thomas Gleixner , Borislav Petkov , "H . Peter Anvin" , Peter Zijlstra , Andy Lutomirski , Ingo Molnar , Brian Gerst , David Woodhouse Subject: [PATCH v2 3/5] x86/smpboot: Remove initial_gs Date: Fri, 24 Feb 2023 10:42:33 -0500 Message-Id: <20230224154235.277350-4-brgerst@gmail.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230224154235.277350-1-brgerst@gmail.com> References: <20230224154235.277350-1-brgerst@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Use the percpu offset directly to set GSBASE. Signed-off-by: Brian Gerst Reviewed-by: David Woodhouse Signed-off-by: David Woodhouse Tested-by: Usama Arif Signed-off-by: Usama Arif --- arch/x86/include/asm/realmode.h | 1 - arch/x86/kernel/acpi/sleep.c | 1 - arch/x86/kernel/head_64.S | 34 ++++++++++----------------------- 3 files changed, 10 insertions(+), 26 deletions(-) diff --git a/arch/x86/include/asm/realmode.h b/arch/x86/include/asm/realmod= e.h index f0357cfe2fb0..87e5482acd0d 100644 --- a/arch/x86/include/asm/realmode.h +++ b/arch/x86/include/asm/realmode.h @@ -60,7 +60,6 @@ extern struct real_mode_header *real_mode_header; extern unsigned char real_mode_blob_end[]; =20 extern unsigned long initial_code; -extern unsigned long initial_gs; extern unsigned long initial_stack; #ifdef CONFIG_AMD_MEM_ENCRYPT extern unsigned long initial_vc_handler; diff --git a/arch/x86/kernel/acpi/sleep.c b/arch/x86/kernel/acpi/sleep.c index 6538ddb55f28..214dd4a79860 100644 --- a/arch/x86/kernel/acpi/sleep.c +++ b/arch/x86/kernel/acpi/sleep.c @@ -114,7 +114,6 @@ int x86_acpi_suspend_lowlevel(void) #else /* CONFIG_64BIT */ #ifdef CONFIG_SMP current->thread.sp =3D (unsigned long)temp_stack + sizeof(temp_stack); - initial_gs =3D per_cpu_offset(smp_processor_id()); /* Force the startup into boot mode */ saved_smpboot_ctrl =3D xchg(&smpboot_control, 0); #endif diff --git a/arch/x86/kernel/head_64.S b/arch/x86/kernel/head_64.S index 0dd57d573a0e..9ed87ba0609f 100644 --- a/arch/x86/kernel/head_64.S +++ b/arch/x86/kernel/head_64.S @@ -67,18 +67,10 @@ SYM_CODE_START_NOALIGN(startup_64) =20 leaq _text(%rip), %rdi =20 - /* - * initial_gs points to initial fixed_percpu_data struct with storage for - * the stack protector canary. Global pointer fixups are needed at this - * stage, so apply them as is done in fixup_pointer(), and initialize %gs - * such that the canary can be accessed at %gs:40 for subsequent C calls. - */ + /* Setup GSBASE to allow stack canary access for C code */ movl $MSR_GS_BASE, %ecx - movq initial_gs(%rip), %rax - movq $_text, %rdx - subq %rdx, %rax - addq %rdi, %rax - movq %rax, %rdx + leaq INIT_PER_CPU_VAR(fixed_percpu_data)(%rip), %rdx + movl %edx, %eax shrq $32, %rdx wrmsr =20 @@ -243,10 +235,7 @@ SYM_INNER_LABEL(secondary_startup_64_no_verify, SYM_L_= GLOBAL) ANNOTATE_NOENDBR // above =20 #ifdef CONFIG_SMP - /* - * Is this the boot CPU coming up? If so everything is available - * in initial_gs. - */ + /* Is this the boot CPU coming up? */ movl smpboot_control(%rip), %edx testl $STARTUP_SECONDARY, %edx jz .Linit_cpu0_data @@ -308,12 +297,7 @@ SYM_INNER_LABEL(secondary_startup_64_no_verify, SYM_L_= GLOBAL) =20 .Linit_cpu_data: /* Get the per cpu offset for the given CPU# which is in ECX */ - leaq __per_cpu_offset(%rip), %rbx - movq (%rbx,%rcx,8), %rbx - /* Save it for GS BASE setup */ - movq %rbx, initial_gs(%rip) - - movq %rbx, %rdx + movq __per_cpu_offset(,%rcx,8), %rdx #else xorl %edx, %edx #endif /* CONFIG_SMP */ @@ -363,8 +347,11 @@ SYM_INNER_LABEL(secondary_startup_64_no_verify, SYM_L_= GLOBAL) * the per cpu areas are set up. */ movl $MSR_GS_BASE,%ecx - movl initial_gs(%rip),%eax - movl initial_gs+4(%rip),%edx +#ifndef CONFIG_SMP + leaq INIT_PER_CPU_VAR(fixed_percpu_data)(%rip), %rdx +#endif + movl %edx, %eax + shrq $32, %rdx wrmsr =20 /* Drop the realmode protection. For the boot CPU the pointer is NULL! */ @@ -514,7 +501,6 @@ SYM_CODE_END(vc_boot_ghcb) __REFDATA .balign 8 SYM_DATA(initial_code, .quad x86_64_start_kernel) -SYM_DATA(initial_gs, .quad INIT_PER_CPU_VAR(fixed_percpu_data)) #ifdef CONFIG_AMD_MEM_ENCRYPT SYM_DATA(initial_vc_handler, .quad handle_vc_boot_ghcb) #endif --=20 2.39.2 From nobody Tue Sep 9 06:22:21 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 75C39C61DA4 for ; Fri, 24 Feb 2023 15:42:56 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230035AbjBXPmy (ORCPT ); Fri, 24 Feb 2023 10:42:54 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:37152 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229615AbjBXPmq (ORCPT ); Fri, 24 Feb 2023 10:42:46 -0500 Received: from mail-qv1-xf30.google.com (mail-qv1-xf30.google.com [IPv6:2607:f8b0:4864:20::f30]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 2FE6A6ADE4 for ; Fri, 24 Feb 2023 07:42:45 -0800 (PST) Received: by mail-qv1-xf30.google.com with SMTP id nf5so13775879qvb.5 for ; Fri, 24 Feb 2023 07:42:45 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=tliLWqZo1ClCFllMBGoxhRkpYCPqcv1PK4tnZkLlMM0=; b=O2Uu3GbTz3FO7MHs1vCp97YWPwcz36gukuqk3vw3IuhBTAYf4vkn+mVDvu2zjRsCpm bEoOBul9nkV1MK3PRvbtKQhUZFkGJGeKTmixHzuujh2E5YmRo50KQgkpu9tqME5e11Q3 Otk0IDQTM1xiknWW9sh+uqbDyqDBCa+0ZNqI5ZfY8NH+OF/+aU+qCuxVcrU/zUYCxxK1 J/sNmbw1aZLj9DC347LlgUdyHatgBvMCRYPFCh8WpXgzZgZP6+kNeorMSpYBCNZeKDM5 fvWEMSTpF22coIW9nCKJ6q9+x67rzknOj1Yb2+CV/flLhXeimewH+oDtb7tyogc9X491 awXw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=tliLWqZo1ClCFllMBGoxhRkpYCPqcv1PK4tnZkLlMM0=; b=2lW7l3ziExeyrM7gAwjtuShGLzJykzpkGJRavtlPn7Y5m7N97bfPzqTd6vdNIVTofC 7YaWAuH3NEON1tVaJlpSMTtH1SmBqQQ91MfFVN3Ck5Cer3ehBkcNsL6v2Yqzh+R3rKnx G5CeB9O0V2igvemrZPpt7B8/CvJdh9h5qEpB3aJ9GYSeztlTRnCzidsEi+Sfa2oE/cZV rwE4J1d5K2KkUSqbeFbNSkr6gDLh/oSMO8f+DwKTKvIKFRSED4B+jxvVjFmbPhrX0vld AfXzxSRPOLx5IXuQMfMAoyibZrU802tXcVP0fJEjKCMCzVlAYIaM+l8ntqfYeEcGb0J8 akhQ== X-Gm-Message-State: AO0yUKUY+DbAvTvAF+/pf8zi7Jg4/xUmNSLtwoKsX06Hoaqvja4bYfcj qpf9VouACLRKTGnTihx9xO89L/e4cQ== X-Google-Smtp-Source: AK7set+H1d3jhAvT2EV/UtMS707IDVtG/4668+VsZMFIcDqSgJ1UMKaLb3d8tQFdweCWvbvV07FkSA== X-Received: by 2002:a05:6214:e44:b0:56f:c948:411b with SMTP id o4-20020a0562140e4400b0056fc948411bmr26341454qvc.29.1677253364009; Fri, 24 Feb 2023 07:42:44 -0800 (PST) Received: from citadel.. (075-129-116-198.res.spectrum.com. [75.129.116.198]) by smtp.gmail.com with ESMTPSA id e26-20020a05620a015a00b0073b399700adsm1276131qkn.3.2023.02.24.07.42.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 24 Feb 2023 07:42:43 -0800 (PST) From: Brian Gerst To: linux-kernel@vger.kernel.org, x86@kernel.org Cc: David Woodhouse , Usama Arif , Thomas Gleixner , Borislav Petkov , "H . Peter Anvin" , Peter Zijlstra , Andy Lutomirski , Ingo Molnar , Brian Gerst , David Woodhouse Subject: [PATCH v2 4/5] x86/smpboot: Simplify boot CPU setup Date: Fri, 24 Feb 2023 10:42:34 -0500 Message-Id: <20230224154235.277350-5-brgerst@gmail.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230224154235.277350-1-brgerst@gmail.com> References: <20230224154235.277350-1-brgerst@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Now that the per-cpu GSBASE, stack, and GDT descriptor can be derived dynamically by CPU number, the boot CPU can use a fixed CPU number and take the same path as secondary CPUs. Signed-off-by: Brian Gerst Reviewed-by: David Woodhouse Signed-off-by: David Woodhouse Tested-by: Usama Arif Signed-off-by: Usama Arif --- arch/x86/kernel/head_64.S | 24 +++++++----------------- 1 file changed, 7 insertions(+), 17 deletions(-) diff --git a/arch/x86/kernel/head_64.S b/arch/x86/kernel/head_64.S index 9ed87ba0609f..8bd29ab523dd 100644 --- a/arch/x86/kernel/head_64.S +++ b/arch/x86/kernel/head_64.S @@ -235,11 +235,6 @@ SYM_INNER_LABEL(secondary_startup_64_no_verify, SYM_L_= GLOBAL) ANNOTATE_NOENDBR // above =20 #ifdef CONFIG_SMP - /* Is this the boot CPU coming up? */ - movl smpboot_control(%rip), %edx - testl $STARTUP_SECONDARY, %edx - jz .Linit_cpu0_data - /* * For parallel boot, the APIC ID is retrieved from CPUID, and then * used to look up the CPU number. For booting a single CPU, the @@ -250,13 +245,13 @@ SYM_INNER_LABEL(secondary_startup_64_no_verify, SYM_L= _GLOBAL) * Bit 29 STARTUP_APICID_CPUID_01 flag (use CPUID 0x01) * Bit 0-24 CPU# if STARTUP_APICID_CPUID_xx flags are not set */ - testl $STARTUP_APICID_CPUID_0B, %edx + movl smpboot_control(%rip), %ecx + testl $STARTUP_APICID_CPUID_0B, %ecx jnz .Luse_cpuid_0b - testl $STARTUP_APICID_CPUID_01, %edx + testl $STARTUP_APICID_CPUID_01, %ecx jnz .Luse_cpuid_01 - andl $0x0FFFFFFF, %edx - movl %edx, %ecx - jmp .Linit_cpu_data + andl $0x0FFFFFFF, %ecx + jmp .Lsetup_cpu =20 .Luse_cpuid_01: mov $0x01, %eax @@ -277,7 +272,7 @@ SYM_INNER_LABEL(secondary_startup_64_no_verify, SYM_L_G= LOBAL) =20 .Lfind_cpunr: cmpl (%rbx,%rcx,4), %edx - jz .Linit_cpu_data + jz .Lsetup_cpu inc %ecx cmpl nr_cpu_ids(%rip), %ecx jb .Lfind_cpunr @@ -291,18 +286,13 @@ SYM_INNER_LABEL(secondary_startup_64_no_verify, SYM_L= _GLOBAL) hlt jmp 1b =20 -.Linit_cpu0_data: - movq __per_cpu_offset(%rip), %rdx - jmp .Lsetup_cpu - -.Linit_cpu_data: +.Lsetup_cpu: /* Get the per cpu offset for the given CPU# which is in ECX */ movq __per_cpu_offset(,%rcx,8), %rdx #else xorl %edx, %edx #endif /* CONFIG_SMP */ =20 -.Lsetup_cpu: /* * Setup a boot time stack - Any secondary CPU will have lost its stack * by now because the cr3-switch above unmaps the real-mode stack --=20 2.39.2 From nobody Tue Sep 9 06:22:21 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8502AC61DA3 for ; Fri, 24 Feb 2023 15:43:04 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230102AbjBXPnC (ORCPT ); Fri, 24 Feb 2023 10:43:02 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:37256 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229653AbjBXPmr (ORCPT ); Fri, 24 Feb 2023 10:42:47 -0500 Received: from mail-qv1-xf30.google.com (mail-qv1-xf30.google.com [IPv6:2607:f8b0:4864:20::f30]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 699B16CF10 for ; Fri, 24 Feb 2023 07:42:46 -0800 (PST) Received: by mail-qv1-xf30.google.com with SMTP id bo10so13032801qvb.12 for ; Fri, 24 Feb 2023 07:42:46 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=WxLgPS/+5KaXp/zoBtDBtP/uxsWooxCOhQ7CVpDn18k=; b=eyz1NKA00Lw2zBJw8qWnAYNwLyG+xI/YX6tKFdo4qjQC7aTvd9ur+YngDoECcktC1O +ThFpMX7Frg4dvJLeYi5HMSUqBnTSFTVRXeY+uJT9lqnHbhITIK9MfIoH8U7iTnBEdyi Dr7wR+yDGaolXkfKsx5o8zKSXEYm/QKUWEZCct+SUm3L03XglZMNi4qlzi1NO2XsYdbx ARf3PaIVAeDozw7kpd2psyoo/XpciY1VueM9I1UX9FVNF7iuGPprDdf+pMhPjOxI7n74 ZJ+pzX+iyqYiUKJwk3l4+fdDvnxiVJKYApdd+Fl0o3E3vjKO6VLrA/We/cZSpcQPNTo2 2vVQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=WxLgPS/+5KaXp/zoBtDBtP/uxsWooxCOhQ7CVpDn18k=; b=QG367u4356pshh6UTyagnfB7/q0wuSmF2FOb/pshnrXg5iWCSkGz4/MMsHVGeJFlKb 1dUbLd8ae6qPFAQjSFrsb9Gycm1oy4xoxKAFKYusdvirdDUX3e5FMjC8efWwkp5x95P8 w8geJbJ8w62PVZszhph/RXG2ZC0JL7rBsnGnk5gReF8O/FBwuo8QS0dkGhlFuq5UuDUm mrcsqYTRPI5G9jen7rN5AUVp3xW42KEapY1TkwcBas74dknseCv/t249Kn9p8vQSQK4c okFQJjPtErD7/BhqZap4y1pFTFD5Xd2Ixd6rNVk62D9Tw/M4KKkhAJkrs09rBtyflsQs Ll2Q== X-Gm-Message-State: AO0yUKX29uGgBe/6TJyjWsdrX4jgR278fkOVGMOALR25nJh3JpauVXP5 t6DK2mI3Wl1dG4fmXt+R45gkRidg3g== X-Google-Smtp-Source: AK7set/8adr9Nmz1qqVvBS9AERl/aAB+DC9nYmbW++QIDj62CrSWY86Vln4pqsTCGj0Mir/6WesSzg== X-Received: by 2002:a05:6214:528b:b0:56e:982c:30 with SMTP id kj11-20020a056214528b00b0056e982c0030mr31996916qvb.16.1677253365172; Fri, 24 Feb 2023 07:42:45 -0800 (PST) Received: from citadel.. (075-129-116-198.res.spectrum.com. [75.129.116.198]) by smtp.gmail.com with ESMTPSA id e26-20020a05620a015a00b0073b399700adsm1276131qkn.3.2023.02.24.07.42.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 24 Feb 2023 07:42:44 -0800 (PST) From: Brian Gerst To: linux-kernel@vger.kernel.org, x86@kernel.org Cc: David Woodhouse , Usama Arif , Thomas Gleixner , Borislav Petkov , "H . Peter Anvin" , Peter Zijlstra , Andy Lutomirski , Ingo Molnar , Brian Gerst Subject: [PATCH v2 5/5] x86/smpboot: Remove STARTUP_SECONDARY Date: Fri, 24 Feb 2023 10:42:35 -0500 Message-Id: <20230224154235.277350-6-brgerst@gmail.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230224154235.277350-1-brgerst@gmail.com> References: <20230224154235.277350-1-brgerst@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" All CPUs now use the same setup path. Remove STARTUP_SECONDARY and renumber the remaining flags. Signed-off-by: Brian Gerst --- arch/x86/include/asm/smp.h | 5 ++--- arch/x86/kernel/head_64.S | 5 ++--- arch/x86/kernel/smpboot.c | 6 +++--- 3 files changed, 7 insertions(+), 9 deletions(-) diff --git a/arch/x86/include/asm/smp.h b/arch/x86/include/asm/smp.h index b4b29e052b6e..97a36d029b0e 100644 --- a/arch/x86/include/asm/smp.h +++ b/arch/x86/include/asm/smp.h @@ -202,8 +202,7 @@ extern unsigned int smpboot_control; #endif /* !__ASSEMBLY__ */ =20 /* Control bits for startup_64 */ -#define STARTUP_SECONDARY 0x80000000 -#define STARTUP_APICID_CPUID_0B 0x40000000 -#define STARTUP_APICID_CPUID_01 0x20000000 +#define STARTUP_APICID_CPUID_0B 0x80000000 +#define STARTUP_APICID_CPUID_01 0x40000000 =20 #endif /* _ASM_X86_SMP_H */ diff --git a/arch/x86/kernel/head_64.S b/arch/x86/kernel/head_64.S index 8bd29ab523dd..f629bf74217b 100644 --- a/arch/x86/kernel/head_64.S +++ b/arch/x86/kernel/head_64.S @@ -240,9 +240,8 @@ SYM_INNER_LABEL(secondary_startup_64_no_verify, SYM_L_G= LOBAL) * used to look up the CPU number. For booting a single CPU, the * CPU number is encoded in smpboot_control. * - * Bit 31 STARTUP_SECONDARY flag (checked above) - * Bit 30 STARTUP_APICID_CPUID_0B flag (use CPUID 0x0b) - * Bit 29 STARTUP_APICID_CPUID_01 flag (use CPUID 0x01) + * Bit 31 STARTUP_APICID_CPUID_0B flag (use CPUID 0x0b) + * Bit 30 STARTUP_APICID_CPUID_01 flag (use CPUID 0x01) * Bit 0-24 CPU# if STARTUP_APICID_CPUID_xx flags are not set */ movl smpboot_control(%rip), %ecx diff --git a/arch/x86/kernel/smpboot.c b/arch/x86/kernel/smpboot.c index e1a2843c2841..c159a5c2df9f 100644 --- a/arch/x86/kernel/smpboot.c +++ b/arch/x86/kernel/smpboot.c @@ -1140,7 +1140,7 @@ static int do_boot_cpu(int apicid, int cpu, struct ta= sk_struct *idle, early_gdt_descr.address =3D (unsigned long)get_cpu_gdt_rw(cpu); initial_stack =3D idle->thread.sp; } else if (!do_parallel_bringup) { - smpboot_control =3D STARTUP_SECONDARY | cpu; + smpboot_control =3D cpu; } =20 /* Enable the espfix hack for this CPU */ @@ -1580,7 +1580,7 @@ void __init native_smp_prepare_cpus(unsigned int max_= cpus) */ if (eax) { pr_debug("Using CPUID 0xb for parallel CPU startup\n"); - smpboot_control =3D STARTUP_SECONDARY | STARTUP_APICID_CPUID_0B; + smpboot_control =3D STARTUP_APICID_CPUID_0B; } else { pr_info("Disabling parallel bringup because CPUID 0xb looks untrustwort= hy\n"); do_parallel_bringup =3D false; @@ -1588,7 +1588,7 @@ void __init native_smp_prepare_cpus(unsigned int max_= cpus) } else if (do_parallel_bringup) { /* Without X2APIC, what's in CPUID 0x01 should suffice. */ pr_debug("Using CPUID 0x1 for parallel CPU startup\n"); - smpboot_control =3D STARTUP_SECONDARY | STARTUP_APICID_CPUID_01; + smpboot_control =3D STARTUP_APICID_CPUID_01; } =20 if (do_parallel_bringup) { --=20 2.39.2