From nobody Tue Sep 9 12:19:18 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 67A3BC64ED8 for ; Fri, 24 Feb 2023 10:11:45 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229763AbjBXKLo (ORCPT ); Fri, 24 Feb 2023 05:11:44 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:59264 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229898AbjBXKL0 (ORCPT ); Fri, 24 Feb 2023 05:11:26 -0500 Received: from loongson.cn (mail.loongson.cn [114.242.206.163]) by lindbergh.monkeyblade.net (Postfix) with ESMTP id 38EE564E3D for ; Fri, 24 Feb 2023 02:10:47 -0800 (PST) Received: from loongson.cn (unknown [111.9.175.10]) by gateway (Coremail) with SMTP id _____8DxUOUmjfhjgqQEAA--.3637S3; Fri, 24 Feb 2023 18:10:46 +0800 (CST) Received: from localhost.localdomain (unknown [111.9.175.10]) by localhost.localdomain (Coremail) with SMTP id AQAAf8AxX+QjjfhjNH86AA--.6368S3; Fri, 24 Feb 2023 18:10:45 +0800 (CST) From: Jinyang He To: Huacai Chen , WANG Xuerui Cc: Xi Ruoyao , Youling Tang , loongarch@lists.linux.dev, linux-kernel@vger.kernel.org Subject: [PATCH 1/6] LoongArch: Rename handle_syscall to handle_sys Date: Fri, 24 Feb 2023 18:10:08 +0800 Message-Id: <20230224101013.26971-2-hejinyang@loongson.cn> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20230224101013.26971-1-hejinyang@loongson.cn> References: <20230224101013.26971-1-hejinyang@loongson.cn> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: AQAAf8AxX+QjjfhjNH86AA--.6368S3 X-CM-SenderInfo: pkhmx0p1dqwqxorr0wxvrqhubq/ X-Coremail-Antispam: 1Uk129KBjvJXoW7WF13Kw43Kw17GF1rCw15urg_yoW8Ar1Dp3 45Ar4kZrWkKFnxZasxC3WUurW8AasrWw129a1UKFWrCFnxXFnY9ry0va93XF1agw4xWFW0 vFn5J392qay5GwUanT9S1TB71UUUUUDqnTZGkaVYY2UrUUUUj1kv1TuYvTs0mT0YCTnIWj qI5I8CrVACY4xI64kE6c02F40Ex7xfYxn0WfASr-VFAUDa7-sFnT9fnUUIcSsGvfJTRUUU b7AYFVCjjxCrM7AC8VAFwI0_Jr0_Gr1l1xkIjI8I6I8E6xAIw20EY4v20xvaj40_Wr0E3s 1l1IIY67AEw4v_Jrv_JF1l8cAvFVAK0II2c7xJM28CjxkF64kEwVA0rcxSw2x7M28EF7xv wVC0I7IYx2IY67AKxVW8JVW5JwA2z4x0Y4vE2Ix0cI8IcVCY1x0267AKxVW8JVWxJwA2z4 x0Y4vEx4A2jsIE14v26r4UJVWxJr1l84ACjcxK6I8E87Iv6xkF7I0E14v26r4UJVWxJr1l e2I262IYc4CY6c8Ij28IcVAaY2xG8wAqjxCEc2xF0cIa020Ex4CE44I27wAqx4xG64xvF2 IEw4CE5I8CrVC2j2WlYx0E2Ix0cI8IcVAFwI0_JF0_Jw1lYx0Ex4A2jsIE14v26r1j6r4U McvjeVCFs4IE7xkEbVWUJVW8JwACjcxG0xvY0x0EwIxGrwCF04k20xvY0x0EwIxGrwCFx2 IqxVCFs4IE7xkEbVWUJVW8JwC20s026c02F40E14v26r1j6r18MI8I3I0E7480Y4vE14v2 6r106r1rMI8E67AF67kF1VAFwI0_JF0_Jw1lIxkGc2Ij64vIr41lIxAIcVC0I7IYx2IY67 AKxVWUJVWUCwCI42IY6xIIjxv20xvEc7CjxVAFwI0_Jr0_Gr1lIxAIcVCF04k26cxKx2IY s7xG6r1j6r1xMIIF0xvEx4A2jsIE14v26r1j6r4UMIIF0xvEx4A2jsIEc7CjxVAFwI0_Jr 0_GrUvcSsGvfC2KfnxnUUI43ZEXa7IU82g43UUUUU== Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" The original handle_sys() is a trampline for handler_syscall. Drop it and rename handle_syscall to handle_sys for invoking it directly. Signed-off-by: Jinyang He --- arch/loongarch/kernel/entry.S | 13 +++++++------ arch/loongarch/kernel/genex.S | 5 ----- 2 files changed, 7 insertions(+), 11 deletions(-) diff --git a/arch/loongarch/kernel/entry.S b/arch/loongarch/kernel/entry.S index d737e3cf42d3..d6e9572eb279 100644 --- a/arch/loongarch/kernel/entry.S +++ b/arch/loongarch/kernel/entry.S @@ -18,9 +18,9 @@ .text .cfi_sections .debug_frame .align 5 -SYM_FUNC_START(handle_syscall) +SYM_FUNC_START(handle_sys) csrrd t0, PERCPU_BASE_KS - la.pcrel t1, kernelsp + la_abs t1, kernelsp add.d t1, t1, t0 move t2, sp ld.d sp, t1, 0 @@ -62,12 +62,13 @@ SYM_FUNC_START(handle_syscall) li.d tp, ~_THREAD_MASK and tp, tp, sp =20 - move a0, sp - bl do_syscall + move a0, sp + la_abs ra, do_syscall + jirl ra, ra, 0 =20 RESTORE_ALL_AND_RET -SYM_FUNC_END(handle_syscall) -_ASM_NOKPROBE(handle_syscall) +SYM_FUNC_END(handle_sys) +_ASM_NOKPROBE(handle_sys) =20 SYM_CODE_START(ret_from_fork) bl schedule_tail # a0 =3D struct task_struct *prev diff --git a/arch/loongarch/kernel/genex.S b/arch/loongarch/kernel/genex.S index 44ff1ff64260..1af169ca3734 100644 --- a/arch/loongarch/kernel/genex.S +++ b/arch/loongarch/kernel/genex.S @@ -91,8 +91,3 @@ SYM_FUNC_END(except_vec_cex) BUILD_HANDLER ri ri none BUILD_HANDLER watch watch none BUILD_HANDLER reserved reserved none /* others */ - -SYM_FUNC_START(handle_sys) - la_abs t0, handle_syscall - jr t0 -SYM_FUNC_END(handle_sys) --=20 2.34.3 From nobody Tue Sep 9 12:19:18 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 76638C64ED8 for ; Fri, 24 Feb 2023 10:11:49 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230037AbjBXKLr (ORCPT ); Fri, 24 Feb 2023 05:11:47 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:52746 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230027AbjBXKL3 (ORCPT ); Fri, 24 Feb 2023 05:11:29 -0500 Received: from loongson.cn (mail.loongson.cn [114.242.206.163]) by lindbergh.monkeyblade.net (Postfix) with ESMTP id 6CF416E94 for ; Fri, 24 Feb 2023 02:10:54 -0800 (PST) Received: from loongson.cn (unknown [111.9.175.10]) by gateway (Coremail) with SMTP id _____8DxJYwtjfhjlKQEAA--.3633S3; Fri, 24 Feb 2023 18:10:53 +0800 (CST) Received: from localhost.localdomain (unknown [111.9.175.10]) by localhost.localdomain (Coremail) with SMTP id AQAAf8AxX+QjjfhjNH86AA--.6368S4; Fri, 24 Feb 2023 18:10:53 +0800 (CST) From: Jinyang He To: Huacai Chen , WANG Xuerui Cc: Xi Ruoyao , Youling Tang , loongarch@lists.linux.dev, linux-kernel@vger.kernel.org Subject: [PATCH 2/6] LoongArch: Move the content defined by SYM_DATA to data or rodata section Date: Fri, 24 Feb 2023 18:10:09 +0800 Message-Id: <20230224101013.26971-3-hejinyang@loongson.cn> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20230224101013.26971-1-hejinyang@loongson.cn> References: <20230224101013.26971-1-hejinyang@loongson.cn> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: AQAAf8AxX+QjjfhjNH86AA--.6368S4 X-CM-SenderInfo: pkhmx0p1dqwqxorr0wxvrqhubq/ X-Coremail-Antispam: 1Uk129KBjvJXoWrtFWxGF45uFy8GFyxXF1xAFb_yoW8Jr4fpr 13ArykWrZ8KFn3Aas8Ja4F9rWDJ34DGw1ag3WqyFyrKanrWrykXrnYvr9FgFyjga1SkrWF qrn5J39rKa1UA3JanT9S1TB71UUUUUDqnTZGkaVYY2UrUUUUj1kv1TuYvTs0mT0YCTnIWj qI5I8CrVACY4xI64kE6c02F40Ex7xfYxn0WfASr-VFAUDa7-sFnT9fnUUIcSsGvfJTRUUU b28YFVCjjxCrM7AC8VAFwI0_Jr0_Gr1l1xkIjI8I6I8E6xAIw20EY4v20xvaj40_Wr0E3s 1l1IIY67AEw4v_Jrv_JF1l8cAvFVAK0II2c7xJM28CjxkF64kEwVA0rcxSw2x7M28EF7xv wVC0I7IYx2IY67AKxVW8JVW5JwA2z4x0Y4vE2Ix0cI8IcVCY1x0267AKxVW8JVWxJwA2z4 x0Y4vEx4A2jsIE14v26r4UJVWxJr1l84ACjcxK6I8E87Iv6xkF7I0E14v26r4UJVWxJr1l e2I262IYc4CY6c8Ij28IcVAaY2xG8wAqjxCEc2xF0cIa020Ex4CE44I27wAqx4xG64xvF2 IEw4CE5I8CrVC2j2WlYx0E2Ix0cI8IcVAFwI0_Jw0_WrylYx0Ex4A2jsIE14v26r4j6F4U McvjeVCFs4IE7xkEbVWUJVW8JwACjcxG0xvY0x0EwIxGrwCF04k20xvY0x0EwIxGrwCFx2 IqxVCFs4IE7xkEbVWUJVW8JwC20s026c02F40E14v26r1j6r18MI8I3I0E7480Y4vE14v2 6r106r1rMI8E67AF67kF1VAFwI0_JF0_Jw1lIxkGc2Ij64vIr41lIxAIcVC0I7IYx2IY67 AKxVW8JVW5JwCI42IY6xIIjxv20xvEc7CjxVAFwI0_Gr0_Cr1lIxAIcVCF04k26cxKx2IY s7xG6r1j6r1xMIIF0xvEx4A2jsIE14v26r4j6F4UMIIF0xvEx4A2jsIEc7CjxVAFwI0_Gr 0_Gr1UYxBIdaVFxhVjvjDU0xZFpf9x07josjUUUUUU= Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Due to the SYM_DATA do not give the section notes, manually set it. Reported-by: Youling Tang Signed-off-by: Jinyang He --- arch/loongarch/kernel/genex.S | 2 ++ arch/loongarch/kernel/head.S | 2 ++ 2 files changed, 4 insertions(+) diff --git a/arch/loongarch/kernel/genex.S b/arch/loongarch/kernel/genex.S index 1af169ca3734..de591a9270bd 100644 --- a/arch/loongarch/kernel/genex.S +++ b/arch/loongarch/kernel/genex.S @@ -77,7 +77,9 @@ SYM_FUNC_END(except_vec_cex) 668: RESTORE_ALL_AND_RET SYM_FUNC_END(handle_\exception) + .pushsection .rodata SYM_DATA(unwind_hint_\exception, .word 668b - 666b) + .popsection .endm =20 BUILD_HANDLER ade ade badv diff --git a/arch/loongarch/kernel/head.S b/arch/loongarch/kernel/head.S index aa64b179744f..7cfa1f850e54 100644 --- a/arch/loongarch/kernel/head.S +++ b/arch/loongarch/kernel/head.S @@ -32,9 +32,11 @@ _head: pe_header: __EFI_PE_HEADER =20 +.pushsection .rodata SYM_DATA(kernel_asize, .long _end - _text); SYM_DATA(kernel_fsize, .long _edata - _text); SYM_DATA(kernel_offset, .long kernel_offset - _text); +.popsection =20 #endif =20 --=20 2.34.3 From nobody Tue Sep 9 12:19:18 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 79CAEC677F1 for ; Fri, 24 Feb 2023 10:11:51 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230059AbjBXKLu (ORCPT ); Fri, 24 Feb 2023 05:11:50 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:52128 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230050AbjBXKLa (ORCPT ); Fri, 24 Feb 2023 05:11:30 -0500 Received: from loongson.cn (mail.loongson.cn [114.242.206.163]) by lindbergh.monkeyblade.net (Postfix) with ESMTP id 64645B767 for ; Fri, 24 Feb 2023 02:10:55 -0800 (PST) Received: from loongson.cn (unknown [111.9.175.10]) by gateway (Coremail) with SMTP id _____8BxttgujfhjnqQEAA--.8663S3; Fri, 24 Feb 2023 18:10:54 +0800 (CST) Received: from localhost.localdomain (unknown [111.9.175.10]) by localhost.localdomain (Coremail) with SMTP id AQAAf8AxX+QjjfhjNH86AA--.6368S5; Fri, 24 Feb 2023 18:10:53 +0800 (CST) From: Jinyang He To: Huacai Chen , WANG Xuerui Cc: Xi Ruoyao , Youling Tang , loongarch@lists.linux.dev, linux-kernel@vger.kernel.org Subject: [PATCH 3/6] LoongArch: Create a exception handlers section Date: Fri, 24 Feb 2023 18:10:10 +0800 Message-Id: <20230224101013.26971-4-hejinyang@loongson.cn> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20230224101013.26971-1-hejinyang@loongson.cn> References: <20230224101013.26971-1-hejinyang@loongson.cn> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: AQAAf8AxX+QjjfhjNH86AA--.6368S5 X-CM-SenderInfo: pkhmx0p1dqwqxorr0wxvrqhubq/ X-Coremail-Antispam: 1Uk129KBjvAXoW3ZF4DZr47uryxWFyxWFyrXrb_yoW8Jr13to W3C3W09F1rKa12vF9xJF4xJa18XF1ktrZ5A397AFyru3yDu34UW34rt3WvvryjvFs3JrW7 Cay3JF1kGws3Zrnrn29KB7ZKAUJUUUU5529EdanIXcx71UUUUU7KY7ZEXasCq-sGcSsGvf J3Ic02F40EFcxC0VAKzVAqx4xG6I80ebIjqfuFe4nvWSU5nxnvy29KBjDU0xBIdaVrnRJU UUk2b4IE77IF4wAFF20E14v26r1j6r4UM7CY07I20VC2zVCF04k26cxKx2IYs7xG6rWj6s 0DM7CIcVAFz4kK6r106r15M28lY4IEw2IIxxk0rwA2F7IY1VAKz4vEj48ve4kI8wA2z4x0 Y4vE2Ix0cI8IcVAFwI0_Xr0_Ar1l84ACjcxK6xIIjxv20xvEc7CjxVAFwI0_Gr0_Cr1l84 ACjcxK6I8E87Iv67AKxVW8Jr0_Cr1UM28EF7xvwVC2z280aVCY1x0267AKxVW8Jr0_Cr1U M2AIxVAIcxkEcVAq07x20xvEncxIr21l57IF6xkI12xvs2x26I8E6xACxx1l5I8CrVACY4 xI64kE6c02F40Ex7xfMcIj6xIIjxv20xvE14v26r1q6rW5McIj6I8E87Iv67AKxVW8JVWx JwAm72CE4IkC6x0Yz7v_Jr0_Gr1lF7xvr2IYc2Ij64vIr41l42xK82IYc2Ij64vIr41l4I 8I3I0E4IkC6x0Yz7v_Jr0_Gr1lx2IqxVAqx4xG67AKxVWUJVWUGwC20s026x8GjcxK67AK xVWUGVWUWwC2zVAF1VAY17CE14v26r126r1DMIIYrxkI7VAKI48JMIIF0xvE2Ix0cI8IcV AFwI0_Gr0_Xr1lIxAIcVC0I7IYx2IY6xkF7I0E14v26r4j6F4UMIIF0xvE42xK8VAvwI8I cIk0rVWUJVWUCwCI42IY6I8E87Iv67AKxVW8JVWxJwCI42IY6I8E87Iv6xkF7I0E14v26r 4j6r4UJbIYCTnIWIevJa73UjIFyTuYvjxUcHUqUUUUU Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Create a section named .ex_handlers to collect exception handlers. Use strict alignment for using it later. As some handlers is shared to other exception, we can not define symbol directly. Correct these symbols by adding suffix or by using number label. Signed-off-by: Jinyang He --- arch/loongarch/include/asm/traps.h | 39 +++++++++++++++++ arch/loongarch/kernel/entry.S | 5 +++ arch/loongarch/kernel/genex.S | 65 ++++++++++++++++++++++------- arch/loongarch/kernel/vmlinux.lds.S | 19 +++++++++ arch/loongarch/mm/tlbex.S | 53 ++++++++++++++++------- 5 files changed, 149 insertions(+), 32 deletions(-) create mode 100644 arch/loongarch/include/asm/traps.h diff --git a/arch/loongarch/include/asm/traps.h b/arch/loongarch/include/as= m/traps.h new file mode 100644 index 000000000000..b348d66c16a1 --- /dev/null +++ b/arch/loongarch/include/asm/traps.h @@ -0,0 +1,39 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2023 Loongson Technology Corporation Limited + */ +#ifndef _ASM_TRAPS_H +#define _ASM_TRAPS_H + +#include // For EXCCODES + +#ifdef __ASSEMBLY__ +/* Used for create exception handlers. */ +#define EXCCODE_UNDEF 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, \ + 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, \ + 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, \ + 59, 60, 61, 62, 63 +#define EXCCODE_NOHND EXCCODE_OOB, EXCCODE_BTE, EXCCODE_PSI, \ + EXCCODE_HYP, EXCCODE_GCM, EXCCODE_SE + +/* As merrentry is set to the same value as eentry, the merr handler can + * be thought as the first exception handler. + */ +#define EXCCODE_MERR EXCCODE_RSV + +#define _SET_EXCEPTION_HANDLER(EXCCODE, ...) \ + .pushsection .exception_handlers.##EXCCODE, "ax"; \ + .align 9; \ + __VA_ARGS__; \ + .popsection; + +#define SET_EXCEPTION_HANDLER(EXCCODE, ...) \ + _SET_EXCEPTION_HANDLER(EXCCODE, __VA_ARGS__) + +#define SET_TLBR_HANDLER(...) \ + .pushsection .tlbrhandler, "ax"; \ + __VA_ARGS__; \ + .popsection; +#endif /* __ASSEMBLY__ */ + +#endif /* _ASM_TRAPS_H */ diff --git a/arch/loongarch/kernel/entry.S b/arch/loongarch/kernel/entry.S index d6e9572eb279..ca4651f91e73 100644 --- a/arch/loongarch/kernel/entry.S +++ b/arch/loongarch/kernel/entry.S @@ -14,9 +14,11 @@ #include #include #include +#include =20 .text .cfi_sections .debug_frame + .macro _handle_sys .align 5 SYM_FUNC_START(handle_sys) csrrd t0, PERCPU_BASE_KS @@ -69,6 +71,9 @@ SYM_FUNC_START(handle_sys) RESTORE_ALL_AND_RET SYM_FUNC_END(handle_sys) _ASM_NOKPROBE(handle_sys) + .endm + +SET_EXCEPTION_HANDLER(EXCCODE_SYS, _handle_sys) =20 SYM_CODE_START(ret_from_fork) bl schedule_tail # a0 =3D struct task_struct *prev diff --git a/arch/loongarch/kernel/genex.S b/arch/loongarch/kernel/genex.S index de591a9270bd..86abafc8b95b 100644 --- a/arch/loongarch/kernel/genex.S +++ b/arch/loongarch/kernel/genex.S @@ -15,6 +15,7 @@ #include #include #include +#include =20 .align 5 SYM_FUNC_START(__arch_cpu_idle) @@ -31,7 +32,8 @@ SYM_FUNC_START(__arch_cpu_idle) 1: jr ra SYM_FUNC_END(__arch_cpu_idle) =20 -SYM_FUNC_START(handle_vint) + .macro _handle_vint idx +SYM_FUNC_START(handle_vint\idx) BACKUP_T0T1 SAVE_ALL la_abs t1, __arch_cpu_idle @@ -46,11 +48,14 @@ SYM_FUNC_START(handle_vint) la_abs t0, do_vint jirl ra, t0, 0 RESTORE_ALL_AND_RET -SYM_FUNC_END(handle_vint) +SYM_FUNC_END(handle_vint\idx) + .endm =20 + .macro _except_vec_cex SYM_FUNC_START(except_vec_cex) b cache_parity_error SYM_FUNC_END(except_vec_cex) + .endm =20 .macro build_prep_badv csrrd t0, LOONGARCH_CSR_BADV @@ -66,7 +71,7 @@ SYM_FUNC_END(except_vec_cex) =20 .macro BUILD_HANDLER exception handler prep .align 5 - SYM_FUNC_START(handle_\exception) +SYM_FUNC_START(handle_\exception) 666: BACKUP_T0T1 SAVE_ALL @@ -76,20 +81,48 @@ SYM_FUNC_END(except_vec_cex) jirl ra, t0, 0 668: RESTORE_ALL_AND_RET - SYM_FUNC_END(handle_\exception) +SYM_FUNC_END(handle_\exception) .pushsection .rodata - SYM_DATA(unwind_hint_\exception, .word 668b - 666b) +SYM_DATA(unwind_hint_\exception, .word 668b - 666b) .popsection .endm =20 - BUILD_HANDLER ade ade badv - BUILD_HANDLER ale ale badv - BUILD_HANDLER bp bp none - BUILD_HANDLER fpe fpe fcsr - BUILD_HANDLER fpu fpu none - BUILD_HANDLER lsx lsx none - BUILD_HANDLER lasx lasx none - BUILD_HANDLER lbt lbt none - BUILD_HANDLER ri ri none - BUILD_HANDLER watch watch none - BUILD_HANDLER reserved reserved none /* others */ +SET_EXCEPTION_HANDLER(EXCCODE_SIP0, _handle_vint) +SET_EXCEPTION_HANDLER(EXCCODE_SIP1, _handle_vint 1) +SET_EXCEPTION_HANDLER(EXCCODE_IP0, _handle_vint 2) +SET_EXCEPTION_HANDLER(EXCCODE_IP1, _handle_vint 3) +SET_EXCEPTION_HANDLER(EXCCODE_IP2, _handle_vint 4) +SET_EXCEPTION_HANDLER(EXCCODE_IP3, _handle_vint 5) +SET_EXCEPTION_HANDLER(EXCCODE_IP4, _handle_vint 6) +SET_EXCEPTION_HANDLER(EXCCODE_IP5, _handle_vint 7) +SET_EXCEPTION_HANDLER(EXCCODE_IP6, _handle_vint 8) +SET_EXCEPTION_HANDLER(EXCCODE_IP7, _handle_vint 9) +SET_EXCEPTION_HANDLER(EXCCODE_PMC, _handle_vint 10) +SET_EXCEPTION_HANDLER(EXCCODE_TIMER, _handle_vint 11) +SET_EXCEPTION_HANDLER(EXCCODE_IPI, _handle_vint 12) +SET_EXCEPTION_HANDLER(EXCCODE_NMI, _handle_vint 13) + +SET_EXCEPTION_HANDLER(EXCCODE_MERR, _except_vec_cex) + +SET_EXCEPTION_HANDLER(EXCCODE_ADE, BUILD_HANDLER ade ade badv) +SET_EXCEPTION_HANDLER(EXCCODE_ALE, BUILD_HANDLER ale ale badv) +SET_EXCEPTION_HANDLER(EXCCODE_BP, BUILD_HANDLER bp bp none) +SET_EXCEPTION_HANDLER(EXCCODE_FPE, BUILD_HANDLER fpe fpe fcsr) +SET_EXCEPTION_HANDLER(EXCCODE_FPDIS, BUILD_HANDLER fpu fpu none) +SET_EXCEPTION_HANDLER(EXCCODE_LSXDIS, BUILD_HANDLER lsx lsx none) +SET_EXCEPTION_HANDLER(EXCCODE_LASXDIS, BUILD_HANDLER lasx lasx none) +SET_EXCEPTION_HANDLER(EXCCODE_BTDIS, BUILD_HANDLER lbt lbt none) +SET_EXCEPTION_HANDLER(EXCCODE_INE, BUILD_HANDLER ri ri none) +SET_EXCEPTION_HANDLER(EXCCODE_IPE, BUILD_HANDLER ri1 ri none) +SET_EXCEPTION_HANDLER(EXCCODE_WATCH, BUILD_HANDLER watch watch none) + +.irp i, EXCCODE_UNDEF +SET_EXCEPTION_HANDLER(\i, BUILD_HANDLER reserved\i reserved none) +.endr + +.irp i, EXCCODE_NOHND +SET_EXCEPTION_HANDLER(\i, BUILD_HANDLER reserved\i reserved none) +.endr + +/* Create handle_reserved for temporary build. */ +BUILD_HANDLER reserved reserved none diff --git a/arch/loongarch/kernel/vmlinux.lds.S b/arch/loongarch/kernel/vm= linux.lds.S index ad2ce1a0908e..e99b50359900 100644 --- a/arch/loongarch/kernel/vmlinux.lds.S +++ b/arch/loongarch/kernel/vmlinux.lds.S @@ -21,6 +21,11 @@ */ PECOFF_FILE_ALIGN =3D 0x200; PECOFF_SEGMENT_ALIGN =3D 0x10000; +EX_HANDLER_ALIGN =3D SZ_512; +EX_HANDLER_SIZE =3D SZ_512; +EX_HANDLER_TOTAL =3D 78; /* 64 Exceptions + 14 Interrupts */ +EXCEPTION_ENTRY_ALIGN =3D SZ_64K; +TLBR_ENTRY_ALIGN =3D SZ_4K; =20 OUTPUT_ARCH(loongarch) ENTRY(kernel_entry) @@ -54,6 +59,17 @@ SECTIONS . =3D ALIGN(PECOFF_SEGMENT_ALIGN); _etext =3D .; =20 + . =3D ALIGN(EXCEPTION_ENTRY_ALIGN); + .ex_handlers : { + __ex_handlers =3D .; + *(SORT_BY_INIT_PRIORITY(.exception_handlers.*)) + . =3D ALIGN(EX_HANDLER_ALIGN); + __ex_handlers_end =3D .; + . =3D ALIGN(TLBR_ENTRY_ALIGN); + __tlbr_entry =3D .; + *(.tlbrhandler) + } + /* * struct alt_inst entries. From the header (alternative.h): * "Alternative instructions for different CPU types or capabilities" @@ -154,3 +170,6 @@ SECTIONS *(.eh_frame) } } + +ASSERT(__ex_handlers_end =3D=3D (__ex_handlers + EX_HANDLER_SIZE * EX_HAND= LER_TOTAL), + "The amount of exception handlers does not match!"); diff --git a/arch/loongarch/mm/tlbex.S b/arch/loongarch/mm/tlbex.S index 244e2f5aeee5..53321d3447a2 100644 --- a/arch/loongarch/mm/tlbex.S +++ b/arch/loongarch/mm/tlbex.S @@ -9,6 +9,7 @@ #include #include #include +#include =20 #define INVTLB_ADDR_GFALSE_AND_ASID 5 =20 @@ -32,7 +33,8 @@ tlb_do_page_fault 0 tlb_do_page_fault 1 =20 -SYM_FUNC_START(handle_tlb_protect) + .macro _handle_tlb_protect idx +SYM_FUNC_START(handle_tlb_protect\idx) BACKUP_T0T1 SAVE_ALL move a0, sp @@ -42,9 +44,11 @@ SYM_FUNC_START(handle_tlb_protect) la_abs t0, do_page_fault jirl ra, t0, 0 RESTORE_ALL_AND_RET -SYM_FUNC_END(handle_tlb_protect) +SYM_FUNC_END(handle_tlb_protect\idx) + .endm =20 -SYM_FUNC_START(handle_tlb_load) + .macro _handle_tlb_load idx +SYM_FUNC_START(handle_tlb_load\idx) csrwr t0, EXCEPTION_KS0 csrwr t1, EXCEPTION_KS1 csrwr ra, EXCEPTION_KS2 @@ -53,10 +57,10 @@ SYM_FUNC_START(handle_tlb_load) * The vmalloc handling is not in the hotpath. */ csrrd t0, LOONGARCH_CSR_BADV - bltz t0, vmalloc_load + bltz t0, 3f csrrd t1, LOONGARCH_CSR_PGDL =20 -vmalloc_done_load: +1: /* vmalloc_done_load: */ /* Get PGD offset in bytes */ bstrpick.d ra, t0, PTRS_PER_PGD_BITS + PGDIR_SHIFT - 1, PGDIR_SHIFT alsl.d t1, ra, t1, 3 @@ -78,25 +82,25 @@ vmalloc_done_load: * see if we need to jump to huge tlb processing. */ rotri.d ra, ra, _PAGE_HUGE_SHIFT + 1 - bltz ra, tlb_huge_update_load + bltz ra, 4f =20 rotri.d ra, ra, 64 - (_PAGE_HUGE_SHIFT + 1) bstrpick.d t0, t0, PTRS_PER_PTE_BITS + PAGE_SHIFT - 1, PAGE_SHIFT alsl.d t1, t0, ra, _PTE_T_LOG2 =20 #ifdef CONFIG_SMP -smp_pgtable_change_load: +2: /* smp_pgtable_change_load: */ ll.d t0, t1, 0 #else ld.d t0, t1, 0 #endif andi ra, t0, _PAGE_PRESENT - beqz ra, nopage_tlb_load + beqz ra, 5f =20 ori t0, t0, _PAGE_VALID #ifdef CONFIG_SMP sc.d t0, t1, 0 - beqz t0, smp_pgtable_change_load + beqz t0, 2b #else st.d t0, t1, 0 #endif @@ -114,23 +118,23 @@ smp_pgtable_change_load: ertn =20 #ifdef CONFIG_64BIT -vmalloc_load: +3: /* vmalloc_load: */ la_abs t1, swapper_pg_dir - b vmalloc_done_load + b 1b #endif =20 /* This is the entry point of a huge page. */ -tlb_huge_update_load: +4: /* tlb_huge_update_load: */ #ifdef CONFIG_SMP ll.d ra, t1, 0 #endif andi t0, ra, _PAGE_PRESENT - beqz t0, nopage_tlb_load + beqz t0, 5f =20 #ifdef CONFIG_SMP ori t0, ra, _PAGE_VALID sc.d t0, t1, 0 - beqz t0, tlb_huge_update_load + beqz t0, 4b ori t0, ra, _PAGE_VALID #else rotri.d ra, ra, 64 - (_PAGE_HUGE_SHIFT + 1) @@ -183,13 +187,15 @@ tlb_huge_update_load: csrrd ra, EXCEPTION_KS2 ertn =20 -nopage_tlb_load: +5: /* nopage_tlb_load: */ dbar 0 csrrd ra, EXCEPTION_KS2 la_abs t0, tlb_do_page_fault_0 jr t0 -SYM_FUNC_END(handle_tlb_load) +SYM_FUNC_END(handle_tlb_load\idx) + .endm =20 + .macro _handle_tlb_store SYM_FUNC_START(handle_tlb_store) csrwr t0, EXCEPTION_KS0 csrwr t1, EXCEPTION_KS1 @@ -338,7 +344,9 @@ nopage_tlb_store: la_abs t0, tlb_do_page_fault_1 jr t0 SYM_FUNC_END(handle_tlb_store) + .endm =20 + .macro _handle_tlb_modify SYM_FUNC_START(handle_tlb_modify) csrwr t0, EXCEPTION_KS0 csrwr t1, EXCEPTION_KS1 @@ -485,7 +493,9 @@ nopage_tlb_modify: la_abs t0, tlb_do_page_fault_1 jr t0 SYM_FUNC_END(handle_tlb_modify) + .endm =20 + .macro _handle_tlb_refill SYM_FUNC_START(handle_tlb_refill) csrwr t0, LOONGARCH_CSR_TLBRSAVE csrrd t0, LOONGARCH_CSR_PGD @@ -502,3 +512,14 @@ SYM_FUNC_START(handle_tlb_refill) csrrd t0, LOONGARCH_CSR_TLBRSAVE ertn SYM_FUNC_END(handle_tlb_refill) + .endm + +SET_EXCEPTION_HANDLER(EXCCODE_TLBI, _handle_tlb_load) +SET_EXCEPTION_HANDLER(EXCCODE_TLBL, _handle_tlb_load 1) +SET_EXCEPTION_HANDLER(EXCCODE_TLBS, _handle_tlb_store) +SET_EXCEPTION_HANDLER(EXCCODE_TLBM, _handle_tlb_modify) +SET_EXCEPTION_HANDLER(EXCCODE_TLBNR, _handle_tlb_protect) +SET_EXCEPTION_HANDLER(EXCCODE_TLBNX, _handle_tlb_protect 1) +SET_EXCEPTION_HANDLER(EXCCODE_TLBPE, _handle_tlb_protect 2) + +SET_TLBR_HANDLER(_handle_tlb_refill) --=20 2.34.3 From nobody Tue Sep 9 12:19:18 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id B2B4AC61DA3 for ; Fri, 24 Feb 2023 10:11:58 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229846AbjBXKL5 (ORCPT ); Fri, 24 Feb 2023 05:11:57 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:52798 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230064AbjBXKLb (ORCPT ); Fri, 24 Feb 2023 05:11:31 -0500 Received: from loongson.cn (mail.loongson.cn [114.242.206.163]) by lindbergh.monkeyblade.net (Postfix) with ESMTP id 8E81B4D604 for ; Fri, 24 Feb 2023 02:10:55 -0800 (PST) Received: from loongson.cn (unknown [111.9.175.10]) by gateway (Coremail) with SMTP id _____8DxE0wujfhjpqQEAA--.3666S3; Fri, 24 Feb 2023 18:10:54 +0800 (CST) Received: from localhost.localdomain (unknown [111.9.175.10]) by localhost.localdomain (Coremail) with SMTP id AQAAf8AxX+QjjfhjNH86AA--.6368S6; Fri, 24 Feb 2023 18:10:54 +0800 (CST) From: Jinyang He To: Huacai Chen , WANG Xuerui Cc: Xi Ruoyao , Youling Tang , loongarch@lists.linux.dev, linux-kernel@vger.kernel.org Subject: [PATCH 4/6] LoongArch: Drop pernode exception handlers Date: Fri, 24 Feb 2023 18:10:11 +0800 Message-Id: <20230224101013.26971-5-hejinyang@loongson.cn> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20230224101013.26971-1-hejinyang@loongson.cn> References: <20230224101013.26971-1-hejinyang@loongson.cn> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: AQAAf8AxX+QjjfhjNH86AA--.6368S6 X-CM-SenderInfo: pkhmx0p1dqwqxorr0wxvrqhubq/ X-Coremail-Antispam: 1Uk129KBjvAXoW3KryfuFyDtr4xWFW5Aw1xGrg_yoW8Jr18to Wava1jyr1rGw47t343t3Zxta48ZF9IyrWkC3sayan3Wr9rAFyUWw4UKFn8t3ySgwn5Jryx Ca43Wrn8Zas7Xr1kn29KB7ZKAUJUUUU5529EdanIXcx71UUUUU7KY7ZEXasCq-sGcSsGvf J3Ic02F40EFcxC0VAKzVAqx4xG6I80ebIjqfuFe4nvWSU5nxnvy29KBjDU0xBIdaVrnRJU UUk2b4IE77IF4wAFF20E14v26r1j6r4UM7CY07I20VC2zVCF04k26cxKx2IYs7xG6rWj6s 0DM7CIcVAFz4kK6r1Y6r17M28lY4IEw2IIxxk0rwA2F7IY1VAKz4vEj48ve4kI8wA2z4x0 Y4vE2Ix0cI8IcVAFwI0_Xr0_Ar1l84ACjcxK6xIIjxv20xvEc7CjxVAFwI0_Gr0_Cr1l84 ACjcxK6I8E87Iv67AKxVW8Jr0_Cr1UM28EF7xvwVC2z280aVCY1x0267AKxVW8Jr0_Cr1U M2AIxVAIcxkEcVAq07x20xvEncxIr21l57IF6xkI12xvs2x26I8E6xACxx1l5I8CrVACY4 xI64kE6c02F40Ex7xfMcIj6xIIjxv20xvE14v26r1q6rW5McIj6I8E87Iv67AKxVW8JVWx JwAm72CE4IkC6x0Yz7v_Jr0_Gr1lF7xvr2IYc2Ij64vIr41l42xK82IYc2Ij64vIr41l4I 8I3I0E4IkC6x0Yz7v_Jr0_Gr1lx2IqxVAqx4xG67AKxVWUJVWUGwC20s026x8GjcxK67AK xVWUGVWUWwC2zVAF1VAY17CE14v26r126r1DMIIYrxkI7VAKI48JMIIF0xvE2Ix0cI8IcV AFwI0_Xr0_Ar1lIxAIcVC0I7IYx2IY6xkF7I0E14v26r4j6F4UMIIF0xvE42xK8VAvwI8I cIk0rVWUJVWUCwCI42IY6I8E87Iv67AKxVW8JVWxJwCI42IY6I8E87Iv6xkF7I0E14v26r 4j6r4UJbIYCTnIWIevJa73UjIFyTuYvjxUcCD7UUUUU Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" 1, set the value of CSR.EENTRY to &__ex_handlers. 2, set the value of CSR.TLBRENTRY to &__tlbr_entry. 3, set the value of CSR.MERRENTRY to &__ex_handlers. Then, we can drop the pernode exception handlers. Signed-off-by: Jinyang He --- arch/loongarch/include/asm/setup.h | 7 --- arch/loongarch/include/asm/traps.h | 29 ++++++++++ arch/loongarch/kernel/genex.S | 8 --- arch/loongarch/kernel/traps.c | 74 +------------------------ arch/loongarch/kernel/unwind_prologue.c | 62 +-------------------- arch/loongarch/mm/cache.c | 6 -- arch/loongarch/mm/tlb.c | 40 ------------- arch/loongarch/power/suspend.c | 5 +- 8 files changed, 33 insertions(+), 198 deletions(-) diff --git a/arch/loongarch/include/asm/setup.h b/arch/loongarch/include/as= m/setup.h index be05c0e706a2..4074225339ec 100644 --- a/arch/loongarch/include/asm/setup.h +++ b/arch/loongarch/include/asm/setup.h @@ -9,17 +9,10 @@ #include #include =20 -#define VECSIZE 0x200 - -extern unsigned long eentry; -extern unsigned long tlbrentry; extern char init_command_line[COMMAND_LINE_SIZE]; extern void tlb_init(int cpu); extern void cpu_cache_init(void); -extern void cache_error_setup(void); extern void per_cpu_trap_init(int cpu); -extern void set_handler(unsigned long offset, void *addr, unsigned long le= n); -extern void set_merr_handler(unsigned long offset, void *addr, unsigned lo= ng len); =20 #ifdef CONFIG_RELOCATABLE =20 diff --git a/arch/loongarch/include/asm/traps.h b/arch/loongarch/include/as= m/traps.h index b348d66c16a1..8f276253f145 100644 --- a/arch/loongarch/include/asm/traps.h +++ b/arch/loongarch/include/asm/traps.h @@ -34,6 +34,35 @@ .pushsection .tlbrhandler, "ax"; \ __VA_ARGS__; \ .popsection; + +#else /* __ASSEMBLY__ */ + +#define VECSIZE 0x200 +extern void *__ex_handlers; +extern void *__tlbr_entry; + +static inline void set_eentry(void *entry) +{ + csr_write64((unsigned long)entry, LOONGARCH_CSR_EENTRY); +} + +static inline void set_tlbrentry(void *entry) +{ + csr_write64((unsigned long)entry, LOONGARCH_CSR_TLBRENTRY); +} + +static inline void set_merrentry(void *entry) +{ + csr_write64((unsigned long)entry, LOONGARCH_CSR_MERRENTRY); +} + +static inline void configure_exception_vector(void) +{ + set_eentry(&__ex_handlers); + set_tlbrentry(&__tlbr_entry); + set_merrentry(&__ex_handlers); +} + #endif /* __ASSEMBLY__ */ =20 #endif /* _ASM_TRAPS_H */ diff --git a/arch/loongarch/kernel/genex.S b/arch/loongarch/kernel/genex.S index 86abafc8b95b..256e2e5b83d4 100644 --- a/arch/loongarch/kernel/genex.S +++ b/arch/loongarch/kernel/genex.S @@ -72,19 +72,14 @@ SYM_FUNC_END(except_vec_cex) .macro BUILD_HANDLER exception handler prep .align 5 SYM_FUNC_START(handle_\exception) - 666: BACKUP_T0T1 SAVE_ALL build_prep_\prep move a0, sp la_abs t0, do_\handler jirl ra, t0, 0 - 668: RESTORE_ALL_AND_RET SYM_FUNC_END(handle_\exception) - .pushsection .rodata -SYM_DATA(unwind_hint_\exception, .word 668b - 666b) - .popsection .endm =20 SET_EXCEPTION_HANDLER(EXCCODE_SIP0, _handle_vint) @@ -123,6 +118,3 @@ SET_EXCEPTION_HANDLER(\i, BUILD_HANDLER reserved\i rese= rved none) .irp i, EXCCODE_NOHND SET_EXCEPTION_HANDLER(\i, BUILD_HANDLER reserved\i reserved none) .endr - -/* Create handle_reserved for temporary build. */ -BUILD_HANDLER reserved reserved none diff --git a/arch/loongarch/kernel/traps.c b/arch/loongarch/kernel/traps.c index c8b3bd76c941..84ac78bc8c57 100644 --- a/arch/loongarch/kernel/traps.c +++ b/arch/loongarch/kernel/traps.c @@ -43,6 +43,7 @@ #include #include #include +#include #include #include =20 @@ -798,25 +799,8 @@ asmlinkage void noinstr do_vint(struct pt_regs *regs, = unsigned long sp) irqentry_exit(regs, state); } =20 -unsigned long eentry; -unsigned long tlbrentry; - -long exception_handlers[VECSIZE * 128 / sizeof(long)] __aligned(SZ_64K); - -static void configure_exception_vector(void) -{ - eentry =3D (unsigned long)exception_handlers; - tlbrentry =3D (unsigned long)exception_handlers + 80*VECSIZE; - - csr_write64(eentry, LOONGARCH_CSR_EENTRY); - csr_write64(eentry, LOONGARCH_CSR_MERRENTRY); - csr_write64(tlbrentry, LOONGARCH_CSR_TLBRENTRY); -} - void per_cpu_trap_init(int cpu) { - unsigned int i; - setup_vint_size(VECSIZE); =20 configure_exception_vector(); @@ -829,62 +813,6 @@ void per_cpu_trap_init(int cpu) BUG_ON(current->mm); enter_lazy_tlb(&init_mm, current); =20 - /* Initialise exception handlers */ - if (cpu =3D=3D 0) - for (i =3D 0; i < 64; i++) - set_handler(i * VECSIZE, handle_reserved, VECSIZE); - tlb_init(cpu); cpu_cache_init(); } - -/* Install CPU exception handler */ -void set_handler(unsigned long offset, void *addr, unsigned long size) -{ - memcpy((void *)(eentry + offset), addr, size); - local_flush_icache_range(eentry + offset, eentry + offset + size); -} - -static const char panic_null_cerr[] =3D - "Trying to set NULL cache error exception handler\n"; - -/* - * Install uncached CPU exception handler. - * This is suitable only for the cache error exception which is the only - * exception handler that is being run uncached. - */ -void set_merr_handler(unsigned long offset, void *addr, unsigned long size) -{ - unsigned long uncached_eentry =3D TO_UNCACHE(__pa(eentry)); - - if (!addr) - panic(panic_null_cerr); - - memcpy((void *)(uncached_eentry + offset), addr, size); -} - -void __init trap_init(void) -{ - long i; - - /* Set interrupt vector handler */ - for (i =3D EXCCODE_INT_START; i < EXCCODE_INT_END; i++) - set_handler(i * VECSIZE, handle_vint, VECSIZE); - - set_handler(EXCCODE_ADE * VECSIZE, handle_ade, VECSIZE); - set_handler(EXCCODE_ALE * VECSIZE, handle_ale, VECSIZE); - set_handler(EXCCODE_SYS * VECSIZE, handle_sys, VECSIZE); - set_handler(EXCCODE_BP * VECSIZE, handle_bp, VECSIZE); - set_handler(EXCCODE_INE * VECSIZE, handle_ri, VECSIZE); - set_handler(EXCCODE_IPE * VECSIZE, handle_ri, VECSIZE); - set_handler(EXCCODE_FPDIS * VECSIZE, handle_fpu, VECSIZE); - set_handler(EXCCODE_LSXDIS * VECSIZE, handle_lsx, VECSIZE); - set_handler(EXCCODE_LASXDIS * VECSIZE, handle_lasx, VECSIZE); - set_handler(EXCCODE_FPE * VECSIZE, handle_fpe, VECSIZE); - set_handler(EXCCODE_BTDIS * VECSIZE, handle_lbt, VECSIZE); - set_handler(EXCCODE_WATCH * VECSIZE, handle_watch, VECSIZE); - - cache_error_setup(); - - local_flush_icache_range(eentry, eentry + 0x400); -} diff --git a/arch/loongarch/kernel/unwind_prologue.c b/arch/loongarch/kerne= l/unwind_prologue.c index 9095fde8e55d..de18335c6ba6 100644 --- a/arch/loongarch/kernel/unwind_prologue.c +++ b/arch/loongarch/kernel/unwind_prologue.c @@ -12,69 +12,9 @@ #include #include =20 -extern const int unwind_hint_ade; -extern const int unwind_hint_ale; -extern const int unwind_hint_bp; -extern const int unwind_hint_fpe; -extern const int unwind_hint_fpu; -extern const int unwind_hint_lsx; -extern const int unwind_hint_lasx; -extern const int unwind_hint_lbt; -extern const int unwind_hint_ri; -extern const int unwind_hint_watch; -extern unsigned long eentry; -#ifdef CONFIG_NUMA -extern unsigned long pcpu_handlers[NR_CPUS]; -#endif - -static inline bool scan_handlers(unsigned long entry_offset) -{ - int idx, offset; - - if (entry_offset >=3D EXCCODE_INT_START * VECSIZE) - return false; - - idx =3D entry_offset / VECSIZE; - offset =3D entry_offset % VECSIZE; - switch (idx) { - case EXCCODE_ADE: - return offset =3D=3D unwind_hint_ade; - case EXCCODE_ALE: - return offset =3D=3D unwind_hint_ale; - case EXCCODE_BP: - return offset =3D=3D unwind_hint_bp; - case EXCCODE_FPE: - return offset =3D=3D unwind_hint_fpe; - case EXCCODE_FPDIS: - return offset =3D=3D unwind_hint_fpu; - case EXCCODE_LSXDIS: - return offset =3D=3D unwind_hint_lsx; - case EXCCODE_LASXDIS: - return offset =3D=3D unwind_hint_lasx; - case EXCCODE_BTDIS: - return offset =3D=3D unwind_hint_lbt; - case EXCCODE_INE: - return offset =3D=3D unwind_hint_ri; - case EXCCODE_WATCH: - return offset =3D=3D unwind_hint_watch; - default: - return false; - } -} - static inline bool fix_exception(unsigned long pc) { -#ifdef CONFIG_NUMA - int cpu; - - for_each_possible_cpu(cpu) { - if (!pcpu_handlers[cpu]) - continue; - if (scan_handlers(pc - pcpu_handlers[cpu])) - return true; - } -#endif - return scan_handlers(pc - eentry); + return false; } =20 /* diff --git a/arch/loongarch/mm/cache.c b/arch/loongarch/mm/cache.c index 72685a48eaf0..d8e53702d61f 100644 --- a/arch/loongarch/mm/cache.c +++ b/arch/loongarch/mm/cache.c @@ -25,12 +25,6 @@ #include #include =20 -void cache_error_setup(void) -{ - extern char __weak except_vec_cex; - set_merr_handler(0x0, &except_vec_cex, 0x80); -} - /* * LoongArch maintains ICache/DCache coherency by hardware, * we just need "ibar" to avoid instruction hazard here. diff --git a/arch/loongarch/mm/tlb.c b/arch/loongarch/mm/tlb.c index 8bad6b0cff59..dda35eae1c49 100644 --- a/arch/loongarch/mm/tlb.c +++ b/arch/loongarch/mm/tlb.c @@ -250,50 +250,10 @@ static void output_pgtable_bits_defines(void) pr_debug("\n"); } =20 -#ifdef CONFIG_NUMA -unsigned long pcpu_handlers[NR_CPUS]; -#endif -extern long exception_handlers[VECSIZE * 128 / sizeof(long)]; - void setup_tlb_handler(int cpu) { setup_ptwalker(); local_flush_tlb_all(); - - /* The tlb handlers are generated only once */ - if (cpu =3D=3D 0) { - memcpy((void *)tlbrentry, handle_tlb_refill, 0x80); - local_flush_icache_range(tlbrentry, tlbrentry + 0x80); - set_handler(EXCCODE_TLBI * VECSIZE, handle_tlb_load, VECSIZE); - set_handler(EXCCODE_TLBL * VECSIZE, handle_tlb_load, VECSIZE); - set_handler(EXCCODE_TLBS * VECSIZE, handle_tlb_store, VECSIZE); - set_handler(EXCCODE_TLBM * VECSIZE, handle_tlb_modify, VECSIZE); - set_handler(EXCCODE_TLBNR * VECSIZE, handle_tlb_protect, VECSIZE); - set_handler(EXCCODE_TLBNX * VECSIZE, handle_tlb_protect, VECSIZE); - set_handler(EXCCODE_TLBPE * VECSIZE, handle_tlb_protect, VECSIZE); - } -#ifdef CONFIG_NUMA - else { - void *addr; - struct page *page; - const int vec_sz =3D sizeof(exception_handlers); - - if (pcpu_handlers[cpu]) - return; - - page =3D alloc_pages_node(cpu_to_node(cpu), GFP_ATOMIC, get_order(vec_sz= )); - if (!page) - return; - - addr =3D page_address(page); - pcpu_handlers[cpu] =3D (unsigned long)addr; - memcpy((void *)addr, (void *)eentry, vec_sz); - local_flush_icache_range((unsigned long)addr, (unsigned long)addr + vec_= sz); - csr_write64(pcpu_handlers[cpu], LOONGARCH_CSR_EENTRY); - csr_write64(pcpu_handlers[cpu], LOONGARCH_CSR_MERRENTRY); - csr_write64(pcpu_handlers[cpu] + 80*VECSIZE, LOONGARCH_CSR_TLBRENTRY); - } -#endif } =20 void tlb_init(int cpu) diff --git a/arch/loongarch/power/suspend.c b/arch/loongarch/power/suspend.c index 5e19733e5e05..b2a10a33b372 100644 --- a/arch/loongarch/power/suspend.c +++ b/arch/loongarch/power/suspend.c @@ -14,6 +14,7 @@ #include #include #include +#include =20 u64 loongarch_suspend_addr; =20 @@ -45,9 +46,7 @@ static void arch_common_resume(void) sync_counter(); local_flush_tlb_all(); csr_write64(per_cpu_offset(0), PERCPU_BASE_KS); - csr_write64(eentry, LOONGARCH_CSR_EENTRY); - csr_write64(eentry, LOONGARCH_CSR_MERRENTRY); - csr_write64(tlbrentry, LOONGARCH_CSR_TLBRENTRY); + configure_exception_vector(); =20 csr_write64(saved_regs.pgd, LOONGARCH_CSR_PGDL); csr_write64(saved_regs.kpgd, LOONGARCH_CSR_PGDH); --=20 2.34.3 From nobody Tue Sep 9 12:19:18 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 58D72C61DA3 for ; Fri, 24 Feb 2023 10:11:55 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229634AbjBXKLx (ORCPT ); Fri, 24 Feb 2023 05:11:53 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:52136 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230055AbjBXKLa (ORCPT ); Fri, 24 Feb 2023 05:11:30 -0500 Received: from loongson.cn (mail.loongson.cn [114.242.206.163]) by lindbergh.monkeyblade.net (Postfix) with ESMTP id 84C6439CED for ; Fri, 24 Feb 2023 02:10:56 -0800 (PST) Received: from loongson.cn (unknown [111.9.175.10]) by gateway (Coremail) with SMTP id _____8Dxj80vjfhjsqQEAA--.3601S3; Fri, 24 Feb 2023 18:10:55 +0800 (CST) Received: from localhost.localdomain (unknown [111.9.175.10]) by localhost.localdomain (Coremail) with SMTP id AQAAf8AxX+QjjfhjNH86AA--.6368S7; Fri, 24 Feb 2023 18:10:55 +0800 (CST) From: Jinyang He To: Huacai Chen , WANG Xuerui Cc: Xi Ruoyao , Youling Tang , loongarch@lists.linux.dev, linux-kernel@vger.kernel.org Subject: [PATCH 5/6] LoongArch: Fix up the prologue unwinder unwind exception frame Date: Fri, 24 Feb 2023 18:10:12 +0800 Message-Id: <20230224101013.26971-6-hejinyang@loongson.cn> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20230224101013.26971-1-hejinyang@loongson.cn> References: <20230224101013.26971-1-hejinyang@loongson.cn> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: AQAAf8AxX+QjjfhjNH86AA--.6368S7 X-CM-SenderInfo: pkhmx0p1dqwqxorr0wxvrqhubq/ X-Coremail-Antispam: 1Uk129KBjvJXoW3GryDAr43AF48uFy5tw45trb_yoW7AF48pF nrAF1kGrWrWasaqryDtryDur98A3s3Gw1aga9rKa4rCF17XF15Wr1vvryDZFyjqaykXrW0 qFyfGFyY9F4Uta7anT9S1TB71UUUUUDqnTZGkaVYY2UrUUUUj1kv1TuYvTs0mT0YCTnIWj qI5I8CrVACY4xI64kE6c02F40Ex7xfYxn0WfASr-VFAUDa7-sFnT9fnUUIcSsGvfJTRUUU b28YFVCjjxCrM7AC8VAFwI0_Jr0_Gr1l1xkIjI8I6I8E6xAIw20EY4v20xvaj40_Wr0E3s 1l1IIY67AEw4v_Jrv_JF1l8cAvFVAK0II2c7xJM28CjxkF64kEwVA0rcxSw2x7M28EF7xv wVC0I7IYx2IY67AKxVW5JVW7JwA2z4x0Y4vE2Ix0cI8IcVCY1x0267AKxVW8JVWxJwA2z4 x0Y4vEx4A2jsIE14v26r4UJVWxJr1l84ACjcxK6I8E87Iv6xkF7I0E14v26r4UJVWxJr1l e2I262IYc4CY6c8Ij28IcVAaY2xG8wAqjxCEc2xF0cIa020Ex4CE44I27wAqx4xG64xvF2 IEw4CE5I8CrVC2j2WlYx0E2Ix0cI8IcVAFwI0_Jw0_WrylYx0Ex4A2jsIE14v26r4j6F4U McvjeVCFs4IE7xkEbVWUJVW8JwACjcxG0xvY0x0EwIxGrwCF04k20xvY0x0EwIxGrwCFx2 IqxVCFs4IE7xkEbVWUJVW8JwC20s026c02F40E14v26r1j6r18MI8I3I0E7480Y4vE14v2 6r106r1rMI8E67AF67kF1VAFwI0_JF0_Jw1lIxkGc2Ij64vIr41lIxAIcVC0I7IYx2IY67 AKxVW5JVW7JwCI42IY6xIIjxv20xvEc7CjxVAFwI0_Gr0_Cr1lIxAIcVCF04k26cxKx2IY s7xG6r1j6r1xMIIF0xvEx4A2jsIE14v26r4j6F4UMIIF0xvEx4A2jsIEc7CjxVAFwI0_Gr 0_Gr1UYxBIdaVFxhVjvjDU0xZFpf9x07josjUUUUUU= Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" It is a simply way to correct the unwind info when the special functions influence the normal prologue analysis. We find out the position where should unwind by PT_REGS, and mark it UNW_NEED_RESET. Linkers will collect them and the prologue unwinder will compare them to pc. Signed-off-by: Jinyang He --- arch/loongarch/include/asm/traps.h | 13 +++++++++ arch/loongarch/include/asm/unwind.h | 2 +- arch/loongarch/kernel/genex.S | 1 + arch/loongarch/kernel/mcount_dyn.S | 2 ++ arch/loongarch/kernel/unwind_prologue.c | 37 +++++++++---------------- arch/loongarch/kernel/vmlinux.lds.S | 9 ++++++ 6 files changed, 39 insertions(+), 25 deletions(-) diff --git a/arch/loongarch/include/asm/traps.h b/arch/loongarch/include/as= m/traps.h index 8f276253f145..0c30a024a9e5 100644 --- a/arch/loongarch/include/asm/traps.h +++ b/arch/loongarch/include/asm/traps.h @@ -5,6 +5,7 @@ #ifndef _ASM_TRAPS_H #define _ASM_TRAPS_H =20 +#include #include // For EXCCODES =20 #ifdef __ASSEMBLY__ @@ -35,11 +36,23 @@ __VA_ARGS__; \ .popsection; =20 +#ifdef CONFIG_UNWINDER_PROLOGUE +#define UNW_NEED_RESET \ + 668: \ + .pushsection .unw_need_reset, "a"; \ + PTR 668b; \ + .popsection; +#else /* CONFIG_UNWINDER_PROLOGUE */ +#define UNW_NEED_RESET +#endif + #else /* __ASSEMBLY__ */ =20 #define VECSIZE 0x200 extern void *__ex_handlers; extern void *__tlbr_entry; +extern void *__unw_need_reset; +extern void *__unw_need_reset_end; =20 static inline void set_eentry(void *entry) { diff --git a/arch/loongarch/include/asm/unwind.h b/arch/loongarch/include/a= sm/unwind.h index b9dce87afd2e..d9a10e264bdd 100644 --- a/arch/loongarch/include/asm/unwind.h +++ b/arch/loongarch/include/asm/unwind.h @@ -22,7 +22,7 @@ struct unwind_state { char type; /* UNWINDER_XXX */ struct stack_info stack_info; struct task_struct *task; - bool first, error, reset; + bool first, error, need_reset; int graph_idx; unsigned long sp, pc, ra; }; diff --git a/arch/loongarch/kernel/genex.S b/arch/loongarch/kernel/genex.S index 256e2e5b83d4..8705a7661ce9 100644 --- a/arch/loongarch/kernel/genex.S +++ b/arch/loongarch/kernel/genex.S @@ -78,6 +78,7 @@ SYM_FUNC_START(handle_\exception) move a0, sp la_abs t0, do_\handler jirl ra, t0, 0 + UNW_NEED_RESET RESTORE_ALL_AND_RET SYM_FUNC_END(handle_\exception) .endm diff --git a/arch/loongarch/kernel/mcount_dyn.S b/arch/loongarch/kernel/mco= unt_dyn.S index bbabf06244c2..3550bab52ff0 100644 --- a/arch/loongarch/kernel/mcount_dyn.S +++ b/arch/loongarch/kernel/mcount_dyn.S @@ -7,6 +7,7 @@ #include #include #include +#include =20 .text /* @@ -81,6 +82,7 @@ SYM_CODE_START(ftrace_common) =20 SYM_INNER_LABEL(ftrace_call, SYM_L_GLOBAL) bl ftrace_stub + UNW_NEED_RESET #ifdef CONFIG_FUNCTION_GRAPH_TRACER SYM_INNER_LABEL(ftrace_graph_call, SYM_L_GLOBAL) nop /* b ftrace_graph_caller */ diff --git a/arch/loongarch/kernel/unwind_prologue.c b/arch/loongarch/kerne= l/unwind_prologue.c index de18335c6ba6..aa01c881481c 100644 --- a/arch/loongarch/kernel/unwind_prologue.c +++ b/arch/loongarch/kernel/unwind_prologue.c @@ -10,33 +10,22 @@ #include #include #include +#include #include =20 -static inline bool fix_exception(unsigned long pc) -{ - return false; -} - -/* - * As we meet ftrace_regs_entry, reset first flag like first doing - * tracing. Prologue analysis will stop soon because PC is at entry. - */ -static inline bool fix_ftrace(unsigned long pc) -{ -#ifdef CONFIG_DYNAMIC_FTRACE - return pc =3D=3D (unsigned long)ftrace_call + LOONGARCH_INSN_SIZE; -#else - return false; -#endif -} - static inline bool unwind_state_fixup(struct unwind_state *state) { - if (!fix_exception(state->pc) && !fix_ftrace(state->pc)) - return false; + unsigned long *p =3D (unsigned long *)&__unw_need_reset; + unsigned long *q =3D (unsigned long *)&__unw_need_reset_end; =20 - state->reset =3D true; - return true; + for (; p < q; p++) { + if (*p !=3D state->pc) + continue; + state->need_reset =3D true; + return true; + } + + return false; } =20 /* @@ -59,10 +48,10 @@ static bool unwind_by_prologue(struct unwind_state *sta= te) if (state->sp >=3D info->end || state->sp < info->begin) return false; =20 - if (state->reset) { + if (state->need_reset) { regs =3D (struct pt_regs *)state->sp; state->first =3D true; - state->reset =3D false; + state->need_reset =3D false; state->pc =3D regs->csr_era; state->ra =3D regs->regs[1]; state->sp =3D regs->regs[3]; diff --git a/arch/loongarch/kernel/vmlinux.lds.S b/arch/loongarch/kernel/vm= linux.lds.S index e99b50359900..00f1f9061961 100644 --- a/arch/loongarch/kernel/vmlinux.lds.S +++ b/arch/loongarch/kernel/vmlinux.lds.S @@ -70,6 +70,15 @@ SECTIONS *(.tlbrhandler) } =20 +#ifdef CONFIG_UNWINDER_PROLOGUE + . =3D ALIGN(8); + .unw_need_reset : { + __unw_need_reset =3D .; + *(.unw_need_reset) + __unw_need_reset_end =3D .; + } +#endif + /* * struct alt_inst entries. From the header (alternative.h): * "Alternative instructions for different CPU types or capabilities" --=20 2.34.3 From nobody Tue Sep 9 12:19:18 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id CDFADC64ED8 for ; Fri, 24 Feb 2023 10:12:00 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230214AbjBXKL7 (ORCPT ); Fri, 24 Feb 2023 05:11:59 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:52170 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230070AbjBXKLb (ORCPT ); Fri, 24 Feb 2023 05:11:31 -0500 Received: from loongson.cn (mail.loongson.cn [114.242.206.163]) by lindbergh.monkeyblade.net (Postfix) with ESMTP id 5AB1316897 for ; Fri, 24 Feb 2023 02:10:57 -0800 (PST) Received: from loongson.cn (unknown [111.9.175.10]) by gateway (Coremail) with SMTP id _____8AxYeUwjfhjuaQEAA--.3679S3; Fri, 24 Feb 2023 18:10:56 +0800 (CST) Received: from localhost.localdomain (unknown [111.9.175.10]) by localhost.localdomain (Coremail) with SMTP id AQAAf8AxX+QjjfhjNH86AA--.6368S8; Fri, 24 Feb 2023 18:10:55 +0800 (CST) From: Jinyang He To: Huacai Chen , WANG Xuerui Cc: Xi Ruoyao , Youling Tang , loongarch@lists.linux.dev, linux-kernel@vger.kernel.org Subject: [PATCH 6/6] LoongArch: Clean up la_abs macro Date: Fri, 24 Feb 2023 18:10:13 +0800 Message-Id: <20230224101013.26971-7-hejinyang@loongson.cn> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20230224101013.26971-1-hejinyang@loongson.cn> References: <20230224101013.26971-1-hejinyang@loongson.cn> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: AQAAf8AxX+QjjfhjNH86AA--.6368S8 X-CM-SenderInfo: pkhmx0p1dqwqxorr0wxvrqhubq/ X-Coremail-Antispam: 1Uk129KBjvJXoWxKryDGFWUXr1xtw13tF4rGrg_yoW3JrWDpF nxZrn7JayrWrn3Za4Dta4DurZ8JwsFg342ganIkFy8u3W7ZF18ZrykA3s7ZFykKay8Xw4I gFyrJws2qF4UJwUanT9S1TB71UUUUUDqnTZGkaVYY2UrUUUUj1kv1TuYvTs0mT0YCTnIWj qI5I8CrVACY4xI64kE6c02F40Ex7xfYxn0WfASr-VFAUDa7-sFnT9fnUUIcSsGvfJTRUUU b28YFVCjjxCrM7AC8VAFwI0_Jr0_Gr1l1xkIjI8I6I8E6xAIw20EY4v20xvaj40_Wr0E3s 1l1IIY67AEw4v_Jrv_JF1l8cAvFVAK0II2c7xJM28CjxkF64kEwVA0rcxSw2x7M28EF7xv wVC0I7IYx2IY67AKxVW5JVW7JwA2z4x0Y4vE2Ix0cI8IcVCY1x0267AKxVW8JVWxJwA2z4 x0Y4vEx4A2jsIE14v26r4UJVWxJr1l84ACjcxK6I8E87Iv6xkF7I0E14v26r4UJVWxJr1l e2I262IYc4CY6c8Ij28IcVAaY2xG8wAqjxCEc2xF0cIa020Ex4CE44I27wAqx4xG64xvF2 IEw4CE5I8CrVC2j2WlYx0E2Ix0cI8IcVAFwI0_Jw0_WrylYx0Ex4A2jsIE14v26r4j6F4U McvjeVCFs4IE7xkEbVWUJVW8JwACjcxG0xvY0x0EwIxGrwCF04k20xvY0x0EwIxGrwCFx2 IqxVCFs4IE7xkEbVWUJVW8JwC20s026c02F40E14v26r1j6r18MI8I3I0E7480Y4vE14v2 6r106r1rMI8E67AF67kF1VAFwI0_JF0_Jw1lIxkGc2Ij64vIr41lIxAIcVC0I7IYx2IY67 AKxVW5JVW7JwCI42IY6xIIjxv20xvEc7CjxVAFwI0_Gr0_Cr1lIxAIcVCF04k26cxKx2IY s7xG6r1j6r1xMIIF0xvEx4A2jsIE14v26r4j6F4UMIIF0xvEx4A2jsIEc7CjxVAFwI0_Gr 0_Gr1UYxBIdaVFxhVjvjDU0xZFpf9x07josjUUUUUU= Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Now we can replace la_abs with la.pcrel. Clean up the la_abs macro. Signed-off-by: Jinyang He --- arch/loongarch/include/asm/asmmacro.h | 17 --------------- arch/loongarch/include/asm/setup.h | 7 ------- arch/loongarch/include/asm/stackframe.h | 2 +- arch/loongarch/kernel/entry.S | 4 ++-- arch/loongarch/kernel/genex.S | 6 +++--- arch/loongarch/kernel/relocate.c | 28 ------------------------- arch/loongarch/kernel/vmlinux.lds.S | 9 -------- arch/loongarch/mm/tlbex.S | 14 ++++++------- 8 files changed, 13 insertions(+), 74 deletions(-) diff --git a/arch/loongarch/include/asm/asmmacro.h b/arch/loongarch/include= /asm/asmmacro.h index 79e1d53fea89..328bb956f241 100644 --- a/arch/loongarch/include/asm/asmmacro.h +++ b/arch/loongarch/include/asm/asmmacro.h @@ -667,21 +667,4 @@ nor \dst, \src, zero .endm =20 -.macro la_abs reg, sym -#ifndef CONFIG_RELOCATABLE - la.abs \reg, \sym -#else - 766: - lu12i.w \reg, 0 - ori \reg, \reg, 0 - lu32i.d \reg, 0 - lu52i.d \reg, \reg, 0 - .pushsection ".la_abs", "aw", %progbits - 768: - .dword 768b-766b - .dword \sym - .popsection -#endif -.endm - #endif /* _ASM_ASMMACRO_H */ diff --git a/arch/loongarch/include/asm/setup.h b/arch/loongarch/include/as= m/setup.h index 4074225339ec..84d131f29e0c 100644 --- a/arch/loongarch/include/asm/setup.h +++ b/arch/loongarch/include/asm/setup.h @@ -16,13 +16,6 @@ extern void per_cpu_trap_init(int cpu); =20 #ifdef CONFIG_RELOCATABLE =20 -struct rela_la_abs { - long offset; - long symvalue; -}; - -extern long __la_abs_begin; -extern long __la_abs_end; extern long __rela_dyn_begin; extern long __rela_dyn_end; =20 diff --git a/arch/loongarch/include/asm/stackframe.h b/arch/loongarch/inclu= de/asm/stackframe.h index bb5e0e2bd3a9..fff4a0ce7750 100644 --- a/arch/loongarch/include/asm/stackframe.h +++ b/arch/loongarch/include/asm/stackframe.h @@ -86,7 +86,7 @@ * new value in sp. */ .macro get_saved_sp docfi=3D0 - la_abs t1, kernelsp + la.pcrel t1, kernelsp #ifdef CONFIG_SMP csrrd t0, PERCPU_BASE_KS LONG_ADD t1, t1, t0 diff --git a/arch/loongarch/kernel/entry.S b/arch/loongarch/kernel/entry.S index ca4651f91e73..4de6b31dc3bf 100644 --- a/arch/loongarch/kernel/entry.S +++ b/arch/loongarch/kernel/entry.S @@ -22,7 +22,7 @@ .align 5 SYM_FUNC_START(handle_sys) csrrd t0, PERCPU_BASE_KS - la_abs t1, kernelsp + la.pcrel t1, kernelsp add.d t1, t1, t0 move t2, sp ld.d sp, t1, 0 @@ -65,7 +65,7 @@ SYM_FUNC_START(handle_sys) and tp, tp, sp =20 move a0, sp - la_abs ra, do_syscall + la.pcrel ra, do_syscall jirl ra, ra, 0 =20 RESTORE_ALL_AND_RET diff --git a/arch/loongarch/kernel/genex.S b/arch/loongarch/kernel/genex.S index 8705a7661ce9..b6a74246d1c4 100644 --- a/arch/loongarch/kernel/genex.S +++ b/arch/loongarch/kernel/genex.S @@ -36,7 +36,7 @@ SYM_FUNC_END(__arch_cpu_idle) SYM_FUNC_START(handle_vint\idx) BACKUP_T0T1 SAVE_ALL - la_abs t1, __arch_cpu_idle + la.pcrel t1, __arch_cpu_idle LONG_L t0, sp, PT_ERA /* 32 byte rollback region */ ori t0, t0, 0x1f @@ -45,7 +45,7 @@ SYM_FUNC_START(handle_vint\idx) LONG_S t0, sp, PT_ERA 1: move a0, sp move a1, sp - la_abs t0, do_vint + la.pcrel t0, do_vint jirl ra, t0, 0 RESTORE_ALL_AND_RET SYM_FUNC_END(handle_vint\idx) @@ -76,7 +76,7 @@ SYM_FUNC_START(handle_\exception) SAVE_ALL build_prep_\prep move a0, sp - la_abs t0, do_\handler + la.pcrel t0, do_\handler jirl ra, t0, 0 UNW_NEED_RESET RESTORE_ALL_AND_RET diff --git a/arch/loongarch/kernel/relocate.c b/arch/loongarch/kernel/reloc= ate.c index 070b9fb87ebc..5ecfd7791268 100644 --- a/arch/loongarch/kernel/relocate.c +++ b/arch/loongarch/kernel/relocate.c @@ -12,7 +12,6 @@ #include #include #include -#include #include #include =20 @@ -41,31 +40,6 @@ static inline __init void relocate_relative(void) } } =20 -static inline void __init relocate_la_abs(long random_offset) -{ - void *begin, *end; - struct rela_la_abs *p; - - begin =3D RELOCATED_KASLR(&__la_abs_begin); - end =3D RELOCATED_KASLR(&__la_abs_end); - - for (p =3D begin; (void *)p < end; p++) { - long v =3D p->symvalue; - uint32_t lu12iw, ori, lu32id, lu52id; - union loongarch_instruction *insn =3D (void *)p - p->offset; - - lu12iw =3D (v >> 12) & 0xfffff; - ori =3D v & 0xfff; - lu32id =3D (v >> 32) & 0xfffff; - lu52id =3D v >> 52; - - insn[0].reg1i20_format.immediate =3D lu12iw; - insn[1].reg2i12_format.immediate =3D ori; - insn[2].reg1i20_format.immediate =3D lu32id; - insn[3].reg2i12_format.immediate =3D lu52id; - } -} - #ifdef CONFIG_RANDOMIZE_BASE static inline __init unsigned long rotate_xor(unsigned long hash, const void *area, size_t size) @@ -202,8 +176,6 @@ void * __init relocate_kernel(void) if (reloc_offset) relocate_relative(); =20 - relocate_la_abs(random_offset); - return kernel_entry; } =20 diff --git a/arch/loongarch/kernel/vmlinux.lds.S b/arch/loongarch/kernel/vm= linux.lds.S index 00f1f9061961..8ae5f245eb2f 100644 --- a/arch/loongarch/kernel/vmlinux.lds.S +++ b/arch/loongarch/kernel/vmlinux.lds.S @@ -91,15 +91,6 @@ SECTIONS __alt_instructions_end =3D .; } =20 -#ifdef CONFIG_RELOCATABLE - . =3D ALIGN(8); - .la_abs : AT(ADDR(.la_abs) - LOAD_OFFSET) { - __la_abs_begin =3D .; - *(.la_abs) - __la_abs_end =3D .; - } -#endif - .got : ALIGN(16) { *(.got) } .plt : ALIGN(16) { *(.plt) } .got.plt : ALIGN(16) { *(.got.plt) } diff --git a/arch/loongarch/mm/tlbex.S b/arch/loongarch/mm/tlbex.S index 53321d3447a2..196d9bc870c5 100644 --- a/arch/loongarch/mm/tlbex.S +++ b/arch/loongarch/mm/tlbex.S @@ -41,7 +41,7 @@ SYM_FUNC_START(handle_tlb_protect\idx) move a1, zero csrrd a2, LOONGARCH_CSR_BADV REG_S a2, sp, PT_BVADDR - la_abs t0, do_page_fault + la.pcrel t0, do_page_fault jirl ra, t0, 0 RESTORE_ALL_AND_RET SYM_FUNC_END(handle_tlb_protect\idx) @@ -119,7 +119,7 @@ SYM_FUNC_START(handle_tlb_load\idx) =20 #ifdef CONFIG_64BIT 3: /* vmalloc_load: */ - la_abs t1, swapper_pg_dir + la.pcrel t1, swapper_pg_dir b 1b #endif =20 @@ -190,7 +190,7 @@ SYM_FUNC_START(handle_tlb_load\idx) 5: /* nopage_tlb_load: */ dbar 0 csrrd ra, EXCEPTION_KS2 - la_abs t0, tlb_do_page_fault_0 + la.pcrel t0, tlb_do_page_fault_0 jr t0 SYM_FUNC_END(handle_tlb_load\idx) .endm @@ -268,7 +268,7 @@ smp_pgtable_change_store: =20 #ifdef CONFIG_64BIT vmalloc_store: - la_abs t1, swapper_pg_dir + la.pcrel t1, swapper_pg_dir b vmalloc_done_store #endif =20 @@ -341,7 +341,7 @@ tlb_huge_update_store: nopage_tlb_store: dbar 0 csrrd ra, EXCEPTION_KS2 - la_abs t0, tlb_do_page_fault_1 + la.pcrel t0, tlb_do_page_fault_1 jr t0 SYM_FUNC_END(handle_tlb_store) .endm @@ -418,7 +418,7 @@ smp_pgtable_change_modify: =20 #ifdef CONFIG_64BIT vmalloc_modify: - la_abs t1, swapper_pg_dir + la.pcrel t1, swapper_pg_dir b vmalloc_done_modify #endif =20 @@ -490,7 +490,7 @@ tlb_huge_update_modify: nopage_tlb_modify: dbar 0 csrrd ra, EXCEPTION_KS2 - la_abs t0, tlb_do_page_fault_1 + la.pcrel t0, tlb_do_page_fault_1 jr t0 SYM_FUNC_END(handle_tlb_modify) .endm --=20 2.34.3