From nobody Thu Sep 11 00:21:41 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id A5960C61DA4 for ; Thu, 23 Feb 2023 05:53:40 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233290AbjBWFxj (ORCPT ); Thu, 23 Feb 2023 00:53:39 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:35606 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233287AbjBWFxf (ORCPT ); Thu, 23 Feb 2023 00:53:35 -0500 Received: from mail-yw1-x1149.google.com (mail-yw1-x1149.google.com [IPv6:2607:f8b0:4864:20::1149]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 862AE4A1E1 for ; Wed, 22 Feb 2023 21:53:32 -0800 (PST) Received: by mail-yw1-x1149.google.com with SMTP id 00721157ae682-536be78056eso107924827b3.1 for ; Wed, 22 Feb 2023 21:53:32 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20210112; h=to:from:subject:references:mime-version:message-id:in-reply-to:date :from:to:cc:subject:date:message-id:reply-to; bh=gHV2MWu6hcWn6rb2AA6nCC6xX1C2U+LxMx/784jLbgQ=; b=b+sJ4qcNYrXX3lgmlyz7ajioBwI7xUmqQ0p39YD+7sXChu2TyyNWFjBmX4K9fzz7oj PNjOx5RHw9LxYTy1kdkoxXh9G1GdybQd0eN0rT7Ip9f+fAYxuS6WrCk8KBq39VaUX5FP BTGHXBu1ycoSpDu+VfFY1ufcZBhnqTzbIZPfmnCvxNZfCYPyZcyYdBtj00+O84X+0J6I HMpNSyUTXrNp55LHRlJxd6UADKhnw3Gu+PP6cvKwdsHLiYLzpAouhUN+r1zheRBtX0c8 7jkBk2cMopk4Wz030UDTRY8G788A3VR6AXZXyQOTfPF00rD8TgOwS6kWADDSfiLPDz0P XuSA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=to:from:subject:references:mime-version:message-id:in-reply-to:date :x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=gHV2MWu6hcWn6rb2AA6nCC6xX1C2U+LxMx/784jLbgQ=; b=n3mqM0+LM0QEtbWHCOXx7DIbRuNwHKXZeNkYnjK+cLRo+1hzJs84iPea4yY0q+nHKP SPA8YBiTb/CDqn51t1NIU4LIA5Ta+KMTUmaotTjwf/eZR5epYqOu69XX/VQEiJJ4/Bny l/tmHaSHQXjZxypHfPFZC06fzbwfyuYkROiu92BItGVjK1pL8welCL1uUYNXNC6zBYoL 2LOHycTPS5GQYEIej1x5uzP7DQi8xBV56xX3XJNtqQJNYBsYva6CK2muq2qRV1tXYOTp TUWSGFiFPQTQxA+sXyLPN7sHlQ/1Z6lUPTxdAQB3vT0kLK2vhUzW6GvQPHzqSQNfKrQt Rung== X-Gm-Message-State: AO0yUKWHsrfGP3Hq/zT/kwwrHjvhgJNFzYu9wDu11axUIUcWm1JCSarP cns416jT1hW22dCc/zn/wy12+oIjny8L X-Google-Smtp-Source: AK7set8sCVMO2ZfpFgOc4CNK1UZmo85h06F0hzI1Lmu31q+Jq7r6ZZvo4+WZAgMEX8QjLocqm6C7ISGbSfC0 X-Received: from irogers.svl.corp.google.com ([2620:15c:2d4:203:9002:67cd:9e6b:7083]) (user=irogers job=sendgmr) by 2002:a81:ae57:0:b0:52e:b235:cd22 with SMTP id g23-20020a81ae57000000b0052eb235cd22mr1696413ywk.8.1677131611611; Wed, 22 Feb 2023 21:53:31 -0800 (PST) Date: Wed, 22 Feb 2023 21:53:04 -0800 In-Reply-To: <20230223055306.296179-1-irogers@google.com> Message-Id: <20230223055306.296179-2-irogers@google.com> Mime-Version: 1.0 References: <20230223055306.296179-1-irogers@google.com> X-Mailer: git-send-email 2.39.2.637.g21b0678d19-goog Subject: [PATCH v1 1/3] perf vendor events intel: Update alderlake to v1.19 From: Ian Rogers To: Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Mark Rutland , Alexander Shishkin , Jiri Olsa , Namhyung Kim , Ian Rogers , Zhengjun Xing , Kan Liang , linux-perf-users@vger.kernel.org, linux-kernel@vger.kernel.org, Edward Baker Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Update alderlake perf json from v1.18 to v1.19. Based on: https://github.com/intel/perfmon/pull/58 perf json files created using: https://github.com/intel/perfmon/blob/main/scripts/create_perf_json.py Signed-off-by: Ian Rogers --- tools/perf/pmu-events/arch/x86/alderlake/memory.json | 8 ++++++++ tools/perf/pmu-events/arch/x86/alderlake/pipeline.json | 10 ++++++++++ tools/perf/pmu-events/arch/x86/mapfile.csv | 2 +- 3 files changed, 19 insertions(+), 1 deletion(-) diff --git a/tools/perf/pmu-events/arch/x86/alderlake/memory.json b/tools/p= erf/pmu-events/arch/x86/alderlake/memory.json index 37f3d062a788..55827b276e6e 100644 --- a/tools/perf/pmu-events/arch/x86/alderlake/memory.json +++ b/tools/perf/pmu-events/arch/x86/alderlake/memory.json @@ -24,6 +24,14 @@ "UMask": "0xf4", "Unit": "cpu_atom" }, + { + "BriefDescription": "Counts the number of cycles that the head (ol= dest load) of the load buffer and retirement are both stalled due to a DL1 = miss.", + "EventCode": "0x05", + "EventName": "LD_HEAD.L1_MISS_AT_RET", + "SampleAfterValue": "1000003", + "UMask": "0x81", + "Unit": "cpu_atom" + }, { "BriefDescription": "Counts the number of cycles that the head (ol= dest load) of the load buffer and retirement are both stalled due to other = block cases.", "EventCode": "0x05", diff --git a/tools/perf/pmu-events/arch/x86/alderlake/pipeline.json b/tools= /perf/pmu-events/arch/x86/alderlake/pipeline.json index 2dba3a115f97..f848530fbf07 100644 --- a/tools/perf/pmu-events/arch/x86/alderlake/pipeline.json +++ b/tools/perf/pmu-events/arch/x86/alderlake/pipeline.json @@ -361,6 +361,16 @@ "UMask": "0xeb", "Unit": "cpu_atom" }, + { + "BriefDescription": "Miss-predicted near indirect branch instructi= ons retired (excluding returns)", + "EventCode": "0xc5", + "EventName": "BR_MISP_RETIRED.INDIRECT", + "PEBS": "1", + "PublicDescription": "Counts miss-predicted near indirect branch i= nstructions retired excluding returns. TSX abort is an indirect branch.", + "SampleAfterValue": "100003", + "UMask": "0x80", + "Unit": "cpu_core" + }, { "BriefDescription": "Counts the number of mispredicted near indire= ct CALL branch instructions retired.", "EventCode": "0xc5", diff --git a/tools/perf/pmu-events/arch/x86/mapfile.csv b/tools/perf/pmu-ev= ents/arch/x86/mapfile.csv index 1c6eef118e61..e69b29123327 100644 --- a/tools/perf/pmu-events/arch/x86/mapfile.csv +++ b/tools/perf/pmu-events/arch/x86/mapfile.csv @@ -1,5 +1,5 @@ Family-model,Version,Filename,EventType -GenuineIntel-6-(97|9A|B7|BA|BF),v1.18,alderlake,core +GenuineIntel-6-(97|9A|B7|BA|BF),v1.19,alderlake,core GenuineIntel-6-BE,v1.18,alderlaken,core GenuineIntel-6-(1C|26|27|35|36),v4,bonnell,core GenuineIntel-6-(3D|47),v26,broadwell,core --=20 2.39.2.637.g21b0678d19-goog From nobody Thu Sep 11 00:21:41 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 52AD2C61DA4 for ; Thu, 23 Feb 2023 05:54:01 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233216AbjBWFx7 (ORCPT ); Thu, 23 Feb 2023 00:53:59 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:36084 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233306AbjBWFxv (ORCPT ); Thu, 23 Feb 2023 00:53:51 -0500 Received: from mail-yw1-x1149.google.com (mail-yw1-x1149.google.com [IPv6:2607:f8b0:4864:20::1149]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id A26434A1F5 for ; Wed, 22 Feb 2023 21:53:40 -0800 (PST) Received: by mail-yw1-x1149.google.com with SMTP id 00721157ae682-536bf635080so110016107b3.23 for ; Wed, 22 Feb 2023 21:53:40 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20210112; h=to:from:subject:references:mime-version:message-id:in-reply-to:date :from:to:cc:subject:date:message-id:reply-to; bh=tqdZ+G+VG1pXrXKKnIZ+HhiVU4LU/SJNnBh8ENQqCxc=; b=FkVPW5Pne6GEsLhxFV5uq6tgPY0W90Ql62F75cJ/6JEft9Qs3BuMx8IqpH6whEnFhB jBiAIFrhRK39OrfdF0OclJnRf4uWrUOV7XgsGUIoh3jK0wMk5lbuHNg4FpCEp5WYbnYM 8y/Ra9oMvTXwm28RkGL+UeON25KoAMcQ+Hds4G45H1byarL2ptd2I999jYaTTQtgeLGN /vxACwmkg5Q8sHitLhu5DdSiN8qG61Zw76Rv0WCSMZdWMznKkMdrVzu0odE+EEFpsLIu 4WFIRZ6HQpvxdCiypiTYi33v+i1op3Ftff7PxLA6HQwLY6GSCI41CrxO5t1RHFXfK9PF Q0Ng== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=to:from:subject:references:mime-version:message-id:in-reply-to:date :x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=tqdZ+G+VG1pXrXKKnIZ+HhiVU4LU/SJNnBh8ENQqCxc=; b=Qu4EBRcs3JG+GUI8LAQJCJC3Y3Auk0QgG892pBo6wFM35ENskCzarSu5DwBMEb7KaA 0Nea1UAeVEjF0YqT+bI3ZhGR6lP42oiqameeWU0dFgnAhACnX8QqgIyRa0E+w0Cwu4mY gR/PnAM57ec0kqRXsQd4v86kfnZ4rZYeeIlOsrHrZOffuta9xPscmV2XO0gzIA/fLuJp zuIjz5u1QvGSXgsSTlmnfimb7WmcxUpPFAGJvni0Msq5SYOVubI8+a8Crrcb55jG7fyB xn3LH2C3UVQkm8PluN76VTapeCKHBPYl2PNa3w8NVuX23QSEwvdc9F4tlRaHknJsOeDk Iryg== X-Gm-Message-State: AO0yUKX+EzUJlyinvzeH3UmEKNH3dLR0KcYN4fVvY+1fX/LtavOnc2t3 0ghIHGkgvCN+/ZqdH/GRgx6W6qwiZ79i X-Google-Smtp-Source: AK7set+dgqX2j8MuW+xdhwgM+ldNVX/T9gkhXNcSHS8RuMbBK8laFiP6db7m4u8zEoccn+w38ASYt8b6K28j X-Received: from irogers.svl.corp.google.com ([2620:15c:2d4:203:9002:67cd:9e6b:7083]) (user=irogers job=sendgmr) by 2002:a05:6902:154b:b0:9f5:af6b:6f69 with SMTP id r11-20020a056902154b00b009f5af6b6f69mr1961555ybu.5.1677131619856; Wed, 22 Feb 2023 21:53:39 -0800 (PST) Date: Wed, 22 Feb 2023 21:53:05 -0800 In-Reply-To: <20230223055306.296179-1-irogers@google.com> Message-Id: <20230223055306.296179-3-irogers@google.com> Mime-Version: 1.0 References: <20230223055306.296179-1-irogers@google.com> X-Mailer: git-send-email 2.39.2.637.g21b0678d19-goog Subject: [PATCH v1 2/3] perf vendor events intel: Update alderlaken to v1.19 From: Ian Rogers To: Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Mark Rutland , Alexander Shishkin , Jiri Olsa , Namhyung Kim , Ian Rogers , Zhengjun Xing , Kan Liang , linux-perf-users@vger.kernel.org, linux-kernel@vger.kernel.org, Edward Baker Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Update alderlaken perf json from v1.18 to v1.19. Based on: https://github.com/intel/perfmon/pull/58 perf json files created using: https://github.com/intel/perfmon/blob/main/scripts/create_perf_json.py Signed-off-by: Ian Rogers --- tools/perf/pmu-events/arch/x86/alderlaken/memory.json | 7 +++++++ tools/perf/pmu-events/arch/x86/mapfile.csv | 2 +- 2 files changed, 8 insertions(+), 1 deletion(-) diff --git a/tools/perf/pmu-events/arch/x86/alderlaken/memory.json b/tools/= perf/pmu-events/arch/x86/alderlaken/memory.json index f84bf8c43495..37259d38a222 100644 --- a/tools/perf/pmu-events/arch/x86/alderlaken/memory.json +++ b/tools/perf/pmu-events/arch/x86/alderlaken/memory.json @@ -13,6 +13,13 @@ "SampleAfterValue": "1000003", "UMask": "0xf4" }, + { + "BriefDescription": "Counts the number of cycles that the head (ol= dest load) of the load buffer and retirement are both stalled due to a DL1 = miss.", + "EventCode": "0x05", + "EventName": "LD_HEAD.L1_MISS_AT_RET", + "SampleAfterValue": "1000003", + "UMask": "0x81" + }, { "BriefDescription": "Counts the number of cycles that the head (ol= dest load) of the load buffer and retirement are both stalled due to other = block cases.", "EventCode": "0x05", diff --git a/tools/perf/pmu-events/arch/x86/mapfile.csv b/tools/perf/pmu-ev= ents/arch/x86/mapfile.csv index e69b29123327..1c5776e37120 100644 --- a/tools/perf/pmu-events/arch/x86/mapfile.csv +++ b/tools/perf/pmu-events/arch/x86/mapfile.csv @@ -1,6 +1,6 @@ Family-model,Version,Filename,EventType GenuineIntel-6-(97|9A|B7|BA|BF),v1.19,alderlake,core -GenuineIntel-6-BE,v1.18,alderlaken,core +GenuineIntel-6-BE,v1.19,alderlaken,core GenuineIntel-6-(1C|26|27|35|36),v4,bonnell,core GenuineIntel-6-(3D|47),v26,broadwell,core GenuineIntel-6-56,v7,broadwellde,core --=20 2.39.2.637.g21b0678d19-goog From nobody Thu Sep 11 00:21:42 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 05657C64ED6 for ; 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Wed, 22 Feb 2023 21:53:48 -0800 (PST) Date: Wed, 22 Feb 2023 21:53:06 -0800 In-Reply-To: <20230223055306.296179-1-irogers@google.com> Message-Id: <20230223055306.296179-4-irogers@google.com> Mime-Version: 1.0 References: <20230223055306.296179-1-irogers@google.com> X-Mailer: git-send-email 2.39.2.637.g21b0678d19-goog Subject: [PATCH v1 3/3] perf vendor events intel: Update icelakex to v1.19 From: Ian Rogers To: Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Mark Rutland , Alexander Shishkin , Jiri Olsa , Namhyung Kim , Ian Rogers , Zhengjun Xing , Kan Liang , linux-perf-users@vger.kernel.org, linux-kernel@vger.kernel.org, Edward Baker Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Update icelakex perf json from v1.18 to v1.19. Based on: https://github.com/intel/perfmon/pull/58 perf json files created using: https://github.com/intel/perfmon/blob/main/scripts/create_perf_json.py Signed-off-by: Ian Rogers --- .../pmu-events/arch/x86/icelakex/cache.json | 8 +++++ .../arch/x86/icelakex/floating-point.json | 31 +++++++++++++++++++ .../arch/x86/icelakex/pipeline.json | 10 ++++++ tools/perf/pmu-events/arch/x86/mapfile.csv | 2 +- 4 files changed, 50 insertions(+), 1 deletion(-) diff --git a/tools/perf/pmu-events/arch/x86/icelakex/cache.json b/tools/per= f/pmu-events/arch/x86/icelakex/cache.json index d6463c8d9462..3bdc56a75097 100644 --- a/tools/perf/pmu-events/arch/x86/icelakex/cache.json +++ b/tools/perf/pmu-events/arch/x86/icelakex/cache.json @@ -825,6 +825,14 @@ "SampleAfterValue": "1000003", "UMask": "0x1" }, + { + "BriefDescription": "Counts bus locks, accounts for cache line spl= it locks and UC locks.", + "EventCode": "0xF4", + "EventName": "SQ_MISC.BUS_LOCK", + "PublicDescription": "Counts the more expensive bus lock needed to= enforce cache coherency for certain memory accesses that need to be done a= tomically. Can be created by issuing an atomic instruction (via the LOCK p= refix) which causes a cache line split or accesses uncacheable memory.", + "SampleAfterValue": "100003", + "UMask": "0x10" + }, { "BriefDescription": "Cycles the queue waiting for offcore response= s is full.", "EventCode": "0xf4", diff --git a/tools/perf/pmu-events/arch/x86/icelakex/floating-point.json b/= tools/perf/pmu-events/arch/x86/icelakex/floating-point.json index 655342dadac6..85c26c889088 100644 --- a/tools/perf/pmu-events/arch/x86/icelakex/floating-point.json +++ b/tools/perf/pmu-events/arch/x86/icelakex/floating-point.json @@ -39,6 +39,14 @@ "SampleAfterValue": "100003", "UMask": "0x20" }, + { + "BriefDescription": "Number of SSE/AVX computational 128-bit packe= d single and 256-bit packed double precision FP instructions retired; some = instructions will count twice as noted below. Each count represents 2 or/a= nd 4 computation operations, 1 for each element. Applies to SSE* and AVX* = packed single precision and packed double precision FP instructions: ADD SU= B HADD HSUB SUBADD MUL DIV MIN MAX RCP14 RSQRT14 SQRT DPP FM(N)ADD/SUB. DP= P and FM(N)ADD/SUB count twice as they perform 2 calculations per element.", + "EventCode": "0xc7", + "EventName": "FP_ARITH_INST_RETIRED.4_FLOPS", + "PublicDescription": "Number of SSE/AVX computational 128-bit pack= ed single precision and 256-bit packed double precision floating-point ins= tructions retired; some instructions will count twice as noted below. Each= count represents 2 or/and 4 computation operations, one for each element. = Applies to SSE* and AVX* packed single precision floating-point and packed= double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL= DIV MIN MAX RCP14 RSQRT14 SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB ins= tructions count twice as they perform 2 calculations per element. The DAZ a= nd FTZ flags in the MXCSR register need to be set when using these events.", + "SampleAfterValue": "100003", + "UMask": "0x18" + }, { "BriefDescription": "Counts number of SSE/AVX computational 512-bi= t packed double precision floating-point instructions retired; some instruc= tions will count twice as noted below. Each count represents 8 computation= operations, one for each element. Applies to SSE* and AVX* packed double = precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT14= RCP14 FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform = 2 calculations per element.", "EventCode": "0xc7", @@ -55,6 +63,22 @@ "SampleAfterValue": "100003", "UMask": "0x80" }, + { + "BriefDescription": "Number of SSE/AVX computational 256-bit packe= d single precision and 512-bit packed double precision FP instructions ret= ired; some instructions will count twice as noted below. Each count repres= ents 8 computation operations, 1 for each element. Applies to SSE* and AVX= * packed single precision and double precision FP instructions: ADD SUB HAD= D HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT RSQRT14 RCP RCP14 DPP FM(N)ADD/SUB= . DPP and FM(N)ADD/SUB count twice as they perform 2 calculations per elem= ent.", + "EventCode": "0xc7", + "EventName": "FP_ARITH_INST_RETIRED.8_FLOPS", + "PublicDescription": "Number of SSE/AVX computational 256-bit pack= ed single precision and 512-bit packed double precision floating-point ins= tructions retired; some instructions will count twice as noted below. Each= count represents 8 computation operations, one for each element. Applies = to SSE* and AVX* packed single precision and double precision floating-poin= t instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT RSQRT14= RCP RCP14 DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice= as they perform 2 calculations per element. The DAZ and FTZ flags in the M= XCSR register need to be set when using these events.", + "SampleAfterValue": "100003", + "UMask": "0x60" + }, + { + "BriefDescription": "Number of SSE/AVX computational scalar floati= ng-point instructions retired; some instructions will count twice as noted = below. Applies to SSE* and AVX* scalar, double and single precision floati= ng-point: ADD SUB MUL DIV MIN MAX RCP14 RSQRT14 SQRT DPP FM(N)ADD/SUB. DPP= and FM(N)ADD/SUB instructions count twice as they perform multiple calcula= tions per element.", + "EventCode": "0xc7", + "EventName": "FP_ARITH_INST_RETIRED.SCALAR", + "PublicDescription": "Number of SSE/AVX computational scalar singl= e precision and double precision floating-point instructions retired; some = instructions will count twice as noted below. Each count represents 1 comp= utational operation. Applies to SSE* and AVX* scalar single precision float= ing-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT RCP FM(N)ADD/SUB= . FM(N)ADD/SUB instructions count twice as they perform 2 calculations per= element. The DAZ and FTZ flags in the MXCSR register need to be set when u= sing these events.", + "SampleAfterValue": "1000003", + "UMask": "0x3" + }, { "BriefDescription": "Counts number of SSE/AVX computational scalar= double precision floating-point instructions retired; some instructions wi= ll count twice as noted below. Each count represents 1 computational opera= tion. Applies to SSE* and AVX* scalar double precision floating-point instr= uctions: ADD SUB MUL DIV MIN MAX SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructi= ons count twice as they perform 2 calculations per element.", "EventCode": "0xc7", @@ -70,5 +94,12 @@ "PublicDescription": "Number of SSE/AVX computational scalar singl= e precision floating-point instructions retired; some instructions will cou= nt twice as noted below. Each count represents 1 computational operation. = Applies to SSE* and AVX* scalar single precision floating-point instruction= s: ADD SUB MUL DIV MIN MAX SQRT RSQRT RCP FM(N)ADD/SUB. FM(N)ADD/SUB instr= uctions count twice as they perform 2 calculations per element. The DAZ and= FTZ flags in the MXCSR register need to be set when using these events.", "SampleAfterValue": "100003", "UMask": "0x2" + }, + { + "BriefDescription": "Number of any Vector retired FP arithmetic in= structions", + "EventCode": "0xc7", + "EventName": "FP_ARITH_INST_RETIRED.VECTOR", + "SampleAfterValue": "1000003", + "UMask": "0xfc" } ] diff --git a/tools/perf/pmu-events/arch/x86/icelakex/pipeline.json b/tools/= perf/pmu-events/arch/x86/icelakex/pipeline.json index 4cf16a1fcad4..442a4c7539dd 100644 --- a/tools/perf/pmu-events/arch/x86/icelakex/pipeline.json +++ b/tools/perf/pmu-events/arch/x86/icelakex/pipeline.json @@ -374,6 +374,16 @@ "SampleAfterValue": "2000003", "UMask": "0x3" }, + { + "BriefDescription": "Clears speculative count", + "CounterMask": "1", + "EdgeDetect": "1", + "EventCode": "0x0D", + "EventName": "INT_MISC.CLEARS_COUNT", + "PublicDescription": "Counts the number of speculative clears due = to any type of branch misprediction or machine clears", + "SampleAfterValue": "500009", + "UMask": "0x1" + }, { "BriefDescription": "Counts cycles after recovery from a branch mi= sprediction or machine clear till the first uop is issued from the resteere= d path.", "EventCode": "0x0d", diff --git a/tools/perf/pmu-events/arch/x86/mapfile.csv b/tools/perf/pmu-ev= ents/arch/x86/mapfile.csv index 1c5776e37120..bb4e545fa100 100644 --- a/tools/perf/pmu-events/arch/x86/mapfile.csv +++ b/tools/perf/pmu-events/arch/x86/mapfile.csv @@ -13,7 +13,7 @@ GenuineIntel-6-A[DE],v1.00,graniterapids,core GenuineIntel-6-(3C|45|46),v32,haswell,core GenuineIntel-6-3F,v26,haswellx,core GenuineIntel-6-(7D|7E|A7),v1.17,icelake,core -GenuineIntel-6-6[AC],v1.18,icelakex,core +GenuineIntel-6-6[AC],v1.19,icelakex,core GenuineIntel-6-3A,v23,ivybridge,core GenuineIntel-6-3E,v22,ivytown,core GenuineIntel-6-2D,v22,jaketown,core --=20 2.39.2.637.g21b0678d19-goog