From nobody Thu Sep 11 00:12:34 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 37134C636D7 for ; Thu, 23 Feb 2023 04:23:09 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233327AbjBWEXH (ORCPT ); Wed, 22 Feb 2023 23:23:07 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:35154 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233218AbjBWEWd (ORCPT ); Wed, 22 Feb 2023 23:22:33 -0500 Received: from mail-ot1-x331.google.com (mail-ot1-x331.google.com [IPv6:2607:f8b0:4864:20::331]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 7415A49892 for ; Wed, 22 Feb 2023 20:21:23 -0800 (PST) Received: by mail-ot1-x331.google.com with SMTP id f19-20020a9d5f13000000b00693ce5a2f3eso561071oti.8 for ; Wed, 22 Feb 2023 20:21:23 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=v+KyrF1DXPa/BBYyuptUwg7+QHC/Wtb90A7GWVnf/LQ=; b=F42rBy0uNCTG5FsGgWJ7gvpyDmSYfo3yFM5gZac73TMYx+LrwX1jO7AwW9dyjHka0h rnHYGX9Wz5vnkb7lNdAosUAC4awxAvzZNGPYxxmbUkBwAdaZMya9euLYtRK5z9j8f+47 TITlZAVhSxWZeTGAjCFg4QLmHwOg+gl5HJyOR6cP71MeSXdW5OkaIbQ9cMf/ZG/zrDTc +fP8NP7Qcz5t1OvWj1iB4G1vHMUZijn1ik1LoNN3MsA92wmsTfB7uNoI57WowQUtAw9e 2gUvAok7e8ZywAy2RfIzRREBCY01wJaBM26hgusDPeAy5CcVpckpu/USushlNF0j1M22 wD0g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=v+KyrF1DXPa/BBYyuptUwg7+QHC/Wtb90A7GWVnf/LQ=; b=4LQvWxYkjk2kmaMWEBt/5lnK4+W5veO9EVX9Z3pJ/ajWIrwCTRHsMUZSb+NyivozkH nik+hIXW4tNOZqDhWtj48xtL+8RmyboV6ungt/rkXkQNzEmOEqbu1209RocAVOFlJfAZ W+t2to1DuQ0FnxjCDh8EcRy7YzSGcNzX0Tg+QW071ylsxsHD8e4F5XbrE0BLWax586yw /h24r2hYltgEiqTdqOya41ogVSGezHAGVp1XQQsOov3p5SQE6KtSAxF7Geq2IFjh4En3 pDDV1vvkoskUei9cNrPSUSkKh8Vmbubg+QniQdXn+hhuW43BU1zl326T4GaL6uQ7th2J mI4g== X-Gm-Message-State: AO0yUKW2bY9nJJYngIR88f6iCr1b8cY94bE9cUWO8Smqb3MEN1Dc4dgF a5rbVrHtm2sbsQaUB0gbWxaixQ== X-Google-Smtp-Source: AK7set+jvVKbzwVqAV0SPhuE7cVbyzq+q+DqSnejyIwB+JA1S1TT05zoCY2O7j66FLwanJ04I8nKMQ== X-Received: by 2002:a9d:1788:0:b0:690:ece7:62d2 with SMTP id j8-20020a9d1788000000b00690ece762d2mr2237610otj.19.1677126079713; Wed, 22 Feb 2023 20:21:19 -0800 (PST) Received: from localhost ([136.49.140.41]) by smtp.gmail.com with ESMTPSA id l3-20020a9d5503000000b00693c66c0692sm1708793oth.29.2023.02.22.20.21.19 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 22 Feb 2023 20:21:19 -0800 (PST) From: Sam Protsenko To: Krzysztof Kozlowski , Chanwoo Choi , Sylwester Nawrocki , Rob Herring Cc: David Virag , Chanho Park , Alim Akhtar , Sumit Semwal , Tomasz Figa , Michael Turquette , Stephen Boyd , linux-samsung-soc@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 1/6] dt-bindings: clock: exynos850: Add Exynos850 CMU_G3D Date: Wed, 22 Feb 2023 22:21:28 -0600 Message-Id: <20230223042133.26551-2-semen.protsenko@linaro.org> X-Mailer: git-send-email 2.39.1 In-Reply-To: <20230223042133.26551-1-semen.protsenko@linaro.org> References: <20230223042133.26551-1-semen.protsenko@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" CMU_G3D generates Gondul GPU and bus clocks for BLK_G3D. Add clock indices and binding documentation for CMU_G3D. Acked-by: Rob Herring Signed-off-by: Sam Protsenko --- Changes in v2: - Rebased on top of most recent soc/for-next tree - Added Rob Herring Acked-by tag .../clock/samsung,exynos850-clock.yaml | 19 ++++++++++++++++++ include/dt-bindings/clock/exynos850.h | 20 ++++++++++++++++++- 2 files changed, 38 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/clock/samsung,exynos850-cloc= k.yaml b/Documentation/devicetree/bindings/clock/samsung,exynos850-clock.ya= ml index 141cf173f87d..8aa87b8c1b33 100644 --- a/Documentation/devicetree/bindings/clock/samsung,exynos850-clock.yaml +++ b/Documentation/devicetree/bindings/clock/samsung,exynos850-clock.yaml @@ -37,6 +37,7 @@ properties: - samsung,exynos850-cmu-cmgp - samsung,exynos850-cmu-core - samsung,exynos850-cmu-dpu + - samsung,exynos850-cmu-g3d - samsung,exynos850-cmu-hsi - samsung,exynos850-cmu-is - samsung,exynos850-cmu-mfcmscl @@ -169,6 +170,24 @@ allOf: - const: oscclk - const: dout_dpu =20 + - if: + properties: + compatible: + contains: + const: samsung,exynos850-cmu-g3d + + then: + properties: + clocks: + items: + - description: External reference clock (26 MHz) + - description: G3D clock (from CMU_TOP) + + clock-names: + items: + - const: oscclk + - const: dout_g3d_switch + - if: properties: compatible: diff --git a/include/dt-bindings/clock/exynos850.h b/include/dt-bindings/cl= ock/exynos850.h index 88d5289883d3..8bb62e43fd60 100644 --- a/include/dt-bindings/clock/exynos850.h +++ b/include/dt-bindings/clock/exynos850.h @@ -85,7 +85,10 @@ #define CLK_DOUT_MFCMSCL_M2M 73 #define CLK_DOUT_MFCMSCL_MCSC 74 #define CLK_DOUT_MFCMSCL_JPEG 75 -#define TOP_NR_CLK 76 +#define CLK_MOUT_G3D_SWITCH 76 +#define CLK_GOUT_G3D_SWITCH 77 +#define CLK_DOUT_G3D_SWITCH 78 +#define TOP_NR_CLK 79 =20 /* CMU_APM */ #define CLK_RCO_I3C_PMIC 1 @@ -195,6 +198,21 @@ #define CLK_GOUT_SYSREG_CMGP_PCLK 15 #define CMGP_NR_CLK 16 =20 +/* CMU_G3D */ +#define CLK_FOUT_G3D_PLL 1 +#define CLK_MOUT_G3D_PLL 2 +#define CLK_MOUT_G3D_SWITCH_USER 3 +#define CLK_MOUT_G3D_BUSD 4 +#define CLK_DOUT_G3D_BUSP 5 +#define CLK_GOUT_G3D_CMU_G3D_PCLK 6 +#define CLK_GOUT_G3D_GPU_CLK 7 +#define CLK_GOUT_G3D_TZPC_PCLK 8 +#define CLK_GOUT_G3D_GRAY2BIN_CLK 9 +#define CLK_GOUT_G3D_BUSD_CLK 10 +#define CLK_GOUT_G3D_BUSP_CLK 11 +#define CLK_GOUT_G3D_SYSREG_PCLK 12 +#define G3D_NR_CLK 13 + /* CMU_HSI */ #define CLK_MOUT_HSI_BUS_USER 1 #define CLK_MOUT_HSI_MMC_CARD_USER 2 --=20 2.39.1 From nobody Thu Sep 11 00:12:34 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4F16FC636D7 for ; Thu, 23 Feb 2023 04:23:13 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233332AbjBWEXM (ORCPT ); Wed, 22 Feb 2023 23:23:12 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:34888 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233276AbjBWEWe (ORCPT ); Wed, 22 Feb 2023 23:22:34 -0500 Received: from mail-ot1-x332.google.com (mail-ot1-x332.google.com [IPv6:2607:f8b0:4864:20::332]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 40053497F8 for ; Wed, 22 Feb 2023 20:21:24 -0800 (PST) Received: by mail-ot1-x332.google.com with SMTP id f19-20020a9d5f13000000b00693ce5a2f3eso561080oti.8 for ; Wed, 22 Feb 2023 20:21:24 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=01ISZatEwoHnY9nhwEKU5Czp8lSia2kyO6GGxMXIwAw=; b=JQrrLrdxv6bM2+L67OBB+Xf34SWha01vxINwnQcSCBnjvnWad9irHinJ76Xc4lpyzT Vu+zx4c3kQiKOjEiC5oRG+C3RTNSFUNrxoBwGTV3iBz540FYnTfKumPEkkyUJYE9sL0c OHgEMrzb4ZD76dNYLoAhuT+Nf6Pj9yn3N24h//Inr1QjxF3edYsebyWybk3vaSlL/RM6 KBkass1tjXqgioefiFe8uCf8Z4diOos8mLySzfeN8N+ZVC/yz8kY0cPT5utC7e7jMvDG dhUxZU9hKCA9NJ3R5q2VBdgOKkzZsI/5Xs9xidjMVTmOrcAVzChitwgYQ/Eemledr8Mk 4q5g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=01ISZatEwoHnY9nhwEKU5Czp8lSia2kyO6GGxMXIwAw=; b=7k2pR0eSMOzegSY0YAsTQNtehKstma6bpZqDuNVXmCCZop2gqGRJI3vep7KDY5jXUJ HYYkTO/3nBSABJNv8UZhlpf07d4t0KidbfV6op9JpIiBKyfS4DFQNb8Cf4RtECu1w3xA ZFKThv4y63CJvIhFuL6nuPu4cOXbtxGUDAeylKF4BnGxZq5Wlxu9bpNjkA7SPL95XDqk joqR36U+iry/10yTk+USUpzXfsxiAvgP6GoitZl9S0oWj13O/XZv5+j83aoFYFbosGQq Lmw/bBbA4+YrrJ0tQZNToBUR2Rq8UyXg4S8rb/x6VY4cFZ4FVKxDavV1zo9xzMjPh0zC dRww== X-Gm-Message-State: AO0yUKUtSGiEWyX/d21Mxw1SL1qAJl4NgLn/GeX239a3q2mSY6W0GiKJ wXMK92Vtnv7lkBi1nkvobug25g== X-Google-Smtp-Source: AK7set94hn97PVKoIygtCMvlArbY6ADOZ2OLeOPxpSypXWW/9O/AF5J2vaGYfbwLoA7rVDTZSR+Orw== X-Received: by 2002:a9d:3e5:0:b0:68b:d0cc:d1c2 with SMTP id f92-20020a9d03e5000000b0068bd0ccd1c2mr1825532otf.19.1677126081271; Wed, 22 Feb 2023 20:21:21 -0800 (PST) Received: from localhost ([136.49.140.41]) by smtp.gmail.com with ESMTPSA id y16-20020a4acb90000000b005200c4b6267sm1448576ooq.9.2023.02.22.20.21.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 22 Feb 2023 20:21:20 -0800 (PST) From: Sam Protsenko To: Krzysztof Kozlowski , Chanwoo Choi , Sylwester Nawrocki , Rob Herring Cc: David Virag , Chanho Park , Alim Akhtar , Sumit Semwal , Tomasz Figa , Michael Turquette , Stephen Boyd , linux-samsung-soc@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 2/6] dt-bindings: clock: exynos850: Add AUD and HSI main gate clocks Date: Wed, 22 Feb 2023 22:21:29 -0600 Message-Id: <20230223042133.26551-3-semen.protsenko@linaro.org> X-Mailer: git-send-email 2.39.1 In-Reply-To: <20230223042133.26551-1-semen.protsenko@linaro.org> References: <20230223042133.26551-1-semen.protsenko@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add main gate clocks for controlling AUD and HSI CMUs: - gout_aud_cmu_aud_pclk - gout_hsi_cmu_hsi_pclk While at it, add missing PPMU (Performance Profiling Monitor Unit) clocks for CMU_HSI. Acked-by: Rob Herring Signed-off-by: Sam Protsenko --- Changes in v2: - Rebased on top of most recent soc/for-next tree - Added Rob Herring Acked-by tag include/dt-bindings/clock/exynos850.h | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/include/dt-bindings/clock/exynos850.h b/include/dt-bindings/cl= ock/exynos850.h index 8bb62e43fd60..afacba338c91 100644 --- a/include/dt-bindings/clock/exynos850.h +++ b/include/dt-bindings/clock/exynos850.h @@ -178,7 +178,8 @@ #define IOCLK_AUDIOCDCLK5 58 #define IOCLK_AUDIOCDCLK6 59 #define TICK_USB 60 -#define AUD_NR_CLK 61 +#define CLK_GOUT_AUD_CMU_AUD_PCLK 61 +#define AUD_NR_CLK 62 =20 /* CMU_CMGP */ #define CLK_RCO_CMGP 1 @@ -227,7 +228,10 @@ #define CLK_GOUT_MMC_CARD_ACLK 11 #define CLK_GOUT_MMC_CARD_SDCLKIN 12 #define CLK_GOUT_SYSREG_HSI_PCLK 13 -#define HSI_NR_CLK 14 +#define CLK_GOUT_HSI_PPMU_ACLK 14 +#define CLK_GOUT_HSI_PPMU_PCLK 15 +#define CLK_GOUT_HSI_CMU_HSI_PCLK 16 +#define HSI_NR_CLK 17 =20 /* CMU_IS */ #define CLK_MOUT_IS_BUS_USER 1 --=20 2.39.1 From nobody Thu Sep 11 00:12:34 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1148FC61DA4 for ; Thu, 23 Feb 2023 04:23:17 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233341AbjBWEXP (ORCPT ); Wed, 22 Feb 2023 23:23:15 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:36144 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233296AbjBWEWg (ORCPT ); Wed, 22 Feb 2023 23:22:36 -0500 Received: from mail-ot1-x332.google.com (mail-ot1-x332.google.com [IPv6:2607:f8b0:4864:20::332]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 0391649895 for ; Wed, 22 Feb 2023 20:21:28 -0800 (PST) Received: by mail-ot1-x332.google.com with SMTP id a14-20020a056830100e00b00690ed91749aso2091995otp.7 for ; Wed, 22 Feb 2023 20:21:27 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=3rOeT+TlXHq+kYJRcc5stz7RolNpClrKSBYxv7SYDZo=; b=yhCAsDnjDQXPkSq2JXGYxr7DKODT6rJDVT7ABVTz0LPZCGng/9MX6BjredcfQt86+r H0e3oKJlyTqJ8MrCHvdLKdt5cQM+ypPuS7PTlEmHRkv1bzO9NeD9/gfJWLbsd8uwVku8 jBbwhFjSJKYkmjjAldFM/FL26FJ64Nven8w7H2pS1N0rxYXApxgTwMLNOqfK7aLorV92 v7OMXYVOziguas23Ag+hc9wMz9oBefPlB4NdDV0+5aCEeewAr9GjIPPyskus6RDaeZ97 b92jROQUjLr9tCGUPuIXN+wienWQ7dZV5Dt3PLRc3rZr2q8fv0UV6Jes8npHCy6r7jyd IXIw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=3rOeT+TlXHq+kYJRcc5stz7RolNpClrKSBYxv7SYDZo=; b=tmWSm7ZLBBvrVdyDhkDS8hyOoC4a9FLKs0y+D+09f0l/irlwS2DM00tuKIlbzglmoL McZSN9RT8k2zjNWv4LFuwuwo95wnxGtV48kFOzcinVrbwcIOalra/xZxe1FJ8sAliBKf yGAIYRtD23tSlkaEeNizcjPOM0Oc15ZPaJ/66s7ACCKKRAc//AYfQXmrCOPVBWMLLARR qHH64AJsXCLwWH2e5yVd9wvIVGDMPN/CfgOLzBBmdTaGb96gAV5H1MtPWG4eoXYj1Wcb 29nwtpYQi+wSa86sk5sUuLXGOFgKQpehO1O/Rr3Y5Xw2Tp91AHrQNd5MQwEEde25uZZN OTLA== X-Gm-Message-State: AO0yUKU8WZLFuvIss0MnTGb98Qz15WExGufSBiU50m01nEujQO2Di2dz GeEnAslK28thd0nsbzJEA5fpBg== X-Google-Smtp-Source: AK7set+lh60j/dD/b3OYUa4K/o8jntVzHLjpfTyTwS2d2UmMik103hQoAN8BIUNLOjLX6bvbM40Jlw== X-Received: by 2002:a05:6830:550:b0:68b:c938:878a with SMTP id l16-20020a056830055000b0068bc938878amr1440059otb.16.1677126082172; Wed, 22 Feb 2023 20:21:22 -0800 (PST) Received: from localhost ([136.49.140.41]) by smtp.gmail.com with ESMTPSA id y7-20020a9d5187000000b0068bb7bd2668sm2225332otg.73.2023.02.22.20.21.21 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 22 Feb 2023 20:21:21 -0800 (PST) From: Sam Protsenko To: Krzysztof Kozlowski , Chanwoo Choi , Sylwester Nawrocki , Rob Herring Cc: David Virag , Chanho Park , Alim Akhtar , Sumit Semwal , Tomasz Figa , Michael Turquette , Stephen Boyd , linux-samsung-soc@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 3/6] clk: samsung: clk-pll: Implement pll0818x PLL type Date: Wed, 22 Feb 2023 22:21:30 -0600 Message-Id: <20230223042133.26551-4-semen.protsenko@linaro.org> X-Mailer: git-send-email 2.39.1 In-Reply-To: <20230223042133.26551-1-semen.protsenko@linaro.org> References: <20230223042133.26551-1-semen.protsenko@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" pll0818x PLL is used in Exynos850 SoC for CMU_G3D PLL. Operation-wise, pll0818x is the same as pll0822x. The only difference is: - pl0822x is integer PLL with Middle FVCO (950 to 2400 MHz) - pl0818x is integer PLL with Low FVCO (600 to 1200 MHz) Add pll0818x type as an alias to pll0822x. Reviewed-by: Chanho Park Signed-off-by: Sam Protsenko --- Changes in v2: - Rebased on top of most recent soc/for-next tree - Added Chanho Park Reviewed-by tag drivers/clk/samsung/clk-pll.c | 1 + drivers/clk/samsung/clk-pll.h | 1 + 2 files changed, 2 insertions(+) diff --git a/drivers/clk/samsung/clk-pll.c b/drivers/clk/samsung/clk-pll.c index 5ceac4c25c1c..74934c6182ce 100644 --- a/drivers/clk/samsung/clk-pll.c +++ b/drivers/clk/samsung/clk-pll.c @@ -1314,6 +1314,7 @@ static void __init _samsung_clk_register_pll(struct s= amsung_clk_provider *ctx, init.ops =3D &samsung_pll35xx_clk_ops; break; case pll_1417x: + case pll_0818x: case pll_0822x: pll->enable_offs =3D PLL0822X_ENABLE_SHIFT; pll->lock_offs =3D PLL0822X_LOCK_STAT_SHIFT; diff --git a/drivers/clk/samsung/clk-pll.h b/drivers/clk/samsung/clk-pll.h index 5d5a58d40e7e..0725d485c6ee 100644 --- a/drivers/clk/samsung/clk-pll.h +++ b/drivers/clk/samsung/clk-pll.h @@ -34,6 +34,7 @@ enum samsung_pll_type { pll_1451x, pll_1452x, pll_1460x, + pll_0818x, pll_0822x, pll_0831x, pll_142xx, --=20 2.39.1 From nobody Thu Sep 11 00:12:34 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id F2C0DC61DA4 for ; Thu, 23 Feb 2023 04:23:21 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233353AbjBWEXU (ORCPT ); Wed, 22 Feb 2023 23:23:20 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:37002 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233178AbjBWEWj (ORCPT ); Wed, 22 Feb 2023 23:22:39 -0500 Received: from mail-ot1-x32c.google.com (mail-ot1-x32c.google.com [IPv6:2607:f8b0:4864:20::32c]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id D28334989E for ; Wed, 22 Feb 2023 20:21:30 -0800 (PST) Received: by mail-ot1-x32c.google.com with SMTP id r23-20020a05683001d700b00690eb18529fso2154662ota.1 for ; Wed, 22 Feb 2023 20:21:30 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=ObXtAc45vWaZLEQ3bxJUlEtdgph9izN+G12E0taCLhE=; b=rIogyiyJtFe3AWx2wtywsnxDsHMumEbBmjza1idOvos6Y0tgSwmU3KSZcU/pV1A/qn UWpItJGdAtElb+SLxsS2ftqpxmnh3KsxffkAJgT0xEHqCHNttzdcx3cqu+kEuCzZq5aw 98tYHF6uWxufjqwf5cMbvpOlI12T56Byz3iBq6nzogzc8uiUl2SHC8gNufWvuSTRRRPN 2E2QeSBd6MYdt9lG+vuqoElVpWrVayGvkizfvkVYQQztmrsHw6gxOo+9bPlxlpWCsax5 aRHXlAq7CnJmh+kL/5zUfcN0g9c/R4ZeWh2qov2ilY+npu/xs4rceSft2KwW/lxj/mO8 8o7w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=ObXtAc45vWaZLEQ3bxJUlEtdgph9izN+G12E0taCLhE=; b=fo/qo+IiWr5Ja6/4mYuthOVvY3AYFXswiv7Jr4e9zn5NXcYzmkg0nKH76pc61kiVAV +trUAIML9KpNivBBvvLhNwcxIX05jbeP+z7dbeYuJUcP+3Z27xl7qqeC3UeM8CM3SFw7 Em5Auivx2AGVLPZ+TgKuVCLdSXVdKOoQARhZR6h0be2+F8Hp6vKF1DKLFjgdtlioMd2m Z3g7CvoYb4827v49yKU3FYHx2F11b7Td7IM5ipEe0GWMv/FxflxN1VxdwqjRmeICxYqM HYjrLl46FaxJzbaQWFkNDjDXKxhJmbA7mTnSTsYgu8OukVoHvdWzB0yoneNEHAlowVNI 8XEg== X-Gm-Message-State: AO0yUKUTmcsyKmC0RwNWVqPZbLJ5Pd88X3W97W/bN6N6AA0b02J2FKjl 2idMqR6PwflTtCHNt6wRxfFuhw== X-Google-Smtp-Source: AK7set+sQrHE6LQnNU2oEOnwJWRL4M+kyA37BAZWuRkR/qaI5RQqHGKOXNbZ3lklv96JMCEn7IuJzQ== X-Received: by 2002:a05:6830:6b0d:b0:690:eb17:89f4 with SMTP id db13-20020a0568306b0d00b00690eb1789f4mr5030836otb.3.1677126083259; Wed, 22 Feb 2023 20:21:23 -0800 (PST) Received: from localhost ([136.49.140.41]) by smtp.gmail.com with ESMTPSA id i3-20020a05683033e300b00684152e9ff2sm2415710otu.0.2023.02.22.20.21.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 22 Feb 2023 20:21:22 -0800 (PST) From: Sam Protsenko To: Krzysztof Kozlowski , Chanwoo Choi , Sylwester Nawrocki , Rob Herring Cc: David Virag , Chanho Park , Alim Akhtar , Sumit Semwal , Tomasz Figa , Michael Turquette , Stephen Boyd , linux-samsung-soc@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 4/6] clk: samsung: exynos850: Implement CMU_G3D domain Date: Wed, 22 Feb 2023 22:21:31 -0600 Message-Id: <20230223042133.26551-5-semen.protsenko@linaro.org> X-Mailer: git-send-email 2.39.1 In-Reply-To: <20230223042133.26551-1-semen.protsenko@linaro.org> References: <20230223042133.26551-1-semen.protsenko@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" CMU_G3D clock domain provides clocks for Mali-G52 GPU and bus clocks for BLK_G3D. This patch adds next clocks: - bus clocks in CMU_TOP for CMU_G3D - all internal CMU_G3D clocks - leaf clocks for GPU, TZPC (TrustZone Protection Controller) and SysReg G3D_CMU_G3D clock was marked as CLK_IGNORE_UNUSED, as system hangs on boot otherwise. Reviewed-by: Chanho Park Signed-off-by: Sam Protsenko --- Changes in v2: - Rebased on top of most recent soc/for-next tree - Added Chanho Park Reviwed-by tag - Removed double empty line (style fix) drivers/clk/samsung/clk-exynos850.c | 120 ++++++++++++++++++++++++++++ 1 file changed, 120 insertions(+) diff --git a/drivers/clk/samsung/clk-exynos850.c b/drivers/clk/samsung/clk-= exynos850.c index 541761e96aeb..601fe05e8555 100644 --- a/drivers/clk/samsung/clk-exynos850.c +++ b/drivers/clk/samsung/clk-exynos850.c @@ -36,6 +36,7 @@ #define CLK_CON_MUX_MUX_CLKCMU_CORE_MMC_EMBD 0x101c #define CLK_CON_MUX_MUX_CLKCMU_CORE_SSS 0x1020 #define CLK_CON_MUX_MUX_CLKCMU_DPU 0x1034 +#define CLK_CON_MUX_MUX_CLKCMU_G3D_SWITCH 0x1038 #define CLK_CON_MUX_MUX_CLKCMU_HSI_BUS 0x103c #define CLK_CON_MUX_MUX_CLKCMU_HSI_MMC_CARD 0x1040 #define CLK_CON_MUX_MUX_CLKCMU_HSI_USB20DRD 0x1044 @@ -57,6 +58,7 @@ #define CLK_CON_DIV_CLKCMU_CORE_MMC_EMBD 0x1828 #define CLK_CON_DIV_CLKCMU_CORE_SSS 0x182c #define CLK_CON_DIV_CLKCMU_DPU 0x1840 +#define CLK_CON_DIV_CLKCMU_G3D_SWITCH 0x1844 #define CLK_CON_DIV_CLKCMU_HSI_BUS 0x1848 #define CLK_CON_DIV_CLKCMU_HSI_MMC_CARD 0x184c #define CLK_CON_DIV_CLKCMU_HSI_USB20DRD 0x1850 @@ -84,6 +86,7 @@ #define CLK_CON_GAT_GATE_CLKCMU_CORE_MMC_EMBD 0x2024 #define CLK_CON_GAT_GATE_CLKCMU_CORE_SSS 0x2028 #define CLK_CON_GAT_GATE_CLKCMU_DPU 0x203c +#define CLK_CON_GAT_GATE_CLKCMU_G3D_SWITCH 0x2040 #define CLK_CON_GAT_GATE_CLKCMU_HSI_BUS 0x2044 #define CLK_CON_GAT_GATE_CLKCMU_HSI_MMC_CARD 0x2048 #define CLK_CON_GAT_GATE_CLKCMU_HSI_USB20DRD 0x204c @@ -116,6 +119,7 @@ static const unsigned long top_clk_regs[] __initconst = =3D { CLK_CON_MUX_MUX_CLKCMU_CORE_MMC_EMBD, CLK_CON_MUX_MUX_CLKCMU_CORE_SSS, CLK_CON_MUX_MUX_CLKCMU_DPU, + CLK_CON_MUX_MUX_CLKCMU_G3D_SWITCH, CLK_CON_MUX_MUX_CLKCMU_HSI_BUS, CLK_CON_MUX_MUX_CLKCMU_HSI_MMC_CARD, CLK_CON_MUX_MUX_CLKCMU_HSI_USB20DRD, @@ -137,6 +141,7 @@ static const unsigned long top_clk_regs[] __initconst = =3D { CLK_CON_DIV_CLKCMU_CORE_MMC_EMBD, CLK_CON_DIV_CLKCMU_CORE_SSS, CLK_CON_DIV_CLKCMU_DPU, + CLK_CON_DIV_CLKCMU_G3D_SWITCH, CLK_CON_DIV_CLKCMU_HSI_BUS, CLK_CON_DIV_CLKCMU_HSI_MMC_CARD, CLK_CON_DIV_CLKCMU_HSI_USB20DRD, @@ -164,6 +169,7 @@ static const unsigned long top_clk_regs[] __initconst = =3D { CLK_CON_GAT_GATE_CLKCMU_CORE_MMC_EMBD, CLK_CON_GAT_GATE_CLKCMU_CORE_SSS, CLK_CON_GAT_GATE_CLKCMU_DPU, + CLK_CON_GAT_GATE_CLKCMU_G3D_SWITCH, CLK_CON_GAT_GATE_CLKCMU_HSI_BUS, CLK_CON_GAT_GATE_CLKCMU_HSI_MMC_CARD, CLK_CON_GAT_GATE_CLKCMU_HSI_USB20DRD, @@ -216,6 +222,9 @@ PNAME(mout_core_mmc_embd_p) =3D { "oscclk", "dout_share= d0_div2", "oscclk", "oscclk" }; PNAME(mout_core_sss_p) =3D { "dout_shared0_div3", "dout_shared1_div3", "dout_shared0_div4", "dout_shared1_div4" }; +/* List of parent clocks for Muxes in CMU_TOP: for CMU_G3D */ +PNAME(mout_g3d_switch_p) =3D { "dout_shared0_div2", "dout_shared1_div2", + "dout_shared0_div3", "dout_shared1_div3" }; /* List of parent clocks for Muxes in CMU_TOP: for CMU_HSI */ PNAME(mout_hsi_bus_p) =3D { "dout_shared0_div2", "dout_shared1_div2" }; PNAME(mout_hsi_mmc_card_p) =3D { "oscclk", "dout_shared0_div2", @@ -283,6 +292,10 @@ static const struct samsung_mux_clock top_mux_clks[] _= _initconst =3D { MUX(CLK_MOUT_DPU, "mout_dpu", mout_dpu_p, CLK_CON_MUX_MUX_CLKCMU_DPU, 0, 2), =20 + /* G3D */ + MUX(CLK_MOUT_G3D_SWITCH, "mout_g3d_switch", mout_g3d_switch_p, + CLK_CON_MUX_MUX_CLKCMU_G3D_SWITCH, 0, 2), + /* HSI */ MUX(CLK_MOUT_HSI_BUS, "mout_hsi_bus", mout_hsi_bus_p, CLK_CON_MUX_MUX_CLKCMU_HSI_BUS, 0, 1), @@ -357,6 +370,10 @@ static const struct samsung_div_clock top_div_clks[] _= _initconst =3D { DIV(CLK_DOUT_DPU, "dout_dpu", "gout_dpu", CLK_CON_DIV_CLKCMU_DPU, 0, 4), =20 + /* G3D */ + DIV(CLK_DOUT_G3D_SWITCH, "dout_g3d_switch", "gout_g3d_switch", + CLK_CON_DIV_CLKCMU_G3D_SWITCH, 0, 3), + /* HSI */ DIV(CLK_DOUT_HSI_BUS, "dout_hsi_bus", "gout_hsi_bus", CLK_CON_DIV_CLKCMU_HSI_BUS, 0, 4), @@ -417,6 +434,10 @@ static const struct samsung_gate_clock top_gate_clks[]= __initconst =3D { GATE(CLK_GOUT_DPU, "gout_dpu", "mout_dpu", CLK_CON_GAT_GATE_CLKCMU_DPU, 21, 0, 0), =20 + /* G3D */ + GATE(CLK_GOUT_G3D_SWITCH, "gout_g3d_switch", "mout_g3d_switch", + CLK_CON_GAT_GATE_CLKCMU_G3D_SWITCH, 21, 0, 0), + /* HSI */ GATE(CLK_GOUT_HSI_BUS, "gout_hsi_bus", "mout_hsi_bus", CLK_CON_GAT_GATE_CLKCMU_HSI_BUS, 21, 0, 0), @@ -992,6 +1013,102 @@ static const struct samsung_cmu_info cmgp_cmu_info _= _initconst =3D { .clk_name =3D "gout_clkcmu_cmgp_bus", }; =20 +/* ---- CMU_G3D ----------------------------------------------------------= --- */ + +/* Register Offset definitions for CMU_G3D (0x11400000) */ +#define PLL_LOCKTIME_PLL_G3D 0x0000 +#define PLL_CON0_PLL_G3D 0x0100 +#define PLL_CON3_PLL_G3D 0x010c +#define PLL_CON0_MUX_CLKCMU_G3D_SWITCH_USER 0x0600 +#define CLK_CON_MUX_MUX_CLK_G3D_BUSD 0x1000 +#define CLK_CON_DIV_DIV_CLK_G3D_BUSP 0x1804 +#define CLK_CON_GAT_CLK_G3D_CMU_G3D_PCLK 0x2000 +#define CLK_CON_GAT_CLK_G3D_GPU_CLK 0x2004 +#define CLK_CON_GAT_GOUT_G3D_TZPC_PCLK 0x200c +#define CLK_CON_GAT_GOUT_G3D_GRAY2BIN_CLK 0x2010 +#define CLK_CON_GAT_GOUT_G3D_BUSD_CLK 0x2024 +#define CLK_CON_GAT_GOUT_G3D_BUSP_CLK 0x2028 +#define CLK_CON_GAT_GOUT_G3D_SYSREG_PCLK 0x202c + +static const unsigned long g3d_clk_regs[] __initconst =3D { + PLL_LOCKTIME_PLL_G3D, + PLL_CON0_PLL_G3D, + PLL_CON3_PLL_G3D, + PLL_CON0_MUX_CLKCMU_G3D_SWITCH_USER, + CLK_CON_MUX_MUX_CLK_G3D_BUSD, + CLK_CON_DIV_DIV_CLK_G3D_BUSP, + CLK_CON_GAT_CLK_G3D_CMU_G3D_PCLK, + CLK_CON_GAT_CLK_G3D_GPU_CLK, + CLK_CON_GAT_GOUT_G3D_TZPC_PCLK, + CLK_CON_GAT_GOUT_G3D_GRAY2BIN_CLK, + CLK_CON_GAT_GOUT_G3D_BUSD_CLK, + CLK_CON_GAT_GOUT_G3D_BUSP_CLK, + CLK_CON_GAT_GOUT_G3D_SYSREG_PCLK, +}; + +/* List of parent clocks for Muxes in CMU_G3D */ +PNAME(mout_g3d_pll_p) =3D { "oscclk", "fout_g3d_pll" }; +PNAME(mout_g3d_switch_user_p) =3D { "oscclk", "dout_g3d_switch" }; +PNAME(mout_g3d_busd_p) =3D { "mout_g3d_pll", "mout_g3d_switch_user" }; + +/* + * Do not provide PLL table to PLL_G3D, as MANUAL_PLL_CTRL bit is not set + * for that PLL by default, so set_rate operation would fail. + */ +static const struct samsung_pll_clock g3d_pll_clks[] __initconst =3D { + PLL(pll_0818x, CLK_FOUT_G3D_PLL, "fout_g3d_pll", "oscclk", + PLL_LOCKTIME_PLL_G3D, PLL_CON3_PLL_G3D, NULL), +}; + +static const struct samsung_mux_clock g3d_mux_clks[] __initconst =3D { + MUX(CLK_MOUT_G3D_PLL, "mout_g3d_pll", mout_g3d_pll_p, + PLL_CON0_PLL_G3D, 4, 1), + MUX(CLK_MOUT_G3D_SWITCH_USER, "mout_g3d_switch_user", + mout_g3d_switch_user_p, + PLL_CON0_MUX_CLKCMU_G3D_SWITCH_USER, 4, 1), + MUX(CLK_MOUT_G3D_BUSD, "mout_g3d_busd", mout_g3d_busd_p, + CLK_CON_MUX_MUX_CLK_G3D_BUSD, 0, 1), +}; + +static const struct samsung_div_clock g3d_div_clks[] __initconst =3D { + DIV(CLK_DOUT_G3D_BUSP, "dout_g3d_busp", "mout_g3d_busd", + CLK_CON_DIV_DIV_CLK_G3D_BUSP, 0, 3), +}; + +static const struct samsung_gate_clock g3d_gate_clks[] __initconst =3D { + GATE(CLK_GOUT_G3D_CMU_G3D_PCLK, "gout_g3d_cmu_g3d_pclk", + "dout_g3d_busp", + CLK_CON_GAT_CLK_G3D_CMU_G3D_PCLK, 21, CLK_IGNORE_UNUSED, 0), + GATE(CLK_GOUT_G3D_GPU_CLK, "gout_g3d_gpu_clk", "mout_g3d_busd", + CLK_CON_GAT_CLK_G3D_GPU_CLK, 21, 0, 0), + GATE(CLK_GOUT_G3D_TZPC_PCLK, "gout_g3d_tzpc_pclk", "dout_g3d_busp", + CLK_CON_GAT_GOUT_G3D_TZPC_PCLK, 21, 0, 0), + GATE(CLK_GOUT_G3D_GRAY2BIN_CLK, "gout_g3d_gray2bin_clk", + "mout_g3d_busd", + CLK_CON_GAT_GOUT_G3D_GRAY2BIN_CLK, 21, 0, 0), + GATE(CLK_GOUT_G3D_BUSD_CLK, "gout_g3d_busd_clk", "mout_g3d_busd", + CLK_CON_GAT_GOUT_G3D_BUSD_CLK, 21, 0, 0), + GATE(CLK_GOUT_G3D_BUSP_CLK, "gout_g3d_busp_clk", "dout_g3d_busp", + CLK_CON_GAT_GOUT_G3D_BUSP_CLK, 21, 0, 0), + GATE(CLK_GOUT_G3D_SYSREG_PCLK, "gout_g3d_sysreg_pclk", "dout_g3d_busp", + CLK_CON_GAT_GOUT_G3D_SYSREG_PCLK, 21, 0, 0), +}; + +static const struct samsung_cmu_info g3d_cmu_info __initconst =3D { + .pll_clks =3D g3d_pll_clks, + .nr_pll_clks =3D ARRAY_SIZE(g3d_pll_clks), + .mux_clks =3D g3d_mux_clks, + .nr_mux_clks =3D ARRAY_SIZE(g3d_mux_clks), + .div_clks =3D g3d_div_clks, + .nr_div_clks =3D ARRAY_SIZE(g3d_div_clks), + .gate_clks =3D g3d_gate_clks, + .nr_gate_clks =3D ARRAY_SIZE(g3d_gate_clks), + .nr_clk_ids =3D G3D_NR_CLK, + .clk_regs =3D g3d_clk_regs, + .nr_clk_regs =3D ARRAY_SIZE(g3d_clk_regs), + .clk_name =3D "dout_g3d_switch", +}; + /* ---- CMU_HSI ----------------------------------------------------------= --- */ =20 /* Register Offset definitions for CMU_HSI (0x13400000) */ @@ -1700,6 +1817,9 @@ static const struct of_device_id exynos850_cmu_of_mat= ch[] =3D { }, { .compatible =3D "samsung,exynos850-cmu-cmgp", .data =3D &cmgp_cmu_info, + }, { + .compatible =3D "samsung,exynos850-cmu-g3d", + .data =3D &g3d_cmu_info, }, { .compatible =3D "samsung,exynos850-cmu-hsi", .data =3D &hsi_cmu_info, --=20 2.39.1 From nobody Thu Sep 11 00:12:34 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 24AF0C64ED8 for ; Thu, 23 Feb 2023 04:23:34 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232814AbjBWEXc (ORCPT ); Wed, 22 Feb 2023 23:23:32 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:35384 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233253AbjBWEWn (ORCPT ); Wed, 22 Feb 2023 23:22:43 -0500 Received: from mail-oi1-x232.google.com (mail-oi1-x232.google.com [IPv6:2607:f8b0:4864:20::232]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 618B7498A8 for ; Wed, 22 Feb 2023 20:21:34 -0800 (PST) Received: by mail-oi1-x232.google.com with SMTP id bg11so10389508oib.5 for ; Wed, 22 Feb 2023 20:21:34 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=qk+E8cQ29D74eb0oXLgwbQz1y9cU//DH5Xrbr3L15Lc=; b=oYgLn0k/fyNBXXm+U0YhuKAt2fJVD3YkOwTzTrx1UQgBe9KUfTyU/aTxgc7MvpNvIi NOAQXYMn+979TvN0M2KQIPVVkZIqSioQr4E1bI5l0EPJHKgu1us7JZagK/8xEbfhH3S0 QX5Jn/DQGGKLNyr2VWWQQOsaEmM3lYtGKaD7lvN2LSVnEmhAYcVZEyzKLa0tvMKtuIWs jpTArOMtyg7/VM/xHhQA+GgPw3fPltA3vUmUJ4sc6/Hdf6LfFcUjJSNxgRgKmC8vOiG8 PR0xqNua62eYbw2wgaXBYG6ADgN2cmCdc+gYYSKp2JnX8StrMZ78sJ46Hhzg4G2RXE8O BfwA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=qk+E8cQ29D74eb0oXLgwbQz1y9cU//DH5Xrbr3L15Lc=; b=AwdmgkMpGCenqy3U6iIauv7gpoj3jY0e19xBIg/jkYRIksA8Jkr/MmF70SiF1qHNbw LOji8w7Y5li5DJHUUqKhaVNqTeCrc/T2Hw+IIjhuNwhXlthgtj0dNRZv3jjP54wwwWNo ArXKOYQH10RhmF7CwYYTLGtXOVUQBplugncDPSGY3eI/M1fY8ZT3vlkegqHtCmfAJ5tH UO48BkHHPidr2de49wHYzYEgUms9B6SkOpjrGwIiHLijFAKEY7sU47kkygnJJ3BpElaW 58/AMG08BdfkzYUkvDUVgQzIcmwSV8YHuVKlxL9a5ZOPvzVVadaEk/47PWTtLDPnzuPZ K2Gg== X-Gm-Message-State: AO0yUKXiDlcaLv1FYOUC7nEcGvhsmEFlo58AwoxBybUdOgMiOska821t pXHzpV+EF92CFzrqrPUaHZrtGA== X-Google-Smtp-Source: AK7set9j6lalehujVDNI/Sm/zk3EK4VMFfdLYd4mugm9iTkRx4gajq5daN8dVFJPHzfqWiKXiHhceA== X-Received: by 2002:a05:6808:105:b0:37d:5cee:6484 with SMTP id b5-20020a056808010500b0037d5cee6484mr1159385oie.46.1677126084114; Wed, 22 Feb 2023 20:21:24 -0800 (PST) Received: from localhost ([136.49.140.41]) by smtp.gmail.com with ESMTPSA id q127-20020acac085000000b0037d813cd612sm1988674oif.43.2023.02.22.20.21.23 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 22 Feb 2023 20:21:23 -0800 (PST) From: Sam Protsenko To: Krzysztof Kozlowski , Chanwoo Choi , Sylwester Nawrocki , Rob Herring Cc: David Virag , Chanho Park , Alim Akhtar , Sumit Semwal , Tomasz Figa , Michael Turquette , Stephen Boyd , linux-samsung-soc@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 5/6] clk: samsung: exynos850: Add AUD and HSI main gate clocks Date: Wed, 22 Feb 2023 22:21:32 -0600 Message-Id: <20230223042133.26551-6-semen.protsenko@linaro.org> X-Mailer: git-send-email 2.39.1 In-Reply-To: <20230223042133.26551-1-semen.protsenko@linaro.org> References: <20230223042133.26551-1-semen.protsenko@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add main gate clocks for controlling AUD and HSI CMUs: - gout_aud_cmu_aud_pclk - gout_hsi_cmu_hsi_pclk Those clocks were marked as CLK_IGNORE_UNUSED, as system hangs on boot otherwise. While at it, add missing PPMU (Performance Profiling Monitor Unit) clocks for CMU_HSI. Signed-off-by: Sam Protsenko Reviewed-by: Chanho Park --- Changes in v2: - Rebased on top of most recent soc/for-next tree - Added comment for CLK_IGNORE_UNUSED flag usage drivers/clk/samsung/clk-exynos850.c | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/drivers/clk/samsung/clk-exynos850.c b/drivers/clk/samsung/clk-= exynos850.c index 601fe05e8555..6ab5fa8c2ef3 100644 --- a/drivers/clk/samsung/clk-exynos850.c +++ b/drivers/clk/samsung/clk-exynos850.c @@ -674,6 +674,7 @@ static const struct samsung_cmu_info apm_cmu_info __ini= tconst =3D { #define CLK_CON_GAT_GOUT_AUD_ABOX_BCLK_UAIF4 0x2014 #define CLK_CON_GAT_GOUT_AUD_ABOX_BCLK_UAIF5 0x2018 #define CLK_CON_GAT_GOUT_AUD_ABOX_BCLK_UAIF6 0x201c +#define CLK_CON_GAT_CLK_AUD_CMU_AUD_PCLK 0x2020 #define CLK_CON_GAT_GOUT_AUD_ABOX_ACLK 0x2048 #define CLK_CON_GAT_GOUT_AUD_ABOX_BCLK_SPDY 0x204c #define CLK_CON_GAT_GOUT_AUD_ABOX_CCLK_ASB 0x2050 @@ -729,6 +730,7 @@ static const unsigned long aud_clk_regs[] __initconst = =3D { CLK_CON_GAT_GOUT_AUD_ABOX_BCLK_UAIF4, CLK_CON_GAT_GOUT_AUD_ABOX_BCLK_UAIF5, CLK_CON_GAT_GOUT_AUD_ABOX_BCLK_UAIF6, + CLK_CON_GAT_CLK_AUD_CMU_AUD_PCLK, CLK_CON_GAT_GOUT_AUD_ABOX_ACLK, CLK_CON_GAT_GOUT_AUD_ABOX_BCLK_SPDY, CLK_CON_GAT_GOUT_AUD_ABOX_CCLK_ASB, @@ -848,6 +850,9 @@ static const struct samsung_div_clock aud_div_clks[] __= initconst =3D { }; =20 static const struct samsung_gate_clock aud_gate_clks[] __initconst =3D { + GATE(CLK_GOUT_AUD_CMU_AUD_PCLK, "gout_aud_cmu_aud_pclk", + "dout_aud_busd", + CLK_CON_GAT_CLK_AUD_CMU_AUD_PCLK, 21, CLK_IGNORE_UNUSED, 0), GATE(CLK_GOUT_AUD_CA32_CCLK, "gout_aud_ca32_cclk", "mout_aud_cpu_hch", CLK_CON_GAT_GOUT_AUD_ABOX_CCLK_CA32, 21, 0, 0), GATE(CLK_GOUT_AUD_ASB_CCLK, "gout_aud_asb_cclk", "dout_aud_cpu_aclk", @@ -1116,12 +1121,15 @@ static const struct samsung_cmu_info g3d_cmu_info _= _initconst =3D { #define PLL_CON0_MUX_CLKCMU_HSI_MMC_CARD_USER 0x0610 #define PLL_CON0_MUX_CLKCMU_HSI_USB20DRD_USER 0x0620 #define CLK_CON_MUX_MUX_CLK_HSI_RTC 0x1000 +#define CLK_CON_GAT_CLK_HSI_CMU_HSI_PCLK 0x2000 #define CLK_CON_GAT_HSI_USB20DRD_TOP_I_RTC_CLK__ALV 0x2008 #define CLK_CON_GAT_HSI_USB20DRD_TOP_I_REF_CLK_50 0x200c #define CLK_CON_GAT_HSI_USB20DRD_TOP_I_PHY_REFCLK_26 0x2010 #define CLK_CON_GAT_GOUT_HSI_GPIO_HSI_PCLK 0x2018 #define CLK_CON_GAT_GOUT_HSI_MMC_CARD_I_ACLK 0x2024 #define CLK_CON_GAT_GOUT_HSI_MMC_CARD_SDCLKIN 0x2028 +#define CLK_CON_GAT_GOUT_HSI_PPMU_ACLK 0x202c +#define CLK_CON_GAT_GOUT_HSI_PPMU_PCLK 0x2030 #define CLK_CON_GAT_GOUT_HSI_SYSREG_HSI_PCLK 0x2038 #define CLK_CON_GAT_GOUT_HSI_USB20DRD_TOP_ACLK_PHYCTRL_20 0x203c #define CLK_CON_GAT_GOUT_HSI_USB20DRD_TOP_BUS_CLK_EARLY 0x2040 @@ -1131,12 +1139,15 @@ static const unsigned long hsi_clk_regs[] __initcon= st =3D { PLL_CON0_MUX_CLKCMU_HSI_MMC_CARD_USER, PLL_CON0_MUX_CLKCMU_HSI_USB20DRD_USER, CLK_CON_MUX_MUX_CLK_HSI_RTC, + CLK_CON_GAT_CLK_HSI_CMU_HSI_PCLK, CLK_CON_GAT_HSI_USB20DRD_TOP_I_RTC_CLK__ALV, CLK_CON_GAT_HSI_USB20DRD_TOP_I_REF_CLK_50, CLK_CON_GAT_HSI_USB20DRD_TOP_I_PHY_REFCLK_26, CLK_CON_GAT_GOUT_HSI_GPIO_HSI_PCLK, CLK_CON_GAT_GOUT_HSI_MMC_CARD_I_ACLK, CLK_CON_GAT_GOUT_HSI_MMC_CARD_SDCLKIN, + CLK_CON_GAT_GOUT_HSI_PPMU_ACLK, + CLK_CON_GAT_GOUT_HSI_PPMU_PCLK, CLK_CON_GAT_GOUT_HSI_SYSREG_HSI_PCLK, CLK_CON_GAT_GOUT_HSI_USB20DRD_TOP_ACLK_PHYCTRL_20, CLK_CON_GAT_GOUT_HSI_USB20DRD_TOP_BUS_CLK_EARLY, @@ -1162,6 +1173,10 @@ static const struct samsung_mux_clock hsi_mux_clks[]= __initconst =3D { }; =20 static const struct samsung_gate_clock hsi_gate_clks[] __initconst =3D { + /* TODO: Should be enabled in corresponding driver */ + GATE(CLK_GOUT_HSI_CMU_HSI_PCLK, "gout_hsi_cmu_hsi_pclk", + "mout_hsi_bus_user", + CLK_CON_GAT_CLK_HSI_CMU_HSI_PCLK, 21, CLK_IGNORE_UNUSED, 0), GATE(CLK_GOUT_USB_RTC_CLK, "gout_usb_rtc", "mout_hsi_rtc", CLK_CON_GAT_HSI_USB20DRD_TOP_I_RTC_CLK__ALV, 21, 0, 0), GATE(CLK_GOUT_USB_REF_CLK, "gout_usb_ref", "mout_hsi_usb20drd_user", @@ -1176,6 +1191,10 @@ static const struct samsung_gate_clock hsi_gate_clks= [] __initconst =3D { GATE(CLK_GOUT_MMC_CARD_SDCLKIN, "gout_mmc_card_sdclkin", "mout_hsi_mmc_card_user", CLK_CON_GAT_GOUT_HSI_MMC_CARD_SDCLKIN, 21, CLK_SET_RATE_PARENT, 0), + GATE(CLK_GOUT_HSI_PPMU_ACLK, "gout_hsi_ppmu_aclk", "mout_hsi_bus_user", + CLK_CON_GAT_GOUT_HSI_PPMU_ACLK, 21, 0, 0), + GATE(CLK_GOUT_HSI_PPMU_PCLK, "gout_hsi_ppmu_pclk", "mout_hsi_bus_user", + CLK_CON_GAT_GOUT_HSI_PPMU_PCLK, 21, 0, 0), GATE(CLK_GOUT_SYSREG_HSI_PCLK, "gout_sysreg_hsi_pclk", "mout_hsi_bus_user", CLK_CON_GAT_GOUT_HSI_SYSREG_HSI_PCLK, 21, 0, 0), --=20 2.39.1 From nobody Thu Sep 11 00:12:34 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 550BAC636D7 for ; Thu, 23 Feb 2023 04:23:39 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233376AbjBWEXh (ORCPT ); Wed, 22 Feb 2023 23:23:37 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:37180 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233256AbjBWEWo (ORCPT ); Wed, 22 Feb 2023 23:22:44 -0500 Received: from mail-oa1-x34.google.com (mail-oa1-x34.google.com [IPv6:2001:4860:4864:20::34]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 036E548E2E for ; Wed, 22 Feb 2023 20:21:37 -0800 (PST) Received: by mail-oa1-x34.google.com with SMTP id 586e51a60fabf-17227cba608so10323240fac.3 for ; Wed, 22 Feb 2023 20:21:36 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=TGmInqCeyC0bjSGfaYON7cbBzHggVKyExnI0LnVwOZk=; b=hNnuU66qswnxXZ0Idb5rbGFkzOFnNXYz5+rS69cLgSK2qhJnyOxCAb+a/K1ng7Ery+ Oiu7dlI07t0q88hPYgDmmCeSi8kWHhnKuxbnNGL+PfJKxIq7ZUREcEFotPM1VcW16BBQ hJwbTgqdciscJUSHy3C4XS02LrgFopp3ZWV/LkqHleC1tfZ8XaWAaMu8C5v+0lpxJCUz ea51+3BDeU2E+s2O/BSvcZ1xFqRIAcT0xI4H48+h+3oRFt3xlaLuk2FGpgRGm+qI2CD3 hYtNsp2YezZy9AGbfzSD7OnAAgcjdmZcQoG/73mtSjODuhXxLwWlCIULx3ciz80S4wyR hRRw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=TGmInqCeyC0bjSGfaYON7cbBzHggVKyExnI0LnVwOZk=; b=fWzAyv02MXS9PYYO0LBEZPM0kTO5xWdGs0+JOjuzrpWOCFo1G1n+sD7f+JaTQnoNkq azEFw+CR6d9x3Y6CBmtDpCxVLDCVIAo6E26g1of/yi0ZKC57jR6UQKNAbAlQNqhx+1S+ 3S67xTuA2nhuLVYj9IhnNEGEbSg+l8RCSP4PDFGYzGfSIoYi2Db+44NaycSlKHW4uXrD tqC4Mq+wn+hAEDAFUVG3WgY7vQbSQ7G5wtOrXWTE3OMtg20taLKADe7ZKNftlP0ipi+/ CQD/cqIZn85Uvv/klFs62Y9eYCx7ZVvJQIIwDdBYx2F+KytNtdFAQEVl2d9TjUE17sIt FIYQ== X-Gm-Message-State: AO0yUKWBD5XP+iy+SYnAwc4vGASwLP8GSnzlcH2b1TgcZlAzVkTIkoOP soHsENfrzG4uKi6+cKtW95S6aQ== X-Google-Smtp-Source: AK7set+Q+laDbcJvzvJZwI/eLi1W2mIUWl6/M4aafhL5u6VMJfb7rqnt2jDqGrEPu0Bqol5tlCb5pw== X-Received: by 2002:a05:6870:64ab:b0:172:5036:1dcc with SMTP id cz43-20020a05687064ab00b0017250361dccmr2606154oab.5.1677126085205; Wed, 22 Feb 2023 20:21:25 -0800 (PST) Received: from localhost ([136.49.140.41]) by smtp.gmail.com with ESMTPSA id w130-20020aca6288000000b0037832f60518sm1154464oib.14.2023.02.22.20.21.24 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 22 Feb 2023 20:21:24 -0800 (PST) From: Sam Protsenko To: Krzysztof Kozlowski , Chanwoo Choi , Sylwester Nawrocki , Rob Herring Cc: David Virag , Chanho Park , Alim Akhtar , Sumit Semwal , Tomasz Figa , Michael Turquette , Stephen Boyd , linux-samsung-soc@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 6/6] arm64: dts: exynos: Add CMU_G3D node for Exynos850 SoC Date: Wed, 22 Feb 2023 22:21:33 -0600 Message-Id: <20230223042133.26551-7-semen.protsenko@linaro.org> X-Mailer: git-send-email 2.39.1 In-Reply-To: <20230223042133.26551-1-semen.protsenko@linaro.org> References: <20230223042133.26551-1-semen.protsenko@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add missing G3D clock domain to Exynos850 SoC device tree. Reviewed-by: Chanho Park Signed-off-by: Sam Protsenko --- Changes in v2: - Rebased on top of most recent soc/for-next tree - Added Chanho Park Reviewed-by tag arch/arm64/boot/dts/exynos/exynos850.dtsi | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/arch/arm64/boot/dts/exynos/exynos850.dtsi b/arch/arm64/boot/dt= s/exynos/exynos850.dtsi index a38fe5129937..d67e98120313 100644 --- a/arch/arm64/boot/dts/exynos/exynos850.dtsi +++ b/arch/arm64/boot/dts/exynos/exynos850.dtsi @@ -245,6 +245,15 @@ cmu_peri: clock-controller@10030000 { "dout_peri_uart", "dout_peri_ip"; }; =20 + cmu_g3d: clock-controller@11400000 { + compatible =3D "samsung,exynos850-cmu-g3d"; + reg =3D <0x11400000 0x8000>; + #clock-cells =3D <1>; + + clocks =3D <&oscclk>, <&cmu_top CLK_DOUT_G3D_SWITCH>; + clock-names =3D "oscclk", "dout_g3d_switch"; + }; + cmu_apm: clock-controller@11800000 { compatible =3D "samsung,exynos850-cmu-apm"; reg =3D <0x11800000 0x8000>; --=20 2.39.1