From nobody Thu Sep 11 00:19:48 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id DB44CC64EC7 for ; Thu, 23 Feb 2023 02:00:13 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233147AbjBWCAL convert rfc822-to-8bit (ORCPT ); Wed, 22 Feb 2023 21:00:11 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:33632 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231558AbjBWCAI (ORCPT ); Wed, 22 Feb 2023 21:00:08 -0500 Received: from fd01.gateway.ufhost.com (fd01.gateway.ufhost.com [61.152.239.71]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 038AB1717F; Wed, 22 Feb 2023 18:00:02 -0800 (PST) Received: from EXMBX166.cuchost.com (unknown [175.102.18.54]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client CN "EXMBX166", Issuer "EXMBX166" (not verified)) by fd01.gateway.ufhost.com (Postfix) with ESMTP id 949A624E046; Thu, 23 Feb 2023 09:59:55 +0800 (CST) Received: from EXMBX162.cuchost.com (172.16.6.72) by EXMBX166.cuchost.com (172.16.6.76) with Microsoft SMTP Server (TLS) id 15.0.1497.42; Thu, 23 Feb 2023 09:59:55 +0800 Received: from ubuntu.localdomain (113.72.147.165) by EXMBX162.cuchost.com (172.16.6.72) with Microsoft SMTP Server (TLS) id 15.0.1497.42; Thu, 23 Feb 2023 09:59:54 +0800 From: Changhuang Liang To: Vinod Koul , Kishon Vijay Abraham I , Rob Herring , Krzysztof Kozlowski , Emil Renner Berthing , Conor Dooley , Paul Walmsley , Palmer Dabbelt , Albert Ou , Philipp Zabel CC: Jack Zhu , Changhuang Liang , , , , Subject: [PATCH v2 1/3] dt-bindings: phy: Add starfive,jh7110-dphy-rx Date: Wed, 22 Feb 2023 17:59:50 -0800 Message-ID: <20230223015952.201841-2-changhuang.liang@starfivetech.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230223015952.201841-1-changhuang.liang@starfivetech.com> References: <20230223015952.201841-1-changhuang.liang@starfivetech.com> MIME-Version: 1.0 X-Originating-IP: [113.72.147.165] X-ClientProxiedBy: EXCAS062.cuchost.com (172.16.6.22) To EXMBX162.cuchost.com (172.16.6.72) X-YovoleRuleAgent: yovoleflag Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Starfive SoCs like the jh7110 use a MIPI D-PHY RX controller based on a M31 IP. Add a binding for it. Signed-off-by: Changhuang Liang --- .../bindings/phy/starfive,jh7110-dphy-rx.yaml | 74 +++++++++++++++++++ 1 file changed, 74 insertions(+) create mode 100644 Documentation/devicetree/bindings/phy/starfive,jh7110-d= phy-rx.yaml diff --git a/Documentation/devicetree/bindings/phy/starfive,jh7110-dphy-rx.= yaml b/Documentation/devicetree/bindings/phy/starfive,jh7110-dphy-rx.yaml new file mode 100644 index 000000000000..a67ca57a6f21 --- /dev/null +++ b/Documentation/devicetree/bindings/phy/starfive,jh7110-dphy-rx.yaml @@ -0,0 +1,74 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/phy/starfive,jh7110-dphy-rx.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Starfive SoC MIPI D-PHY Rx Controller + +maintainers: + - Jack Zhu + - Changhuang Liang + +description: + The Starfive SoC uses the MIPI CSI D-PHY based on M31 IP to transfer + CSI camera data. + +properties: + compatible: + const: starfive,jh7110-dphy-rx + + reg: + maxItems: 1 + + clocks: + maxItems: 3 + + clock-names: + items: + - const: cfg + - const: ref + - const: tx + + resets: + items: + - description: DPHY_HW reset + - description: DPHY_B09_ALWAYS_ON reset + + starfive,aon-syscon: + $ref: /schemas/types.yaml#/definitions/phandle-array + items: + items: + - description: phandle of AON SYSCON + - description: register offset + description: The power of dphy rx is configured by AON SYSCON + in this property. + + "#phy-cells": + const: 0 + +required: + - compatible + - reg + - clocks + - clock-names + - resets + - starfive,aon-syscon + - "#phy-cells" + +additionalProperties: false + +examples: + - | + phy@19820000 { + compatible =3D "starfive,jh7110-dphy-rx"; + reg =3D <0x19820000 0x10000>; + clocks =3D <&ispcrg 3>, + <&ispcrg 4>, + <&ispcrg 5>; + clock-names =3D "cfg", "ref", "tx"; + resets =3D <&ispcrg 2>, + <&ispcrg 3>; + starfive,aon-syscon =3D <&aon_syscon 0x00>; + #phy-cells =3D <0>; + }; --=20 2.25.1 From nobody Thu Sep 11 00:19:48 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id DB350C636D6 for ; Thu, 23 Feb 2023 02:00:18 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233156AbjBWCAR convert rfc822-to-8bit (ORCPT ); Wed, 22 Feb 2023 21:00:17 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:33658 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233132AbjBWCAJ (ORCPT ); Wed, 22 Feb 2023 21:00:09 -0500 Received: from ex01.ufhost.com (ex01.ufhost.com [61.152.239.75]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id F1BEE1C327; Wed, 22 Feb 2023 18:00:03 -0800 (PST) Received: from EXMBX165.cuchost.com (unknown [175.102.18.54]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client CN "EXMBX165", Issuer "EXMBX165" (not verified)) by ex01.ufhost.com (Postfix) with ESMTP id A759C24E248; Thu, 23 Feb 2023 09:59:56 +0800 (CST) Received: from EXMBX162.cuchost.com (172.16.6.72) by EXMBX165.cuchost.com (172.16.6.75) with Microsoft SMTP Server (TLS) id 15.0.1497.42; Thu, 23 Feb 2023 09:59:56 +0800 Received: from ubuntu.localdomain (113.72.147.165) by EXMBX162.cuchost.com (172.16.6.72) with Microsoft SMTP Server (TLS) id 15.0.1497.42; Thu, 23 Feb 2023 09:59:55 +0800 From: Changhuang Liang To: Vinod Koul , Kishon Vijay Abraham I , Rob Herring , Krzysztof Kozlowski , Emil Renner Berthing , Conor Dooley , Paul Walmsley , Palmer Dabbelt , Albert Ou , Philipp Zabel CC: Jack Zhu , Changhuang Liang , , , , Subject: [PATCH v2 2/3] phy: starfive: Add mipi dphy rx support Date: Wed, 22 Feb 2023 17:59:51 -0800 Message-ID: <20230223015952.201841-3-changhuang.liang@starfivetech.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230223015952.201841-1-changhuang.liang@starfivetech.com> References: <20230223015952.201841-1-changhuang.liang@starfivetech.com> MIME-Version: 1.0 X-Originating-IP: [113.72.147.165] X-ClientProxiedBy: EXCAS062.cuchost.com (172.16.6.22) To EXMBX162.cuchost.com (172.16.6.72) X-YovoleRuleAgent: yovoleflag Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add mipi dphy rx support for the Starfive JH7110 SoC. It is used to transfer CSI camera data. Signed-off-by: Changhuang Liang --- MAINTAINERS | 7 + drivers/phy/Kconfig | 1 + drivers/phy/Makefile | 1 + drivers/phy/starfive/Kconfig | 13 + drivers/phy/starfive/Makefile | 2 + drivers/phy/starfive/phy-starfive-dphy-rx.c | 362 ++++++++++++++++++++ 6 files changed, 386 insertions(+) create mode 100644 drivers/phy/starfive/Kconfig create mode 100644 drivers/phy/starfive/Makefile create mode 100644 drivers/phy/starfive/phy-starfive-dphy-rx.c diff --git a/MAINTAINERS b/MAINTAINERS index 2e70c9f21989..8ddef8669efb 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -19952,6 +19952,13 @@ F: Documentation/devicetree/bindings/power/starfiv= e* F: drivers/soc/starfive/jh71xx_pmu.c F: include/dt-bindings/power/starfive,jh7110-pmu.h =20 +STARFIVE JH7110 DPHY RX DRIVER +M: Jack Zhu +M: Changhuang Liang +S: Supported +F: Documentation/devicetree/bindings/phy/starfive,jh7110-dphy-rx.yaml +F: drivers/phy/starfive/phy-starfive-dphy-rx.c + STATIC BRANCH/CALL M: Peter Zijlstra M: Josh Poimboeuf diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig index 7bd00a11d074..c4b2a86e2afb 100644 --- a/drivers/phy/Kconfig +++ b/drivers/phy/Kconfig @@ -91,6 +91,7 @@ source "drivers/phy/rockchip/Kconfig" source "drivers/phy/samsung/Kconfig" source "drivers/phy/socionext/Kconfig" source "drivers/phy/st/Kconfig" +source "drivers/phy/starfive/Kconfig" source "drivers/phy/sunplus/Kconfig" source "drivers/phy/tegra/Kconfig" source "drivers/phy/ti/Kconfig" diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile index 54f312c10a40..fb3dc9de6111 100644 --- a/drivers/phy/Makefile +++ b/drivers/phy/Makefile @@ -31,6 +31,7 @@ obj-y +=3D allwinner/ \ samsung/ \ socionext/ \ st/ \ + starfive/ \ sunplus/ \ tegra/ \ ti/ \ diff --git a/drivers/phy/starfive/Kconfig b/drivers/phy/starfive/Kconfig new file mode 100644 index 000000000000..e449a662acf5 --- /dev/null +++ b/drivers/phy/starfive/Kconfig @@ -0,0 +1,13 @@ +# SPDX-License-Identifier: GPL-2.0-only +# +# Phy drivers for Starfive platforms +# + +config PHY_STARFIVE_DPHY_RX + tristate "Starfive D-PHY RX Support" + select GENERIC_PHY + select GENERIC_PHY_MIPI_DPHY + help + Choose this option if you have a Starfive D-PHY in your + system. If M is selected, the module will be called + phy-starfive-dphy-rx. diff --git a/drivers/phy/starfive/Makefile b/drivers/phy/starfive/Makefile new file mode 100644 index 000000000000..7ec576cb30ae --- /dev/null +++ b/drivers/phy/starfive/Makefile @@ -0,0 +1,2 @@ +# SPDX-License-Identifier: GPL-2.0 +obj-$(CONFIG_PHY_STARFIVE_DPHY_RX) +=3D phy-starfive-dphy-rx.o diff --git a/drivers/phy/starfive/phy-starfive-dphy-rx.c b/drivers/phy/star= five/phy-starfive-dphy-rx.c new file mode 100644 index 000000000000..2a7c5453f4ce --- /dev/null +++ b/drivers/phy/starfive/phy-starfive-dphy-rx.c @@ -0,0 +1,362 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * DPHY driver for the StarFive JH7110 SoC + * + * Copyright (C) 2023 StarFive Technology Co., Ltd. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define STF_DPHY_APBCFGSAIF__SYSCFG(x) (x) + +#define STF_DPHY_DA_CDPHY_R100_CTRL0_2D1C_EFUSE_EN BIT(6) +#define STF_DPHY_DA_CDPHY_R100_CTRL0_2D1C_EFUSE_IN GENMASK(12, 7) +#define STF_DPHY_DA_CDPHY_R100_CTRL1_2D1C_EFUSE_EN BIT(19) +#define STF_DPHY_DA_CDPHY_R100_CTRL1_2D1C_EFUSE_IN GENMASK(25, 20) + +#define STF_DPHY_DATA_BUS16_8 BIT(8) +#define STF_DPHY_DEBUG_MODE_SEL GENMASK(15, 9) + +#define STF_DPHY_ENABLE_CLK BIT(6) +#define STF_DPHY_ENABLE_CLK1 BIT(7) +#define STF_DPHY_ENABLE_LAN0 BIT(8) +#define STF_DPHY_ENABLE_LAN1 BIT(9) +#define STF_DPHY_ENABLE_LAN2 BIT(10) +#define STF_DPHY_ENABLE_LAN3 BIT(11) +#define STF_DPHY_GPI_EN GENMASK(17, 12) +#define STF_DPHY_HS_FREQ_CHANGE_CLK BIT(18) +#define STF_DPHY_HS_FREQ_CHANGE_CLK1 BIT(19) +#define STF_DPHY_LANE_SWAP_CLK GENMASK(22, 20) +#define STF_DPHY_LANE_SWAP_CLK1 GENMASK(25, 23) +#define STF_DPHY_LANE_SWAP_LAN0 GENMASK(28, 26) +#define STF_DPHY_LANE_SWAP_LAN1 GENMASK(31, 29) + +#define STF_DPHY_LANE_SWAP_LAN2 GENMASK(2, 0) +#define STF_DPHY_LANE_SWAP_LAN3 GENMASK(5, 3) +#define STF_DPHY_MP_TEST_EN BIT(6) +#define STF_DPHY_MP_TEST_MODE_SEL GENMASK(11, 7) +#define STF_DPHY_PLL_CLK_SEL GENMASK(21, 12) +#define STF_DPHY_PRECOUNTER_IN_CLK GENMASK(29, 22) + +#define STF_DPHY_PRECOUNTER_IN_CLK1 GENMASK(7, 0) +#define STF_DPHY_PRECOUNTER_IN_LAN0 GENMASK(15, 8) +#define STF_DPHY_PRECOUNTER_IN_LAN1 GENMASK(23, 16) +#define STF_DPHY_PRECOUNTER_IN_LAN2 GENMASK(31, 24) + +#define STF_DPHY_PRECOUNTER_IN_LAN3 GENMASK(7, 0) +#define STF_DPHY_RX_1C2C_SEL BIT(8) + +struct regval_t { + u32 addr; + u32 val; +}; + +struct stf_dphy { + struct device *dev; + void __iomem *regs; + struct clk *cfg_clk; + struct clk *ref_clk; + struct clk *tx_clk; + struct reset_control *rstc; + struct regulator *mipi_0p9; + struct phy *phy; + struct regmap *stf_aon_syscon; + unsigned int aon_gp_reg; +}; + +struct stf_dphy_info { + bool external_support; + int (*external_get)(struct stf_dphy *dphy); + void (*external_init)(struct stf_dphy *dphy); + void (*external_exit)(struct stf_dphy *dphy); +}; + +static const struct stf_dphy_info *stf_dphy_info; + +static const struct regval_t stf_dphy_init_list[] =3D { + { STF_DPHY_APBCFGSAIF__SYSCFG(4), 0x00000000 }, + { STF_DPHY_APBCFGSAIF__SYSCFG(8), 0x00000000 }, + { STF_DPHY_APBCFGSAIF__SYSCFG(12), 0x0000fff0 }, + { STF_DPHY_APBCFGSAIF__SYSCFG(16), 0x00000000 }, + { STF_DPHY_APBCFGSAIF__SYSCFG(20), 0x00000000 }, + { STF_DPHY_APBCFGSAIF__SYSCFG(24), 0x00000000 }, + { STF_DPHY_APBCFGSAIF__SYSCFG(28), 0x00000000 }, + { STF_DPHY_APBCFGSAIF__SYSCFG(32), 0x00000000 }, + { STF_DPHY_APBCFGSAIF__SYSCFG(36), 0x00000000 }, + { STF_DPHY_APBCFGSAIF__SYSCFG(40), 0x00000000 }, + { STF_DPHY_APBCFGSAIF__SYSCFG(40), 0x00000000 }, + { STF_DPHY_APBCFGSAIF__SYSCFG(48), 0x24000000 }, + { STF_DPHY_APBCFGSAIF__SYSCFG(52), 0x00000000 }, + { STF_DPHY_APBCFGSAIF__SYSCFG(56), 0x00000000 }, + { STF_DPHY_APBCFGSAIF__SYSCFG(60), 0x00000000 }, + { STF_DPHY_APBCFGSAIF__SYSCFG(64), 0x00000000 }, + { STF_DPHY_APBCFGSAIF__SYSCFG(68), 0x00000000 }, + { STF_DPHY_APBCFGSAIF__SYSCFG(72), 0x00000000 }, + { STF_DPHY_APBCFGSAIF__SYSCFG(76), 0x00000000 }, + { STF_DPHY_APBCFGSAIF__SYSCFG(80), 0x00000000 }, + { STF_DPHY_APBCFGSAIF__SYSCFG(84), 0x00000000 }, + { STF_DPHY_APBCFGSAIF__SYSCFG(88), 0x00000000 }, + { STF_DPHY_APBCFGSAIF__SYSCFG(92), 0x00000000 }, + { STF_DPHY_APBCFGSAIF__SYSCFG(96), 0x00000000 }, + { STF_DPHY_APBCFGSAIF__SYSCFG(100), 0x02000000 }, + { STF_DPHY_APBCFGSAIF__SYSCFG(104), 0x00000000 }, + { STF_DPHY_APBCFGSAIF__SYSCFG(108), 0x00000000 }, + { STF_DPHY_APBCFGSAIF__SYSCFG(112), 0x00000000 }, + { STF_DPHY_APBCFGSAIF__SYSCFG(116), 0x00000000 }, + { STF_DPHY_APBCFGSAIF__SYSCFG(120), 0x00000000 }, + { STF_DPHY_APBCFGSAIF__SYSCFG(124), 0x0000000c }, + { STF_DPHY_APBCFGSAIF__SYSCFG(128), 0x00000000 }, + { STF_DPHY_APBCFGSAIF__SYSCFG(132), 0xcc500000 }, + { STF_DPHY_APBCFGSAIF__SYSCFG(136), 0x000000cc }, + { STF_DPHY_APBCFGSAIF__SYSCFG(140), 0x00000000 }, + { STF_DPHY_APBCFGSAIF__SYSCFG(144), 0x00000000 }, +}; + +static int stf_dphy_configure(struct phy *phy, union phy_configure_opts *o= pts) +{ + struct stf_dphy *dphy =3D phy_get_drvdata(phy); + int map[6] =3D {4, 0, 1, 2, 3, 5}; + int i; + + for (i =3D 0; i < ARRAY_SIZE(stf_dphy_init_list); i++) + writel(stf_dphy_init_list[i].val, + dphy->regs + stf_dphy_init_list[i].addr); + + writel(FIELD_PREP(STF_DPHY_DA_CDPHY_R100_CTRL0_2D1C_EFUSE_EN, 1) | + FIELD_PREP(STF_DPHY_DA_CDPHY_R100_CTRL0_2D1C_EFUSE_IN, 0x1b) | + FIELD_PREP(STF_DPHY_DA_CDPHY_R100_CTRL1_2D1C_EFUSE_EN, 1) | + FIELD_PREP(STF_DPHY_DA_CDPHY_R100_CTRL1_2D1C_EFUSE_IN, 0x1b), + dphy->regs + STF_DPHY_APBCFGSAIF__SYSCFG(0)); + + writel(FIELD_PREP(STF_DPHY_DATA_BUS16_8, 0) | + FIELD_PREP(STF_DPHY_DEBUG_MODE_SEL, 0x5a), + dphy->regs + STF_DPHY_APBCFGSAIF__SYSCFG(184)); + + writel(FIELD_PREP(STF_DPHY_ENABLE_CLK, 1) | + FIELD_PREP(STF_DPHY_ENABLE_CLK1, 1) | + FIELD_PREP(STF_DPHY_ENABLE_LAN0, 1) | + FIELD_PREP(STF_DPHY_ENABLE_LAN1, 1) | + FIELD_PREP(STF_DPHY_ENABLE_LAN2, 1) | + FIELD_PREP(STF_DPHY_ENABLE_LAN3, 1) | + FIELD_PREP(STF_DPHY_GPI_EN, 0) | + FIELD_PREP(STF_DPHY_HS_FREQ_CHANGE_CLK, 0) | + FIELD_PREP(STF_DPHY_HS_FREQ_CHANGE_CLK1, 0) | + FIELD_PREP(STF_DPHY_LANE_SWAP_CLK, map[0]) | + FIELD_PREP(STF_DPHY_LANE_SWAP_CLK1, map[5]) | + FIELD_PREP(STF_DPHY_LANE_SWAP_LAN0, map[1]) | + FIELD_PREP(STF_DPHY_LANE_SWAP_LAN1, map[2]), + dphy->regs + STF_DPHY_APBCFGSAIF__SYSCFG(188)); + + writel(FIELD_PREP(STF_DPHY_LANE_SWAP_LAN2, map[3]) | + FIELD_PREP(STF_DPHY_LANE_SWAP_LAN3, map[4]) | + FIELD_PREP(STF_DPHY_MP_TEST_EN, 0) | + FIELD_PREP(STF_DPHY_MP_TEST_MODE_SEL, 0) | + FIELD_PREP(STF_DPHY_PLL_CLK_SEL, 0x37c) | + FIELD_PREP(STF_DPHY_PRECOUNTER_IN_CLK, 8), + dphy->regs + STF_DPHY_APBCFGSAIF__SYSCFG(192)); + + writel(FIELD_PREP(STF_DPHY_PRECOUNTER_IN_CLK1, 8) | + FIELD_PREP(STF_DPHY_PRECOUNTER_IN_LAN0, 7) | + FIELD_PREP(STF_DPHY_PRECOUNTER_IN_LAN1, 7) | + FIELD_PREP(STF_DPHY_PRECOUNTER_IN_LAN2, 7), + dphy->regs + STF_DPHY_APBCFGSAIF__SYSCFG(196)); + + writel(FIELD_PREP(STF_DPHY_PRECOUNTER_IN_LAN3, 7) | + FIELD_PREP(STF_DPHY_RX_1C2C_SEL, 0), + dphy->regs + STF_DPHY_APBCFGSAIF__SYSCFG(200)); + + return 0; +} + +static int stf_dphy_init(struct phy *phy) +{ + struct stf_dphy *dphy =3D phy_get_drvdata(phy); + int ret; + + ret =3D regulator_enable(dphy->mipi_0p9); + if (ret) + goto err_0p9; + + if (stf_dphy_info->external_support && stf_dphy_info->external_init) + stf_dphy_info->external_init(dphy); + + return 0; + +err_0p9: + return ret; +} + +static int stf_dphy_exit(struct phy *phy) +{ + struct stf_dphy *dphy =3D phy_get_drvdata(phy); + + if (stf_dphy_info->external_support && stf_dphy_info->external_exit) + stf_dphy_info->external_exit(dphy); + + regulator_disable(dphy->mipi_0p9); + + return 0; +} + +static int stf_dphy_power_on(struct phy *phy) +{ + struct stf_dphy *dphy =3D phy_get_drvdata(phy); + + clk_set_rate(dphy->cfg_clk, 99000000); + clk_set_rate(dphy->ref_clk, 49500000); + clk_set_rate(dphy->tx_clk, 19800000); + reset_control_deassert(dphy->rstc); + + return 0; +} + +static int stf_dphy_power_off(struct phy *phy) +{ + struct stf_dphy *dphy =3D phy_get_drvdata(phy); + + reset_control_assert(dphy->rstc); + + return 0; +} + +static const struct phy_ops stf_dphy_ops =3D { + .init =3D stf_dphy_init, + .exit =3D stf_dphy_exit, + .configure =3D stf_dphy_configure, + .power_on =3D stf_dphy_power_on, + .power_off =3D stf_dphy_power_off, +}; + +static int stf_dphy_probe(struct platform_device *pdev) +{ + struct phy_provider *phy_provider; + struct stf_dphy *dphy; + int ret; + + dphy =3D devm_kzalloc(&pdev->dev, sizeof(*dphy), GFP_KERNEL); + if (!dphy) + return -ENOMEM; + stf_dphy_info =3D of_device_get_match_data(&pdev->dev); + dev_set_drvdata(&pdev->dev, dphy); + dphy->dev =3D &pdev->dev; + + dphy->regs =3D devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(dphy->regs)) + return PTR_ERR(dphy->regs); + + dphy->cfg_clk =3D devm_clk_get(&pdev->dev, "cfg"); + if (IS_ERR(dphy->cfg_clk)) + return PTR_ERR(dphy->cfg_clk); + + dphy->ref_clk =3D devm_clk_get(&pdev->dev, "ref"); + if (IS_ERR(dphy->ref_clk)) + return PTR_ERR(dphy->ref_clk); + + dphy->tx_clk =3D devm_clk_get(&pdev->dev, "tx"); + if (IS_ERR(dphy->tx_clk)) + return PTR_ERR(dphy->tx_clk); + + dphy->rstc =3D devm_reset_control_array_get_exclusive(&pdev->dev); + if (IS_ERR(dphy->rstc)) + return PTR_ERR(dphy->rstc); + + dphy->mipi_0p9 =3D devm_regulator_get(&pdev->dev, "mipi_0p9"); + if (IS_ERR(dphy->mipi_0p9)) + return PTR_ERR(dphy->mipi_0p9); + + if (stf_dphy_info->external_support && stf_dphy_info->external_get) { + ret =3D stf_dphy_info->external_get(dphy); + if (ret < 0) { + dev_err(&pdev->dev, "Failed to get PHY external info\n"); + return ret; + } + } + + dphy->phy =3D devm_phy_create(&pdev->dev, NULL, &stf_dphy_ops); + if (IS_ERR(dphy->phy)) { + dev_err(&pdev->dev, "Failed to create PHY\n"); + return PTR_ERR(dphy->phy); + } + + phy_set_drvdata(dphy->phy, dphy); + phy_provider =3D devm_of_phy_provider_register(&pdev->dev, + of_phy_simple_xlate); + + return PTR_ERR_OR_ZERO(phy_provider); +} + +static int stf_external_get(struct stf_dphy *dphy) +{ + struct of_phandle_args args; + int ret; + + ret =3D of_parse_phandle_with_fixed_args(dphy->dev->of_node, + "starfive,aon-syscon", + 1, 0, &args); + if (ret < 0) { + dev_err(dphy->dev, "Failed to parse starfive,aon-syscon\n"); + return -EINVAL; + } + + dphy->stf_aon_syscon =3D syscon_node_to_regmap(args.np); + of_node_put(args.np); + if (IS_ERR(dphy->stf_aon_syscon)) + return PTR_ERR(dphy->stf_aon_syscon); + + dphy->aon_gp_reg =3D args.args[0]; + + return 0; +} + +static void stf_external_init(struct stf_dphy *dphy) +{ + regmap_update_bits(dphy->stf_aon_syscon, dphy->aon_gp_reg, + BIT(31), BIT(31)); +} + +static void stf_external_exit(struct stf_dphy *dphy) +{ + regmap_update_bits(dphy->stf_aon_syscon, dphy->aon_gp_reg, + BIT(31), 0); +} + +static const struct stf_dphy_info starfive_dphy_info =3D { + .external_support =3D true, + .external_get =3D stf_external_get, + .external_init =3D stf_external_init, + .external_exit =3D stf_external_exit, +}; + +static const struct of_device_id stf_dphy_dt_ids[] =3D { + { + .compatible =3D "starfive,jh7110-dphy-rx", + .data =3D &starfive_dphy_info, + }, + { /* sentinel */ }, +}; +MODULE_DEVICE_TABLE(of, stf_dphy_dt_ids); + +static struct platform_driver stf_dphy_driver =3D { + .probe =3D stf_dphy_probe, + .driver =3D { + .name =3D "starfive-dphy-rx", + .of_match_table =3D stf_dphy_dt_ids, + }, +}; +module_platform_driver(stf_dphy_driver); + +MODULE_AUTHOR("Jack Zhu "); +MODULE_AUTHOR("Changhuang Liang "); +MODULE_DESCRIPTION("Starfive DPHY RX driver"); +MODULE_LICENSE("GPL"); --=20 2.25.1 From nobody Thu Sep 11 00:19:48 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 14FE4C636D6 for ; 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Thu, 23 Feb 2023 09:59:56 +0800 From: Changhuang Liang To: Vinod Koul , Kishon Vijay Abraham I , Rob Herring , Krzysztof Kozlowski , Emil Renner Berthing , Conor Dooley , Paul Walmsley , Palmer Dabbelt , Albert Ou , Philipp Zabel CC: Jack Zhu , Changhuang Liang , , , , Subject: [PATCH v2 3/3] riscv: dts: starfive: Add dphy rx node Date: Wed, 22 Feb 2023 17:59:52 -0800 Message-ID: <20230223015952.201841-4-changhuang.liang@starfivetech.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230223015952.201841-1-changhuang.liang@starfivetech.com> References: <20230223015952.201841-1-changhuang.liang@starfivetech.com> MIME-Version: 1.0 X-Originating-IP: [113.72.147.165] X-ClientProxiedBy: EXCAS062.cuchost.com (172.16.6.22) To EXMBX162.cuchost.com (172.16.6.72) X-YovoleRuleAgent: yovoleflag Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add dphy rx node for the Starfive JH7110 SoC. It is used to transfer CSI camera data. Signed-off-by: Changhuang Liang --- arch/riscv/boot/dts/starfive/jh7110.dtsi | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/arch/riscv/boot/dts/starfive/jh7110.dtsi b/arch/riscv/boot/dts= /starfive/jh7110.dtsi index 697ab59191a1..074423d17786 100644 --- a/arch/riscv/boot/dts/starfive/jh7110.dtsi +++ b/arch/riscv/boot/dts/starfive/jh7110.dtsi @@ -563,6 +563,19 @@ ispcrg: clock-controller@19810000 { power-domains =3D <&pwrc JH7110_PD_ISP>; }; =20 + csi_phy: phy@19820000 { + compatible =3D "starfive,jh7110-dphy-rx"; + reg =3D <0x0 0x19820000 0x0 0x10000>; + clocks =3D <&ispcrg JH7110_ISPCLK_M31DPHY_CFGCLK_IN>, + <&ispcrg JH7110_ISPCLK_M31DPHY_REFCLK_IN>, + <&ispcrg JH7110_ISPCLK_M31DPHY_TXCLKESC_LAN0>; + clock-names =3D "cfg", "ref", "tx"; + resets =3D <&ispcrg JH7110_ISPRST_M31DPHY_HW>, + <&ispcrg JH7110_ISPRST_M31DPHY_B09_ALWAYS_ON>; + starfive,aon-syscon =3D <&aon_syscon 0x00>; + #phy-cells =3D <0>; + }; + voutcrg: clock-controller@295C0000 { compatible =3D "starfive,jh7110-voutcrg"; reg =3D <0x0 0x295C0000 0x0 0x10000>; --=20 2.25.1