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[83.9.2.151]) by smtp.gmail.com with ESMTPSA id 12-20020ac2482c000000b004dc807b904bsm427376lft.120.2023.02.22.17.47.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 22 Feb 2023 17:47:40 -0800 (PST) From: Konrad Dybcio Date: Thu, 23 Feb 2023 02:47:37 +0100 Subject: [PATCH v2 1/6] drm/msm/a2xx: Include perf counter reg values in XML MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20230223-topic-opp-v2-1-24ed24cd7358@linaro.org> References: <20230223-topic-opp-v2-0-24ed24cd7358@linaro.org> In-Reply-To: <20230223-topic-opp-v2-0-24ed24cd7358@linaro.org> To: Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , David Airlie , Daniel Vetter Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org, Konrad Dybcio X-Mailer: b4 0.12.1 X-Developer-Signature: v=1; a=ed25519-sha256; t=1677116858; l=830; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=mzjSUO+qHIiKaLiyXFVom/GoyNVpw37b+tvLzQHI5RY=; b=sOt90zAVghwEBEdFaBDhwOmr+WDEq6xWWtPbhadU8HLedLihLtGPgw3G+utNjj5nKzLKe9UXi7Sp /8dBYiuOABV7JJpxXdNZpynZqYX62ZFL3PLs9g7th7h4bt1MOJga X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org This is a partial merge of [1], subject to be dropped if a header update is executed. [1] https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21480/ Signed-off-by: Konrad Dybcio --- drivers/gpu/drm/msm/adreno/a2xx.xml.h | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/drivers/gpu/drm/msm/adreno/a2xx.xml.h b/drivers/gpu/drm/msm/ad= reno/a2xx.xml.h index afa6023346c4..b85fdc082bc1 100644 --- a/drivers/gpu/drm/msm/adreno/a2xx.xml.h +++ b/drivers/gpu/drm/msm/adreno/a2xx.xml.h @@ -1060,6 +1060,12 @@ enum a2xx_mh_perfcnt_select { AXI_TOTAL_READ_REQUEST_DATA_BEATS =3D 181, }; =20 +enum perf_mode_cnt { + PERF_STATE_RESET =3D 0, + PERF_STATE_ENABLE =3D 1, + PERF_STATE_FREEZE =3D 2, +}; + enum adreno_mmu_clnt_beh { BEH_NEVR =3D 0, BEH_TRAN_RNG =3D 1, --=20 2.39.2 From nobody Thu Sep 11 00:07:47 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 75914C61DA4 for ; Thu, 23 Feb 2023 01:47:53 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232947AbjBWBrv (ORCPT ); Wed, 22 Feb 2023 20:47:51 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:50376 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232942AbjBWBrp (ORCPT ); Wed, 22 Feb 2023 20:47:45 -0500 Received: from mail-lf1-x129.google.com (mail-lf1-x129.google.com [IPv6:2a00:1450:4864:20::129]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id F369942BC1 for ; Wed, 22 Feb 2023 17:47:43 -0800 (PST) Received: by mail-lf1-x129.google.com with SMTP id bp25so12613542lfb.0 for ; Wed, 22 Feb 2023 17:47:43 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=0I63GzqZ4/pdwcdXOU5rzNuBienj4oVxRvi/wF6aWHM=; b=Lqbt+WCssCVhJH/OOOabLEzoesPyNKKHbilHUFk+4QO5irDF0xosnm+5q0Y4tMto1E uJhnTGKopIRN2Ph6fnS49cmDkbkb3AgUphEyv+3dM7lURxXyV2qJrpfEYQPfxduh0jxB Fykh/C/FTn1J2laX+JDUR9lBFFr3Et8H3GbZWsdPlZ04N91aRmEiiXac/qWmBHh7LG20 4QIOHPaK0xZm6s6h+7iPIdX+8LJnRlBeUYZijpY5sRSafPVvY3FJG09xGTPhcaAe+Z8L Ex6sLq4rWxVHudUa/P5/Fm7FC3sTBl5S8R88OoLXANZvD+sK4+UWj/lFEX+7OsgMm16j sCag== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=0I63GzqZ4/pdwcdXOU5rzNuBienj4oVxRvi/wF6aWHM=; b=28xUzRXqkDIsdUnwQdJPPt4ulHkmiNr2H/MkzjAUqCG3HHrW6yWprUy73wRagx45so iegthjWqyywCSincrT3bQrwLlaHUe4a+KfhQ36V7OChJNWNpobcQGNKiSbUVXN0dCFtr 6W3WZbJca1QdtfkvV4+BZlOuL7rOHuSzSPQiI7QT2rdwsWNGUP1Y9ldHkJfLgxa2Ykyq UzRyrqLn0SW7zK+z9c1zcCK0gwXkjD1PicD0VpqoMQ4OH5X4fvLBAd7BzcN/BVIOQOQ0 BvxO4XHOutG29iA/PYKbkGeXTts3hbGMPdfzQKQeeQ34fZfdTkFqsdSnKPdzYh3On/LW W2kA== X-Gm-Message-State: AO0yUKVqDMH1ajG0FIQSqaxzv3gIUKYuc84os+7ahBKoTKenTRm4iYhw mwVoyZchdsYUtls1GB1A/WrKMg== X-Google-Smtp-Source: AK7set+hNiP8e2YnQwhmrwZkk0874NqpqVAwu81d4anrdCgMrX0BBdy4BekWdcyZxCe3XneuqJ4OnQ== X-Received: by 2002:ac2:5a5c:0:b0:4d7:58c8:5f44 with SMTP id r28-20020ac25a5c000000b004d758c85f44mr3476080lfn.12.1677116862256; Wed, 22 Feb 2023 17:47:42 -0800 (PST) Received: from [192.168.1.101] (abxi151.neoplus.adsl.tpnet.pl. [83.9.2.151]) by smtp.gmail.com with ESMTPSA id 12-20020ac2482c000000b004dc807b904bsm427376lft.120.2023.02.22.17.47.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 22 Feb 2023 17:47:41 -0800 (PST) From: Konrad Dybcio Date: Thu, 23 Feb 2023 02:47:38 +0100 Subject: [PATCH v2 2/6] drm/msm/adreno: Use OPP for every GPU generation MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20230223-topic-opp-v2-2-24ed24cd7358@linaro.org> References: <20230223-topic-opp-v2-0-24ed24cd7358@linaro.org> In-Reply-To: <20230223-topic-opp-v2-0-24ed24cd7358@linaro.org> To: Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , David Airlie , Daniel Vetter Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org, Konrad Dybcio X-Mailer: b4 0.12.1 X-Developer-Signature: v=1; a=ed25519-sha256; t=1677116858; l=6235; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=ZLdJVtXa5OKKmfHA12Ep31JDGaPgYsonm/CsCSOeZZM=; b=j3U8ryJ7Pa3zdIXcfPRy23GXdpn9yPokiQ7mfYAzTieE3Gpo7ryz1533HQvPz+0QDeSF/Y9E8cMj Td95oUplAlRZddmwjbCPMx2UoOKLYhWDSbzDtFjUplLEpw4u/C5Q X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Some older GPUs (namely a2xx with no opp tables at all and a320 with downstream-remnants gpu pwrlevels) used not to have OPP tables. They both however had just one frequency defined, making it extremely easy to construct such an OPP table from within the driver if need be. Do so and switch all clk_set_rate calls on core_clk to their OPP counterparts. Signed-off-by: Konrad Dybcio Reviewed-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/adreno/adreno_gpu.c | 99 +++++++++++++++--------------= ---- drivers/gpu/drm/msm/msm_gpu.c | 4 +- drivers/gpu/drm/msm/msm_gpu_devfreq.c | 2 +- 3 files changed, 48 insertions(+), 57 deletions(-) diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.c b/drivers/gpu/drm/msm/= adreno/adreno_gpu.c index ce6b76c45b6f..8721e3d6231a 100644 --- a/drivers/gpu/drm/msm/adreno/adreno_gpu.c +++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.c @@ -922,73 +922,48 @@ void adreno_wait_ring(struct msm_ringbuffer *ring, ui= nt32_t ndwords) ring->id); } =20 -/* Get legacy powerlevels from qcom,gpu-pwrlevels and populate the opp tab= le */ -static int adreno_get_legacy_pwrlevels(struct device *dev) -{ - struct device_node *child, *node; - int ret; - - node =3D of_get_compatible_child(dev->of_node, "qcom,gpu-pwrlevels"); - if (!node) { - DRM_DEV_DEBUG(dev, "Could not find the GPU powerlevels\n"); - return -ENXIO; - } - - for_each_child_of_node(node, child) { - unsigned int val; - - ret =3D of_property_read_u32(child, "qcom,gpu-freq", &val); - if (ret) - continue; - - /* - * Skip the intentionally bogus clock value found at the bottom - * of most legacy frequency tables - */ - if (val !=3D 27000000) - dev_pm_opp_add(dev, val, 0); - } - - of_node_put(node); - - return 0; -} - -static void adreno_get_pwrlevels(struct device *dev, +static int adreno_get_pwrlevels(struct device *dev, struct msm_gpu *gpu) { + struct adreno_gpu *adreno_gpu =3D to_adreno_gpu(gpu); unsigned long freq =3D ULONG_MAX; struct dev_pm_opp *opp; int ret; =20 gpu->fast_rate =3D 0; =20 - /* You down with OPP? */ - if (!of_find_property(dev->of_node, "operating-points-v2", NULL)) - ret =3D adreno_get_legacy_pwrlevels(dev); - else { - ret =3D devm_pm_opp_of_add_table(dev); - if (ret) - DRM_DEV_ERROR(dev, "Unable to set the OPP table\n"); - } - - if (!ret) { - /* Find the fastest defined rate */ - opp =3D dev_pm_opp_find_freq_floor(dev, &freq); - if (!IS_ERR(opp)) { - gpu->fast_rate =3D freq; - dev_pm_opp_put(opp); + /* devm_pm_opp_of_add_table may error out but will still create an OPP ta= ble */ + ret =3D devm_pm_opp_of_add_table(dev); + if (ret =3D=3D -ENODEV) { + /* Special cases for ancient hw with ancient DT bindings */ + if (adreno_is_a2xx(adreno_gpu)) { + dev_warn(dev, "Unable to find the OPP table. Falling back to 200 MHz.\n= "); + dev_pm_opp_add(dev, 200000000, 0); + } else if (adreno_is_a320(adreno_gpu)) { + dev_warn(dev, "Unable to find the OPP table. Falling back to 450 MHz.\n= "); + dev_pm_opp_add(dev, 450000000, 0); + } else { + DRM_DEV_ERROR(dev, "Unable to find the OPP table\n"); + return -ENODEV; } + } else if (ret) { + DRM_DEV_ERROR(dev, "Unable to set the OPP table\n"); + return ret; } =20 - if (!gpu->fast_rate) { - dev_warn(dev, - "Could not find a clock rate. Using a reasonable default\n"); - /* Pick a suitably safe clock speed for any target */ - gpu->fast_rate =3D 200000000; + /* Find the fastest defined rate */ + opp =3D dev_pm_opp_find_freq_floor(dev, &freq); + + if (IS_ERR(opp)) + return PTR_ERR(opp); + else { + gpu->fast_rate =3D freq; + dev_pm_opp_put(opp); } =20 DBG("fast_rate=3D%u, slow_rate=3D27000000", gpu->fast_rate); + + return 0; } =20 int adreno_gpu_ocmem_init(struct device *dev, struct adreno_gpu *adreno_gp= u, @@ -1046,6 +1021,20 @@ int adreno_gpu_init(struct drm_device *drm, struct p= latform_device *pdev, struct adreno_rev *rev =3D &config->rev; const char *gpu_name; u32 speedbin; + int ret; + + /* + * This can only be done before devm_pm_opp_of_add_table(), or + * dev_pm_opp_set_config() will WARN_ON() + */ + if (IS_ERR(devm_clk_get(dev, "core"))) { + /* + * If "core" is absent, go for the legacy clock name. + * If we got this far in probing, it's a given one of them exists. + */ + devm_pm_opp_set_clkname(dev, "core_clk"); + } else + devm_pm_opp_set_clkname(dev, "core"); =20 adreno_gpu->funcs =3D funcs; adreno_gpu->info =3D adreno_info(config->rev); @@ -1070,7 +1059,9 @@ int adreno_gpu_init(struct drm_device *drm, struct pl= atform_device *pdev, =20 adreno_gpu_config.nr_rings =3D nr_rings; =20 - adreno_get_pwrlevels(dev, gpu); + ret =3D adreno_get_pwrlevels(dev, gpu); + if (ret) + return ret; =20 pm_runtime_set_autosuspend_delay(dev, adreno_gpu->info->inactive_period); diff --git a/drivers/gpu/drm/msm/msm_gpu.c b/drivers/gpu/drm/msm/msm_gpu.c index 380249500325..cdcb00df3f25 100644 --- a/drivers/gpu/drm/msm/msm_gpu.c +++ b/drivers/gpu/drm/msm/msm_gpu.c @@ -59,7 +59,7 @@ static int disable_pwrrail(struct msm_gpu *gpu) static int enable_clk(struct msm_gpu *gpu) { if (gpu->core_clk && gpu->fast_rate) - clk_set_rate(gpu->core_clk, gpu->fast_rate); + dev_pm_opp_set_rate(&gpu->pdev->dev, gpu->fast_rate); =20 /* Set the RBBM timer rate to 19.2Mhz */ if (gpu->rbbmtimer_clk) @@ -78,7 +78,7 @@ static int disable_clk(struct msm_gpu *gpu) * will be rounded down to zero anyway so it all works out. */ if (gpu->core_clk) - clk_set_rate(gpu->core_clk, 27000000); + dev_pm_opp_set_rate(&gpu->pdev->dev, 27000000); =20 if (gpu->rbbmtimer_clk) clk_set_rate(gpu->rbbmtimer_clk, 0); diff --git a/drivers/gpu/drm/msm/msm_gpu_devfreq.c b/drivers/gpu/drm/msm/ms= m_gpu_devfreq.c index e27dbf12b5e8..ea70c1c32d94 100644 --- a/drivers/gpu/drm/msm/msm_gpu_devfreq.c +++ b/drivers/gpu/drm/msm/msm_gpu_devfreq.c @@ -48,7 +48,7 @@ static int msm_devfreq_target(struct device *dev, unsigne= d long *freq, gpu->funcs->gpu_set_freq(gpu, opp, df->suspended); mutex_unlock(&df->lock); } else { - clk_set_rate(gpu->core_clk, *freq); + dev_pm_opp_set_rate(dev, *freq); } =20 dev_pm_opp_put(opp); --=20 2.39.2 From nobody Thu Sep 11 00:07:47 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 678E3C64EC7 for ; Thu, 23 Feb 2023 01:47:57 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233035AbjBWBry (ORCPT ); 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[83.9.2.151]) by smtp.gmail.com with ESMTPSA id 12-20020ac2482c000000b004dc807b904bsm427376lft.120.2023.02.22.17.47.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 22 Feb 2023 17:47:43 -0800 (PST) From: Konrad Dybcio Date: Thu, 23 Feb 2023 02:47:39 +0100 Subject: [PATCH v2 3/6] drm/msm/a2xx: Implement .gpu_busy MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20230223-topic-opp-v2-3-24ed24cd7358@linaro.org> References: <20230223-topic-opp-v2-0-24ed24cd7358@linaro.org> In-Reply-To: <20230223-topic-opp-v2-0-24ed24cd7358@linaro.org> To: Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , David Airlie , Daniel Vetter Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org, Konrad Dybcio X-Mailer: b4 0.12.1 X-Developer-Signature: v=1; a=ed25519-sha256; t=1677116858; l=2023; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=o2IJoNBHAOSR6oYp4+Uz08OuccC4IUsqkONjhNT3F0Q=; b=s5/hbhoiSbqwQp+Bkv9gVx0WwGsnEjR+kvSlH359RLCiLjLo6w9Ek4Y4RWaXdFQy9iukWvt19fpG zU+0c93AADckr0oItDowSnXRKpk58/ORvjCDnY3rxbK1odDVmjDT X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Implement gpu_busy based on the downstream msm-3.4 code [1]. This allows us to use devfreq on this old old old hardware! [1] https://github.com/LineageOS/android_kernel_sony_apq8064/blob/lineage-1= 6.0/drivers/gpu/msm/adreno_a2xx.c#L1975 Signed-off-by: Konrad Dybcio Reviewed-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/adreno/a2xx_gpu.c | 24 ++++++++++++++++++++++++ 1 file changed, 24 insertions(+) diff --git a/drivers/gpu/drm/msm/adreno/a2xx_gpu.c b/drivers/gpu/drm/msm/ad= reno/a2xx_gpu.c index c67089a7ebc1..6f9876b37db5 100644 --- a/drivers/gpu/drm/msm/adreno/a2xx_gpu.c +++ b/drivers/gpu/drm/msm/adreno/a2xx_gpu.c @@ -481,6 +481,29 @@ a2xx_create_address_space(struct msm_gpu *gpu, struct = platform_device *pdev) return aspace; } =20 +/* While the precise size of this field is unknown, it holds at least thes= e three values.. */ +static u64 a2xx_gpu_busy(struct msm_gpu *gpu, unsigned long *out_sample_ra= te) +{ + u64 busy_cycles; + + /* Freeze the counter */ + gpu_write(gpu, REG_A2XX_CP_PERFMON_CNTL, PERF_STATE_FREEZE); + + busy_cycles =3D gpu_read64(gpu, REG_A2XX_RBBM_PERFCOUNTER1_LO); + + /* Reset the counter */ + gpu_write(gpu, REG_A2XX_CP_PERFMON_CNTL, PERF_STATE_RESET); + + /* Re-enable the performance monitors */ + gpu_rmw(gpu, REG_A2XX_RBBM_PM_OVERRIDE2, BIT(6), BIT(6)); + gpu_write(gpu, REG_A2XX_RBBM_PERFCOUNTER1_SELECT, 1); + gpu_write(gpu, REG_A2XX_CP_PERFMON_CNTL, PERF_STATE_ENABLE); + + *out_sample_rate =3D clk_get_rate(gpu->core_clk); + + return busy_cycles; +} + static u32 a2xx_get_rptr(struct msm_gpu *gpu, struct msm_ringbuffer *ring) { ring->memptrs->rptr =3D gpu_read(gpu, REG_AXXX_CP_RB_RPTR); @@ -502,6 +525,7 @@ static const struct adreno_gpu_funcs funcs =3D { #if defined(CONFIG_DEBUG_FS) || defined(CONFIG_DEV_COREDUMP) .show =3D adreno_show, #endif + .gpu_busy =3D a2xx_gpu_busy, .gpu_state_get =3D a2xx_gpu_state_get, .gpu_state_put =3D adreno_gpu_state_put, .create_address_space =3D a2xx_create_address_space, --=20 2.39.2 From nobody Thu Sep 11 00:07:47 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id D4B27C636D6 for ; Thu, 23 Feb 2023 01:47:59 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232999AbjBWBr6 (ORCPT ); Wed, 22 Feb 2023 20:47:58 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:50514 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232981AbjBWBrs (ORCPT ); Wed, 22 Feb 2023 20:47:48 -0500 Received: from mail-lf1-x132.google.com (mail-lf1-x132.google.com [IPv6:2a00:1450:4864:20::132]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 31FEB43446 for ; Wed, 22 Feb 2023 17:47:46 -0800 (PST) Received: by mail-lf1-x132.google.com with SMTP id bp25so12613661lfb.0 for ; Wed, 22 Feb 2023 17:47:46 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=4RozdFg8UcjNGaMEUfY94uV2Q1ptXwQxOYUwNdKHWzQ=; b=esohPNulw2M7Ju+p/HyTXssOZPF43TTgdrx9PSZfSpeex+8N4B7DBUkRzpDp48A09v DaOM/jOmfgSoxNXBbdwRIwrxK1fhe7sI1RtggfazHsUl/aTcPiOIcRn+4LB+HLLalwhJ +TnDmrtffCDZ/mpmathGjIFtgVSyJNkAtPnaiaQWRbQT6sj7UUdmPaBFD0M6XbR8I97l UQzEmubUTAq+cm1eN7YokQ8N29SudFC9aZvbaHcvB/aZBOu9KnN07fBLC5M2LLvkr3mT fDiC2g9CsNgFyndqQSsUr0JV4BZDOLKKHPxTMeswaq6N2Euw4K8xfPBNdYgc3LhKbE9S Faig== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=4RozdFg8UcjNGaMEUfY94uV2Q1ptXwQxOYUwNdKHWzQ=; b=GB7qV4DoJprJDpdU3JO5k1iOgAX0Sj35QMA4vYjOg9eouf37IhcED2tfCOfCJ508Vn RxDM36WDyr/b+dOSBo2ir1gZrckIFIwxjeHtp9sSEjI6tH1tOwjVmVyHh8Il9iBEfEIh UfoKV2hTbWIlLx7lqiS0iPOH73E74J/XTAiFKaPCU3PXDjqq6IDgg4Gpo5MSGMBJjj4w I35u9SwUU5dW+/gKGLb+MYYUbPxlaANE7CJuq6X1+I7c4eMXQmeq93QcaEflCEXWjM80 ZDAkbolSzzp/So2B7Lo13j8eBqgXC1MSMAQUrRZF6Yfp9IxqwamHSdTe/ElF/x9TMLyt FgNA== X-Gm-Message-State: AO0yUKXi6GsNdP6UcEzR+epyyRm3cmOdb8pGCmZeznbrOCmiG/h5+TcF s0Suat7ka8ID3HZkcuurfkKcjw== X-Google-Smtp-Source: AK7set/NOhyhF49utUZLVRvxPiTB2uoF1cCq+QQKx/9emXY264rqOyfCOP1exk5q0CITTox6BfZsqA== X-Received: by 2002:a19:f005:0:b0:4a4:68b9:19f6 with SMTP id p5-20020a19f005000000b004a468b919f6mr3708824lfc.30.1677116864589; Wed, 22 Feb 2023 17:47:44 -0800 (PST) Received: from [192.168.1.101] (abxi151.neoplus.adsl.tpnet.pl. [83.9.2.151]) by smtp.gmail.com with ESMTPSA id 12-20020ac2482c000000b004dc807b904bsm427376lft.120.2023.02.22.17.47.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 22 Feb 2023 17:47:44 -0800 (PST) From: Konrad Dybcio Date: Thu, 23 Feb 2023 02:47:40 +0100 Subject: [PATCH v2 4/6] drm/msm/a3xx: Implement .gpu_busy MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20230223-topic-opp-v2-4-24ed24cd7358@linaro.org> References: <20230223-topic-opp-v2-0-24ed24cd7358@linaro.org> In-Reply-To: <20230223-topic-opp-v2-0-24ed24cd7358@linaro.org> To: Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , David Airlie , Daniel Vetter Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org, Konrad Dybcio X-Mailer: b4 0.12.1 X-Developer-Signature: v=1; a=ed25519-sha256; t=1677116858; l=1452; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=sAA92dCqoQlGesDQKUB68UAlcg2YIqQbh8UmjiEN524=; b=GVnaZnlQ6N+BD1eAG7ueoV0GF0HZZ3QeXEdiAAHLSxSj/otEEt/esgibqfS+fVabGvCIunPtJz75 w8iUO2JPBBZO7i/A1THaoFJbtoSTtLJ5z0wq/ODIxwXqLY6lcU75 X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add support for gpu_busy on a3xx, which is required for devfreq support. Tested-by: Dmitry Baryshkov #ifc6410 Reviewed-by: Dmitry Baryshkov Signed-off-by: Konrad Dybcio --- drivers/gpu/drm/msm/adreno/a3xx_gpu.c | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/drivers/gpu/drm/msm/adreno/a3xx_gpu.c b/drivers/gpu/drm/msm/ad= reno/a3xx_gpu.c index 948785ed07bb..c86b377f6f0d 100644 --- a/drivers/gpu/drm/msm/adreno/a3xx_gpu.c +++ b/drivers/gpu/drm/msm/adreno/a3xx_gpu.c @@ -477,6 +477,16 @@ static struct msm_gpu_state *a3xx_gpu_state_get(struct= msm_gpu *gpu) return state; } =20 +static u64 a3xx_gpu_busy(struct msm_gpu *gpu, unsigned long *out_sample_ra= te) +{ + u64 busy_cycles; + + busy_cycles =3D gpu_read64(gpu, REG_A3XX_RBBM_PERFCTR_RBBM_1_LO); + *out_sample_rate =3D clk_get_rate(gpu->core_clk); + + return busy_cycles; +} + static u32 a3xx_get_rptr(struct msm_gpu *gpu, struct msm_ringbuffer *ring) { ring->memptrs->rptr =3D gpu_read(gpu, REG_AXXX_CP_RB_RPTR); @@ -498,6 +508,7 @@ static const struct adreno_gpu_funcs funcs =3D { #if defined(CONFIG_DEBUG_FS) || defined(CONFIG_DEV_COREDUMP) .show =3D adreno_show, #endif + .gpu_busy =3D a3xx_gpu_busy, .gpu_state_get =3D a3xx_gpu_state_get, .gpu_state_put =3D adreno_gpu_state_put, .create_address_space =3D adreno_create_address_space, --=20 2.39.2 From nobody Thu Sep 11 00:07:47 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id B0D78C64EC7 for ; Thu, 23 Feb 2023 01:48:02 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233024AbjBWBsA (ORCPT ); Wed, 22 Feb 2023 20:48:00 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:50560 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232867AbjBWBrt (ORCPT ); Wed, 22 Feb 2023 20:47:49 -0500 Received: from mail-lf1-x136.google.com (mail-lf1-x136.google.com [IPv6:2a00:1450:4864:20::136]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 6FC29457C6 for ; Wed, 22 Feb 2023 17:47:47 -0800 (PST) Received: by mail-lf1-x136.google.com with SMTP id r27so10353636lfe.10 for ; Wed, 22 Feb 2023 17:47:47 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=GGhJ8k8BvYcG4UvdUcw3fi971zbE82bjXqWQD3F+nXY=; b=ldmW/ilzYBZSCA++GxzPyyWkJ9St3Yw6f0acU3vMlovh8nGZ09axkbDopIWmHhy5r3 RKk+BcjWDQxjERBaHcat7fpz3LJGOOObvDIDk0MZuhT9fQhrNKcIOUJ7YqNe1DhsMtHD UEsQoAHfImfOpsgDVwB420ikxTcKMboeuC+1TOyiVcP1cjUJK4WQGj6QBFQXsyvORhhG OkuE3Xv1cU+UU9JiEEBxVqX2kQ+5BFKiY0XmeMPx5AS6ZVoVW3is9ZoxctlOPDFuBG4R WS8lBPianCAIhWBJuj7YyR9+Rm6l+U5D2DUx3IRJ1yhA9DEGXSnLzEzQRpbVqRIqzdZF MF6Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=GGhJ8k8BvYcG4UvdUcw3fi971zbE82bjXqWQD3F+nXY=; b=6792KNeOc1C/j4OmqSiScSSQGEg+VIEsILokOlci+YtLkC3Qp3bcXprX87SFeuIqGa rYQfuIyj23cFpKSmU0VBUhlnP18Czx40MZIXucjyR2qGH/JmBt2o3A5n9X3zlFHyiA4a EDPQ0UqOESg35Y+6onNP+dSDW8z5Z8o+NLUP/l5k68cTvytzBLHR7C5GfrNaqVj+2S+F Rk3UOk/tqDrptd0wLc1JOgFc0vt9ndsU3e98FaLrx6sBJqB/xcTJACqMtThtYo2iopXP G5Kd3ukhsBpWuSXf4O1v3pVz2RsynsjqjvnKR4E36dk2JIgSQixe354nn2caNu4TkXBy C/zw== X-Gm-Message-State: AO0yUKX+qiYfWRgUjr3lRri0ZUOR6oONw2Kcc8fGCfKfYnPf6rl8LuJw rg3dtvmpJj51irV2WoHBf2IX5Q== X-Google-Smtp-Source: AK7set9PMp+yF3wgjC3PGFWQ8f6vxlGN6VYMdTeVO7IMMHRkvT3q22dmsGb7RDmy4uqz1vm6Ewjb2g== X-Received: by 2002:ac2:5207:0:b0:4dc:8192:c5e6 with SMTP id a7-20020ac25207000000b004dc8192c5e6mr3568694lfl.13.1677116865722; Wed, 22 Feb 2023 17:47:45 -0800 (PST) Received: from [192.168.1.101] (abxi151.neoplus.adsl.tpnet.pl. [83.9.2.151]) by smtp.gmail.com with ESMTPSA id 12-20020ac2482c000000b004dc807b904bsm427376lft.120.2023.02.22.17.47.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 22 Feb 2023 17:47:45 -0800 (PST) From: Konrad Dybcio Date: Thu, 23 Feb 2023 02:47:41 +0100 Subject: [PATCH v2 5/6] drm/msm/a4xx: Implement .gpu_busy MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20230223-topic-opp-v2-5-24ed24cd7358@linaro.org> References: <20230223-topic-opp-v2-0-24ed24cd7358@linaro.org> In-Reply-To: <20230223-topic-opp-v2-0-24ed24cd7358@linaro.org> To: Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , David Airlie , Daniel Vetter Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org, Konrad Dybcio X-Mailer: b4 0.12.1 X-Developer-Signature: v=1; a=ed25519-sha256; t=1677116858; l=1379; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=Mfqjq6oPzn0mWycAv8UA9lcR+KDEDYvYmMvB7YZF6m4=; b=Mfz5NyNGrq9Nm2ebit78yYPih/DJD0y9rsEuSb/O6TQITG+HY8Lpy7U/ZcaAMxslu1ZDXovwWvec Sl2idkBSBQcCcNyqzRAVoMvNDIdkXp2SWe4SvswlugR1Av5gR6yI X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add support for gpu_busy on a4xx, which is required for devfreq support. Reviewed-by: Dmitry Baryshkov Signed-off-by: Konrad Dybcio --- drivers/gpu/drm/msm/adreno/a4xx_gpu.c | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/drivers/gpu/drm/msm/adreno/a4xx_gpu.c b/drivers/gpu/drm/msm/ad= reno/a4xx_gpu.c index 3e09d3a7a0ac..715436cb3996 100644 --- a/drivers/gpu/drm/msm/adreno/a4xx_gpu.c +++ b/drivers/gpu/drm/msm/adreno/a4xx_gpu.c @@ -611,6 +611,16 @@ static int a4xx_get_timestamp(struct msm_gpu *gpu, uin= t64_t *value) return 0; } =20 +static u64 a4xx_gpu_busy(struct msm_gpu *gpu, unsigned long *out_sample_ra= te) +{ + u64 busy_cycles; + + busy_cycles =3D gpu_read64(gpu, REG_A4XX_RBBM_PERFCTR_RBBM_1_LO); + *out_sample_rate =3D clk_get_rate(gpu->core_clk); + + return busy_cycles; +} + static u32 a4xx_get_rptr(struct msm_gpu *gpu, struct msm_ringbuffer *ring) { ring->memptrs->rptr =3D gpu_read(gpu, REG_A4XX_CP_RB_RPTR); @@ -632,6 +642,7 @@ static const struct adreno_gpu_funcs funcs =3D { #if defined(CONFIG_DEBUG_FS) || defined(CONFIG_DEV_COREDUMP) .show =3D adreno_show, #endif + .gpu_busy =3D a4xx_gpu_busy, .gpu_state_get =3D a4xx_gpu_state_get, .gpu_state_put =3D adreno_gpu_state_put, .create_address_space =3D adreno_create_address_space, --=20 2.39.2 From nobody Thu Sep 11 00:07:47 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1A124C64EC7 for ; Thu, 23 Feb 2023 01:48:06 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233060AbjBWBsE (ORCPT ); Wed, 22 Feb 2023 20:48:04 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:50640 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232992AbjBWBrt (ORCPT ); Wed, 22 Feb 2023 20:47:49 -0500 Received: from mail-lf1-x12e.google.com (mail-lf1-x12e.google.com [IPv6:2a00:1450:4864:20::12e]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 75EE610D1 for ; Wed, 22 Feb 2023 17:47:48 -0800 (PST) Received: by mail-lf1-x12e.google.com with SMTP id f18so12475889lfa.3 for ; Wed, 22 Feb 2023 17:47:48 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=Uw9ANW8A0HIEHlu0J95K8GI8spDLrbsMISUzwV0ijx4=; b=tQWLe5WcJzNbK/0p370q5JCC8xgYGmEwPZJ1u6Jeop0GH/tTM6fKYVde7vjXHCszdz f/ZjfII2Yl+byBaNLDjx0CQfwG3e0seCepo4C4GVKGCVRZmJByOi0FjsUQHZE8NTYyXD 6Ipy9iEz8c9OGNaIua1la3+dYcQjQ5wrpAkN9nkNKtGd37SwjHq0fGXCpH1cAOWMCyK7 LNNwXLk3mMsep1eDtljLQAr/JxPlaTqfaFeiZvMdLEPMmSU8T0ykV/iMy2Sar3KaGFNS k8eNDCmuGPhCtt3HlOSqjC+lTp8Wp2DJsdE/BzOuBJTjlKFf+1TDR2RwuybWldBf7YO7 u4tQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Uw9ANW8A0HIEHlu0J95K8GI8spDLrbsMISUzwV0ijx4=; b=4isOBbrBY/xK0KTDhSfwnKOw8AM/W8TolpHO9mmQ1mxLiUVAwSl7sVG0e5BsyZKQOt mJVnVy4hf70YP+2yh1cMo+nU+gzfcQJIWgi+Y9kfTmfvHluAggGyz8JeEhsiJelQ+3mU H2rA671Co15dlqg3wHmppos/8RdG0896xMW1UyYuY4NtZ466air8HbN83dK9aEaQURpx 9yWGSKviuudGf3c2RvdqsMRYN5YGa8OS7hZFAC24K2tMgQ/HxmucXKCdeFBc2UonHVmS ZrSDwOecPUoAxYyCQaptjykVpQ6cn/H70ycIRoBPdeZ4AuDBRhxYE1fYBzFGJBxYWUfC W7nA== X-Gm-Message-State: AO0yUKWQLAefZXECR/rLegdOq+Ek2uuOaUHnh93FOOvgllvnH6sY0K1U 0bTbPY+XpOCVM1RhwVG3zWmrsXwzK2K9x1fv X-Google-Smtp-Source: AK7set9HAxRsGbwERh+lUn3YGqAoTzETv5bCEZ+5Z5csnzzygLG1C8GvwRh/vu7HzJtKMzBd/rQ6vQ== X-Received: by 2002:a19:f512:0:b0:4cb:c11:d01f with SMTP id j18-20020a19f512000000b004cb0c11d01fmr3528085lfb.22.1677116866864; Wed, 22 Feb 2023 17:47:46 -0800 (PST) Received: from [192.168.1.101] (abxi151.neoplus.adsl.tpnet.pl. [83.9.2.151]) by smtp.gmail.com with ESMTPSA id 12-20020ac2482c000000b004dc807b904bsm427376lft.120.2023.02.22.17.47.45 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 22 Feb 2023 17:47:46 -0800 (PST) From: Konrad Dybcio Date: Thu, 23 Feb 2023 02:47:42 +0100 Subject: [PATCH v2 6/6] drm/msm/adreno: Enable optional icc voting from OPP tables MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20230223-topic-opp-v2-6-24ed24cd7358@linaro.org> References: <20230223-topic-opp-v2-0-24ed24cd7358@linaro.org> In-Reply-To: <20230223-topic-opp-v2-0-24ed24cd7358@linaro.org> To: Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , David Airlie , Daniel Vetter Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org, Konrad Dybcio X-Mailer: b4 0.12.1 X-Developer-Signature: v=1; a=ed25519-sha256; t=1677116858; l=767; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=lx2DqRTcWzcl/VYcOjFYV+HDGYAZOMxix7RaJuIvTv8=; b=mYkZ7qwqRbSRNaoLVDbG+NeuUgSJomROk/h9vglxkqTqHBuqRkB9BIoLFrYD7vD+bXjLGT7PYIoJ MeljqooSASz7mlvRrVYqcvglbqNK7hJ+uUF4kGeKVT8KaExP5mtI X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add the dev_pm_opp_of_find_icc_paths() call to let the OPP framework handle bus voting as part of power level setting. Signed-off-by: Konrad Dybcio Reviewed-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/adreno/adreno_device.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/gpu/drm/msm/adreno/adreno_device.c b/drivers/gpu/drm/m= sm/adreno/adreno_device.c index 36f062c7582f..5142a4c72cfc 100644 --- a/drivers/gpu/drm/msm/adreno/adreno_device.c +++ b/drivers/gpu/drm/msm/adreno/adreno_device.c @@ -548,6 +548,10 @@ static int adreno_bind(struct device *dev, struct devi= ce *master, void *data) return PTR_ERR(gpu); } =20 + ret =3D dev_pm_opp_of_find_icc_paths(dev, NULL); + if (ret) + return ret; + return 0; } =20 --=20 2.39.2