From nobody Tue Sep 9 22:24:54 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 14409EB64DB for ; Thu, 15 Jun 2023 23:22:15 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S239340AbjFOXWN (ORCPT ); Thu, 15 Jun 2023 19:22:13 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:45970 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S239977AbjFOXVn (ORCPT ); Thu, 15 Jun 2023 19:21:43 -0400 Received: from mail-lf1-x135.google.com (mail-lf1-x135.google.com [IPv6:2a00:1450:4864:20::135]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 66A642D60 for ; Thu, 15 Jun 2023 16:21:35 -0700 (PDT) Received: by mail-lf1-x135.google.com with SMTP id 2adb3069b0e04-4f84d70bf96so225628e87.0 for ; Thu, 15 Jun 2023 16:21:35 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1686871293; x=1689463293; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=FArdX5TBaRtyEgFmzlEIkawN60f/9KNXaxifqatEN80=; b=lgRI1pKr7OarGe1fyPxQD0FW/7BbLSCbjw99ajPlQ4AXC/8BKH4fzG3NyVWIGZmaCp ouvndgXpA3RoP4J35SA7lq8gq3jKIZy2F2SdDwuazvjtJxFZBHLVoogJpo5Y5RHMuO7r Rk//O+izXJp8RAATO1TtwsQgJqEVXpftFhoS8SDOUljc07DbtrYtP+sTJaYeHrKY29SQ rqkn7cKJhmgJL/Jmlywa1Iyoq+YT7vX2JTEJ9zWSuhSRSkm/XIhRxPX37vych/Xe9jJx yqE17KEk0mIKYsdDWT42uc2UufLr21nh5sb7mUtFdqh7wApv4GOcYa1pO78zjyyq4qjA k8/A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1686871293; x=1689463293; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=FArdX5TBaRtyEgFmzlEIkawN60f/9KNXaxifqatEN80=; b=kN7YQl2oEN7dsxcBrcHZ2y/CLxxrcSZrwlf6jjgqzLWK76KHWX2ir2z5HYyb/SJHFY +mQpksY1MpALs+GA+fc++GPrl71O7FPsTfBpLj5O26dAk3ODKBkmeSJvq1torEb104Qa tU97V+ztsSBhAk9ba9TIxLqzObo9vEYKoOumZJgW5eVKlGXnrM2vy5su/oRd7IKszX9Y c4G2iM5XV1hS7E7fGxxMQCIuu3x0hBJO6hPwt4HB0GxyZ83K4LQ5vb1XhL8+ragzKO89 t49DY8jF19jurhZHUiUbRRqHlqyBD4ut6cIRZanypapucqjW3/z/N06ndgDJLjKb1NdN kJ1w== X-Gm-Message-State: AC+VfDzw7FLQ+PCLoYyG/oPQixw5chShXaIVSR0bSFX3/4Vpb9yCq/tu tYykqF4CYszM1ZUsXPBOCNyWnQ== X-Google-Smtp-Source: ACHHUZ4dZM/nJyPupye1DNgW/MA8+4mZrVcoghmRv+dVbxkAZa1IW4UGF3Gqp7gSh/z3n0tUy4+cjw== X-Received: by 2002:a05:6512:3052:b0:4f7:47bb:2ce0 with SMTP id b18-20020a056512305200b004f747bb2ce0mr2000501lfb.4.1686871293575; Thu, 15 Jun 2023 16:21:33 -0700 (PDT) Received: from [192.168.1.101] (abyj190.neoplus.adsl.tpnet.pl. [83.9.29.190]) by smtp.gmail.com with ESMTPSA id u25-20020a056512041900b004f24ee39661sm2744852lfk.137.2023.06.15.16.21.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 15 Jun 2023 16:21:33 -0700 (PDT) From: Konrad Dybcio Date: Fri, 16 Jun 2023 01:20:51 +0200 Subject: [PATCH v9 10/20] drm/msm/a6xx: Extend and explain UBWC config MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20230223-topic-gmuwrapper-v9-10-890d8f470c8b@linaro.org> References: <20230223-topic-gmuwrapper-v9-0-890d8f470c8b@linaro.org> In-Reply-To: <20230223-topic-gmuwrapper-v9-0-890d8f470c8b@linaro.org> To: Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , David Airlie , Daniel Vetter , Rob Herring , Krzysztof Kozlowski , Bjorn Andersson , Konrad Dybcio , Akhil P Oommen , Conor Dooley Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Rob Clark , Marijn Suijten , Konrad Dybcio X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1686871277; l=3228; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=qlz+dGbiTZkptUzjat5pbZCHt/vo5Ur5/uPhfZn2V7s=; b=F1kYVr/t6oi6U8zbpCNcQjOjoB6OhCkl7GfCz02Qa7F0iJcMHIr+3a3NSu5+1zF22s+gNPZLr rNwBjx94vy/Aal7zsS65zU1L0BwciT12/lSgCuhtJRxhMSfuR++Q+B5 X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Rename lower_bit to hbb_lo and explain what it signifies. Add explanations (wherever possible to other tunables). Port setting min_access_length, ubwc_mode and hbb_hi from downstream. Reviewed-by: Rob Clark Reviewed-by: Akhil P Oommen Signed-off-by: Konrad Dybcio --- drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 41 ++++++++++++++++++++++++++-----= ---- 1 file changed, 31 insertions(+), 10 deletions(-) diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/ad= reno/a6xx_gpu.c index 7e0d1dfcd993..8aa4670b4308 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c @@ -887,10 +887,25 @@ static void a6xx_set_cp_protect(struct msm_gpu *gpu) static void a6xx_set_ubwc_config(struct msm_gpu *gpu) { struct adreno_gpu *adreno_gpu =3D to_adreno_gpu(gpu); - u32 lower_bit =3D 2; - u32 amsbc =3D 0; + /* Unknown, introduced with A650 family, related to UBWC mode/ver 4 */ u32 rgb565_predicator =3D 0; + /* Unknown, introduced with A650 family */ u32 uavflagprd_inv =3D 0; + /* Whether the minimum access length is 64 bits */ + u32 min_acc_len =3D 0; + /* Entirely magic, per-GPU-gen value */ + u32 ubwc_mode =3D 0; + /* + * The Highest Bank Bit value represents the bit of the highest DDR bank. + * We then subtract 13 from it (13 is the minimum value allowed by hw) and + * write the lowest two bits of the remaining value as hbb_lo and the + * one above it as hbb_hi to the hardware. This should ideally use DRAM + * type detection. + */ + u32 hbb_hi =3D 0; + u32 hbb_lo =3D 2; + /* Unknown, introduced with A640/680 */ + u32 amsbc =3D 0; =20 /* a618 is using the hw default values */ if (adreno_is_a618(adreno_gpu)) @@ -901,32 +916,38 @@ static void a6xx_set_ubwc_config(struct msm_gpu *gpu) =20 if (adreno_is_a650(adreno_gpu) || adreno_is_a660(adreno_gpu)) { /* TODO: get ddr type from bootloader and use 2 for LPDDR4 */ - lower_bit =3D 3; + hbb_lo =3D 3; amsbc =3D 1; rgb565_predicator =3D 1; uavflagprd_inv =3D 2; } =20 if (adreno_is_a690(adreno_gpu)) { - lower_bit =3D 2; + hbb_lo =3D 2; amsbc =3D 1; rgb565_predicator =3D 1; uavflagprd_inv =3D 2; } =20 if (adreno_is_7c3(adreno_gpu)) { - lower_bit =3D 1; + hbb_lo =3D 1; amsbc =3D 1; rgb565_predicator =3D 1; uavflagprd_inv =3D 2; } =20 gpu_write(gpu, REG_A6XX_RB_NC_MODE_CNTL, - rgb565_predicator << 11 | amsbc << 4 | lower_bit << 1); - gpu_write(gpu, REG_A6XX_TPL1_NC_MODE_CNTL, lower_bit << 1); - gpu_write(gpu, REG_A6XX_SP_NC_MODE_CNTL, - uavflagprd_inv << 4 | lower_bit << 1); - gpu_write(gpu, REG_A6XX_UCHE_MODE_CNTL, lower_bit << 21); + rgb565_predicator << 11 | hbb_hi << 10 | amsbc << 4 | + min_acc_len << 3 | hbb_lo << 1 | ubwc_mode); + + gpu_write(gpu, REG_A6XX_TPL1_NC_MODE_CNTL, hbb_hi << 4 | + min_acc_len << 3 | hbb_lo << 1 | ubwc_mode); + + gpu_write(gpu, REG_A6XX_SP_NC_MODE_CNTL, hbb_hi << 10 | + uavflagprd_inv << 4 | min_acc_len << 3 | + hbb_lo << 1 | ubwc_mode); + + gpu_write(gpu, REG_A6XX_UCHE_MODE_CNTL, min_acc_len << 23 | hbb_lo << 21); } =20 static int a6xx_cp_init(struct msm_gpu *gpu) --=20 2.41.0