From nobody Tue Sep 9 17:14:06 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id C8C88C001DE for ; Thu, 15 Jun 2023 23:21:30 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S237408AbjFOXV3 (ORCPT ); Thu, 15 Jun 2023 19:21:29 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:45538 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229575AbjFOXVZ (ORCPT ); Thu, 15 Jun 2023 19:21:25 -0400 Received: from mail-lf1-x135.google.com (mail-lf1-x135.google.com [IPv6:2a00:1450:4864:20::135]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id B8C05296B for ; Thu, 15 Jun 2023 16:21:21 -0700 (PDT) Received: by mail-lf1-x135.google.com with SMTP id 2adb3069b0e04-4f764e92931so4115037e87.2 for ; Thu, 15 Jun 2023 16:21:21 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1686871280; x=1689463280; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=kMTREHxXwjgBGSRG8kW/LTEJK2OJPvk6iHyZ2GPscdU=; b=Pkb0AK4nFi7hIzVGvRr7NhaNT1nU+GExrpFaq/1jcZWwy6d1QwGae6yYpXyd6mLSSe xhn3HQngxDF4TdIhPMc/zgAMDu7A9zJ4unvX3PGO4Y9O1CfJ7fC4pAFBhdAe15Nmq9Sw 11DDg653oJvXguZj5VPOL2L0PGP5UR8n8dPyzYYbIQDfkgvsiJs4js1xyBAjPII9TQuK agy//jrC4YsV1o8cOmybGHGtWW+G743LVcW7Bq4UIQrgDVU6oJxRMklGwlf6z/Y/PfJc NQNRid0Wf8Hza3VUQettnn0LvOGC4JG9Jb7f1gV0JmfNYScMpIt1I1dia+xppzkrmZl6 +t2w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1686871280; x=1689463280; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=kMTREHxXwjgBGSRG8kW/LTEJK2OJPvk6iHyZ2GPscdU=; b=kGgF0+05vxbGZnxFKLLEjF7K7yQq6H0ou5DRG/chrWnSqsOUMVm8BWEmYc8u5eFqzq NHDP2fIO7yWQ7z1clvLO1dK1SN2f6MsD4suErexLof9wlLumH015nzWNBDYAwljIyOg9 DbMdE1rh4IKZB5VdhJMzPcLDDDfY9J1+68fZvhAm1VjxMcCVYUiCr0Fq9LAbIZXRsCmy T0IhjldnVz3B8kb2divNpMRBNoSHAykBYpG54VfDE4hGBz7lNpIeSpSbnafHCA5V5ycg V0CjKkuq6QSwK8n0f9RXOM2CB15kCXlr6/2KLhkChSfMkrZQ7f+shXmZs0zIloMkGAou WjCA== X-Gm-Message-State: AC+VfDzlllSOJcPscPlddAfc6m6RwPvlg3N6CQhNSAQPPEDTlefCPQRT kPrjZCb8L8TILUOO8aAYIlcong== X-Google-Smtp-Source: ACHHUZ6cNn0JLg7f+Qztkv/PVL4KcCqUQAJq/rv/AEJwrpXQdBTwKQzQhkGZiU6HLycUEYndgLtKEg== X-Received: by 2002:ac2:504f:0:b0:4f5:1ac9:ab1b with SMTP id a15-20020ac2504f000000b004f51ac9ab1bmr105841lfm.23.1686871280052; Thu, 15 Jun 2023 16:21:20 -0700 (PDT) Received: from [192.168.1.101] (abyj190.neoplus.adsl.tpnet.pl. [83.9.29.190]) by smtp.gmail.com with ESMTPSA id u25-20020a056512041900b004f24ee39661sm2744852lfk.137.2023.06.15.16.21.18 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 15 Jun 2023 16:21:19 -0700 (PDT) From: Konrad Dybcio Date: Fri, 16 Jun 2023 01:20:42 +0200 Subject: [PATCH v9 01/20] dt-bindings: display/msm: gpu: Document GMU wrapper-equipped A6xx MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20230223-topic-gmuwrapper-v9-1-890d8f470c8b@linaro.org> References: <20230223-topic-gmuwrapper-v9-0-890d8f470c8b@linaro.org> In-Reply-To: <20230223-topic-gmuwrapper-v9-0-890d8f470c8b@linaro.org> To: Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , David Airlie , Daniel Vetter , Rob Herring , Krzysztof Kozlowski , Bjorn Andersson , Konrad Dybcio , Akhil P Oommen , Conor Dooley Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Rob Clark , Marijn Suijten , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1686871276; l=3381; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=N5wcBgtggmBgTiMxeUpDDPAD+kSRlpLcAHOE+psk1YU=; b=2L8VGdGcd+tRVOs8WnvZF/iqW/m2UxCAWFnh4wAPUO1ZBpxv8CyiNLiwVP4OW7/EX71cOCozF omQYycOxjgNDN5jGLvnuBVrV9L0Zw2A1Tqwr3z26D54lBpWl7tyPVWU X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The "GMU Wrapper" is Qualcomm's name for "let's treat the GPU blocks we'd normally assign to the GMU as if they were a part of the GMU, even though they are not". It's a (good) software representation of the GMU_CX and GMU_GX register spaces within the GPUSS that helps us programatically treat these de-facto GMU-less parts in a way that's very similar to their GMU-equipped cousins, massively saving up on code duplication. The "wrapper" register space was specifically designed to mimic the layout of a real GMU, though it rather obviously does not have the M3 core et al. GMU wrapper-equipped A6xx GPUs require clocks and clock-names to be specified under the GPU node, just like their older cousins. Account for that. Acked-by: Rob Herring Reviewed-by: Krzysztof Kozlowski Signed-off-by: Konrad Dybcio --- .../devicetree/bindings/display/msm/gpu.yaml | 61 ++++++++++++++++++= ---- 1 file changed, 52 insertions(+), 9 deletions(-) diff --git a/Documentation/devicetree/bindings/display/msm/gpu.yaml b/Docum= entation/devicetree/bindings/display/msm/gpu.yaml index 5dabe7b6794b..58ca8912a8c3 100644 --- a/Documentation/devicetree/bindings/display/msm/gpu.yaml +++ b/Documentation/devicetree/bindings/display/msm/gpu.yaml @@ -36,10 +36,7 @@ properties: =20 reg-names: minItems: 1 - items: - - const: kgsl_3d0_reg_memory - - const: cx_mem - - const: cx_dbgc + maxItems: 3 =20 interrupts: maxItems: 1 @@ -157,16 +154,62 @@ allOf: required: - clocks - clock-names + - if: properties: compatible: contains: - pattern: '^qcom,adreno-6[0-9][0-9]\.[0-9]$' - - then: # Since Adreno 6xx series clocks should be defined in GMU + enum: + - qcom,adreno-610.0 + - qcom,adreno-619.1 + then: properties: - clocks: false - clock-names: false + clocks: + minItems: 6 + maxItems: 6 + + clock-names: + items: + - const: core + description: GPU Core clock + - const: iface + description: GPU Interface clock + - const: mem_iface + description: GPU Memory Interface clock + - const: alt_mem_iface + description: GPU Alternative Memory Interface clock + - const: gmu + description: CX GMU clock + - const: xo + description: GPUCC clocksource clock + + reg-names: + minItems: 1 + items: + - const: kgsl_3d0_reg_memory + - const: cx_dbgc + + required: + - clocks + - clock-names + else: + if: + properties: + compatible: + contains: + pattern: '^qcom,adreno-6[0-9][0-9]\.[0-9]$' + + then: # Starting with A6xx, the clocks are usually defined in the GM= U node + properties: + clocks: false + clock-names: false + + reg-names: + minItems: 1 + items: + - const: kgsl_3d0_reg_memory + - const: cx_mem + - const: cx_dbgc =20 examples: - | --=20 2.41.0 From nobody Tue Sep 9 17:14:06 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id B451AEB64D9 for ; Thu, 15 Jun 2023 23:21:34 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S238937AbjFOXVc (ORCPT ); Thu, 15 Jun 2023 19:21:32 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:45554 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234125AbjFOXV0 (ORCPT ); Thu, 15 Jun 2023 19:21:26 -0400 Received: from mail-lf1-x12a.google.com (mail-lf1-x12a.google.com [IPv6:2a00:1450:4864:20::12a]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 4FAB02976 for ; Thu, 15 Jun 2023 16:21:23 -0700 (PDT) Received: by mail-lf1-x12a.google.com with SMTP id 2adb3069b0e04-4f76b6db73fso1633602e87.1 for ; Thu, 15 Jun 2023 16:21:23 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1686871281; x=1689463281; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=/+hkbAri//BlmjhG5C13xznJ13y0IFu3pr4Lxy+kSnM=; b=KlaWt6x7aAj7+SBdcV04Iz+74Ych6deBH7VFnQUkQlX7+baOBeOUKk/7B5QuZn6QfP 44qKQ6Qu3Af/DlWBTmVSXjaENkete7Np0d5mvuqxC44DV1bv4da5Kl0MbpfLGU2GJhW/ hq6lUoFMB/x122ujrh8WL99DdF2xR2acsm2KT0wwiDwRypUISxqlAkXInxs604YbpD61 T3qSD5gUdMqoOzTMf4K87ij3aKD7G59k5N6JHpeztbgkpDscJ5LpVpm/CX7qKrS3Rfzt Q6uywodd/LI+pPSzqq9iO7Mr4DJjUsWmuWHZNexK9EDOx0oq2sJTok24OoGxhpW2NdBF KU9A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1686871281; x=1689463281; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=/+hkbAri//BlmjhG5C13xznJ13y0IFu3pr4Lxy+kSnM=; b=HFi+hg16B+UYHLSxKva9OgD7vTRcMOsXtzFSE5OLHu4kqBfH1EZ47EGZhtvGPJO7wC TV4ihDpa0yJlKId9LqWfmDCjvafNqFSnLKrT+zOkPQ1/9zn5KoALiujaPy2TUekAb+vl +sefTu45NyYh9XSpE9cgl3liUQ28XVz67b+Gc9HLXa/E2CwFTOk+tFDr9emHcoxUrbsO ZgXpEx8U6RkIxIhwH3Hl6DSVeJxVwI4NkjxNUY/AubJMYPtK02Avg6/rnrGzu8RkQ2SX nK79SV4M68ZWSMT18z4xProulVNhIKspCzKU/jvAsLwrNuJcAPTYKN2Jjz63M5iPOTqW UbOA== X-Gm-Message-State: AC+VfDwuMXN+JZxKMdDFu5zHop13YvJS7jlV++C72xUY1Ds0BGPCFfYk sTAdf8TOwZUdIYc02JFLr5JAWQ== X-Google-Smtp-Source: ACHHUZ6cSB8YJVrvHIc83G4NChVLheO9dHRX52H1y9zHy1/cPyECH0I9RwJrE+BA5Njaxv07qT5+Qg== X-Received: by 2002:a19:e00b:0:b0:4f4:d60a:e387 with SMTP id x11-20020a19e00b000000b004f4d60ae387mr84771lfg.1.1686871281582; Thu, 15 Jun 2023 16:21:21 -0700 (PDT) Received: from [192.168.1.101] (abyj190.neoplus.adsl.tpnet.pl. [83.9.29.190]) by smtp.gmail.com with ESMTPSA id u25-20020a056512041900b004f24ee39661sm2744852lfk.137.2023.06.15.16.21.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 15 Jun 2023 16:21:21 -0700 (PDT) From: Konrad Dybcio Date: Fri, 16 Jun 2023 01:20:43 +0200 Subject: [PATCH v9 02/20] dt-bindings: display/msm/gmu: Add GMU wrapper MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20230223-topic-gmuwrapper-v9-2-890d8f470c8b@linaro.org> References: <20230223-topic-gmuwrapper-v9-0-890d8f470c8b@linaro.org> In-Reply-To: <20230223-topic-gmuwrapper-v9-0-890d8f470c8b@linaro.org> To: Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , David Airlie , Daniel Vetter , Rob Herring , Krzysztof Kozlowski , Bjorn Andersson , Konrad Dybcio , Akhil P Oommen , Conor Dooley Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Rob Clark , Marijn Suijten , Konrad Dybcio , Krzysztof Kozlowski X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1686871276; l=3381; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=kd2GL+6kraj/R4RcWEcOPoUZnK/8zjl8aP1uEdr4Jxs=; b=oKWG53vY0+XycscfurpAfhUB4q16s5rgIDgZnpjg7eX13Dok/I5J71dx54iJ/ulPCAy2UEqB1 SWnBGcA0s2zDfi/ydcGRAhpQt2iB4UBaegkM+tlvgDZvZONtSBYkr9p X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The "GMU Wrapper" is Qualcomm's name for "let's treat the GPU blocks we'd normally assign to the GMU as if they were a part of the GMU, even though they are not". It's a (good) software representation of the GMU_CX and GMU_GX register spaces within the GPUSS that helps us programatically treat these de-facto GMU-less parts in a way that's very similar to their GMU-equipped cousins, massively saving up on code duplication. The "wrapper" register space was specifically designed to mimic the layout of a real GMU, though it rather obviously does not have the M3 core et al. To sum it all up, the GMU wrapper is essentially a register space within the GPU, which Linux sees as a dumbed-down regular GMU: there's no clocks, interrupts, multiple reg spaces, iommus and OPP. Document it. Reviewed-by: Krzysztof Kozlowski Signed-off-by: Konrad Dybcio --- .../devicetree/bindings/display/msm/gmu.yaml | 50 ++++++++++++++++--= ---- 1 file changed, 38 insertions(+), 12 deletions(-) diff --git a/Documentation/devicetree/bindings/display/msm/gmu.yaml b/Docum= entation/devicetree/bindings/display/msm/gmu.yaml index f31a26305ca9..5fc4106110ad 100644 --- a/Documentation/devicetree/bindings/display/msm/gmu.yaml +++ b/Documentation/devicetree/bindings/display/msm/gmu.yaml @@ -19,16 +19,18 @@ description: | =20 properties: compatible: - items: - - pattern: '^qcom,adreno-gmu-6[0-9][0-9]\.[0-9]$' - - const: qcom,adreno-gmu + oneOf: + - items: + - pattern: '^qcom,adreno-gmu-6[0-9][0-9]\.[0-9]$' + - const: qcom,adreno-gmu + - const: qcom,adreno-gmu-wrapper =20 reg: - minItems: 3 + minItems: 1 maxItems: 4 =20 reg-names: - minItems: 3 + minItems: 1 maxItems: 4 =20 clocks: @@ -44,7 +46,6 @@ properties: - description: GMU HFI interrupt - description: GMU interrupt =20 - interrupt-names: items: - const: hfi @@ -72,14 +73,8 @@ required: - compatible - reg - reg-names - - clocks - - clock-names - - interrupts - - interrupt-names - power-domains - power-domain-names - - iommus - - operating-points-v2 =20 additionalProperties: false =20 @@ -218,6 +213,28 @@ allOf: - const: axi - const: memnoc =20 + - if: + properties: + compatible: + contains: + const: qcom,adreno-gmu-wrapper + then: + properties: + reg: + items: + - description: GMU wrapper register space + reg-names: + items: + - const: gmu + else: + required: + - clocks + - clock-names + - interrupts + - interrupt-names + - iommus + - operating-points-v2 + examples: - | #include @@ -250,3 +267,12 @@ examples: iommus =3D <&adreno_smmu 5>; operating-points-v2 =3D <&gmu_opp_table>; }; + + gmu_wrapper: gmu@596a000 { + compatible =3D "qcom,adreno-gmu-wrapper"; + reg =3D <0x0596a000 0x30000>; + reg-names =3D "gmu"; + power-domains =3D <&gpucc GPU_CX_GDSC>, + <&gpucc GPU_GX_GDSC>; + power-domain-names =3D "cx", "gx"; + }; --=20 2.41.0 From nobody Tue Sep 9 17:14:06 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id BC4DFEB64DA for ; Thu, 15 Jun 2023 23:21:36 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S239043AbjFOXVf (ORCPT ); Thu, 15 Jun 2023 19:21:35 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:45572 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232578AbjFOXV1 (ORCPT ); Thu, 15 Jun 2023 19:21:27 -0400 Received: from mail-lf1-x12d.google.com (mail-lf1-x12d.google.com [IPv6:2a00:1450:4864:20::12d]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id A99A0296A for ; Thu, 15 Jun 2023 16:21:24 -0700 (PDT) Received: by mail-lf1-x12d.google.com with SMTP id 2adb3069b0e04-4f845060481so1674107e87.3 for ; Thu, 15 Jun 2023 16:21:24 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1686871283; x=1689463283; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=6a1QMmj81oXqiu8nN+luqgMSndStx7gXh0gMxhBOOQU=; b=bnm2oqpcOD3oUBEBY4/+9G1rwJOOkHaxxb/MKoOlS4zT4IbznR7AYXh0nexgmiF0kn 48BtXsBNuWaURsK/FTEBnbFS0YgaiRKrqmaBxyogMz8Vqk0WWSpXlrhUMJzAJh3oC3Tj vNjjaDKIcaNzlJwqrN8gWI9gUOgTdBnErOuzlHmdw9qCH+lf/cpnEhM7byVE5JkW+SPq tXtnGauYGKhHfUc86ZTEyectBvgAxdZxR/96uSzNYzH4oIXDOvWDTS/wG+WFbZ6hWqPV QY3WJdWZ3wR4xzNi8c71vFo2VIyAmaqcXZikCaT5YhuDWsjTO8T4fmUDnRtE33ihgbng YjrA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1686871283; x=1689463283; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=6a1QMmj81oXqiu8nN+luqgMSndStx7gXh0gMxhBOOQU=; b=JZplTgiOldm/euuwOEYATTgAx43sc9y2skPY1T946bd6xNAua7h9zW+LpXZ/maZHWo W/2VfuhEvgGzioP6/uHEsbbh+is2hxlGgA1iOCIkwP9WzsfAIpM7iACYf+GjNKvo3huZ NAkWb7NH+MEj7sARkIedr3NyPZSccXwW0Z2de7cAaIGHejdY2q4uxdlgZ4IVHv5/Jqbc PFDR2ZMFWuWqlU8liVSvxibQ6I3NFc5mj86AmLmFobU/KF+HeCfx3LEf3PNSszWc1Rc/ 3z2pizPcd0LC0dZv+9coTNEM7Z3QDdH/VgkQ5b9vWz2qYANLT6JEumjqMQngPPZ4IYKo AKBQ== X-Gm-Message-State: AC+VfDwUOGTE1Y49NfjkWUUYO3BARZsRoXyWBvcDCWmz3B1c67mgu1hD 6Lr+8T7tJROZ7QP06hwQW9K82Q== X-Google-Smtp-Source: ACHHUZ4YEcCeVa8ugJonftGODrNlpJM5dJgZg94FEbXaKFQpvvxHse3N3U7BrVsY6xiGjq6JVIYaBQ== X-Received: by 2002:a19:5f15:0:b0:4f3:92a9:aa06 with SMTP id t21-20020a195f15000000b004f392a9aa06mr70560lfb.48.1686871282945; Thu, 15 Jun 2023 16:21:22 -0700 (PDT) Received: from [192.168.1.101] (abyj190.neoplus.adsl.tpnet.pl. [83.9.29.190]) by smtp.gmail.com with ESMTPSA id u25-20020a056512041900b004f24ee39661sm2744852lfk.137.2023.06.15.16.21.21 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 15 Jun 2023 16:21:22 -0700 (PDT) From: Konrad Dybcio Date: Fri, 16 Jun 2023 01:20:44 +0200 Subject: [PATCH v9 03/20] drm/msm/adreno: Use adreno_is_revn for A690 MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20230223-topic-gmuwrapper-v9-3-890d8f470c8b@linaro.org> References: <20230223-topic-gmuwrapper-v9-0-890d8f470c8b@linaro.org> In-Reply-To: <20230223-topic-gmuwrapper-v9-0-890d8f470c8b@linaro.org> To: Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , David Airlie , Daniel Vetter , Rob Herring , Krzysztof Kozlowski , Bjorn Andersson , Konrad Dybcio , Akhil P Oommen , Conor Dooley Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Rob Clark , Marijn Suijten , Konrad Dybcio X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1686871276; l=824; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=zkQglxSAYJ6XB8sCRIg7Jh2Ryhgw+vFHA/mfzuc8H1A=; b=97c9wz7gJsAfoY56WRmkvESFippkdb670pINXb4BLBXtrNr+y4CB2brw3RN31wQvf5iaVN4AH DITwGzQ0X3ZBxOJeLPRD/Q42Dk0XxQhL0jDuD39KPtAKI+sfROBTHBl X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The adreno_is_revn rework came at the same time as A690 introduction and that resulted in it not covering all cases. Fix it. Signed-off-by: Konrad Dybcio --- drivers/gpu/drm/msm/adreno/adreno_gpu.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.h b/drivers/gpu/drm/msm/= adreno/adreno_gpu.h index 9a7626c7ac4d..5a26c8a2de7c 100644 --- a/drivers/gpu/drm/msm/adreno/adreno_gpu.h +++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.h @@ -286,7 +286,7 @@ static inline int adreno_is_a660(const struct adreno_gp= u *gpu) =20 static inline int adreno_is_a690(const struct adreno_gpu *gpu) { - return gpu->revn =3D=3D 690; + return adreno_is_revn(gpu, 690); }; =20 /* check for a615, a616, a618, a619 or any derivatives */ --=20 2.41.0 From nobody Tue Sep 9 17:14:06 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7075BEB64DA for ; Thu, 15 Jun 2023 23:21:46 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S239130AbjFOXVo (ORCPT ); Thu, 15 Jun 2023 19:21:44 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:45602 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S238338AbjFOXV2 (ORCPT ); Thu, 15 Jun 2023 19:21:28 -0400 Received: from mail-lf1-x131.google.com (mail-lf1-x131.google.com [IPv6:2a00:1450:4864:20::131]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 63CBF2965 for ; Thu, 15 Jun 2023 16:21:26 -0700 (PDT) Received: by mail-lf1-x131.google.com with SMTP id 2adb3069b0e04-4f611ac39c5so11608782e87.2 for ; Thu, 15 Jun 2023 16:21:26 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1686871284; x=1689463284; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=CL+aFMA9fwhg/LbwUl6UjJh2esp/SEji7J1FzzytEtk=; b=jlkcU1bfEJLvocxXC2RxBFFxEakGyR2g4Huz9UGfH01M44XSZfu1mt3O/JGxCwApbe LEPX+8XkHbQ2vcesKLM8SZK+oOHjSy/MLt3ZcbqMMrweMD6+wBvchB5sY+Zu+wJ9nzVa M1p1E9D9MugEciVPLNoPikUTwvaxhMkjyHiuY8l5zWHaSNVrIXTdKSBOv8zsKk+DYmAK Ae0KjlrZYC6GQtH87OoFcZMdOtx6o+Rkbcrwcf4ncAJO67hp/+IHzlO6eCjcPuxE981V R1o684RkEZQ39cT6CFT+JbuUxDE4/WmEtmk+qQeGc+GWpDt0M5XVCuVcVxAFaOS05d8O dK8g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1686871284; x=1689463284; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=CL+aFMA9fwhg/LbwUl6UjJh2esp/SEji7J1FzzytEtk=; b=THrWXVx17tADvSPP2CTIkCo/xUkPwfweuYNpqkEAKPRpOYHOVLMbRGaq6hsyMYA4up inmhmmMcTRbbshi5w/kvzYHLdzb0XTFqOagfuX2PeV7ZDa27nA0YQ8YRyLsT7yP8Bj+3 z6k4Ui6th7rqkaPbiyBmhWKzF8iHa4be7BW8Ej4cZZHPOmsmAp343I9kolrUBiB8KuQf xDg/fTCs3BIUn4bpFDpj1edDoucK2ZyFqmuVhWI0HDEh4D2EWagif7otkhYKxg8x41fL IjdQ+CWVBVjfMDQVI2WTX+rn1jbRgJrwmuqXrTo/ZwwCiW4pBQC/a57lRlJ9gWstefC2 6FOw== X-Gm-Message-State: AC+VfDzu25g1qecfztFa3vX86uBNW3pVXxCt49UGz5pz47aJS+R8FrcV 9Uf070RyXGvasw7zYbBk0ucczQ== X-Google-Smtp-Source: ACHHUZ654L+xLoxzbpZrN7wTbIP6nc5g8iVTMMyggUCWw4rPCgIvY/jBK10Ib0eDVRDEbx1IlO2N6Q== X-Received: by 2002:a19:911e:0:b0:4f1:1de7:1aac with SMTP id t30-20020a19911e000000b004f11de71aacmr95299lfd.20.1686871284648; Thu, 15 Jun 2023 16:21:24 -0700 (PDT) Received: from [192.168.1.101] (abyj190.neoplus.adsl.tpnet.pl. [83.9.29.190]) by smtp.gmail.com with ESMTPSA id u25-20020a056512041900b004f24ee39661sm2744852lfk.137.2023.06.15.16.21.23 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 15 Jun 2023 16:21:24 -0700 (PDT) From: Konrad Dybcio Date: Fri, 16 Jun 2023 01:20:45 +0200 Subject: [PATCH v9 04/20] drm/msm/a6xx: Remove static keyword from sptprac en/disable functions MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20230223-topic-gmuwrapper-v9-4-890d8f470c8b@linaro.org> References: <20230223-topic-gmuwrapper-v9-0-890d8f470c8b@linaro.org> In-Reply-To: <20230223-topic-gmuwrapper-v9-0-890d8f470c8b@linaro.org> To: Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , David Airlie , Daniel Vetter , Rob Herring , Krzysztof Kozlowski , Bjorn Andersson , Konrad Dybcio , Akhil P Oommen , Conor Dooley Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Rob Clark , Marijn Suijten , Konrad Dybcio X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1686871276; l=1711; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=iPYRkIYnCMZbHrTlhZfW6CMBHZeM6Q89aR8VM/+J45c=; b=VAHlqWYfQ+1RKxETxDudvSOyIiT84B2tMY7nZpZZURe50LpIFLk5HeH/NsxAACZM4X8oHqSY5 WJSumb2TQlkA2XltW4oKghz8H+9CHPltCT0HZWa8UbhwsUB050g6UZX X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org These two will be reused by at least A619_holi in the non-gmu paths. Turn them non-static them to make it possible. Reviewed-by: Dmitry Baryshkov Signed-off-by: Konrad Dybcio --- drivers/gpu/drm/msm/adreno/a6xx_gmu.c | 4 ++-- drivers/gpu/drm/msm/adreno/a6xx_gmu.h | 2 ++ 2 files changed, 4 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c b/drivers/gpu/drm/msm/ad= reno/a6xx_gmu.c index 8914992378f2..a6fa273d700e 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_gmu.c @@ -354,7 +354,7 @@ void a6xx_gmu_clear_oob(struct a6xx_gmu *gmu, enum a6xx= _gmu_oob_state state) } =20 /* Enable CPU control of SPTP power power collapse */ -static int a6xx_sptprac_enable(struct a6xx_gmu *gmu) +int a6xx_sptprac_enable(struct a6xx_gmu *gmu) { int ret; u32 val; @@ -376,7 +376,7 @@ static int a6xx_sptprac_enable(struct a6xx_gmu *gmu) } =20 /* Disable CPU control of SPTP power power collapse */ -static void a6xx_sptprac_disable(struct a6xx_gmu *gmu) +void a6xx_sptprac_disable(struct a6xx_gmu *gmu) { u32 val; int ret; diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gmu.h b/drivers/gpu/drm/msm/ad= reno/a6xx_gmu.h index 4759a8ce51e4..236f81a43caa 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gmu.h +++ b/drivers/gpu/drm/msm/adreno/a6xx_gmu.h @@ -193,5 +193,7 @@ int a6xx_hfi_set_freq(struct a6xx_gmu *gmu, int index); =20 bool a6xx_gmu_gx_is_on(struct a6xx_gmu *gmu); bool a6xx_gmu_sptprac_is_on(struct a6xx_gmu *gmu); +void a6xx_sptprac_disable(struct a6xx_gmu *gmu); +int a6xx_sptprac_enable(struct a6xx_gmu *gmu); =20 #endif --=20 2.41.0 From nobody Tue Sep 9 17:14:06 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 08FCFC001DC for ; Thu, 15 Jun 2023 23:21:54 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S239601AbjFOXVw (ORCPT ); Thu, 15 Jun 2023 19:21:52 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:45618 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S238762AbjFOXV3 (ORCPT ); Thu, 15 Jun 2023 19:21:29 -0400 Received: from mail-lf1-x129.google.com (mail-lf1-x129.google.com [IPv6:2a00:1450:4864:20::129]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id B0CCD2967 for ; Thu, 15 Jun 2023 16:21:27 -0700 (PDT) Received: by mail-lf1-x129.google.com with SMTP id 2adb3069b0e04-4f764e9295dso5967e87.0 for ; Thu, 15 Jun 2023 16:21:27 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1686871286; x=1689463286; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=BuB9Tj3lhLuLPP+OSus2KoxyF5MNAI7rxRyrL+OaBKk=; b=GDx3/ylhlFGa+u4e1N3K/H12cWZd+STzURGDfpkc6kaomxVp4hEY+L/MuM3/S7+4jR a5H/GootRG2UGQ/8SqE8aETxYZWmQ4ylO1fp2MLlkHu0UTF/RNcSHlTzTtAoSCZG3172 Gj3SOfT9AX9nGPl1/eoufZfvQzsE+LB4dm7hf4bjk6upU+GnVnTUrdWTkiihBubFcoyE qFPXjqf7bXkf00jx6hf27nZ5WdIEQHJdRBRxig/iFiLW/IGH1YTYpQVCSXoLtV+5sH0U 8zI665p+7BHWqa0hdqY1NpURj9oK+bPMZdts8jXuURgLQxkO7xmgC/rk2eSbtmgugpzp zJ6g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1686871286; x=1689463286; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=BuB9Tj3lhLuLPP+OSus2KoxyF5MNAI7rxRyrL+OaBKk=; b=H7wLTeGuu62a9mHAVmpFPWgCjogLsN3M3HIylo1YMSIjOV5HSWk/JYXcwyRFKtFGKT AfRGmO9CyrPecHAxIZsR4i/FNsYXPH8O2gpg7o4AhkKuGWfF8EX02XdbVysUGqjjoWcn PlIxR3hEF32Fw3uUhHZTEPxDgxoE+O9o4pB5weHnOE1jRNXiGh/NJooiID+UI6utBUsM naXpiHZjyojaI/Kid4whupDSA7+SpEOlBqcE+qrkcTLItKzsBhH5ZUa9KeR9R7/p5TL/ WPMJN9cQOa0RW8HAFIJZKn7ja3O+F7xGBAb1j2QUwmhkIdcUZssHUEwNcyD6JQ7ozwSV cOWQ== X-Gm-Message-State: AC+VfDy7Jo8ZfRicbHzDQBqAreEO+OT8oy4QMW0FZgTpGhvm2Yxjp/W7 VGox9f2gk+dnd/2VL+nxtfeF0A== X-Google-Smtp-Source: ACHHUZ6qqy7E6+dgcsRnv7PEHpaoEppzdnx/yQvZi5dMEO8auG//UfDcm1ESF0ZrJklWWvabJvsqXg== X-Received: by 2002:a19:6446:0:b0:4e9:bafc:88d0 with SMTP id b6-20020a196446000000b004e9bafc88d0mr89551lfj.23.1686871286122; Thu, 15 Jun 2023 16:21:26 -0700 (PDT) Received: from [192.168.1.101] (abyj190.neoplus.adsl.tpnet.pl. [83.9.29.190]) by smtp.gmail.com with ESMTPSA id u25-20020a056512041900b004f24ee39661sm2744852lfk.137.2023.06.15.16.21.24 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 15 Jun 2023 16:21:25 -0700 (PDT) From: Konrad Dybcio Date: Fri, 16 Jun 2023 01:20:46 +0200 Subject: [PATCH v9 05/20] drm/msm/a6xx: Move force keepalive vote removal to a6xx_gmu_force_off() MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20230223-topic-gmuwrapper-v9-5-890d8f470c8b@linaro.org> References: <20230223-topic-gmuwrapper-v9-0-890d8f470c8b@linaro.org> In-Reply-To: <20230223-topic-gmuwrapper-v9-0-890d8f470c8b@linaro.org> To: Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , David Airlie , Daniel Vetter , Rob Herring , Krzysztof Kozlowski , Bjorn Andersson , Konrad Dybcio , Akhil P Oommen , Conor Dooley Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Rob Clark , Marijn Suijten , Konrad Dybcio X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1686871276; l=2130; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=9KH8lCaBgwLdxlAk0sWl81+4/n3YOG4pQpo7CFNSD30=; b=9I90MQDfdyQD1tgytuAf4T635fSPxOaRHR0iUUkSaqqzxaiqMM/ikfVBEXm8Z/0e5DP5NI2Uv ng1kN10ljNYBrzxRTEqkpvE2NsWqcNDJU79yMENtfElLz6VGwn47jr6 X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org As pointed out by Akhil during the review process of GMU wrapper introduction [1], it makes sense to move this write into the function that's responsible for forcibly shutting the GMU off. It is also very convenient to move this to GMU-specific code, so that it does not have to be guarded by an if-condition to avoid calling it on GMU wrapper targets. Move the write to the aforementioned a6xx_gmu_force_off() to achieve that. No effective functional change. [1] https://lore.kernel.org/linux-arm-msm/20230501194022.GA18382@akhilpo-li= nux.qualcomm.com/ Reviewed-by: Akhil P Oommen Signed-off-by: Konrad Dybcio --- drivers/gpu/drm/msm/adreno/a6xx_gmu.c | 6 ++++++ drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 6 ------ 2 files changed, 6 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c b/drivers/gpu/drm/msm/ad= reno/a6xx_gmu.c index a6fa273d700e..32852c161aab 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_gmu.c @@ -912,6 +912,12 @@ static void a6xx_gmu_force_off(struct a6xx_gmu *gmu) struct adreno_gpu *adreno_gpu =3D &a6xx_gpu->base; struct msm_gpu *gpu =3D &adreno_gpu->base; =20 + /* + * Turn off keep alive that might have been enabled by the hang + * interrupt + */ + gmu_write(&a6xx_gpu->gmu, REG_A6XX_GMU_GMU_PWR_COL_KEEPALIVE, 0); + /* Flush all the queues */ a6xx_hfi_stop(gmu); =20 diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/ad= reno/a6xx_gpu.c index ab5c446e4409..eebb4bc7c0f9 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c @@ -1382,12 +1382,6 @@ static void a6xx_recover(struct msm_gpu *gpu) /* Halt SQE first */ gpu_write(gpu, REG_A6XX_CP_SQE_CNTL, 3); =20 - /* - * Turn off keep alive that might have been enabled by the hang - * interrupt - */ - gmu_write(&a6xx_gpu->gmu, REG_A6XX_GMU_GMU_PWR_COL_KEEPALIVE, 0); - pm_runtime_dont_use_autosuspend(&gpu->pdev->dev); =20 /* active_submit won't change until we make a submission */ --=20 2.41.0 From nobody Tue Sep 9 17:14:06 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id C3B91EB64D9 for ; Thu, 15 Jun 2023 23:22:07 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S239272AbjFOXWG (ORCPT ); Thu, 15 Jun 2023 19:22:06 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:45880 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S239068AbjFOXVl (ORCPT ); Thu, 15 Jun 2023 19:21:41 -0400 Received: from mail-lf1-x135.google.com (mail-lf1-x135.google.com [IPv6:2a00:1450:4864:20::135]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 887F12972 for ; Thu, 15 Jun 2023 16:21:29 -0700 (PDT) Received: by mail-lf1-x135.google.com with SMTP id 2adb3069b0e04-4f762b3227dso256518e87.1 for ; Thu, 15 Jun 2023 16:21:29 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1686871288; x=1689463288; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=VdelOgpuK3XacSGUaivE1M7Dtjzj0Im9GIbVnmMBHAI=; b=fwMjNHV8C5nXO8bPmPoAb20mcUZa+AOFrkxPgzS0kC57dPb3d5cMn0aehR9t0ZLmbK JTiyTBpqZEXXhdNbOoAzE1CMuWrau9s2wN/EOeHmtFSq2aO7H/CCkB+brJKZAeN29Afr 4uJs/mt+NvoCBHGayJX5Xn3S7LZzUvVO2h4Y+8EiqG7aRyN7Z8tJuqGIVzXzQnHMrhyI cqZTIne0j09rd8mzdkMqwDpptedKMXJBtefHPoHY3kvCWpXpcgI3jpIMIYj6B7pFUD/e uoGPO0H0yljadwsqzaQ93YdomBGnrJwbU5Pph9HNSPwjo5ITYhTvm6xL8+G82eYajin8 hGEQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1686871288; x=1689463288; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=VdelOgpuK3XacSGUaivE1M7Dtjzj0Im9GIbVnmMBHAI=; b=L8Qhju587tRBPs5y1HbkC4uuYlK/IsDQ6vSrJXsj2394a6jEGLxhWJwVgJiRrAOlA4 PW/tsJJ2AKyhrE0lOR0JMwuxSBn+GBrXNa7IotWWFLyk2ElD4NOFA+ozoPayKKkxOJ4L IXdB468j2tKcXIaurnV5F7sjSGwf4qN8KVyiGnTxWb3wlkVdbvTfsH4VcXhrF0m2AKBT kCI5GfFezkWwlZRqf6K+M3M8PjWtdenvCLUZq7wcBUAWBOyNpYYLJ3Ix9mVDz1nhAgfi Lhg6UR8nOmEXaywCmGtMnuCqaofSjhxBmbyn9VCNc+VXYB14hpWj6LJyTavmwVMETBQw a2Kg== X-Gm-Message-State: AC+VfDwsTPZyc0IZ2AyKc9ErjBNwbFdEnuoUBTIeNvHiBzGnXLDHt4w4 /VSSjescacEsODo7VtqIlSfhfA== X-Google-Smtp-Source: ACHHUZ4gYgm8y3d78Ar5R5M9B+KlPNlCGKZowaamYleHcxabm31ozYxTOc2Zudlx2F7TIsoZc7rjQQ== X-Received: by 2002:a19:e341:0:b0:4f1:2ebf:536f with SMTP id c1-20020a19e341000000b004f12ebf536fmr63508lfk.16.1686871287800; Thu, 15 Jun 2023 16:21:27 -0700 (PDT) Received: from [192.168.1.101] (abyj190.neoplus.adsl.tpnet.pl. [83.9.29.190]) by smtp.gmail.com with ESMTPSA id u25-20020a056512041900b004f24ee39661sm2744852lfk.137.2023.06.15.16.21.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 15 Jun 2023 16:21:27 -0700 (PDT) From: Konrad Dybcio Date: Fri, 16 Jun 2023 01:20:47 +0200 Subject: [PATCH v9 06/20] drm/msm/a6xx: Move a6xx_bus_clear_pending_transactions to a6xx_gpu MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20230223-topic-gmuwrapper-v9-6-890d8f470c8b@linaro.org> References: <20230223-topic-gmuwrapper-v9-0-890d8f470c8b@linaro.org> In-Reply-To: <20230223-topic-gmuwrapper-v9-0-890d8f470c8b@linaro.org> To: Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , David Airlie , Daniel Vetter , Rob Herring , Krzysztof Kozlowski , Bjorn Andersson , Konrad Dybcio , Akhil P Oommen , Conor Dooley Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Rob Clark , Marijn Suijten , Konrad Dybcio X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1686871277; l=4596; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=Du7BRzmQsw5lwzfigmccIbHnHbypFGrfE8cKEgMRcLA=; b=5mb8ok8pQk2TM4oNRuuBYYgw0XKe4Y1lGERaQ7pd0r1T6fekl5TW7pD1CgliPFmqxe2aeAbJJ P6dnhKmYTeOC0HTvH0XtRIBN37rzwY3fKPL0isfg3m3L5u0cFj6GNSW X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org This function is responsible for telling the GPU to halt transactions on all of its relevant buses, drain them and leave them in a predictable state, so that the GPU can be e.g. reset cleanly. Move the function to a6xx_gpu.c, remove the static keyword and add a prototype in a6xx_gpu.h to accomodate for the move. Reviewed-by: Akhil P Oommen Signed-off-by: Konrad Dybcio --- drivers/gpu/drm/msm/adreno/a6xx_gmu.c | 37 -------------------------------= ---- drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 36 +++++++++++++++++++++++++++++++= +++ drivers/gpu/drm/msm/adreno/a6xx_gpu.h | 2 ++ 3 files changed, 38 insertions(+), 37 deletions(-) diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c b/drivers/gpu/drm/msm/ad= reno/a6xx_gmu.c index 32852c161aab..6402544f6849 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_gmu.c @@ -868,43 +868,6 @@ static void a6xx_gmu_rpmh_off(struct a6xx_gmu *gmu) (val & 1), 100, 1000); } =20 -#define GBIF_CLIENT_HALT_MASK BIT(0) -#define GBIF_ARB_HALT_MASK BIT(1) - -static void a6xx_bus_clear_pending_transactions(struct adreno_gpu *adreno_= gpu, - bool gx_off) -{ - struct msm_gpu *gpu =3D &adreno_gpu->base; - - if (!a6xx_has_gbif(adreno_gpu)) { - gpu_write(gpu, REG_A6XX_VBIF_XIN_HALT_CTRL0, 0xf); - spin_until((gpu_read(gpu, REG_A6XX_VBIF_XIN_HALT_CTRL1) & - 0xf) =3D=3D 0xf); - gpu_write(gpu, REG_A6XX_VBIF_XIN_HALT_CTRL0, 0); - - return; - } - - if (gx_off) { - /* Halt the gx side of GBIF */ - gpu_write(gpu, REG_A6XX_RBBM_GBIF_HALT, 1); - spin_until(gpu_read(gpu, REG_A6XX_RBBM_GBIF_HALT_ACK) & 1); - } - - /* Halt new client requests on GBIF */ - gpu_write(gpu, REG_A6XX_GBIF_HALT, GBIF_CLIENT_HALT_MASK); - spin_until((gpu_read(gpu, REG_A6XX_GBIF_HALT_ACK) & - (GBIF_CLIENT_HALT_MASK)) =3D=3D GBIF_CLIENT_HALT_MASK); - - /* Halt all AXI requests on GBIF */ - gpu_write(gpu, REG_A6XX_GBIF_HALT, GBIF_ARB_HALT_MASK); - spin_until((gpu_read(gpu, REG_A6XX_GBIF_HALT_ACK) & - (GBIF_ARB_HALT_MASK)) =3D=3D GBIF_ARB_HALT_MASK); - - /* The GBIF halt needs to be explicitly cleared */ - gpu_write(gpu, REG_A6XX_GBIF_HALT, 0x0); -} - /* Force the GMU off in case it isn't responsive */ static void a6xx_gmu_force_off(struct a6xx_gmu *gmu) { diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/ad= reno/a6xx_gpu.c index eebb4bc7c0f9..a48f4e3a754a 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c @@ -1705,6 +1705,42 @@ static void a6xx_llc_slices_init(struct platform_dev= ice *pdev, a6xx_gpu->llc_mmio =3D ERR_PTR(-EINVAL); } =20 +#define GBIF_CLIENT_HALT_MASK BIT(0) +#define GBIF_ARB_HALT_MASK BIT(1) + +void a6xx_bus_clear_pending_transactions(struct adreno_gpu *adreno_gpu, bo= ol gx_off) +{ + struct msm_gpu *gpu =3D &adreno_gpu->base; + + if (!a6xx_has_gbif(adreno_gpu)) { + gpu_write(gpu, REG_A6XX_VBIF_XIN_HALT_CTRL0, 0xf); + spin_until((gpu_read(gpu, REG_A6XX_VBIF_XIN_HALT_CTRL1) & + 0xf) =3D=3D 0xf); + gpu_write(gpu, REG_A6XX_VBIF_XIN_HALT_CTRL0, 0); + + return; + } + + if (gx_off) { + /* Halt the gx side of GBIF */ + gpu_write(gpu, REG_A6XX_RBBM_GBIF_HALT, 1); + spin_until(gpu_read(gpu, REG_A6XX_RBBM_GBIF_HALT_ACK) & 1); + } + + /* Halt new client requests on GBIF */ + gpu_write(gpu, REG_A6XX_GBIF_HALT, GBIF_CLIENT_HALT_MASK); + spin_until((gpu_read(gpu, REG_A6XX_GBIF_HALT_ACK) & + (GBIF_CLIENT_HALT_MASK)) =3D=3D GBIF_CLIENT_HALT_MASK); + + /* Halt all AXI requests on GBIF */ + gpu_write(gpu, REG_A6XX_GBIF_HALT, GBIF_ARB_HALT_MASK); + spin_until((gpu_read(gpu, REG_A6XX_GBIF_HALT_ACK) & + (GBIF_ARB_HALT_MASK)) =3D=3D GBIF_ARB_HALT_MASK); + + /* The GBIF halt needs to be explicitly cleared */ + gpu_write(gpu, REG_A6XX_GBIF_HALT, 0x0); +} + static int a6xx_pm_resume(struct msm_gpu *gpu) { struct adreno_gpu *adreno_gpu =3D to_adreno_gpu(gpu); diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.h b/drivers/gpu/drm/msm/ad= reno/a6xx_gpu.h index eea2e60ce3b7..9580def06d45 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.h +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.h @@ -88,4 +88,6 @@ void a6xx_show(struct msm_gpu *gpu, struct msm_gpu_state = *state, struct msm_gpu_state *a6xx_gpu_state_get(struct msm_gpu *gpu); int a6xx_gpu_state_put(struct msm_gpu_state *state); =20 +void a6xx_bus_clear_pending_transactions(struct adreno_gpu *adreno_gpu, bo= ol gx_off); + #endif /* __A6XX_GPU_H__ */ --=20 2.41.0 From nobody Tue Sep 9 17:14:06 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3D738EB64D9 for ; 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[83.9.29.190]) by smtp.gmail.com with ESMTPSA id u25-20020a056512041900b004f24ee39661sm2744852lfk.137.2023.06.15.16.21.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 15 Jun 2023 16:21:28 -0700 (PDT) From: Konrad Dybcio Date: Fri, 16 Jun 2023 01:20:48 +0200 Subject: [PATCH v9 07/20] drm/msm/a6xx: Improve a6xx_bus_clear_pending_transactions() MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20230223-topic-gmuwrapper-v9-7-890d8f470c8b@linaro.org> References: <20230223-topic-gmuwrapper-v9-0-890d8f470c8b@linaro.org> In-Reply-To: <20230223-topic-gmuwrapper-v9-0-890d8f470c8b@linaro.org> To: Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , David Airlie , Daniel Vetter , Rob Herring , Krzysztof Kozlowski , Bjorn Andersson , Konrad Dybcio , Akhil P Oommen , Conor Dooley Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Rob Clark , Marijn Suijten , Konrad Dybcio X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1686871277; l=1415; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=DRGqhpFzhDNQhxx5j97tqEL/ORDaa2xLNnRcBrvxk+I=; b=20lGkYLKlOXNgAl41BoltFryorb2un2mRZZOBZExBSXPDrbKc/bg50HjamGPBK9owpvzNnkYT fCj5EZeMjQoC3pscJe3/j8131yDod+0deyTgWkdnBQyvwUsFSfbsd4S X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Unify the indentation and explain the cryptic 0xF value. Reviewed-by: Akhil P Oommen Signed-off-by: Konrad Dybcio --- drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/ad= reno/a6xx_gpu.c index a48f4e3a754a..d5bd008c2947 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c @@ -1705,17 +1705,18 @@ static void a6xx_llc_slices_init(struct platform_de= vice *pdev, a6xx_gpu->llc_mmio =3D ERR_PTR(-EINVAL); } =20 -#define GBIF_CLIENT_HALT_MASK BIT(0) -#define GBIF_ARB_HALT_MASK BIT(1) +#define GBIF_CLIENT_HALT_MASK BIT(0) +#define GBIF_ARB_HALT_MASK BIT(1) +#define VBIF_XIN_HALT_CTRL0_MASK GENMASK(3, 0) =20 void a6xx_bus_clear_pending_transactions(struct adreno_gpu *adreno_gpu, bo= ol gx_off) { struct msm_gpu *gpu =3D &adreno_gpu->base; =20 if (!a6xx_has_gbif(adreno_gpu)) { - gpu_write(gpu, REG_A6XX_VBIF_XIN_HALT_CTRL0, 0xf); + gpu_write(gpu, REG_A6XX_VBIF_XIN_HALT_CTRL0, VBIF_XIN_HALT_CTRL0_MASK); spin_until((gpu_read(gpu, REG_A6XX_VBIF_XIN_HALT_CTRL1) & - 0xf) =3D=3D 0xf); + (VBIF_XIN_HALT_CTRL0_MASK)) =3D=3D VBIF_XIN_HALT_CTRL0_MASK); gpu_write(gpu, REG_A6XX_VBIF_XIN_HALT_CTRL0, 0); =20 return; --=20 2.41.0 From nobody Tue Sep 9 17:14:06 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id D4F47EB64D9 for ; Thu, 15 Jun 2023 23:22:04 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229713AbjFOXWD (ORCPT ); Thu, 15 Jun 2023 19:22:03 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:45862 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S239612AbjFOXVm (ORCPT ); Thu, 15 Jun 2023 19:21:42 -0400 Received: from mail-lf1-x133.google.com (mail-lf1-x133.google.com [IPv6:2a00:1450:4864:20::133]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 8EB012D53 for ; Thu, 15 Jun 2023 16:21:32 -0700 (PDT) Received: by mail-lf1-x133.google.com with SMTP id 2adb3069b0e04-4f62b512fe2so11627361e87.1 for ; Thu, 15 Jun 2023 16:21:32 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1686871290; x=1689463290; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=cWBWjSF1nxb4y2V3Mv+crQrjFgIo/GaLCfzRkH/TfkU=; b=QVZvniBWsJ8h+OenYCRnew/fLXwpZpO80jAhjXA7MXEUE/ZzSR+yMw4R5zSIcSbjR+ W6h/FC0YXKdMFEUk+W+ojWh0KIAZwk6ldV4h7WMSY5BvSCZTVYlsDi0aQ9+LbfFs1o2K blXy22YZFwOcu/EWVhyVDz0oodfxks6FYTJZaRgs4GhnJdbIY0VEGL5y8G1q0yeLUrnz p7S/MJlTyHXC9R0ucPi8qC498tpjzeqcbwp9wQctO5LkIWWjrRfhPQPBleLhPuVnK5eV fjmFjHKhVW/7wxWcm5WyP3tPsN8Ia3GwbuAvEW9tHa9lVPRyofbMKtr0a3HHdJC6Gymq vLTg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1686871290; x=1689463290; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=cWBWjSF1nxb4y2V3Mv+crQrjFgIo/GaLCfzRkH/TfkU=; b=YGs9dDn08Bq89X3TQZy0nozqCb4ZEgoxrBNt78k2QB1sAOOXHIvRFkYJwLUiZhKfzP ZZ2xK2q66eX9mnMd3Gyl87pbRPytM4rXYoV5YK+w95D6+9+Na7vOIH4Jl+4CtC1LcR9N nlU8yV9e63bkxlShW+TnMZhf4h5bFjHRBpUBGVrhe0n0UQ8xQN/PdPXC2j/8xLupNMsc RiCrX5yiimJzBxWliwF9fkTpxy0qR1n/KfZHtydVAS4NtzEXgXOgm5HhPTQgx3y7QF6A Zaw0yqJ+CrPbsz9tMR+UgPhLkuz4JEpzFhC8eZozsHt64ie7qkGueNJnNSafA61UbvXY h+HA== X-Gm-Message-State: AC+VfDxoculDDg3Ru5TbKYYf9sfKkCC9RpEZkEJeeTpqCbwd9yxQ2mtW 7kIsrDe/HDowtjmqfOsecs6KBA== X-Google-Smtp-Source: ACHHUZ7QNw8GxO27TLJN76WVDNXmdi40/BDzJLma3CCK4sCvQG+sDQyDejq9JeWLtVh22hvAlvrOow== X-Received: by 2002:a19:711c:0:b0:4f6:3000:4d5a with SMTP id m28-20020a19711c000000b004f630004d5amr68373lfc.38.1686871290719; Thu, 15 Jun 2023 16:21:30 -0700 (PDT) Received: from [192.168.1.101] (abyj190.neoplus.adsl.tpnet.pl. [83.9.29.190]) by smtp.gmail.com with ESMTPSA id u25-20020a056512041900b004f24ee39661sm2744852lfk.137.2023.06.15.16.21.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 15 Jun 2023 16:21:30 -0700 (PDT) From: Konrad Dybcio Date: Fri, 16 Jun 2023 01:20:49 +0200 Subject: [PATCH v9 08/20] drm/msm/a6xx: Add a helper for software-resetting the GPU MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20230223-topic-gmuwrapper-v9-8-890d8f470c8b@linaro.org> References: <20230223-topic-gmuwrapper-v9-0-890d8f470c8b@linaro.org> In-Reply-To: <20230223-topic-gmuwrapper-v9-0-890d8f470c8b@linaro.org> To: Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , David Airlie , Daniel Vetter , Rob Herring , Krzysztof Kozlowski , Bjorn Andersson , Konrad Dybcio , Akhil P Oommen , Conor Dooley Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Rob Clark , Marijn Suijten , Konrad Dybcio X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1686871277; l=2561; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=+qs1naLo5mMLIb06LDrZUW3mvvjoeZYSPQxSiYbvaL4=; b=hePXBLkkz1Ku4+iP0379WgmcuORZblLksSBkEmpkEPT3q5TpvmWGcT39az9jXcbBY8XGdkpeA 4tnNZzcPdSEBQSadfv5Z1vDy8YZzaffSfOBtB6b3QsoCbrLR8cKBUFc X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Introduce a6xx_gpu_sw_reset() in preparation for adding GMU wrapper GPUs and reuse it in a6xx_gmu_force_off(). This helper, contrary to the original usage in GMU code paths, adds a readback+delay sequence to ensure that the reset is never deasserted too quickly due to e.g. OoO execution going crazy. Signed-off-by: Konrad Dybcio --- drivers/gpu/drm/msm/adreno/a6xx_gmu.c | 3 +-- drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 12 ++++++++++++ drivers/gpu/drm/msm/adreno/a6xx_gpu.h | 1 + 3 files changed, 14 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c b/drivers/gpu/drm/msm/ad= reno/a6xx_gmu.c index 6402544f6849..906bed49f27d 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_gmu.c @@ -899,8 +899,7 @@ static void a6xx_gmu_force_off(struct a6xx_gmu *gmu) a6xx_bus_clear_pending_transactions(adreno_gpu, true); =20 /* Reset GPU core blocks */ - gpu_write(gpu, REG_A6XX_RBBM_SW_RESET_CMD, 1); - udelay(100); + a6xx_gpu_sw_reset(gpu, true); } =20 static void a6xx_gmu_set_initial_freq(struct msm_gpu *gpu, struct a6xx_gmu= *gmu) diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/ad= reno/a6xx_gpu.c index d5bd008c2947..b627be3f6360 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c @@ -1742,6 +1742,18 @@ void a6xx_bus_clear_pending_transactions(struct adre= no_gpu *adreno_gpu, bool gx_ gpu_write(gpu, REG_A6XX_GBIF_HALT, 0x0); } =20 +void a6xx_gpu_sw_reset(struct msm_gpu *gpu, bool assert) +{ + gpu_write(gpu, REG_A6XX_RBBM_SW_RESET_CMD, assert); + /* Perform a bogus read and add a brief delay to ensure ordering. */ + gpu_read(gpu, REG_A6XX_RBBM_SW_RESET_CMD); + udelay(1); + + /* The reset line needs to be asserted for at least 100 us */ + if (assert) + udelay(100); +} + static int a6xx_pm_resume(struct msm_gpu *gpu) { struct adreno_gpu *adreno_gpu =3D to_adreno_gpu(gpu); diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.h b/drivers/gpu/drm/msm/ad= reno/a6xx_gpu.h index 9580def06d45..aa70390ee1c6 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.h +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.h @@ -89,5 +89,6 @@ struct msm_gpu_state *a6xx_gpu_state_get(struct msm_gpu *= gpu); int a6xx_gpu_state_put(struct msm_gpu_state *state); =20 void a6xx_bus_clear_pending_transactions(struct adreno_gpu *adreno_gpu, bo= ol gx_off); +void a6xx_gpu_sw_reset(struct msm_gpu *gpu, bool assert); =20 #endif /* __A6XX_GPU_H__ */ --=20 2.41.0 From nobody Tue Sep 9 17:14:06 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4ED28EB64D9 for ; Thu, 15 Jun 2023 23:22:11 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S240172AbjFOXWK (ORCPT ); Thu, 15 Jun 2023 19:22:10 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:45922 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236692AbjFOXVm (ORCPT ); Thu, 15 Jun 2023 19:21:42 -0400 Received: from mail-lf1-x135.google.com (mail-lf1-x135.google.com [IPv6:2a00:1450:4864:20::135]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id C95AE2D57 for ; Thu, 15 Jun 2023 16:21:33 -0700 (PDT) Received: by mail-lf1-x135.google.com with SMTP id 2adb3069b0e04-4f845060481so1674239e87.3 for ; Thu, 15 Jun 2023 16:21:33 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1686871292; x=1689463292; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=3aBLLbacTh+Ex0pHk2CQnOlcKWWCMhpUkJM7hf2NJ5E=; b=pQO28YupZ9aQNmPH57PCXKbJ7ClPx9R1cSV4mAVW+5eLTWiXUmsNKoirLZy4DR7DgN IQRYHL8ZMpnexAqMsly1t4iumFD081Iw6mrv313VThuAodq5nIQ+cr2JszLerO9N5fUf XioSLLQc42j1rZd4rz6+U3sudyX9DlwA3KwIvrTCfEfdlLMaJautR4UuunWxnWdQG1R0 Sdp2z7V9kYwDfXKkUELtOYAu++LQ103aGLurNt+y91vWJd4BhsLMD6lkASUmVXpCQp0x Cxe48vDsVBteyrJ2Uz7ns+8sdlnjmPMdX1kT9JA1e3gW5Pkpux+jYkIXo/Wu14aE1bV/ Dorw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1686871292; x=1689463292; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=3aBLLbacTh+Ex0pHk2CQnOlcKWWCMhpUkJM7hf2NJ5E=; b=ImCpwBtdo1A9W5D0YR2/p94J5PZja4IfZHPjZxTEEIFfohoxbkIKfSEBxRHz4oRVqi Mg7Hr9s2riRqUdMIwWIxTtrJL9ac+mViX/nQbCbFXSqVi9Qe+PIJiA6AdhapQdQhnQPG wWhyFngCASV3pDKC8K7Npn8V5Gjf5BcYntTCKdhtYZTgbVtDmcY9oSsyVwcNM40SvMNG x+Bv54GFGj4tLxFOJnsyQ9TcUi5lwvMM82qYGgMKFTXwGHnqXe9mUHHHNkaU9y+GPoo5 2NON6NAT2VZ1sL9S7GUdemhMn66QVdOHLW4kDu2BiUWwg8jWHdaTVzF2qZLIaeJL6cpK CoDw== X-Gm-Message-State: AC+VfDyEsMw/tjYhlytqAKHqHJ16ZDKzR7+C96Vwq7HuDzbe57WpLuQH p6euPInl63w7I4S8TaeedlewEA== X-Google-Smtp-Source: ACHHUZ6uSakf1tY4JEIXkQ0gM3/D3sQL606O7CbVblONG2RLtbxQfY630L3KUjtWs8Od6iZ8M4iS8Q== X-Received: by 2002:a19:4f56:0:b0:4f7:6a7e:f079 with SMTP id a22-20020a194f56000000b004f76a7ef079mr93019lfk.31.1686871292167; Thu, 15 Jun 2023 16:21:32 -0700 (PDT) Received: from [192.168.1.101] (abyj190.neoplus.adsl.tpnet.pl. [83.9.29.190]) by smtp.gmail.com with ESMTPSA id u25-20020a056512041900b004f24ee39661sm2744852lfk.137.2023.06.15.16.21.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 15 Jun 2023 16:21:31 -0700 (PDT) From: Konrad Dybcio Date: Fri, 16 Jun 2023 01:20:50 +0200 Subject: [PATCH v9 09/20] drm/msm/a6xx: Remove both GBIF and RBBM GBIF halt on hw init MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20230223-topic-gmuwrapper-v9-9-890d8f470c8b@linaro.org> References: <20230223-topic-gmuwrapper-v9-0-890d8f470c8b@linaro.org> In-Reply-To: <20230223-topic-gmuwrapper-v9-0-890d8f470c8b@linaro.org> To: Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , David Airlie , Daniel Vetter , Rob Herring , Krzysztof Kozlowski , Bjorn Andersson , Konrad Dybcio , Akhil P Oommen , Conor Dooley Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Rob Clark , Marijn Suijten , Konrad Dybcio X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1686871277; l=1283; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=mn897aEmmor9k1FnbUx226+ojITBGwyH7cFTcD9yASI=; b=gtQN0aOUrpE5N6ygJFNwpAMGUaAS5m1yMnYkP9WZlpYHW2rsdM5BsDSIgdCIKhJ0JgiI3IihR ow8xjMnR/wYDUV6MSxRwx9w2Cdu1vFlojj4aomXy5dlDrNtxUka8bXX X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Currently we're only deasserting REG_A6XX_RBBM_GBIF_HALT, but we also need REG_A6XX_GBIF_HALT to be set to 0. This is typically done automatically on successful GX collapse, but in case that fails, we should take care of it. Also, add a memory barrier to ensure it's gone through before jumping to further initialization. Reviewed-by: Dmitry Baryshkov Signed-off-by: Konrad Dybcio --- drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/ad= reno/a6xx_gpu.c index b627be3f6360..7e0d1dfcd993 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c @@ -1111,8 +1111,12 @@ static int hw_init(struct msm_gpu *gpu) a6xx_gmu_set_oob(&a6xx_gpu->gmu, GMU_OOB_GPU_SET); =20 /* Clear GBIF halt in case GX domain was not collapsed */ - if (a6xx_has_gbif(adreno_gpu)) + if (a6xx_has_gbif(adreno_gpu)) { + gpu_write(gpu, REG_A6XX_GBIF_HALT, 0); gpu_write(gpu, REG_A6XX_RBBM_GBIF_HALT, 0); + /* Let's make extra sure that the GPU can access the memory.. */ + mb(); + } =20 gpu_write(gpu, REG_A6XX_RBBM_SECVID_TSB_CNTL, 0); =20 --=20 2.41.0 From nobody Tue Sep 9 17:14:06 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 14409EB64DB for ; Thu, 15 Jun 2023 23:22:15 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S239340AbjFOXWN (ORCPT ); Thu, 15 Jun 2023 19:22:13 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:45970 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S239977AbjFOXVn (ORCPT ); Thu, 15 Jun 2023 19:21:43 -0400 Received: from mail-lf1-x135.google.com (mail-lf1-x135.google.com [IPv6:2a00:1450:4864:20::135]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 66A642D60 for ; Thu, 15 Jun 2023 16:21:35 -0700 (PDT) Received: by mail-lf1-x135.google.com with SMTP id 2adb3069b0e04-4f84d70bf96so225628e87.0 for ; Thu, 15 Jun 2023 16:21:35 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1686871293; x=1689463293; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=FArdX5TBaRtyEgFmzlEIkawN60f/9KNXaxifqatEN80=; b=lgRI1pKr7OarGe1fyPxQD0FW/7BbLSCbjw99ajPlQ4AXC/8BKH4fzG3NyVWIGZmaCp ouvndgXpA3RoP4J35SA7lq8gq3jKIZy2F2SdDwuazvjtJxFZBHLVoogJpo5Y5RHMuO7r Rk//O+izXJp8RAATO1TtwsQgJqEVXpftFhoS8SDOUljc07DbtrYtP+sTJaYeHrKY29SQ rqkn7cKJhmgJL/Jmlywa1Iyoq+YT7vX2JTEJ9zWSuhSRSkm/XIhRxPX37vych/Xe9jJx yqE17KEk0mIKYsdDWT42uc2UufLr21nh5sb7mUtFdqh7wApv4GOcYa1pO78zjyyq4qjA k8/A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1686871293; x=1689463293; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=FArdX5TBaRtyEgFmzlEIkawN60f/9KNXaxifqatEN80=; b=kN7YQl2oEN7dsxcBrcHZ2y/CLxxrcSZrwlf6jjgqzLWK76KHWX2ir2z5HYyb/SJHFY +mQpksY1MpALs+GA+fc++GPrl71O7FPsTfBpLj5O26dAk3ODKBkmeSJvq1torEb104Qa tU97V+ztsSBhAk9ba9TIxLqzObo9vEYKoOumZJgW5eVKlGXnrM2vy5su/oRd7IKszX9Y c4G2iM5XV1hS7E7fGxxMQCIuu3x0hBJO6hPwt4HB0GxyZ83K4LQ5vb1XhL8+ragzKO89 t49DY8jF19jurhZHUiUbRRqHlqyBD4ut6cIRZanypapucqjW3/z/N06ndgDJLjKb1NdN kJ1w== X-Gm-Message-State: AC+VfDzw7FLQ+PCLoYyG/oPQixw5chShXaIVSR0bSFX3/4Vpb9yCq/tu tYykqF4CYszM1ZUsXPBOCNyWnQ== X-Google-Smtp-Source: ACHHUZ4dZM/nJyPupye1DNgW/MA8+4mZrVcoghmRv+dVbxkAZa1IW4UGF3Gqp7gSh/z3n0tUy4+cjw== X-Received: by 2002:a05:6512:3052:b0:4f7:47bb:2ce0 with SMTP id b18-20020a056512305200b004f747bb2ce0mr2000501lfb.4.1686871293575; Thu, 15 Jun 2023 16:21:33 -0700 (PDT) Received: from [192.168.1.101] (abyj190.neoplus.adsl.tpnet.pl. [83.9.29.190]) by smtp.gmail.com with ESMTPSA id u25-20020a056512041900b004f24ee39661sm2744852lfk.137.2023.06.15.16.21.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 15 Jun 2023 16:21:33 -0700 (PDT) From: Konrad Dybcio Date: Fri, 16 Jun 2023 01:20:51 +0200 Subject: [PATCH v9 10/20] drm/msm/a6xx: Extend and explain UBWC config MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20230223-topic-gmuwrapper-v9-10-890d8f470c8b@linaro.org> References: <20230223-topic-gmuwrapper-v9-0-890d8f470c8b@linaro.org> In-Reply-To: <20230223-topic-gmuwrapper-v9-0-890d8f470c8b@linaro.org> To: Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , David Airlie , Daniel Vetter , Rob Herring , Krzysztof Kozlowski , Bjorn Andersson , Konrad Dybcio , Akhil P Oommen , Conor Dooley Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Rob Clark , Marijn Suijten , Konrad Dybcio X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1686871277; l=3228; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=qlz+dGbiTZkptUzjat5pbZCHt/vo5Ur5/uPhfZn2V7s=; b=F1kYVr/t6oi6U8zbpCNcQjOjoB6OhCkl7GfCz02Qa7F0iJcMHIr+3a3NSu5+1zF22s+gNPZLr rNwBjx94vy/Aal7zsS65zU1L0BwciT12/lSgCuhtJRxhMSfuR++Q+B5 X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Rename lower_bit to hbb_lo and explain what it signifies. Add explanations (wherever possible to other tunables). Port setting min_access_length, ubwc_mode and hbb_hi from downstream. Reviewed-by: Rob Clark Reviewed-by: Akhil P Oommen Signed-off-by: Konrad Dybcio --- drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 41 ++++++++++++++++++++++++++-----= ---- 1 file changed, 31 insertions(+), 10 deletions(-) diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/ad= reno/a6xx_gpu.c index 7e0d1dfcd993..8aa4670b4308 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c @@ -887,10 +887,25 @@ static void a6xx_set_cp_protect(struct msm_gpu *gpu) static void a6xx_set_ubwc_config(struct msm_gpu *gpu) { struct adreno_gpu *adreno_gpu =3D to_adreno_gpu(gpu); - u32 lower_bit =3D 2; - u32 amsbc =3D 0; + /* Unknown, introduced with A650 family, related to UBWC mode/ver 4 */ u32 rgb565_predicator =3D 0; + /* Unknown, introduced with A650 family */ u32 uavflagprd_inv =3D 0; + /* Whether the minimum access length is 64 bits */ + u32 min_acc_len =3D 0; + /* Entirely magic, per-GPU-gen value */ + u32 ubwc_mode =3D 0; + /* + * The Highest Bank Bit value represents the bit of the highest DDR bank. + * We then subtract 13 from it (13 is the minimum value allowed by hw) and + * write the lowest two bits of the remaining value as hbb_lo and the + * one above it as hbb_hi to the hardware. This should ideally use DRAM + * type detection. + */ + u32 hbb_hi =3D 0; + u32 hbb_lo =3D 2; + /* Unknown, introduced with A640/680 */ + u32 amsbc =3D 0; =20 /* a618 is using the hw default values */ if (adreno_is_a618(adreno_gpu)) @@ -901,32 +916,38 @@ static void a6xx_set_ubwc_config(struct msm_gpu *gpu) =20 if (adreno_is_a650(adreno_gpu) || adreno_is_a660(adreno_gpu)) { /* TODO: get ddr type from bootloader and use 2 for LPDDR4 */ - lower_bit =3D 3; + hbb_lo =3D 3; amsbc =3D 1; rgb565_predicator =3D 1; uavflagprd_inv =3D 2; } =20 if (adreno_is_a690(adreno_gpu)) { - lower_bit =3D 2; + hbb_lo =3D 2; amsbc =3D 1; rgb565_predicator =3D 1; uavflagprd_inv =3D 2; } =20 if (adreno_is_7c3(adreno_gpu)) { - lower_bit =3D 1; + hbb_lo =3D 1; amsbc =3D 1; rgb565_predicator =3D 1; uavflagprd_inv =3D 2; } =20 gpu_write(gpu, REG_A6XX_RB_NC_MODE_CNTL, - rgb565_predicator << 11 | amsbc << 4 | lower_bit << 1); - gpu_write(gpu, REG_A6XX_TPL1_NC_MODE_CNTL, lower_bit << 1); - gpu_write(gpu, REG_A6XX_SP_NC_MODE_CNTL, - uavflagprd_inv << 4 | lower_bit << 1); - gpu_write(gpu, REG_A6XX_UCHE_MODE_CNTL, lower_bit << 21); + rgb565_predicator << 11 | hbb_hi << 10 | amsbc << 4 | + min_acc_len << 3 | hbb_lo << 1 | ubwc_mode); + + gpu_write(gpu, REG_A6XX_TPL1_NC_MODE_CNTL, hbb_hi << 4 | + min_acc_len << 3 | hbb_lo << 1 | ubwc_mode); + + gpu_write(gpu, REG_A6XX_SP_NC_MODE_CNTL, hbb_hi << 10 | + uavflagprd_inv << 4 | min_acc_len << 3 | + hbb_lo << 1 | ubwc_mode); + + gpu_write(gpu, REG_A6XX_UCHE_MODE_CNTL, min_acc_len << 23 | hbb_lo << 21); } =20 static int a6xx_cp_init(struct msm_gpu *gpu) --=20 2.41.0 From nobody Tue Sep 9 17:14:06 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6F817EB64DB for ; Thu, 15 Jun 2023 23:22:19 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S239593AbjFOXWQ (ORCPT ); Thu, 15 Jun 2023 19:22:16 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:45980 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229480AbjFOXVo (ORCPT ); Thu, 15 Jun 2023 19:21:44 -0400 Received: from mail-lf1-x12b.google.com (mail-lf1-x12b.google.com [IPv6:2a00:1450:4864:20::12b]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id AD46B2D68 for ; Thu, 15 Jun 2023 16:21:36 -0700 (PDT) Received: by mail-lf1-x12b.google.com with SMTP id 2adb3069b0e04-4f845060481so1674290e87.3 for ; Thu, 15 Jun 2023 16:21:36 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1686871295; x=1689463295; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=FsmM0RVmGhdEwe/rih/x+k+rX6jJFYBfre/lrv7PkUc=; b=QxK4BzIR8IUBhOCy5aUHkaSxQ1FVwiCX9v8TWjmIKZxrM6iQhdZS075YcYr0T6/T5V cG3qCIAwYyWo5MXlUMb5/8OW+ZeInwEOo99SAvLMzeYqssas7QAY+7QsXkuCVT2GUg0x vv3hy70lsqmtHVCgnxKEbTuZppbJaCyn7xkPigVOR+HIwnmdcfsy0bgOOnzxSet0LOPf jB7qnjWq6y9G/vicSJr7Y51S4eW14hqGyROb4C6jziViqEei+zgrtAfGdLKswE4zVeqq 04QDyy5jkZKfaMMa5dF5qLgKrhh3ZU6BVqL6idgqv5Dt4QaoICXLmi2QjKRs/S4pwuum lo0Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1686871295; x=1689463295; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=FsmM0RVmGhdEwe/rih/x+k+rX6jJFYBfre/lrv7PkUc=; b=F1V0ez2HAgwU1nrrszLRD3OdHYG/ADyrUP51dtpv/xxkVCguTHEhwqL40TDIkeo2wx GrqhLW0Ka47rfiTlgbiQT8oO00zC+5jMlFFZ7qDbaE8HysmHs6u64Gm52RtnR2DN/pYN bKSTnWLs16iRINqqrq+EIehTD4FEdEDKLRkbDL/pJtChDOH59wM16wzROzl1FoMXdKGT WRtLmAQT3VS00sd31RqxYO7KqbHTiiC/JWHJNQ1FkB8BXk0pROK4f3ZCLSfNS/baiCGj eK883xzO3doEU4Jsk/qUCuxlHMugR63Qdb1tT4FV7qmCFiUcIuIYfazNr0xZfhv6bWmc XSyA== X-Gm-Message-State: AC+VfDxe7GFJEMWfxkowRk+kjiXLQK5QBnAocur/OKpnLAxq3PODJWx7 JbHvX3ng3JqZzIIC1Wi5obdW0g== X-Google-Smtp-Source: ACHHUZ57bxPcpLH/W26TQt+WKOvyGY/VYKwN0jb23n3AXd24tArYBiB8EX6js3HDzk6cTEl/2S6N3g== X-Received: by 2002:a19:675a:0:b0:4f1:4468:ee65 with SMTP id e26-20020a19675a000000b004f14468ee65mr96060lfj.30.1686871295061; Thu, 15 Jun 2023 16:21:35 -0700 (PDT) Received: from [192.168.1.101] (abyj190.neoplus.adsl.tpnet.pl. [83.9.29.190]) by smtp.gmail.com with ESMTPSA id u25-20020a056512041900b004f24ee39661sm2744852lfk.137.2023.06.15.16.21.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 15 Jun 2023 16:21:34 -0700 (PDT) From: Konrad Dybcio Date: Fri, 16 Jun 2023 01:20:52 +0200 Subject: [PATCH v9 11/20] drm/msm/a6xx: Move CX GMU power counter enablement to hw_init MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20230223-topic-gmuwrapper-v9-11-890d8f470c8b@linaro.org> References: <20230223-topic-gmuwrapper-v9-0-890d8f470c8b@linaro.org> In-Reply-To: <20230223-topic-gmuwrapper-v9-0-890d8f470c8b@linaro.org> To: Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , David Airlie , Daniel Vetter , Rob Herring , Krzysztof Kozlowski , Bjorn Andersson , Konrad Dybcio , Akhil P Oommen , Conor Dooley Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Rob Clark , Marijn Suijten , Konrad Dybcio X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1686871277; l=1883; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=NcBNg698ol/YkEOdeY7ojQoggNClubg5869lLN304Tc=; b=8sFX06msZKeW+kwKP3ZOXVdyHN22k+stTfTspDXSv/V6MFiUsi8VyYOuJztXYN7vAuhXvhy9v lEKWJf1OyO/AMgeFZYi9GWfzVwOr97iNrKw9rNMga9ujWibv7/jc7wo X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Since the introduction of A6xx support, we've been enabling the CX GMU power counter 0 in a bit of a weird spot. Move it to hw_init so that GMU wrapper GPUs can reuse the same code paths. As a bonus, this order makes it easier to compare mainline and downstream register access traces. Signed-off-by: Konrad Dybcio --- drivers/gpu/drm/msm/adreno/a6xx_gmu.c | 6 ------ drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 7 +++++++ 2 files changed, 7 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c b/drivers/gpu/drm/msm/ad= reno/a6xx_gmu.c index 906bed49f27d..aae7ea651607 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_gmu.c @@ -479,12 +479,6 @@ static int a6xx_rpmh_start(struct a6xx_gmu *gmu) =20 gmu_write(gmu, REG_A6XX_GMU_RSCC_CONTROL_REQ, 0); =20 - /* Set up CX GMU counter 0 to count busy ticks */ - gmu_write(gmu, REG_A6XX_GPU_GMU_AO_GPU_CX_BUSY_MASK, 0xff000000); - gmu_rmw(gmu, REG_A6XX_GMU_CX_GMU_POWER_COUNTER_SELECT_0, 0xff, 0x20); - - /* Enable the power counter */ - gmu_write(gmu, REG_A6XX_GMU_CX_GMU_POWER_COUNTER_ENABLE, 1); return 0; } =20 diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/ad= reno/a6xx_gpu.c index 8aa4670b4308..0efecde2af1a 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c @@ -1256,6 +1256,13 @@ static int hw_init(struct msm_gpu *gpu) 0x3f0243f0); } =20 + /* Set up the CX GMU counter 0 to count busy ticks */ + gmu_write(gmu, REG_A6XX_GPU_GMU_AO_GPU_CX_BUSY_MASK, 0xff000000); + + /* Enable the power counter */ + gmu_rmw(gmu, REG_A6XX_GMU_CX_GMU_POWER_COUNTER_SELECT_0, 0xff, BIT(5)); + gmu_write(gmu, REG_A6XX_GMU_CX_GMU_POWER_COUNTER_ENABLE, 1); + /* Protect registers from the CP */ a6xx_set_cp_protect(gpu); =20 --=20 2.41.0 From nobody Tue Sep 9 17:14:06 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id A0A1FEB64D9 for ; Thu, 15 Jun 2023 23:22:23 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231312AbjFOXWW (ORCPT ); Thu, 15 Jun 2023 19:22:22 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:45880 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230522AbjFOXVs (ORCPT ); Thu, 15 Jun 2023 19:21:48 -0400 Received: from mail-lf1-x12b.google.com (mail-lf1-x12b.google.com [IPv6:2a00:1450:4864:20::12b]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id AA2AB2D7F for ; Thu, 15 Jun 2023 16:21:38 -0700 (PDT) Received: by mail-lf1-x12b.google.com with SMTP id 2adb3069b0e04-4f841b7a697so2158020e87.3 for ; Thu, 15 Jun 2023 16:21:38 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1686871297; x=1689463297; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=/zxmhAnEmxSVMknXQwyXBluuzz0sqFgLH39JqXiH4vs=; b=FMghnXptOmXW0FtLGsL35qO1ePlBxFNNGx07R2zB7xFRPCmVYbsOZIpFpvHX/gnNy7 T95HcC3QHkkBllJmhkrjqNe853mggJOpVYOD8QWkECmThg3A3Cse5nJe5N/EiRxP6wRQ hp9PkqDAdJglY6c1ogyjLb+n0M+PUFOOeIuDrSizfn6kLNHid4pfZabz2DBIwGJPga6E qxRF4V6IAY8wibCZCh3yuawoo8Bhom48VzkEKlGcfF1hwsgWoNpcDBNhGKQBSR/Ti2nH 5fAzYYzudtv56UW2MaOCJRTgsc34/jIo3MdELcFGL31cW1OIm7Udh2Ofh/dj3s6XoadP obHA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1686871297; x=1689463297; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=/zxmhAnEmxSVMknXQwyXBluuzz0sqFgLH39JqXiH4vs=; b=OqCeuq63IHZLxBAuZMNXR1rlnVN3oG0CxZdsUILwB6ZId8XE9FO/4FiLTyEbVI4rY0 oQ0wAv4Uicd9leozvGnTOib/F5YlKahhblUIzvhVZb4G7PWd1C19TPcWkjW28rLUU912 6bufnNUcnNXeXEER9glGEAk+/ltK2nrazKzKR4Cppxw5dgZr841SfSE1wPkejN55K8q1 bP0NrPOwC7vqRnAkUW1MenXYEuv8CH02+cnySyG/URCwif4Vcw5e0RqH2bceJcCQ7GV/ R8PxqM1Lnv81dGu/TaAP+sXbx5ov0lkp2eMRzQuzFsBGKW/x6ywRjxxKh1ic+M/fcd6Z Up1A== X-Gm-Message-State: AC+VfDz9RJIWq+1xdwsPzi+uAC6gCR8ju2lMkGAURp6Z3rv8SG37n2vu aNAxB05EwOX9n/lXP0CadICCPg== X-Google-Smtp-Source: ACHHUZ6Zaba56BkYObGzpwHawVg0/2OGYPZxO/YWcoG2vev3ns0yC9ce71DCKtgzIApeU7/VFBh5yQ== X-Received: by 2002:a19:6d0e:0:b0:4f6:520d:6b9b with SMTP id i14-20020a196d0e000000b004f6520d6b9bmr59979lfc.60.1686871296747; Thu, 15 Jun 2023 16:21:36 -0700 (PDT) Received: from [192.168.1.101] (abyj190.neoplus.adsl.tpnet.pl. [83.9.29.190]) by smtp.gmail.com with ESMTPSA id u25-20020a056512041900b004f24ee39661sm2744852lfk.137.2023.06.15.16.21.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 15 Jun 2023 16:21:36 -0700 (PDT) From: Konrad Dybcio Date: Fri, 16 Jun 2023 01:20:53 +0200 Subject: [PATCH v9 12/20] drm/msm/a6xx: Introduce GMU wrapper support MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20230223-topic-gmuwrapper-v9-12-890d8f470c8b@linaro.org> References: <20230223-topic-gmuwrapper-v9-0-890d8f470c8b@linaro.org> In-Reply-To: <20230223-topic-gmuwrapper-v9-0-890d8f470c8b@linaro.org> To: Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , David Airlie , Daniel Vetter , Rob Herring , Krzysztof Kozlowski , Bjorn Andersson , Konrad Dybcio , Akhil P Oommen , Conor Dooley Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Rob Clark , Marijn Suijten , Konrad Dybcio X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1686871277; l=18851; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=Mg3KIbbf0SPJD9Gso3Hg42h9a7bjesm92tOZRXmVyes=; b=3gzmQAEKDh92/ZLPfCPxiCC9KjUtopCicRPv33SvXtYWfWIp0At2qpN78+skWoKb73MC/o9xn oH2gmv7SA3LAOL5T7eIvF03B7sCzsIG/aDxt+vLBpcrCuipOgOQidZ+ X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Some (particularly SMD_RPM, a.k.a non-RPMh) SoCs implement A6XX GPUs but don't implement the associated GMUs. This is due to the fact that the GMU directly pokes at RPMh. Sadly, this means we have to take care of enabling & scaling power rails, clocks and bandwidth ourselves. Reuse existing Adreno-common code and modify the deeply-GMU-infused A6XX code to facilitate these GPUs. This involves if-ing out lots of GMU callbacks and introducing a new type of GMU - GMU wrapper (it's the actual name that Qualcomm uses in their downstream kernels). This is essentially a register region which is convenient to model as a device. We'll use it for managing the GDSCs. The register layout matches the actual GMU_CX/GX regions on the "real GMU" devices and lets us reuse quite a bit of gmu_read/write/rmw calls. Signed-off-by: Konrad Dybcio --- drivers/gpu/drm/msm/adreno/a6xx_gmu.c | 72 +++++++++- drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 201 ++++++++++++++++++++++++= ---- drivers/gpu/drm/msm/adreno/a6xx_gpu.h | 1 + drivers/gpu/drm/msm/adreno/a6xx_gpu_state.c | 14 +- drivers/gpu/drm/msm/adreno/adreno_gpu.c | 8 +- drivers/gpu/drm/msm/adreno/adreno_gpu.h | 6 + 6 files changed, 266 insertions(+), 36 deletions(-) diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c b/drivers/gpu/drm/msm/ad= reno/a6xx_gmu.c index aae7ea651607..5deb79924897 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_gmu.c @@ -1431,6 +1431,7 @@ static int a6xx_gmu_get_irq(struct a6xx_gmu *gmu, str= uct platform_device *pdev, =20 void a6xx_gmu_remove(struct a6xx_gpu *a6xx_gpu) { + struct adreno_gpu *adreno_gpu =3D &a6xx_gpu->base; struct a6xx_gmu *gmu =3D &a6xx_gpu->gmu; struct platform_device *pdev =3D to_platform_device(gmu->dev); =20 @@ -1456,10 +1457,12 @@ void a6xx_gmu_remove(struct a6xx_gpu *a6xx_gpu) gmu->mmio =3D NULL; gmu->rscc =3D NULL; =20 - a6xx_gmu_memory_free(gmu); + if (!adreno_has_gmu_wrapper(adreno_gpu)) { + a6xx_gmu_memory_free(gmu); =20 - free_irq(gmu->gmu_irq, gmu); - free_irq(gmu->hfi_irq, gmu); + free_irq(gmu->gmu_irq, gmu); + free_irq(gmu->hfi_irq, gmu); + } =20 /* Drop reference taken in of_find_device_by_node */ put_device(gmu->dev); @@ -1478,6 +1481,69 @@ static int cxpd_notifier_cb(struct notifier_block *n= b, return 0; } =20 +int a6xx_gmu_wrapper_init(struct a6xx_gpu *a6xx_gpu, struct device_node *n= ode) +{ + struct platform_device *pdev =3D of_find_device_by_node(node); + struct a6xx_gmu *gmu =3D &a6xx_gpu->gmu; + int ret; + + if (!pdev) + return -ENODEV; + + gmu->dev =3D &pdev->dev; + + of_dma_configure(gmu->dev, node, true); + + pm_runtime_enable(gmu->dev); + + /* Mark legacy for manual SPTPRAC control */ + gmu->legacy =3D true; + + /* Map the GMU registers */ + gmu->mmio =3D a6xx_gmu_get_mmio(pdev, "gmu"); + if (IS_ERR(gmu->mmio)) { + ret =3D PTR_ERR(gmu->mmio); + goto err_mmio; + } + + gmu->cxpd =3D dev_pm_domain_attach_by_name(gmu->dev, "cx"); + if (IS_ERR(gmu->cxpd)) { + ret =3D PTR_ERR(gmu->cxpd); + goto err_mmio; + } + + if (!device_link_add(gmu->dev, gmu->cxpd, DL_FLAG_PM_RUNTIME)) { + ret =3D -ENODEV; + goto detach_cxpd; + } + + init_completion(&gmu->pd_gate); + complete_all(&gmu->pd_gate); + gmu->pd_nb.notifier_call =3D cxpd_notifier_cb; + + /* Get a link to the GX power domain to reset the GPU */ + gmu->gxpd =3D dev_pm_domain_attach_by_name(gmu->dev, "gx"); + if (IS_ERR(gmu->gxpd)) { + ret =3D PTR_ERR(gmu->gxpd); + goto err_mmio; + } + + gmu->initialized =3D true; + + return 0; + +detach_cxpd: + dev_pm_domain_detach(gmu->cxpd, false); + +err_mmio: + iounmap(gmu->mmio); + + /* Drop reference taken in of_find_device_by_node */ + put_device(gmu->dev); + + return ret; +} + int a6xx_gmu_init(struct a6xx_gpu *a6xx_gpu, struct device_node *node) { struct adreno_gpu *adreno_gpu =3D &a6xx_gpu->base; diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/ad= reno/a6xx_gpu.c index 0efecde2af1a..b91fc02eb08c 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c @@ -21,7 +21,7 @@ static inline bool _a6xx_check_idle(struct msm_gpu *gpu) struct a6xx_gpu *a6xx_gpu =3D to_a6xx_gpu(adreno_gpu); =20 /* Check that the GMU is idle */ - if (!a6xx_gmu_isidle(&a6xx_gpu->gmu)) + if (!adreno_has_gmu_wrapper(adreno_gpu) && !a6xx_gmu_isidle(&a6xx_gpu->gm= u)) return false; =20 /* Check tha the CX master is idle */ @@ -1126,10 +1126,13 @@ static int hw_init(struct msm_gpu *gpu) { struct adreno_gpu *adreno_gpu =3D to_adreno_gpu(gpu); struct a6xx_gpu *a6xx_gpu =3D to_a6xx_gpu(adreno_gpu); + struct a6xx_gmu *gmu =3D &a6xx_gpu->gmu; int ret; =20 - /* Make sure the GMU keeps the GPU on while we set it up */ - a6xx_gmu_set_oob(&a6xx_gpu->gmu, GMU_OOB_GPU_SET); + if (!adreno_has_gmu_wrapper(adreno_gpu)) { + /* Make sure the GMU keeps the GPU on while we set it up */ + a6xx_gmu_set_oob(&a6xx_gpu->gmu, GMU_OOB_GPU_SET); + } =20 /* Clear GBIF halt in case GX domain was not collapsed */ if (a6xx_has_gbif(adreno_gpu)) { @@ -1352,6 +1355,8 @@ static int hw_init(struct msm_gpu *gpu) } =20 out: + if (adreno_has_gmu_wrapper(adreno_gpu)) + return ret; /* * Tell the GMU that we are done touching the GPU and it can start power * management @@ -1386,9 +1391,6 @@ static void a6xx_dump(struct msm_gpu *gpu) adreno_dump(gpu); } =20 -#define VBIF_RESET_ACK_TIMEOUT 100 -#define VBIF_RESET_ACK_MASK 0x00f0 - static void a6xx_recover(struct msm_gpu *gpu) { struct adreno_gpu *adreno_gpu =3D to_adreno_gpu(gpu); @@ -1426,6 +1428,15 @@ static void a6xx_recover(struct msm_gpu *gpu) */ gpu->active_submits =3D 0; =20 + if (adreno_has_gmu_wrapper(adreno_gpu)) { + /* Drain the outstanding traffic on memory buses */ + a6xx_bus_clear_pending_transactions(adreno_gpu, true); + + /* Reset the GPU to a clean state */ + a6xx_gpu_sw_reset(gpu, true); + a6xx_gpu_sw_reset(gpu, false); + } + reinit_completion(&gmu->pd_gate); dev_pm_genpd_add_notifier(gmu->cxpd, &gmu->pd_nb); dev_pm_genpd_synced_poweroff(gmu->cxpd); @@ -1576,7 +1587,8 @@ static void a6xx_fault_detect_irq(struct msm_gpu *gpu) * Force the GPU to stay on until after we finish * collecting information */ - gmu_write(&a6xx_gpu->gmu, REG_A6XX_GMU_GMU_PWR_COL_KEEPALIVE, 1); + if (!adreno_has_gmu_wrapper(adreno_gpu)) + gmu_write(&a6xx_gpu->gmu, REG_A6XX_GMU_GMU_PWR_COL_KEEPALIVE, 1); =20 DRM_DEV_ERROR(&gpu->pdev->dev, "gpu fault ring %d fence %x status %8.8X rb %4.4x/%4.4x ib1 %16.16llX/%4= .4x ib2 %16.16llX/%4.4x\n", @@ -1707,6 +1719,10 @@ static void a6xx_llc_activate(struct a6xx_gpu *a6xx_= gpu) =20 static void a6xx_llc_slices_destroy(struct a6xx_gpu *a6xx_gpu) { + /* No LLCC on non-RPMh (and by extension, non-GMU) SoCs */ + if (adreno_has_gmu_wrapper(&a6xx_gpu->base)) + return; + llcc_slice_putd(a6xx_gpu->llc_slice); llcc_slice_putd(a6xx_gpu->htw_llc_slice); } @@ -1716,6 +1732,10 @@ static void a6xx_llc_slices_init(struct platform_dev= ice *pdev, { struct device_node *phandle; =20 + /* No LLCC on non-RPMh (and by extension, non-GMU) SoCs */ + if (adreno_has_gmu_wrapper(&a6xx_gpu->base)) + return; + /* * There is a different programming path for targets with an mmu500 * attached, so detect if that is the case @@ -1786,7 +1806,7 @@ void a6xx_gpu_sw_reset(struct msm_gpu *gpu, bool asse= rt) udelay(100); } =20 -static int a6xx_pm_resume(struct msm_gpu *gpu) +static int a6xx_gmu_pm_resume(struct msm_gpu *gpu) { struct adreno_gpu *adreno_gpu =3D to_adreno_gpu(gpu); struct a6xx_gpu *a6xx_gpu =3D to_a6xx_gpu(adreno_gpu); @@ -1806,10 +1826,58 @@ static int a6xx_pm_resume(struct msm_gpu *gpu) =20 a6xx_llc_activate(a6xx_gpu); =20 - return 0; + return ret; } =20 -static int a6xx_pm_suspend(struct msm_gpu *gpu) +static int a6xx_pm_resume(struct msm_gpu *gpu) +{ + struct adreno_gpu *adreno_gpu =3D to_adreno_gpu(gpu); + struct a6xx_gpu *a6xx_gpu =3D to_a6xx_gpu(adreno_gpu); + struct a6xx_gmu *gmu =3D &a6xx_gpu->gmu; + unsigned long freq =3D gpu->fast_rate; + struct dev_pm_opp *opp; + int ret; + + gpu->needs_hw_init =3D true; + + trace_msm_gpu_resume(0); + + mutex_lock(&a6xx_gpu->gmu.lock); + + opp =3D dev_pm_opp_find_freq_ceil(&gpu->pdev->dev, &freq); + if (IS_ERR(opp)) { + ret =3D PTR_ERR(opp); + goto err_set_opp; + } + dev_pm_opp_put(opp); + + /* Set the core clock and bus bw, having VDD scaling in mind */ + dev_pm_opp_set_opp(&gpu->pdev->dev, opp); + + pm_runtime_resume_and_get(gmu->dev); + pm_runtime_resume_and_get(gmu->gxpd); + + ret =3D clk_bulk_prepare_enable(gpu->nr_clocks, gpu->grp_clks); + if (ret) + goto err_bulk_clk; + + /* If anything goes south, tear the GPU down piece by piece.. */ + if (ret) { +err_bulk_clk: + pm_runtime_put(gmu->gxpd); + pm_runtime_put(gmu->dev); + dev_pm_opp_set_opp(&gpu->pdev->dev, NULL); + } +err_set_opp: + mutex_unlock(&a6xx_gpu->gmu.lock); + + if (!ret) + msm_devfreq_resume(gpu); + + return ret; +} + +static int a6xx_gmu_pm_suspend(struct msm_gpu *gpu) { struct adreno_gpu *adreno_gpu =3D to_adreno_gpu(gpu); struct a6xx_gpu *a6xx_gpu =3D to_a6xx_gpu(adreno_gpu); @@ -1836,7 +1904,40 @@ static int a6xx_pm_suspend(struct msm_gpu *gpu) return 0; } =20 -static int a6xx_get_timestamp(struct msm_gpu *gpu, uint64_t *value) +static int a6xx_pm_suspend(struct msm_gpu *gpu) +{ + struct adreno_gpu *adreno_gpu =3D to_adreno_gpu(gpu); + struct a6xx_gpu *a6xx_gpu =3D to_a6xx_gpu(adreno_gpu); + struct a6xx_gmu *gmu =3D &a6xx_gpu->gmu; + int i; + + trace_msm_gpu_suspend(0); + + msm_devfreq_suspend(gpu); + + mutex_lock(&a6xx_gpu->gmu.lock); + + /* Drain the outstanding traffic on memory buses */ + a6xx_bus_clear_pending_transactions(adreno_gpu, true); + + clk_bulk_disable_unprepare(gpu->nr_clocks, gpu->grp_clks); + + pm_runtime_put_sync(gmu->gxpd); + dev_pm_opp_set_opp(&gpu->pdev->dev, NULL); + pm_runtime_put_sync(gmu->dev); + + mutex_unlock(&a6xx_gpu->gmu.lock); + + if (a6xx_gpu->shadow_bo) + for (i =3D 0; i < gpu->nr_rings; i++) + a6xx_gpu->shadow[i] =3D 0; + + gpu->suspend_count++; + + return 0; +} + +static int a6xx_gmu_get_timestamp(struct msm_gpu *gpu, uint64_t *value) { struct adreno_gpu *adreno_gpu =3D to_adreno_gpu(gpu); struct a6xx_gpu *a6xx_gpu =3D to_a6xx_gpu(adreno_gpu); @@ -1855,6 +1956,12 @@ static int a6xx_get_timestamp(struct msm_gpu *gpu, u= int64_t *value) return 0; } =20 +static int a6xx_get_timestamp(struct msm_gpu *gpu, uint64_t *value) +{ + *value =3D gpu_read64(gpu, REG_A6XX_CP_ALWAYS_ON_COUNTER); + return 0; +} + static struct msm_ringbuffer *a6xx_active_ring(struct msm_gpu *gpu) { struct adreno_gpu *adreno_gpu =3D to_adreno_gpu(gpu); @@ -2121,8 +2228,8 @@ static const struct adreno_gpu_funcs funcs =3D { .set_param =3D adreno_set_param, .hw_init =3D a6xx_hw_init, .ucode_load =3D a6xx_ucode_load, - .pm_suspend =3D a6xx_pm_suspend, - .pm_resume =3D a6xx_pm_resume, + .pm_suspend =3D a6xx_gmu_pm_suspend, + .pm_resume =3D a6xx_gmu_pm_resume, .recover =3D a6xx_recover, .submit =3D a6xx_submit, .active_ring =3D a6xx_active_ring, @@ -2137,6 +2244,35 @@ static const struct adreno_gpu_funcs funcs =3D { #if defined(CONFIG_DRM_MSM_GPU_STATE) .gpu_state_get =3D a6xx_gpu_state_get, .gpu_state_put =3D a6xx_gpu_state_put, +#endif + .create_address_space =3D a6xx_create_address_space, + .create_private_address_space =3D a6xx_create_private_address_space, + .get_rptr =3D a6xx_get_rptr, + .progress =3D a6xx_progress, + }, + .get_timestamp =3D a6xx_gmu_get_timestamp, +}; + +static const struct adreno_gpu_funcs funcs_gmuwrapper =3D { + .base =3D { + .get_param =3D adreno_get_param, + .set_param =3D adreno_set_param, + .hw_init =3D a6xx_hw_init, + .ucode_load =3D a6xx_ucode_load, + .pm_suspend =3D a6xx_pm_suspend, + .pm_resume =3D a6xx_pm_resume, + .recover =3D a6xx_recover, + .submit =3D a6xx_submit, + .active_ring =3D a6xx_active_ring, + .irq =3D a6xx_irq, + .destroy =3D a6xx_destroy, +#if defined(CONFIG_DRM_MSM_GPU_STATE) + .show =3D a6xx_show, +#endif + .gpu_busy =3D a6xx_gpu_busy, +#if defined(CONFIG_DRM_MSM_GPU_STATE) + .gpu_state_get =3D a6xx_gpu_state_get, + .gpu_state_put =3D a6xx_gpu_state_put, #endif .create_address_space =3D a6xx_create_address_space, .create_private_address_space =3D a6xx_create_private_address_space, @@ -2169,16 +2305,31 @@ struct msm_gpu *a6xx_gpu_init(struct drm_device *de= v) =20 adreno_gpu->registers =3D NULL; =20 + /* Check if there is a GMU phandle and set it up */ + node =3D of_parse_phandle(pdev->dev.of_node, "qcom,gmu", 0); + /* FIXME: How do we gracefully handle this? */ + BUG_ON(!node); + + adreno_gpu->gmu_is_wrapper =3D of_device_is_compatible(node, "qcom,adreno= -gmu-wrapper"); + /* * We need to know the platform type before calling into adreno_gpu_init * so that the hw_apriv flag can be correctly set. Snoop into the info * and grab the revision number */ info =3D adreno_info(config->rev); - - if (info && (info->revn =3D=3D 650 || info->revn =3D=3D 660 || - info->revn =3D=3D 690 || - adreno_cmp_rev(ADRENO_REV(6, 3, 5, ANY_ID), info->rev))) + if (!info) + return ERR_PTR(-EINVAL); + + /* Assign these early so that we can use the is_aXYZ helpers */ + /* Numeric revision IDs (e.g. 630) */ + adreno_gpu->revn =3D info->revn; + /* New-style ADRENO_REV()-only */ + adreno_gpu->rev =3D info->rev; + /* Quirk data */ + adreno_gpu->info =3D info; + + if (adreno_is_a650(adreno_gpu) || adreno_is_a660_family(adreno_gpu)) adreno_gpu->base.hw_apriv =3D true; =20 a6xx_llc_slices_init(pdev, a6xx_gpu); @@ -2189,7 +2340,10 @@ struct msm_gpu *a6xx_gpu_init(struct drm_device *dev) return ERR_PTR(ret); } =20 - ret =3D adreno_gpu_init(dev, pdev, adreno_gpu, &funcs, 1); + if (adreno_has_gmu_wrapper(adreno_gpu)) + ret =3D adreno_gpu_init(dev, pdev, adreno_gpu, &funcs_gmuwrapper, 1); + else + ret =3D adreno_gpu_init(dev, pdev, adreno_gpu, &funcs, 1); if (ret) { a6xx_destroy(&(a6xx_gpu->base.base)); return ERR_PTR(ret); @@ -2202,13 +2356,10 @@ struct msm_gpu *a6xx_gpu_init(struct drm_device *de= v) if (adreno_is_a618(adreno_gpu) || adreno_is_7c3(adreno_gpu)) priv->gpu_clamp_to_idle =3D true; =20 - /* Check if there is a GMU phandle and set it up */ - node =3D of_parse_phandle(pdev->dev.of_node, "qcom,gmu", 0); - - /* FIXME: How do we gracefully handle this? */ - BUG_ON(!node); - - ret =3D a6xx_gmu_init(a6xx_gpu, node); + if (adreno_has_gmu_wrapper(adreno_gpu)) + ret =3D a6xx_gmu_wrapper_init(a6xx_gpu, node); + else + ret =3D a6xx_gmu_init(a6xx_gpu, node); of_node_put(node); if (ret) { a6xx_destroy(&(a6xx_gpu->base.base)); diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.h b/drivers/gpu/drm/msm/ad= reno/a6xx_gpu.h index aa70390ee1c6..c788b06e72da 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.h +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.h @@ -76,6 +76,7 @@ int a6xx_gmu_set_oob(struct a6xx_gmu *gmu, enum a6xx_gmu_= oob_state state); void a6xx_gmu_clear_oob(struct a6xx_gmu *gmu, enum a6xx_gmu_oob_state stat= e); =20 int a6xx_gmu_init(struct a6xx_gpu *a6xx_gpu, struct device_node *node); +int a6xx_gmu_wrapper_init(struct a6xx_gpu *a6xx_gpu, struct device_node *n= ode); void a6xx_gmu_remove(struct a6xx_gpu *a6xx_gpu); =20 void a6xx_gmu_set_freq(struct msm_gpu *gpu, struct dev_pm_opp *opp, diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu_state.c b/drivers/gpu/drm/= msm/adreno/a6xx_gpu_state.c index 30ecdff363e7..4e5d650578c6 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu_state.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu_state.c @@ -1041,16 +1041,18 @@ struct msm_gpu_state *a6xx_gpu_state_get(struct msm= _gpu *gpu) /* Get the generic state from the adreno core */ adreno_gpu_state_get(gpu, &a6xx_state->base); =20 - a6xx_get_gmu_registers(gpu, a6xx_state); + if (!adreno_has_gmu_wrapper(adreno_gpu)) { + a6xx_get_gmu_registers(gpu, a6xx_state); =20 - a6xx_state->gmu_log =3D a6xx_snapshot_gmu_bo(a6xx_state, &a6xx_gpu->gmu.l= og); - a6xx_state->gmu_hfi =3D a6xx_snapshot_gmu_bo(a6xx_state, &a6xx_gpu->gmu.h= fi); - a6xx_state->gmu_debug =3D a6xx_snapshot_gmu_bo(a6xx_state, &a6xx_gpu->gmu= .debug); + a6xx_state->gmu_log =3D a6xx_snapshot_gmu_bo(a6xx_state, &a6xx_gpu->gmu.= log); + a6xx_state->gmu_hfi =3D a6xx_snapshot_gmu_bo(a6xx_state, &a6xx_gpu->gmu.= hfi); + a6xx_state->gmu_debug =3D a6xx_snapshot_gmu_bo(a6xx_state, &a6xx_gpu->gm= u.debug); =20 - a6xx_snapshot_gmu_hfi_history(gpu, a6xx_state); + a6xx_snapshot_gmu_hfi_history(gpu, a6xx_state); + } =20 /* If GX isn't on the rest of the data isn't going to be accessible */ - if (!a6xx_gmu_gx_is_on(&a6xx_gpu->gmu)) + if (!adreno_has_gmu_wrapper(adreno_gpu) && !a6xx_gmu_gx_is_on(&a6xx_gpu->= gmu)) return &a6xx_state->base; =20 /* Get the banks of indexed registers */ diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.c b/drivers/gpu/drm/msm/= adreno/adreno_gpu.c index 6934cee07d42..5c5901d65950 100644 --- a/drivers/gpu/drm/msm/adreno/adreno_gpu.c +++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.c @@ -528,6 +528,10 @@ int adreno_load_fw(struct adreno_gpu *adreno_gpu) if (!adreno_gpu->info->fw[i]) continue; =20 + /* Skip loading GMU firwmare with GMU Wrapper */ + if (adreno_has_gmu_wrapper(adreno_gpu) && i =3D=3D ADRENO_FW_GMU) + continue; + /* Skip if the firmware has already been loaded */ if (adreno_gpu->fw[i]) continue; @@ -1074,8 +1078,8 @@ int adreno_gpu_init(struct drm_device *drm, struct pl= atform_device *pdev, u32 speedbin; int ret; =20 - /* Only handle the core clock when GMU is not in use */ - if (config->rev.core < 6) { + /* Only handle the core clock when GMU is not in use (or is absent). */ + if (adreno_has_gmu_wrapper(adreno_gpu) || config->rev.core < 6) { /* * This can only be done before devm_pm_opp_of_add_table(), or * dev_pm_opp_set_config() will WARN_ON() diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.h b/drivers/gpu/drm/msm/= adreno/adreno_gpu.h index 5a26c8a2de7c..de0b03a4b594 100644 --- a/drivers/gpu/drm/msm/adreno/adreno_gpu.h +++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.h @@ -115,6 +115,7 @@ struct adreno_gpu { * code (a3xx_gpu.c) and stored in this common location. */ const unsigned int *reg_offsets; + bool gmu_is_wrapper; }; #define to_adreno_gpu(x) container_of(x, struct adreno_gpu, base) =20 @@ -152,6 +153,11 @@ static inline bool adreno_is_revn(const struct adreno_= gpu *gpu, uint32_t revn) return gpu->revn =3D=3D revn; } =20 +static inline bool adreno_has_gmu_wrapper(const struct adreno_gpu *gpu) +{ + return gpu->gmu_is_wrapper; +} + static inline bool adreno_is_a2xx(const struct adreno_gpu *gpu) { WARN_ON_ONCE(!gpu->revn); --=20 2.41.0 From nobody Tue Sep 9 17:14:06 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 10E59EB64DA for ; Thu, 15 Jun 2023 23:22:27 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232728AbjFOXWZ (ORCPT ); Thu, 15 Jun 2023 19:22:25 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:46258 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S239645AbjFOXVy (ORCPT ); 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[83.9.29.190]) by smtp.gmail.com with ESMTPSA id u25-20020a056512041900b004f24ee39661sm2744852lfk.137.2023.06.15.16.21.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 15 Jun 2023 16:21:37 -0700 (PDT) From: Konrad Dybcio Date: Fri, 16 Jun 2023 01:20:54 +0200 Subject: [PATCH v9 13/20] drm/msm/adreno: Disable has_cached_coherent in GMU wrapper configurations MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20230223-topic-gmuwrapper-v9-13-890d8f470c8b@linaro.org> References: <20230223-topic-gmuwrapper-v9-0-890d8f470c8b@linaro.org> In-Reply-To: <20230223-topic-gmuwrapper-v9-0-890d8f470c8b@linaro.org> To: Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , David Airlie , Daniel Vetter , Rob Herring , Krzysztof Kozlowski , Bjorn Andersson , Konrad Dybcio , Akhil P Oommen , Conor Dooley Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Rob Clark , Marijn Suijten , Konrad Dybcio X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1686871277; l=1430; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=Xr2C8rg/eKOmAE/x7OQkyp9EfaNGZPqe0Lxab2HmrKc=; b=TWC5nlDeosgnXX2hBRiZbEr49M/kZJyXkjcjYXovl75lUeVOVfWfpQHiyUExXRwOxGl584SWi syvk1F4dNg8C7yPvZHL//bi07kvZ0H4NybFifTpcpmrERp0LVo2IVyL X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org A610 and A619_holi don't support the feature. Disable it to make the GPU st= op crashing after almost each and every submission - the received data on the GPU end was simply incomplete in garbled, resulting in almost nothing being executed properly. Extend the disablement to adreno_has_gmu_wrapper, as none of the GMU wrapper Adrenos that don't support yet seem to feature i= t. Reviewed-by: Akhil P Oommen Signed-off-by: Konrad Dybcio --- drivers/gpu/drm/msm/adreno/adreno_device.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/msm/adreno/adreno_device.c b/drivers/gpu/drm/m= sm/adreno/adreno_device.c index e5a865024e94..6ea24b8ddcf8 100644 --- a/drivers/gpu/drm/msm/adreno/adreno_device.c +++ b/drivers/gpu/drm/msm/adreno/adreno_device.c @@ -565,7 +565,6 @@ static int adreno_bind(struct device *dev, struct devic= e *master, void *data) config.rev.minor, config.rev.patchid); =20 priv->is_a2xx =3D config.rev.core =3D=3D 2; - priv->has_cached_coherent =3D config.rev.core >=3D 6; =20 gpu =3D info->init(drm); if (IS_ERR(gpu)) { @@ -577,6 +576,10 @@ static int adreno_bind(struct device *dev, struct devi= ce *master, void *data) if (ret) return ret; =20 + if (config.rev.core >=3D 6) + if (!adreno_has_gmu_wrapper(to_adreno_gpu(gpu))) + priv->has_cached_coherent =3D true; + return 0; } =20 --=20 2.41.0 From nobody Tue Sep 9 17:14:06 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 76C4FEB64D9 for ; Thu, 15 Jun 2023 23:22:36 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230081AbjFOXWe (ORCPT ); Thu, 15 Jun 2023 19:22:34 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:46434 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S239185AbjFOXWF (ORCPT ); Thu, 15 Jun 2023 19:22:05 -0400 Received: from mail-lf1-x131.google.com (mail-lf1-x131.google.com [IPv6:2a00:1450:4864:20::131]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 5505830DC for ; Thu, 15 Jun 2023 16:21:41 -0700 (PDT) Received: by mail-lf1-x131.google.com with SMTP id 2adb3069b0e04-4f640e48bc3so11252696e87.2 for ; Thu, 15 Jun 2023 16:21:41 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1686871299; x=1689463299; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=L+TVhBBKRUS2B/z8pS7wjP7swdoiJrJVs5F8KW7VIYM=; b=WV8n5HFl5rBMncwRQgxWFtUGnZvsSUJAk14Qygq5K/fTGLN9SXB3p2pM3AONYV2eRR nWPHVuR3fIJk7+DTgIGp31tnAl2qja+52rui9M+JCAxZ8PB+Z01D/zZLK3427nj/Sf7r Zm/PsV+3NBN+eYLYFmYZACGDtHO4cevmrrFfDcqIVmHRJ0zWn+RLhufwZFjpH39nZnzA pfRylr+GqtkIKmj9nq71JxApn8vHr7nhy4TMlLX7fsxTJncyraEThweMrBzUvq45mTrq eK5uN5UDUTOYhrj+Fg1QpXKxJbLn/VvyT8eieWEzFvqiSddoijBWYAN2yrqhogdlpjlc hgrg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1686871299; x=1689463299; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=L+TVhBBKRUS2B/z8pS7wjP7swdoiJrJVs5F8KW7VIYM=; b=dut47daulvHlkOfr8DDNa86FHT8In8Rf4begChnJGVDljHAD5Sy3c8qDz0pVc6oAWu TdpoqUMbkrnb+nSSLvmKahBv1E0bx0gKsNjbvTJbmcTsIS22uAthFL/2s4qGcHhNwUJ6 7rnNxy7yhGERBFz9tFKN2qaMNbuYNMQk0093vWl1qaeybOYEzWDkKYN9Ka8vVYQY3Xk3 VZmS7qs7L4DHQXLflfZN3QNGM+QeFCnmln1u2mM9xDy7SJTUDtQ+yxJfgoYQ5mlEk5g8 8eBND0g/fYJf9y9iYW80rMYb5h9tsTrxkoIjKOWKagpH+0zfhQyIVdLohSPef2Gs7qAk qgCg== X-Gm-Message-State: AC+VfDyohypz4anGaAsG3elxGYjZ8fz3pBH5mkLaOmk9P8wypRE2p+cF b4xPQQjYoVpknHF34uRAN2Yhqg== X-Google-Smtp-Source: ACHHUZ4n36pYAckaRYbqmGsxTzHTFoV5ax5z5iMVD0zHb+446aB8zkIuGFCiXjQAg0ZUIdpQBbM+Ig== X-Received: by 2002:a19:8c02:0:b0:4f8:4961:6aa9 with SMTP id o2-20020a198c02000000b004f849616aa9mr99387lfd.8.1686871299682; Thu, 15 Jun 2023 16:21:39 -0700 (PDT) Received: from [192.168.1.101] (abyj190.neoplus.adsl.tpnet.pl. [83.9.29.190]) by smtp.gmail.com with ESMTPSA id u25-20020a056512041900b004f24ee39661sm2744852lfk.137.2023.06.15.16.21.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 15 Jun 2023 16:21:39 -0700 (PDT) From: Konrad Dybcio Date: Fri, 16 Jun 2023 01:20:55 +0200 Subject: [PATCH v9 14/20] drm/msm/a6xx: Add support for A619_holi MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20230223-topic-gmuwrapper-v9-14-890d8f470c8b@linaro.org> References: <20230223-topic-gmuwrapper-v9-0-890d8f470c8b@linaro.org> In-Reply-To: <20230223-topic-gmuwrapper-v9-0-890d8f470c8b@linaro.org> To: Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , David Airlie , Daniel Vetter , Rob Herring , Krzysztof Kozlowski , Bjorn Andersson , Konrad Dybcio , Akhil P Oommen , Conor Dooley Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Rob Clark , Marijn Suijten , Konrad Dybcio X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1686871277; l=4063; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=ATtA2V/YLegt8/q2Uu20SduFtLhbxHciiWCX+CGAu+4=; b=+ygqn6qEEI4gFIhGSWrLrM1KaKJPg06Dr12/WJ1UnxAa0ImLj7nrdziLC4Pk++hsQ2h46rcD1 uFozTkkHrmlBhpfeAT7V7g3aGQIeZGhKeI9WaoHdKYl8hAYqmIk5rPx X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org A619_holi is a GMU-less variant of the already-supported A619 GPU. It's present on at least SM4350 (holi) and SM6375 (blair). No mesa changes are required. Add the required kernel-side support for it. Signed-off-by: Konrad Dybcio --- drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 27 +++++++++++++++++++++++++-- drivers/gpu/drm/msm/adreno/adreno_gpu.h | 5 +++++ 2 files changed, 30 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/ad= reno/a6xx_gpu.c index b91fc02eb08c..2ca9e0440396 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c @@ -911,6 +911,9 @@ static void a6xx_set_ubwc_config(struct msm_gpu *gpu) if (adreno_is_a618(adreno_gpu)) return; =20 + if (adreno_is_a619_holi(adreno_gpu)) + hbb_lo =3D 0; + if (adreno_is_a640_family(adreno_gpu)) amsbc =3D 1; =20 @@ -1135,7 +1138,12 @@ static int hw_init(struct msm_gpu *gpu) } =20 /* Clear GBIF halt in case GX domain was not collapsed */ - if (a6xx_has_gbif(adreno_gpu)) { + if (adreno_is_a619_holi(adreno_gpu)) { + gpu_write(gpu, REG_A6XX_GBIF_HALT, 0); + gpu_write(gpu, REG_A6XX_RBBM_GPR0_CNTL, 0); + /* Let's make extra sure that the GPU can access the memory.. */ + mb(); + } else if (a6xx_has_gbif(adreno_gpu)) { gpu_write(gpu, REG_A6XX_GBIF_HALT, 0); gpu_write(gpu, REG_A6XX_RBBM_GBIF_HALT, 0); /* Let's make extra sure that the GPU can access the memory.. */ @@ -1144,6 +1152,9 @@ static int hw_init(struct msm_gpu *gpu) =20 gpu_write(gpu, REG_A6XX_RBBM_SECVID_TSB_CNTL, 0); =20 + if (adreno_is_a619_holi(adreno_gpu)) + a6xx_sptprac_enable(gmu); + /* * Disable the trusted memory range - we don't actually supported secure * memory rendering at this point in time and we don't want to block off @@ -1760,12 +1771,18 @@ static void a6xx_llc_slices_init(struct platform_de= vice *pdev, #define GBIF_CLIENT_HALT_MASK BIT(0) #define GBIF_ARB_HALT_MASK BIT(1) #define VBIF_XIN_HALT_CTRL0_MASK GENMASK(3, 0) +#define VBIF_RESET_ACK_MASK 0xF0 +#define GPR0_GBIF_HALT_REQUEST 0x1E0 =20 void a6xx_bus_clear_pending_transactions(struct adreno_gpu *adreno_gpu, bo= ol gx_off) { struct msm_gpu *gpu =3D &adreno_gpu->base; =20 - if (!a6xx_has_gbif(adreno_gpu)) { + if (adreno_is_a619_holi(adreno_gpu)) { + gpu_write(gpu, REG_A6XX_RBBM_GPR0_CNTL, GPR0_GBIF_HALT_REQUEST); + spin_until((gpu_read(gpu, REG_A6XX_RBBM_VBIF_GX_RESET_STATUS) & + (VBIF_RESET_ACK_MASK)) =3D=3D VBIF_RESET_ACK_MASK); + } else if (!a6xx_has_gbif(adreno_gpu)) { gpu_write(gpu, REG_A6XX_VBIF_XIN_HALT_CTRL0, VBIF_XIN_HALT_CTRL0_MASK); spin_until((gpu_read(gpu, REG_A6XX_VBIF_XIN_HALT_CTRL1) & (VBIF_XIN_HALT_CTRL0_MASK)) =3D=3D VBIF_XIN_HALT_CTRL0_MASK); @@ -1861,6 +1878,9 @@ static int a6xx_pm_resume(struct msm_gpu *gpu) if (ret) goto err_bulk_clk; =20 + if (adreno_is_a619_holi(adreno_gpu)) + a6xx_sptprac_enable(gmu); + /* If anything goes south, tear the GPU down piece by piece.. */ if (ret) { err_bulk_clk: @@ -1920,6 +1940,9 @@ static int a6xx_pm_suspend(struct msm_gpu *gpu) /* Drain the outstanding traffic on memory buses */ a6xx_bus_clear_pending_transactions(adreno_gpu, true); =20 + if (adreno_is_a619_holi(adreno_gpu)) + a6xx_sptprac_disable(gmu); + clk_bulk_disable_unprepare(gpu->nr_clocks, gpu->grp_clks); =20 pm_runtime_put_sync(gmu->gxpd); diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.h b/drivers/gpu/drm/msm/= adreno/adreno_gpu.h index de0b03a4b594..efd35b7bc4cf 100644 --- a/drivers/gpu/drm/msm/adreno/adreno_gpu.h +++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.h @@ -263,6 +263,11 @@ static inline int adreno_is_a619(const struct adreno_g= pu *gpu) return adreno_is_revn(gpu, 619); } =20 +static inline int adreno_is_a619_holi(const struct adreno_gpu *gpu) +{ + return adreno_is_a619(gpu) && adreno_has_gmu_wrapper(gpu); +} + static inline int adreno_is_a630(const struct adreno_gpu *gpu) { return adreno_is_revn(gpu, 630); --=20 2.41.0 From nobody Tue Sep 9 17:14:06 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id A4876EB64DB for ; Thu, 15 Jun 2023 23:22:43 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S240117AbjFOXWm (ORCPT ); Thu, 15 Jun 2023 19:22:42 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:45902 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S240102AbjFOXWI (ORCPT ); Thu, 15 Jun 2023 19:22:08 -0400 Received: from mail-lf1-x12f.google.com (mail-lf1-x12f.google.com [IPv6:2a00:1450:4864:20::12f]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 6291D2976 for ; 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[83.9.29.190]) by smtp.gmail.com with ESMTPSA id u25-20020a056512041900b004f24ee39661sm2744852lfk.137.2023.06.15.16.21.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 15 Jun 2023 16:21:40 -0700 (PDT) From: Konrad Dybcio Date: Fri, 16 Jun 2023 01:20:56 +0200 Subject: [PATCH v9 15/20] drm/msm/a6xx: Add A610 support MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20230223-topic-gmuwrapper-v9-15-890d8f470c8b@linaro.org> References: <20230223-topic-gmuwrapper-v9-0-890d8f470c8b@linaro.org> In-Reply-To: <20230223-topic-gmuwrapper-v9-0-890d8f470c8b@linaro.org> To: Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , David Airlie , Daniel Vetter , Rob Herring , Krzysztof Kozlowski , Bjorn Andersson , Konrad Dybcio , Akhil P Oommen , Conor Dooley Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Rob Clark , Marijn Suijten , Konrad Dybcio X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1686871277; l=10797; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=o1jpKvRp4VpeNX3sBcuDTmgqNGNcqTvXnAAs/T7l/OE=; b=slpXbwZogsvwgsh8jIvnGAYfqRUkgGGMB7R6iwOVmNDvzNtDsSTavqHBds3Kqew3yEJvVHXx3 T6Ka1icytmVBH73KLRWhUlUYa8tgopE4UceQxnsp9W+5YrGLZjrZpq9 X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org A610 is one of (if not the) lowest-tier SKUs in the A6XX family. It features no GMU, as it's implemented solely on SoCs with SMD_RPM. What's more interesting is that it does not feature a VDDGX line either, being powered solely by VDDCX and has an unfortunate hardware quirk that makes its reset line broken - after a couple of assert/ deassert cycles, it will hang for good and will not wake up again. This GPU requires mesa changes for proper rendering, and lots of them at that. The command streams are quite far away from any other A6XX GPU and hence it needs special care. This patch was validated both by running an (incomplete) downstream mesa with some hacks (frames rendered correctly, though some instructions made the GPU hangcheck which is expected - garbage in, garbage out) and by replaying RD traces captured with the downstream KGSL driver - no crashes there, ever. Add support for this GPU on the kernel side, which comes down to pretty simply adding A612 HWCG tables, altering a few values and adding a special case for handling the reset line. Reviewed-by: Dmitry Baryshkov Signed-off-by: Konrad Dybcio --- drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 99 ++++++++++++++++++++++++++= ---- drivers/gpu/drm/msm/adreno/adreno_device.c | 12 ++++ drivers/gpu/drm/msm/adreno/adreno_gpu.h | 8 ++- 3 files changed, 107 insertions(+), 12 deletions(-) diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/ad= reno/a6xx_gpu.c index 2ca9e0440396..47aafc9deaf8 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c @@ -252,6 +252,56 @@ static void a6xx_submit(struct msm_gpu *gpu, struct ms= m_gem_submit *submit) a6xx_flush(gpu, ring); } =20 +const struct adreno_reglist a612_hwcg[] =3D { + {REG_A6XX_RBBM_CLOCK_CNTL_SP0, 0x22222222}, + {REG_A6XX_RBBM_CLOCK_CNTL2_SP0, 0x02222220}, + {REG_A6XX_RBBM_CLOCK_DELAY_SP0, 0x00000081}, + {REG_A6XX_RBBM_CLOCK_HYST_SP0, 0x0000f3cf}, + {REG_A6XX_RBBM_CLOCK_CNTL_TP0, 0x22222222}, + {REG_A6XX_RBBM_CLOCK_CNTL2_TP0, 0x22222222}, + {REG_A6XX_RBBM_CLOCK_CNTL3_TP0, 0x22222222}, + {REG_A6XX_RBBM_CLOCK_CNTL4_TP0, 0x00022222}, + {REG_A6XX_RBBM_CLOCK_DELAY_TP0, 0x11111111}, + {REG_A6XX_RBBM_CLOCK_DELAY2_TP0, 0x11111111}, + {REG_A6XX_RBBM_CLOCK_DELAY3_TP0, 0x11111111}, + {REG_A6XX_RBBM_CLOCK_DELAY4_TP0, 0x00011111}, + {REG_A6XX_RBBM_CLOCK_HYST_TP0, 0x77777777}, + {REG_A6XX_RBBM_CLOCK_HYST2_TP0, 0x77777777}, + {REG_A6XX_RBBM_CLOCK_HYST3_TP0, 0x77777777}, + {REG_A6XX_RBBM_CLOCK_HYST4_TP0, 0x00077777}, + {REG_A6XX_RBBM_CLOCK_CNTL_RB0, 0x22222222}, + {REG_A6XX_RBBM_CLOCK_CNTL2_RB0, 0x01202222}, + {REG_A6XX_RBBM_CLOCK_CNTL_CCU0, 0x00002220}, + {REG_A6XX_RBBM_CLOCK_HYST_RB_CCU0, 0x00040f00}, + {REG_A6XX_RBBM_CLOCK_CNTL_RAC, 0x05522022}, + {REG_A6XX_RBBM_CLOCK_CNTL2_RAC, 0x00005555}, + {REG_A6XX_RBBM_CLOCK_DELAY_RAC, 0x00000011}, + {REG_A6XX_RBBM_CLOCK_HYST_RAC, 0x00445044}, + {REG_A6XX_RBBM_CLOCK_CNTL_TSE_RAS_RBBM, 0x04222222}, + {REG_A6XX_RBBM_CLOCK_MODE_VFD, 0x00002222}, + {REG_A6XX_RBBM_CLOCK_MODE_GPC, 0x02222222}, + {REG_A6XX_RBBM_CLOCK_DELAY_HLSQ_2, 0x00000002}, + {REG_A6XX_RBBM_CLOCK_MODE_HLSQ, 0x00002222}, + {REG_A6XX_RBBM_CLOCK_DELAY_TSE_RAS_RBBM, 0x00004000}, + {REG_A6XX_RBBM_CLOCK_DELAY_VFD, 0x00002222}, + {REG_A6XX_RBBM_CLOCK_DELAY_GPC, 0x00000200}, + {REG_A6XX_RBBM_CLOCK_DELAY_HLSQ, 0x00000000}, + {REG_A6XX_RBBM_CLOCK_HYST_TSE_RAS_RBBM, 0x00000000}, + {REG_A6XX_RBBM_CLOCK_HYST_VFD, 0x00000000}, + {REG_A6XX_RBBM_CLOCK_HYST_GPC, 0x04104004}, + {REG_A6XX_RBBM_CLOCK_HYST_HLSQ, 0x00000000}, + {REG_A6XX_RBBM_CLOCK_CNTL_UCHE, 0x22222222}, + {REG_A6XX_RBBM_CLOCK_HYST_UCHE, 0x00000004}, + {REG_A6XX_RBBM_CLOCK_DELAY_UCHE, 0x00000002}, + {REG_A6XX_RBBM_ISDB_CNT, 0x00000182}, + {REG_A6XX_RBBM_RAC_THRESHOLD_CNT, 0x00000000}, + {REG_A6XX_RBBM_SP_HYST_CNT, 0x00000000}, + {REG_A6XX_RBBM_CLOCK_CNTL_GMU_GX, 0x00000222}, + {REG_A6XX_RBBM_CLOCK_DELAY_GMU_GX, 0x00000111}, + {REG_A6XX_RBBM_CLOCK_HYST_GMU_GX, 0x00000555}, + {}, +}; + /* For a615 family (a615, a616, a618 and a619) */ const struct adreno_reglist a615_hwcg[] =3D { {REG_A6XX_RBBM_CLOCK_CNTL_SP0, 0x02222222}, @@ -659,6 +709,8 @@ static void a6xx_set_hwcg(struct msm_gpu *gpu, bool sta= te) =20 if (adreno_is_a630(adreno_gpu)) clock_cntl_on =3D 0x8aa8aa02; + else if (adreno_is_a610(adreno_gpu)) + clock_cntl_on =3D 0xaaa8aa82; else clock_cntl_on =3D 0x8aa8aa82; =20 @@ -669,13 +721,15 @@ static void a6xx_set_hwcg(struct msm_gpu *gpu, bool s= tate) return; =20 /* Disable SP clock before programming HWCG registers */ - gmu_rmw(gmu, REG_A6XX_GPU_GMU_GX_SPTPRAC_CLOCK_CONTROL, 1, 0); + if (!adreno_is_a610(adreno_gpu)) + gmu_rmw(gmu, REG_A6XX_GPU_GMU_GX_SPTPRAC_CLOCK_CONTROL, 1, 0); =20 for (i =3D 0; (reg =3D &adreno_gpu->info->hwcg[i], reg->offset); i++) gpu_write(gpu, reg->offset, state ? reg->value : 0); =20 /* Enable SP clock */ - gmu_rmw(gmu, REG_A6XX_GPU_GMU_GX_SPTPRAC_CLOCK_CONTROL, 0, 1); + if (!adreno_is_a610(adreno_gpu)) + gmu_rmw(gmu, REG_A6XX_GPU_GMU_GX_SPTPRAC_CLOCK_CONTROL, 0, 1); =20 gpu_write(gpu, REG_A6XX_RBBM_CLOCK_CNTL, state ? clock_cntl_on : 0); } @@ -907,6 +961,13 @@ static void a6xx_set_ubwc_config(struct msm_gpu *gpu) /* Unknown, introduced with A640/680 */ u32 amsbc =3D 0; =20 + if (adreno_is_a610(adreno_gpu)) { + /* HBB =3D 14 */ + hbb_lo =3D 1; + min_acc_len =3D 1; + ubwc_mode =3D 1; + } + /* a618 is using the hw default values */ if (adreno_is_a618(adreno_gpu)) return; @@ -1181,13 +1242,13 @@ static int hw_init(struct msm_gpu *gpu) a6xx_set_hwcg(gpu, true); =20 /* VBIF/GBIF start*/ - if (adreno_is_a640_family(adreno_gpu) || + if (adreno_is_a610(adreno_gpu) || + adreno_is_a640_family(adreno_gpu) || adreno_is_a650_family(adreno_gpu)) { gpu_write(gpu, REG_A6XX_GBIF_QSB_SIDE0, 0x00071620); gpu_write(gpu, REG_A6XX_GBIF_QSB_SIDE1, 0x00071620); gpu_write(gpu, REG_A6XX_GBIF_QSB_SIDE2, 0x00071620); gpu_write(gpu, REG_A6XX_GBIF_QSB_SIDE3, 0x00071620); - gpu_write(gpu, REG_A6XX_GBIF_QSB_SIDE3, 0x00071620); gpu_write(gpu, REG_A6XX_RBBM_GBIF_CLIENT_QOS_CNTL, 0x3); } else { gpu_write(gpu, REG_A6XX_RBBM_VBIF_CLIENT_QOS_CNTL, 0x3); @@ -1215,18 +1276,26 @@ static int hw_init(struct msm_gpu *gpu) gpu_write(gpu, REG_A6XX_UCHE_FILTER_CNTL, 0x804); gpu_write(gpu, REG_A6XX_UCHE_CACHE_WAYS, 0x4); =20 - if (adreno_is_a640_family(adreno_gpu) || - adreno_is_a650_family(adreno_gpu)) + if (adreno_is_a640_family(adreno_gpu) || adreno_is_a650_family(adreno_gpu= )) { gpu_write(gpu, REG_A6XX_CP_ROQ_THRESHOLDS_2, 0x02000140); - else + gpu_write(gpu, REG_A6XX_CP_ROQ_THRESHOLDS_1, 0x8040362c); + } else if (adreno_is_a610(adreno_gpu)) { + gpu_write(gpu, REG_A6XX_CP_ROQ_THRESHOLDS_2, 0x00800060); + gpu_write(gpu, REG_A6XX_CP_ROQ_THRESHOLDS_1, 0x40201b16); + } else { gpu_write(gpu, REG_A6XX_CP_ROQ_THRESHOLDS_2, 0x010000c0); - gpu_write(gpu, REG_A6XX_CP_ROQ_THRESHOLDS_1, 0x8040362c); + gpu_write(gpu, REG_A6XX_CP_ROQ_THRESHOLDS_1, 0x8040362c); + } =20 if (adreno_is_a660_family(adreno_gpu)) gpu_write(gpu, REG_A6XX_CP_LPAC_PROG_FIFO_SIZE, 0x00000020); =20 /* Setting the mem pool size */ - gpu_write(gpu, REG_A6XX_CP_MEM_POOL_SIZE, 128); + if (adreno_is_a610(adreno_gpu)) { + gpu_write(gpu, REG_A6XX_CP_MEM_POOL_SIZE, 48); + gpu_write(gpu, REG_A6XX_CP_MEM_POOL_DBG_ADDR, 47); + } else + gpu_write(gpu, REG_A6XX_CP_MEM_POOL_SIZE, 128); =20 /* Setting the primFifo thresholds default values, * and vccCacheSkipDis=3D1 bit (0x200) for A640 and newer @@ -1237,6 +1306,8 @@ static int hw_init(struct msm_gpu *gpu) gpu_write(gpu, REG_A6XX_PC_DBG_ECO_CNTL, 0x00200200); else if (adreno_is_a650(adreno_gpu) || adreno_is_a660(adreno_gpu)) gpu_write(gpu, REG_A6XX_PC_DBG_ECO_CNTL, 0x00300200); + else if (adreno_is_a610(adreno_gpu)) + gpu_write(gpu, REG_A6XX_PC_DBG_ECO_CNTL, 0x00080000); else gpu_write(gpu, REG_A6XX_PC_DBG_ECO_CNTL, 0x00180000); =20 @@ -1252,8 +1323,10 @@ static int hw_init(struct msm_gpu *gpu) a6xx_set_ubwc_config(gpu); =20 /* Enable fault detection */ - gpu_write(gpu, REG_A6XX_RBBM_INTERFACE_HANG_INT_CNTL, - (1 << 30) | 0x1fffff); + if (adreno_is_a610(adreno_gpu)) + gpu_write(gpu, REG_A6XX_RBBM_INTERFACE_HANG_INT_CNTL, (1 << 30) | 0x3fff= f); + else + gpu_write(gpu, REG_A6XX_RBBM_INTERFACE_HANG_INT_CNTL, (1 << 30) | 0x1fff= ff); =20 gpu_write(gpu, REG_A6XX_UCHE_CLIENT_PF, 1); =20 @@ -1813,6 +1886,10 @@ void a6xx_bus_clear_pending_transactions(struct adre= no_gpu *adreno_gpu, bool gx_ =20 void a6xx_gpu_sw_reset(struct msm_gpu *gpu, bool assert) { + /* 11nm chips (e.g. ones with A610) have hw issues with the reset line! */ + if (adreno_is_a610(to_adreno_gpu(gpu))) + return; + gpu_write(gpu, REG_A6XX_RBBM_SW_RESET_CMD, assert); /* Perform a bogus read and add a brief delay to ensure ordering. */ gpu_read(gpu, REG_A6XX_RBBM_SW_RESET_CMD); diff --git a/drivers/gpu/drm/msm/adreno/adreno_device.c b/drivers/gpu/drm/m= sm/adreno/adreno_device.c index 6ea24b8ddcf8..cb94cfd137a8 100644 --- a/drivers/gpu/drm/msm/adreno/adreno_device.c +++ b/drivers/gpu/drm/msm/adreno/adreno_device.c @@ -253,6 +253,18 @@ static const struct adreno_info gpulist[] =3D { .quirks =3D ADRENO_QUIRK_LMLOADKILL_DISABLE, .init =3D a5xx_gpu_init, .zapfw =3D "a540_zap.mdt", + }, { + .rev =3D ADRENO_REV(6, 1, 0, ANY_ID), + .revn =3D 610, + .name =3D "A610", + .fw =3D { + [ADRENO_FW_SQE] =3D "a630_sqe.fw", + }, + .gmem =3D (SZ_128K + SZ_4K), + .inactive_period =3D DRM_MSM_INACTIVE_PERIOD, + .init =3D a6xx_gpu_init, + .zapfw =3D "a610_zap.mdt", + .hwcg =3D a612_hwcg, }, { .rev =3D ADRENO_REV(6, 1, 8, ANY_ID), .revn =3D 618, diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.h b/drivers/gpu/drm/msm/= adreno/adreno_gpu.h index efd35b7bc4cf..3a8af5fdaea8 100644 --- a/drivers/gpu/drm/msm/adreno/adreno_gpu.h +++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.h @@ -55,7 +55,8 @@ struct adreno_reglist { u32 value; }; =20 -extern const struct adreno_reglist a615_hwcg[], a630_hwcg[], a640_hwcg[], = a650_hwcg[], a660_hwcg[], a690_hwcg[]; +extern const struct adreno_reglist a612_hwcg[], a615_hwcg[], a630_hwcg[], = a640_hwcg[], a650_hwcg[]; +extern const struct adreno_reglist a660_hwcg[], a690_hwcg[]; =20 struct adreno_info { struct adreno_rev rev; @@ -253,6 +254,11 @@ static inline int adreno_is_a540(const struct adreno_g= pu *gpu) return adreno_is_revn(gpu, 540); } =20 +static inline int adreno_is_a610(const struct adreno_gpu *gpu) +{ + return adreno_is_revn(gpu, 610); +} + static inline int adreno_is_a618(const struct adreno_gpu *gpu) { return adreno_is_revn(gpu, 618); --=20 2.41.0 From nobody Tue Sep 9 17:14:06 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id AF325EB64DA for ; Thu, 15 Jun 2023 23:22:50 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S240151AbjFOXWs (ORCPT ); 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[83.9.29.190]) by smtp.gmail.com with ESMTPSA id u25-20020a056512041900b004f24ee39661sm2744852lfk.137.2023.06.15.16.21.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 15 Jun 2023 16:21:42 -0700 (PDT) From: Konrad Dybcio Date: Fri, 16 Jun 2023 01:20:57 +0200 Subject: [PATCH v9 16/20] drm/msm/a6xx: Fix some A619 tunables MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20230223-topic-gmuwrapper-v9-16-890d8f470c8b@linaro.org> References: <20230223-topic-gmuwrapper-v9-0-890d8f470c8b@linaro.org> In-Reply-To: <20230223-topic-gmuwrapper-v9-0-890d8f470c8b@linaro.org> To: Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , David Airlie , Daniel Vetter , Rob Herring , Krzysztof Kozlowski , Bjorn Andersson , Konrad Dybcio , Akhil P Oommen , Conor Dooley Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Rob Clark , Marijn Suijten , Konrad Dybcio X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1686871277; l=1593; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=4Gkjo2VDVoi67z3y3hIRakJY3LPFFJYUf+088rGo/nQ=; b=plJVOj6DU3u87R7U6VX8KOxp/8dRK/42FlGKYQ7gNc1INHp6+QX8s1lmrdm+M4+MaPJrbMWvx ML+PsOizE9eB34tgy9ZV8Xxcz1cu5Tc/vi4y24gMwVwfEiFZ1VmlY1i X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Adreno 619 expects some tunables to be set differently. Make up for it. Fixes: b7616b5c69e6 ("drm/msm/adreno: Add A619 support") Reviewed-by: Dmitry Baryshkov Reviewed-by: Akhil P Oommen Signed-off-by: Konrad Dybcio --- drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/ad= reno/a6xx_gpu.c index 47aafc9deaf8..97e261d33312 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c @@ -1306,6 +1306,8 @@ static int hw_init(struct msm_gpu *gpu) gpu_write(gpu, REG_A6XX_PC_DBG_ECO_CNTL, 0x00200200); else if (adreno_is_a650(adreno_gpu) || adreno_is_a660(adreno_gpu)) gpu_write(gpu, REG_A6XX_PC_DBG_ECO_CNTL, 0x00300200); + else if (adreno_is_a619(adreno_gpu)) + gpu_write(gpu, REG_A6XX_PC_DBG_ECO_CNTL, 0x00018000); else if (adreno_is_a610(adreno_gpu)) gpu_write(gpu, REG_A6XX_PC_DBG_ECO_CNTL, 0x00080000); else @@ -1323,7 +1325,9 @@ static int hw_init(struct msm_gpu *gpu) a6xx_set_ubwc_config(gpu); =20 /* Enable fault detection */ - if (adreno_is_a610(adreno_gpu)) + if (adreno_is_a619(adreno_gpu)) + gpu_write(gpu, REG_A6XX_RBBM_INTERFACE_HANG_INT_CNTL, (1 << 30) | 0x3fff= ff); + else if (adreno_is_a610(adreno_gpu)) gpu_write(gpu, REG_A6XX_RBBM_INTERFACE_HANG_INT_CNTL, (1 << 30) | 0x3fff= f); else gpu_write(gpu, REG_A6XX_RBBM_INTERFACE_HANG_INT_CNTL, (1 << 30) | 0x1fff= ff); --=20 2.41.0 From nobody Tue Sep 9 17:14:06 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2F4EAEB64D9 for ; Thu, 15 Jun 2023 23:23:05 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S240267AbjFOXXD (ORCPT ); Thu, 15 Jun 2023 19:23:03 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:46552 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S240240AbjFOXWK (ORCPT ); Thu, 15 Jun 2023 19:22:10 -0400 Received: from mail-lf1-x136.google.com (mail-lf1-x136.google.com [IPv6:2a00:1450:4864:20::136]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id EE33630E1 for ; Thu, 15 Jun 2023 16:21:45 -0700 (PDT) Received: by mail-lf1-x136.google.com with SMTP id 2adb3069b0e04-4f76a4c211dso3260608e87.3 for ; Thu, 15 Jun 2023 16:21:45 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1686871304; x=1689463304; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=Dc6/XqCeUuMLD90IMPpV+vPMqBRNYNN2pYcIpUptGVM=; b=OkRl7pZbjuDj11gUKKRzut/ej6pLmDzTndWR19Y8LlvqWvXNPNFUgPi2L9eJMwydvv crmo4HamIW9Snrxf7J5XTNyWLZ+B13ZrpBdkEeA39msQ6jrYQ1HkRjVEt6uv0tw3BvvO kRWrjrn1QTnq8YHc8USEljhbHotDd0p4G/Xa9KA1YkHLpJcQtN+vbUGSMkW+QyD5xDBO 44Kg54SjEx7Wj9jLJ7j/8MxkJg8tcIB+tihit2bNXzwuCcCVumFrb/3sCBQ6rei3GyrT LEv0xtYeb2/zdesgyQAKlmlA1oywkPNe+7AO7kPNu0pERDsvTRJ57qa7ZtbDgLp/us9B 6fjA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1686871304; x=1689463304; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Dc6/XqCeUuMLD90IMPpV+vPMqBRNYNN2pYcIpUptGVM=; b=SyWushym4k+FMs40lwMezH0GvLagv0kjt/Ip3C4XiAPaJZPKs8A9UQ7BlrgL7zfJVp w4omWzCwbo2IWpprV5OQtS9L1YDdVRvUeZ+B88Zd8yC/x2MambhL0HsnGaGwksjLiLtM rEo9h35RexBZXc7s/EeiK0wctaaR775Gy5Bq4tXheXErYyv5huWrEcLU+I+0DPbMujCu 0S7nyElYH/OH4OeG/WSqtV1UY0Ps5Qo3q6jVD81zZAaQSKkDmDiqg2nhHBN+3vCitLr8 0scNJ1FhcW+R9F1gFMUKzKDhjGOEYDcIK7/suj1g2ikI6yf8d/E3pOR6EUNQlET4eT4q 5ESA== X-Gm-Message-State: AC+VfDwkZcW63BdOM4NkFeBK/UfUOQXOU3u3YOZ7+TSP5YDXf1UuAq2G 3a1if6sWRzC8rw/GuvZh1FreHg== X-Google-Smtp-Source: ACHHUZ5wa3FIk3WqUXtN8QjH/SMq7+LoUWWAIre/XBEl18/iuPObvkhqcAhzM7o1iLwG6Ih1odoo3A== X-Received: by 2002:a19:6743:0:b0:4f6:2dbd:1e23 with SMTP id e3-20020a196743000000b004f62dbd1e23mr109620lfj.29.1686871304242; Thu, 15 Jun 2023 16:21:44 -0700 (PDT) Received: from [192.168.1.101] (abyj190.neoplus.adsl.tpnet.pl. [83.9.29.190]) by smtp.gmail.com with ESMTPSA id u25-20020a056512041900b004f24ee39661sm2744852lfk.137.2023.06.15.16.21.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 15 Jun 2023 16:21:43 -0700 (PDT) From: Konrad Dybcio Date: Fri, 16 Jun 2023 01:20:58 +0200 Subject: [PATCH v9 17/20] drm/msm/a6xx: Use "else if" in GPU speedbin rev matching MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20230223-topic-gmuwrapper-v9-17-890d8f470c8b@linaro.org> References: <20230223-topic-gmuwrapper-v9-0-890d8f470c8b@linaro.org> In-Reply-To: <20230223-topic-gmuwrapper-v9-0-890d8f470c8b@linaro.org> To: Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , David Airlie , Daniel Vetter , Rob Herring , Krzysztof Kozlowski , Bjorn Andersson , Konrad Dybcio , Akhil P Oommen , Conor Dooley Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Rob Clark , Marijn Suijten , Konrad Dybcio X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1686871277; l=1490; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=b8LS5q9YvSCzB73Uar1eH42Lv4QsJyCePzskZmQchAE=; b=CNAsUfQ7uGCvtpgiJ1tOWQ0c0LOfaa0E+6D+fWNOJT3Q1OF7ippRfWtWP8itV+fZ9fKYtIjWq B+aOjwCBfiXC3YpgUlHnvl4ioZdNTy2W+DJ7Ck1mxzov3pMMJivUk66 X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The GPU can only be one at a time. Turn a series of ifs into if + elseifs to save some CPU cycles. Reviewed-by: Dmitry Baryshkov Reviewed-by: Akhil P Oommen Signed-off-by: Konrad Dybcio --- drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/ad= reno/a6xx_gpu.c index 97e261d33312..d0ba0844079c 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c @@ -2276,16 +2276,16 @@ static u32 fuse_to_supp_hw(struct device *dev, stru= ct adreno_rev rev, u32 fuse) if (adreno_cmp_rev(ADRENO_REV(6, 1, 8, ANY_ID), rev)) val =3D a618_get_speed_bin(fuse); =20 - if (adreno_cmp_rev(ADRENO_REV(6, 1, 9, ANY_ID), rev)) + else if (adreno_cmp_rev(ADRENO_REV(6, 1, 9, ANY_ID), rev)) val =3D a619_get_speed_bin(fuse); =20 - if (adreno_cmp_rev(ADRENO_REV(6, 3, 5, ANY_ID), rev)) + else if (adreno_cmp_rev(ADRENO_REV(6, 3, 5, ANY_ID), rev)) val =3D adreno_7c3_get_speed_bin(fuse); =20 - if (adreno_cmp_rev(ADRENO_REV(6, 4, 0, ANY_ID), rev)) + else if (adreno_cmp_rev(ADRENO_REV(6, 4, 0, ANY_ID), rev)) val =3D a640_get_speed_bin(fuse); =20 - if (adreno_cmp_rev(ADRENO_REV(6, 5, 0, ANY_ID), rev)) + else if (adreno_cmp_rev(ADRENO_REV(6, 5, 0, ANY_ID), rev)) val =3D a650_get_speed_bin(fuse); =20 if (val =3D=3D UINT_MAX) { --=20 2.41.0 From nobody Tue Sep 9 17:14:06 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 748C2EB64D9 for ; Thu, 15 Jun 2023 23:23:11 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S240300AbjFOXXI (ORCPT ); Thu, 15 Jun 2023 19:23:08 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:46078 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S240067AbjFOXWL (ORCPT ); Thu, 15 Jun 2023 19:22:11 -0400 Received: from mail-lf1-x132.google.com (mail-lf1-x132.google.com [IPv6:2a00:1450:4864:20::132]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 820A930ED for ; Thu, 15 Jun 2023 16:21:47 -0700 (PDT) Received: by mail-lf1-x132.google.com with SMTP id 2adb3069b0e04-4f642a24555so11524320e87.3 for ; Thu, 15 Jun 2023 16:21:47 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1686871305; x=1689463305; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=fGKcpEvkgmqH8JrPvfpYm9khdGtKckmhAQlZimMOlwM=; b=An+srEX/8jDgXDMne86tgg/E+Eo0hDOXuPddzJ1e18eYDduiONyapUeLscJgIPzsVu 2j3/f1OlFDPFP3pyK1fKBprhQ6FPHncNxQT6wZLu9eRiPRIp6R5tPxnrJbJNZY3FZ0Ih 8+vl/gjj7zakgnPtJegSJEEwcH8jXTwlyBEtpLB0U7pdGrkV2qX5QNL/S0zKLPUrznsh 6UE+Xj0sSz+J2QH+glur4HDDxR13EAAWSB/J4+907g22kbTGLWmRc4i8UfcXJEhT2JPF hHwlcwa/089oR9Syah1/5vKdtIRw9uUN3Psko4UVMyVdhMzJX9dKe7A3OViHZEAZB9MR BsJQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1686871305; x=1689463305; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=fGKcpEvkgmqH8JrPvfpYm9khdGtKckmhAQlZimMOlwM=; b=GhTpnmqu7IGi5b6FEIsKygiDFrmwwHsNzICwMPbhmzUvruJ6028o19WWUSvpvpKxYb 9FYHWYUrHvOyVW/gKFGGRynoMOY/UyCcaNQi2cZirKLM7n78GSiyT93/OUEQH6AACRfa KYLH+/of/+KtPm4wvK+zU0tCSJp148g9YSNvvr/STEM+1fFKpZOXV0EEMMTWoiuioxB3 RwP7V5V5iOrm0gP8KBobcTyevfDQqNGG9KtDPa3oPnKYzlYmcW3cbAayTxSj23wE9Aow uVSsE6Yqd7FneN+9vh1yRB7cOiCBkyH/jENGE7RSYVuag6edqXWwKZ2kXCkpqprdl8hb eyCQ== X-Gm-Message-State: AC+VfDxUVArH0Km/tT6alpohnVxR2mFAYbI2qKdKEqWT7XGFaFZ4FSKr KLydMSyXnPOpLxG5oFk7VLJpcA== X-Google-Smtp-Source: ACHHUZ6FCyMtk9JyV2iTtox/5DCg87uU52C6Kat5Kgn9n9SHVeLA0tXNf8uY+t5aOWUaocLYaOaAQg== X-Received: by 2002:a05:6512:b0e:b0:4e0:a426:6ddc with SMTP id w14-20020a0565120b0e00b004e0a4266ddcmr137459lfu.0.1686871305658; Thu, 15 Jun 2023 16:21:45 -0700 (PDT) Received: from [192.168.1.101] (abyj190.neoplus.adsl.tpnet.pl. [83.9.29.190]) by smtp.gmail.com with ESMTPSA id u25-20020a056512041900b004f24ee39661sm2744852lfk.137.2023.06.15.16.21.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 15 Jun 2023 16:21:45 -0700 (PDT) From: Konrad Dybcio Date: Fri, 16 Jun 2023 01:20:59 +0200 Subject: [PATCH v9 18/20] drm/msm/a6xx: Use adreno_is_aXYZ macros in speedbin matching MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20230223-topic-gmuwrapper-v9-18-890d8f470c8b@linaro.org> References: <20230223-topic-gmuwrapper-v9-0-890d8f470c8b@linaro.org> In-Reply-To: <20230223-topic-gmuwrapper-v9-0-890d8f470c8b@linaro.org> To: Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , David Airlie , Daniel Vetter , Rob Herring , Krzysztof Kozlowski , Bjorn Andersson , Konrad Dybcio , Akhil P Oommen , Conor Dooley Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Rob Clark , Marijn Suijten , Konrad Dybcio X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1686871277; l=4358; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=CAqNqmWtpAnvqWY7hFQMZF9pqR7q8thwLVZflMn/w4Q=; b=/7J9MKJRkhAK/FnRoKsqPJODxigozx8KvlLPv76KA0Lz2GaJzru1C5oXlC8NCiVVpfpl1z5ES 0WNZTrqbAzWBbBNdi+pfhjhfGbwg4YOcQxbPAJj7t8LX8tzMaF8Bp+3 X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Before transitioning to using per-SoC and not per-Adreno speedbin fuse values (need another patchset to land elsewhere), a good improvement/stopgap solution is to use adreno_is_aXYZ macros in place of explicit revision matching. Do so to allow differentiating between A619 and A619_holi. Reviewed-by: Dmitry Baryshkov Reviewed-by: Akhil P Oommen Signed-off-by: Konrad Dybcio --- drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 18 +++++++++--------- drivers/gpu/drm/msm/adreno/adreno_gpu.h | 15 ++++++++++++--- 2 files changed, 21 insertions(+), 12 deletions(-) diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/ad= reno/a6xx_gpu.c index d0ba0844079c..d7139eae0f73 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c @@ -2269,23 +2269,23 @@ static u32 adreno_7c3_get_speed_bin(u32 fuse) return UINT_MAX; } =20 -static u32 fuse_to_supp_hw(struct device *dev, struct adreno_rev rev, u32 = fuse) +static u32 fuse_to_supp_hw(struct device *dev, struct adreno_gpu *adreno_g= pu, u32 fuse) { u32 val =3D UINT_MAX; =20 - if (adreno_cmp_rev(ADRENO_REV(6, 1, 8, ANY_ID), rev)) + if (adreno_is_a618(adreno_gpu)) val =3D a618_get_speed_bin(fuse); =20 - else if (adreno_cmp_rev(ADRENO_REV(6, 1, 9, ANY_ID), rev)) + else if (adreno_is_a619(adreno_gpu)) val =3D a619_get_speed_bin(fuse); =20 - else if (adreno_cmp_rev(ADRENO_REV(6, 3, 5, ANY_ID), rev)) + else if (adreno_is_7c3(adreno_gpu)) val =3D adreno_7c3_get_speed_bin(fuse); =20 - else if (adreno_cmp_rev(ADRENO_REV(6, 4, 0, ANY_ID), rev)) + else if (adreno_is_a640(adreno_gpu)) val =3D a640_get_speed_bin(fuse); =20 - else if (adreno_cmp_rev(ADRENO_REV(6, 5, 0, ANY_ID), rev)) + else if (adreno_is_a650(adreno_gpu)) val =3D a650_get_speed_bin(fuse); =20 if (val =3D=3D UINT_MAX) { @@ -2298,7 +2298,7 @@ static u32 fuse_to_supp_hw(struct device *dev, struct= adreno_rev rev, u32 fuse) return (1 << val); } =20 -static int a6xx_set_supported_hw(struct device *dev, struct adreno_rev rev) +static int a6xx_set_supported_hw(struct device *dev, struct adreno_gpu *ad= reno_gpu) { u32 supp_hw; u32 speedbin; @@ -2317,7 +2317,7 @@ static int a6xx_set_supported_hw(struct device *dev, = struct adreno_rev rev) return ret; } =20 - supp_hw =3D fuse_to_supp_hw(dev, rev, speedbin); + supp_hw =3D fuse_to_supp_hw(dev, adreno_gpu, speedbin); =20 ret =3D devm_pm_opp_set_supported_hw(dev, &supp_hw, 1); if (ret) @@ -2438,7 +2438,7 @@ struct msm_gpu *a6xx_gpu_init(struct drm_device *dev) =20 a6xx_llc_slices_init(pdev, a6xx_gpu); =20 - ret =3D a6xx_set_supported_hw(&pdev->dev, config->rev); + ret =3D a6xx_set_supported_hw(&pdev->dev, adreno_gpu); if (ret) { a6xx_destroy(&(a6xx_gpu->base.base)); return ERR_PTR(ret); diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.h b/drivers/gpu/drm/msm/= adreno/adreno_gpu.h index 3a8af5fdaea8..d8c9e8cc3753 100644 --- a/drivers/gpu/drm/msm/adreno/adreno_gpu.h +++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.h @@ -279,10 +279,9 @@ static inline int adreno_is_a630(const struct adreno_g= pu *gpu) return adreno_is_revn(gpu, 630); } =20 -static inline int adreno_is_a640_family(const struct adreno_gpu *gpu) +static inline int adreno_is_a640(const struct adreno_gpu *gpu) { - return adreno_is_revn(gpu, 640) || - adreno_is_revn(gpu, 680); + return adreno_is_revn(gpu, 640); } =20 static inline int adreno_is_a650(const struct adreno_gpu *gpu) @@ -301,6 +300,11 @@ static inline int adreno_is_a660(const struct adreno_g= pu *gpu) return adreno_is_revn(gpu, 660); } =20 +static inline int adreno_is_a680(const struct adreno_gpu *gpu) +{ + return adreno_is_revn(gpu, 680); +} + static inline int adreno_is_a690(const struct adreno_gpu *gpu) { return adreno_is_revn(gpu, 690); @@ -328,6 +332,11 @@ static inline int adreno_is_a650_family(const struct a= dreno_gpu *gpu) adreno_is_a660_family(gpu); } =20 +static inline int adreno_is_a640_family(const struct adreno_gpu *gpu) +{ + return adreno_is_a640(gpu) || adreno_is_a680(gpu); +} + u64 adreno_private_address_space_size(struct msm_gpu *gpu); int adreno_get_param(struct msm_gpu *gpu, struct msm_file_private *ctx, uint32_t param, uint64_t *value, uint32_t *len); --=20 2.41.0 From nobody Tue Sep 9 17:14:06 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id A31B8EB64DA for ; Thu, 15 Jun 2023 23:23:30 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S240415AbjFOXXZ (ORCPT ); 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[83.9.29.190]) by smtp.gmail.com with ESMTPSA id u25-20020a056512041900b004f24ee39661sm2744852lfk.137.2023.06.15.16.21.45 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 15 Jun 2023 16:21:46 -0700 (PDT) From: Konrad Dybcio Date: Fri, 16 Jun 2023 01:21:00 +0200 Subject: [PATCH v9 19/20] drm/msm/a6xx: Add A619_holi speedbin support MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20230223-topic-gmuwrapper-v9-19-890d8f470c8b@linaro.org> References: <20230223-topic-gmuwrapper-v9-0-890d8f470c8b@linaro.org> In-Reply-To: <20230223-topic-gmuwrapper-v9-0-890d8f470c8b@linaro.org> To: Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , David Airlie , Daniel Vetter , Rob Herring , Krzysztof Kozlowski , Bjorn Andersson , Konrad Dybcio , Akhil P Oommen , Conor Dooley Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Rob Clark , Marijn Suijten , Konrad Dybcio X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1686871277; l=2089; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=NX9ATH/Ev8PlZhCVhECzg9N+SgoP/jwCI/pQ0YNJQOY=; b=YrJ5CN8SWgMcflHDAkdH4AO6i2fC6lh3OlFqiDjWhiSOCXFO3qusmmxcSIxOKmmAc/apeUeP7 kpCV/GnTH9pAV0Son2yVEiFfcmldMHDzlXfXs2vLVHKp0dlfI7MgkU5 X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org A619_holi is implemented on at least two SoCs: SM4350 (holi) and SM6375 (blair). This is what seems to be a first occurrence of this happening, but it's easy to overcome by guarding the SoC-specific fuse values with of_machine_is_compatible(). Do just that to enable frequency limiting on these SoCs. Reviewed-by: Dmitry Baryshkov Reviewed-by: Akhil P Oommen Signed-off-by: Konrad Dybcio --- drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 31 +++++++++++++++++++++++++++++++ 1 file changed, 31 insertions(+) diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/ad= reno/a6xx_gpu.c index d7139eae0f73..ff9a8d342c77 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c @@ -2216,6 +2216,34 @@ static u32 a618_get_speed_bin(u32 fuse) return UINT_MAX; } =20 +static u32 a619_holi_get_speed_bin(u32 fuse) +{ + /* + * There are (at least) two SoCs implementing A619_holi: SM4350 (holi) + * and SM6375 (blair). Limit the fuse matching to the corresponding + * SoC to prevent bogus frequency setting (as improbable as it may be, + * given unexpected fuse values are.. unexpected! But still possible.) + */ + + if (fuse =3D=3D 0) + return 0; + + if (of_machine_is_compatible("qcom,sm4350")) { + if (fuse =3D=3D 138) + return 1; + else if (fuse =3D=3D 92) + return 2; + } else if (of_machine_is_compatible("qcom,sm6375")) { + if (fuse =3D=3D 190) + return 1; + else if (fuse =3D=3D 177) + return 2; + } else + pr_warn("Unknown SoC implementing A619_holi!\n"); + + return UINT_MAX; +} + static u32 a619_get_speed_bin(u32 fuse) { if (fuse =3D=3D 0) @@ -2276,6 +2304,9 @@ static u32 fuse_to_supp_hw(struct device *dev, struct= adreno_gpu *adreno_gpu, u3 if (adreno_is_a618(adreno_gpu)) val =3D a618_get_speed_bin(fuse); =20 + else if (adreno_is_a619_holi(adreno_gpu)) + val =3D a619_holi_get_speed_bin(fuse); + else if (adreno_is_a619(adreno_gpu)) val =3D a619_get_speed_bin(fuse); =20 --=20 2.41.0 From nobody Tue Sep 9 17:14:06 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id EFB52EB64D9 for ; Thu, 15 Jun 2023 23:23:33 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S240463AbjFOXXc (ORCPT ); Thu, 15 Jun 2023 19:23:32 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:45928 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S240444AbjFOXWX (ORCPT ); Thu, 15 Jun 2023 19:22:23 -0400 Received: from mail-lf1-x133.google.com (mail-lf1-x133.google.com [IPv6:2a00:1450:4864:20::133]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 23BC130FC for ; Thu, 15 Jun 2023 16:21:50 -0700 (PDT) Received: by mail-lf1-x133.google.com with SMTP id 2adb3069b0e04-4f762b3227dso256753e87.1 for ; Thu, 15 Jun 2023 16:21:50 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1686871308; x=1689463308; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=a+svBDf4CLgOAipv+j0r6qWFrZWv28OUfTzAcDFjW8k=; b=GCHOdnkoYXEvs/0jT/JPEJ88fwlvgz9KRcr4tdd1kVEoRdap5/XoymnOMrVgKYqg0u qtgkwIV+8jgAeRsJ96GdMoqzjhufEGhX+iz2zQYykJuxurBiJreSCezAnbSqIXFy2Zok QERYixcwm6AqzZPtv3VXY8bkQTgFQBEFQ+euYXRdArxUUoIoUCS1HhCvCF2is2Y3uqDd 3M3aSuie9CCXNOYaBSPUR/xJiWgDCpUwot/U7PAEs07FHHyBnuSaceKng+gOXCBPW7Aj v1RPpRa6oPIKlo6oXNkkTPbOaJf3dfADfbNbutC57q5M2cz/W0qHjaatksJ4EtRhQ9uY zAvQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1686871308; x=1689463308; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=a+svBDf4CLgOAipv+j0r6qWFrZWv28OUfTzAcDFjW8k=; b=POUk0Zo5WYoS0XJ4bGPXwgeS8V+hIXnRipgw2xaRKuB8zxo6UrrAiqjEcD7bpV0kmb YUOp3LAVEqu5B8VEIvEK5DiXJZl63kGeX/qV5TV1FF9NVsYeVr4PH+y1LBKoBtZjR4D1 tCKi6kKkPt4jgAWhtbYkkpFqBbFiWmgerFi0rJkcxgsJHlmX7UTI5G9dEluYgxmKI5WY I0Y74xdqhlgCPXVb2lO883BpNc1o/vL19nfu9pEphX9gANCW7cOVGILZaTGJZ9f26kj+ hfbUrn5Pvs85BQnDRkEIFd2lt74pMyHx4Jmze4hlA5pCHgGzxXJnYOOwu7xhDx73AZmR jehg== X-Gm-Message-State: AC+VfDzk6VD8TUJwDZayzI67uWWAYGWVcj6ib6rIdgxKThJoPHa3s19y ouaufC+4+BwX5IPWAUGxPlsNDw== X-Google-Smtp-Source: ACHHUZ5M8+Y1tEEhAxhunZ5k31fQ0kTL8g5RSZ1OpELl8hso07LURPszaXvFfhbNwT0tuON+1GdjNQ== X-Received: by 2002:a05:6512:398a:b0:4f4:e509:ef56 with SMTP id j10-20020a056512398a00b004f4e509ef56mr1852623lfu.25.1686871308495; Thu, 15 Jun 2023 16:21:48 -0700 (PDT) Received: from [192.168.1.101] (abyj190.neoplus.adsl.tpnet.pl. [83.9.29.190]) by smtp.gmail.com with ESMTPSA id u25-20020a056512041900b004f24ee39661sm2744852lfk.137.2023.06.15.16.21.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 15 Jun 2023 16:21:48 -0700 (PDT) From: Konrad Dybcio Date: Fri, 16 Jun 2023 01:21:01 +0200 Subject: [PATCH v9 20/20] drm/msm/a6xx: Add A610 speedbin support MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20230223-topic-gmuwrapper-v9-20-890d8f470c8b@linaro.org> References: <20230223-topic-gmuwrapper-v9-0-890d8f470c8b@linaro.org> In-Reply-To: <20230223-topic-gmuwrapper-v9-0-890d8f470c8b@linaro.org> To: Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , David Airlie , Daniel Vetter , Rob Herring , Krzysztof Kozlowski , Bjorn Andersson , Konrad Dybcio , Akhil P Oommen , Conor Dooley Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Rob Clark , Marijn Suijten , Konrad Dybcio X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1686871277; l=1908; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=QopxU5AaMC+j/o5cTOrG8wzEEwTggnAJi8IemaS+5vw=; b=NYNylG8pigD3OTBd3OI53qX8ugm96hvBv8g6mwWgFpPpKI2cLy28RrZAm4FAkNYNvy9fmXUEY hEPbQ2EAryQCVzo06LJNPngbVcuJId2kFj0Bwt1/Dxnfm7lLvCfe6/I X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org A610 is implemented on at least three SoCs: SM6115 (bengal), SM6125 (trinket) and SM6225 (khaje). Trinket does not support speed binning (only a single SKU exists) and we don't yet support khaje upstream. Hence, add a fuse mapping table for bengal to allow for per-chip frequency limiting. Reviewed-by: Dmitry Baryshkov Reviewed-by: Akhil P Oommen Signed-off-by: Konrad Dybcio --- drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 27 +++++++++++++++++++++++++++ 1 file changed, 27 insertions(+) diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/ad= reno/a6xx_gpu.c index ff9a8d342c77..b3ada1e7b598 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c @@ -2204,6 +2204,30 @@ static bool a6xx_progress(struct msm_gpu *gpu, struc= t msm_ringbuffer *ring) return progress; } =20 +static u32 a610_get_speed_bin(u32 fuse) +{ + /* + * There are (at least) three SoCs implementing A610: SM6125 (trinket), + * SM6115 (bengal) and SM6225 (khaje). Trinket does not have speedbinning, + * as only a single SKU exists and we don't support khaje upstream yet. + * Hence, this matching table is only valid for bengal and can be easily + * expanded if need be. + */ + + if (fuse =3D=3D 0) + return 0; + else if (fuse =3D=3D 206) + return 1; + else if (fuse =3D=3D 200) + return 2; + else if (fuse =3D=3D 157) + return 3; + else if (fuse =3D=3D 127) + return 4; + + return UINT_MAX; +} + static u32 a618_get_speed_bin(u32 fuse) { if (fuse =3D=3D 0) @@ -2301,6 +2325,9 @@ static u32 fuse_to_supp_hw(struct device *dev, struct= adreno_gpu *adreno_gpu, u3 { u32 val =3D UINT_MAX; =20 + if (adreno_is_a610(adreno_gpu)) + val =3D a610_get_speed_bin(fuse); + if (adreno_is_a618(adreno_gpu)) val =3D a618_get_speed_bin(fuse); =20 --=20 2.41.0