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[83.9.29.77]) by smtp.gmail.com with ESMTPSA id c16-20020ac25310000000b004f2532cfbc1sm4700lfh.81.2023.05.29.06.52.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 29 May 2023 06:52:49 -0700 (PDT) From: Konrad Dybcio Date: Mon, 29 May 2023 15:52:36 +0200 Subject: [PATCH v8 17/18] drm/msm/a6xx: Add A619_holi speedbin support MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20230223-topic-gmuwrapper-v8-17-69c68206609e@linaro.org> References: <20230223-topic-gmuwrapper-v8-0-69c68206609e@linaro.org> In-Reply-To: <20230223-topic-gmuwrapper-v8-0-69c68206609e@linaro.org> To: Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , David Airlie , Daniel Vetter , Rob Herring , Krzysztof Kozlowski , Bjorn Andersson , Konrad Dybcio , Akhil P Oommen , Conor Dooley Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Rob Clark , Marijn Suijten , Konrad Dybcio X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1685368343; l=2033; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=gUTIPidqDWS0P1lNtbrS0Px4anPItm4IBqiFMyfoOxc=; b=BvUhulc/6Bw/MuEau8P6DGoJnIw9T0wdrzyGspLuR6E71zrUFFTJ/lVWz/hYaFuMnnttmKNC4 uLsYGoq/f5HDcWEdrzmUfLwv0SGrtjvxois6uMGcwAuXSvrK71uOuSk X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org A619_holi is implemented on at least two SoCs: SM4350 (holi) and SM6375 (blair). This is what seems to be a first occurrence of this happening, but it's easy to overcome by guarding the SoC-specific fuse values with of_machine_is_compatible(). Do just that to enable frequency limiting on these SoCs. Reviewed-by: Dmitry Baryshkov Signed-off-by: Konrad Dybcio Reviewed-by: Akhil P Oommen --- drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 31 +++++++++++++++++++++++++++++++ 1 file changed, 31 insertions(+) diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/ad= reno/a6xx_gpu.c index ca4ffa44097e..d046af5f6de2 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c @@ -2110,6 +2110,34 @@ static u32 a618_get_speed_bin(u32 fuse) return UINT_MAX; } =20 +static u32 a619_holi_get_speed_bin(u32 fuse) +{ + /* + * There are (at least) two SoCs implementing A619_holi: SM4350 (holi) + * and SM6375 (blair). Limit the fuse matching to the corresponding + * SoC to prevent bogus frequency setting (as improbable as it may be, + * given unexpected fuse values are.. unexpected! But still possible.) + */ + + if (fuse =3D=3D 0) + return 0; + + if (of_machine_is_compatible("qcom,sm4350")) { + if (fuse =3D=3D 138) + return 1; + else if (fuse =3D=3D 92) + return 2; + } else if (of_machine_is_compatible("qcom,sm6375")) { + if (fuse =3D=3D 190) + return 1; + else if (fuse =3D=3D 177) + return 2; + } else + pr_warn("Unknown SoC implementing A619_holi!\n"); + + return UINT_MAX; +} + static u32 a619_get_speed_bin(u32 fuse) { if (fuse =3D=3D 0) @@ -2170,6 +2198,9 @@ static u32 fuse_to_supp_hw(struct device *dev, struct= adreno_gpu *adreno_gpu, u3 if (adreno_is_a618(adreno_gpu)) val =3D a618_get_speed_bin(fuse); =20 + else if (adreno_is_a619_holi(adreno_gpu)) + val =3D a619_holi_get_speed_bin(fuse); + else if (adreno_is_a619(adreno_gpu)) val =3D a619_get_speed_bin(fuse); =20 --=20 2.40.1