From nobody Mon Feb 9 12:42:58 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1FE0BC7EE29 for ; Mon, 29 May 2023 13:54:31 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229806AbjE2Ny3 (ORCPT ); Mon, 29 May 2023 09:54:29 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:36494 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229999AbjE2Nxu (ORCPT ); Mon, 29 May 2023 09:53:50 -0400 Received: from mail-lf1-x130.google.com (mail-lf1-x130.google.com [IPv6:2a00:1450:4864:20::130]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 1304FE64 for ; Mon, 29 May 2023 06:53:10 -0700 (PDT) Received: by mail-lf1-x130.google.com with SMTP id 2adb3069b0e04-4f122ff663eso3574657e87.2 for ; Mon, 29 May 2023 06:53:09 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1685368368; x=1687960368; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=6RwomgLtFuBAJdhvtFWYoHVBhBEZiHKMCWh0DbnY+6M=; b=MfFlU8AR2A2p82aHPGJe/D2zIhMQYbK6998C/3cZxElnlKxxnMNOHM4lgLN6q+v6cW Mp3+kVGlnxW36meBoqMv3vWBTcMRl2tZbQvDXKM3Cr2uKNllH/Y+gqE62dNqsJZV3BdW XoVno96dcsvWaRKtg25eF+pmdzkyDkuyeenWfEvHzqjU8pQNG3ethpktTPjJSzU8AwBr ZkHkjKw0ahixGZ7xW3lsG4Wnn2kDpelCNCUszGiPp8J/Mu2P5Lj5tQ8AAniv1P+F0kma igOVNEuv0GAwZDZAnxSKzzYkHYnS0mBBqNoivwCgDtInoCARtX9LTkd96fID7ZWtFDol ronw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1685368368; x=1687960368; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=6RwomgLtFuBAJdhvtFWYoHVBhBEZiHKMCWh0DbnY+6M=; b=FMWOkXPv5FX55BCQJMDbjhCYpi+v5Nvlc/psGQRpwQwZSSsKQhrISLjjMHy2S2qls4 uUuAJ7NcXwkSp6UK2XpssNBBiaz1UbnyFNfOY0sfM2JeE/JZLHfNv1zNIbnQ7pn3+2ST d1EJd/8TixSp28ppFjhmjWYiMNryT28zdgHaT0yzfeDimc0soD3RqPYcQmGdFjC0CPlP mzJL338U1wMnsTdvhWqi+3ozO/4wjbMOW2Qp49kqCxsFrwSgGoP+1IGNsPu0tHPr4ydX kpb4qFSEUEITArxSsEMkep1GuyOzqovBGE1/6s85Cq6Nt/YMGd2QZ0E0i1e8bmIeI0Om rzOA== X-Gm-Message-State: AC+VfDzgnv7GN443E5fNVDONF0ZIYAxzcWR0rFTcqSjokpHL8qScgqPE 779LlFvtGhDYd032WjzkcMfABQ== X-Google-Smtp-Source: ACHHUZ4i0v08P7CplUoBbNdpbrFlYTpaNXoDskAZBJbgbVg1AA1n+ZgBL0yiTHvk5AuCPizvlYqcSw== X-Received: by 2002:ac2:4a68:0:b0:4f4:dfd4:33e7 with SMTP id q8-20020ac24a68000000b004f4dfd433e7mr3813645lfp.33.1685368368701; Mon, 29 May 2023 06:52:48 -0700 (PDT) Received: from [192.168.1.101] (abyj77.neoplus.adsl.tpnet.pl. [83.9.29.77]) by smtp.gmail.com with ESMTPSA id c16-20020ac25310000000b004f2532cfbc1sm4700lfh.81.2023.05.29.06.52.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 29 May 2023 06:52:48 -0700 (PDT) From: Konrad Dybcio Date: Mon, 29 May 2023 15:52:35 +0200 Subject: [PATCH v8 16/18] drm/msm/a6xx: Use adreno_is_aXYZ macros in speedbin matching MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20230223-topic-gmuwrapper-v8-16-69c68206609e@linaro.org> References: <20230223-topic-gmuwrapper-v8-0-69c68206609e@linaro.org> In-Reply-To: <20230223-topic-gmuwrapper-v8-0-69c68206609e@linaro.org> To: Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , David Airlie , Daniel Vetter , Rob Herring , Krzysztof Kozlowski , Bjorn Andersson , Konrad Dybcio , Akhil P Oommen , Conor Dooley Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Rob Clark , Marijn Suijten , Konrad Dybcio X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1685368343; l=4275; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=iW1LHxRNIioRxxvJOIY0HtRkF0YVxdyIsQo1SElsxfY=; b=fqQIaJVSaqTt5KgCQk/0aQwss4Wknvm540jpXM9MmpdZP2YB7pDgaHUkES8HWlBi+LczQTrbK MbpsP5q3dxPBVbFX8yyU+5TmuxuDSquS8ytLrwvZK5nil84gjzXi/1W X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Before transitioning to using per-SoC and not per-Adreno speedbin fuse values (need another patchset to land elsewhere), a good improvement/stopgap solution is to use adreno_is_aXYZ macros in place of explicit revision matching. Do so to allow differentiating between A619 and A619_holi. Reviewed-by: Dmitry Baryshkov Signed-off-by: Konrad Dybcio Reviewed-by: Akhil P Oommen --- drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 18 +++++++++--------- drivers/gpu/drm/msm/adreno/adreno_gpu.h | 14 ++++++++++++-- 2 files changed, 21 insertions(+), 11 deletions(-) diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/ad= reno/a6xx_gpu.c index 5faa85543428..ca4ffa44097e 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c @@ -2163,23 +2163,23 @@ static u32 adreno_7c3_get_speed_bin(u32 fuse) return UINT_MAX; } =20 -static u32 fuse_to_supp_hw(struct device *dev, struct adreno_rev rev, u32 = fuse) +static u32 fuse_to_supp_hw(struct device *dev, struct adreno_gpu *adreno_g= pu, u32 fuse) { u32 val =3D UINT_MAX; =20 - if (adreno_cmp_rev(ADRENO_REV(6, 1, 8, ANY_ID), rev)) + if (adreno_is_a618(adreno_gpu)) val =3D a618_get_speed_bin(fuse); =20 - else if (adreno_cmp_rev(ADRENO_REV(6, 1, 9, ANY_ID), rev)) + else if (adreno_is_a619(adreno_gpu)) val =3D a619_get_speed_bin(fuse); =20 - else if (adreno_cmp_rev(ADRENO_REV(6, 3, 5, ANY_ID), rev)) + else if (adreno_is_7c3(adreno_gpu)) val =3D adreno_7c3_get_speed_bin(fuse); =20 - else if (adreno_cmp_rev(ADRENO_REV(6, 4, 0, ANY_ID), rev)) + else if (adreno_is_a640(adreno_gpu)) val =3D a640_get_speed_bin(fuse); =20 - else if (adreno_cmp_rev(ADRENO_REV(6, 5, 0, ANY_ID), rev)) + else if (adreno_is_a650(adreno_gpu)) val =3D a650_get_speed_bin(fuse); =20 if (val =3D=3D UINT_MAX) { @@ -2192,7 +2192,7 @@ static u32 fuse_to_supp_hw(struct device *dev, struct= adreno_rev rev, u32 fuse) return (1 << val); } =20 -static int a6xx_set_supported_hw(struct device *dev, struct adreno_rev rev) +static int a6xx_set_supported_hw(struct device *dev, struct adreno_gpu *ad= reno_gpu) { u32 supp_hw; u32 speedbin; @@ -2211,7 +2211,7 @@ static int a6xx_set_supported_hw(struct device *dev, = struct adreno_rev rev) return ret; } =20 - supp_hw =3D fuse_to_supp_hw(dev, rev, speedbin); + supp_hw =3D fuse_to_supp_hw(dev, adreno_gpu, speedbin); =20 ret =3D devm_pm_opp_set_supported_hw(dev, &supp_hw, 1); if (ret) @@ -2330,7 +2330,7 @@ struct msm_gpu *a6xx_gpu_init(struct drm_device *dev) =20 a6xx_llc_slices_init(pdev, a6xx_gpu); =20 - ret =3D a6xx_set_supported_hw(&pdev->dev, config->rev); + ret =3D a6xx_set_supported_hw(&pdev->dev, adreno_gpu); if (ret) { a6xx_destroy(&(a6xx_gpu->base.base)); return ERR_PTR(ret); diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.h b/drivers/gpu/drm/msm/= adreno/adreno_gpu.h index 7a5d595d4b99..21513cec038f 100644 --- a/drivers/gpu/drm/msm/adreno/adreno_gpu.h +++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.h @@ -268,9 +268,9 @@ static inline int adreno_is_a630(struct adreno_gpu *gpu) return gpu->revn =3D=3D 630; } =20 -static inline int adreno_is_a640_family(struct adreno_gpu *gpu) +static inline int adreno_is_a640(struct adreno_gpu *gpu) { - return (gpu->revn =3D=3D 640) || (gpu->revn =3D=3D 680); + return gpu->revn =3D=3D 640; } =20 static inline int adreno_is_a650(struct adreno_gpu *gpu) @@ -289,6 +289,11 @@ static inline int adreno_is_a660(struct adreno_gpu *gp= u) return gpu->revn =3D=3D 660; } =20 +static inline int adreno_is_a680(struct adreno_gpu *gpu) +{ + return gpu->revn =3D=3D 680; +} + /* check for a615, a616, a618, a619 or any derivatives */ static inline int adreno_is_a615_family(struct adreno_gpu *gpu) { @@ -306,6 +311,11 @@ static inline int adreno_is_a650_family(struct adreno_= gpu *gpu) return gpu->revn =3D=3D 650 || gpu->revn =3D=3D 620 || adreno_is_a660_fam= ily(gpu); } =20 +static inline int adreno_is_a640_family(struct adreno_gpu *gpu) +{ + return adreno_is_a640(gpu) || adreno_is_a680(gpu); +} + u64 adreno_private_address_space_size(struct msm_gpu *gpu); int adreno_get_param(struct msm_gpu *gpu, struct msm_file_private *ctx, uint32_t param, uint64_t *value, uint32_t *len); --=20 2.40.1