From nobody Sun Feb 8 23:23:18 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id D20E3C77B7D for ; Sat, 20 May 2023 12:20:16 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231683AbjETMUP (ORCPT ); Sat, 20 May 2023 08:20:15 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:50860 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231576AbjETMTx (ORCPT ); Sat, 20 May 2023 08:19:53 -0400 Received: from mail-lf1-x129.google.com (mail-lf1-x129.google.com [IPv6:2a00:1450:4864:20::129]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 46C2A132 for ; Sat, 20 May 2023 05:19:51 -0700 (PDT) Received: by mail-lf1-x129.google.com with SMTP id 2adb3069b0e04-4f3a611b3ddso2236788e87.0 for ; Sat, 20 May 2023 05:19:51 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1684585189; x=1687177189; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=rmQkm9eIpP4KwgdytmogY94a+6CcbBOn0isFTbbL77w=; b=GhljqGlQ9QrJYz01T97CgWhEuftE3BCFDJDfX8TOr0Uv/vrDwwoJqb/dKqtIiSQihy 0Up8USCanLryU+94kUSU7vvMIvjV2YL2czuJdiNg0eOiUvnBzPu4fHYDVzhcOp0PcrE0 5YrHorq91hnQE8hlZt1EBdxlxro9KhJOfk1rBmUrJrq6Jrrwyb4Q3eqEDMto1j/n58a/ s4My0zz7ngoMT6xnFRjocwmTGD0DT4G6gFcEAuAU7Bve06sjn8FzWQCrT5emDVb3bc8Y mZPzgEDHZl5SIDrmeb+NBK9gooBw/4udrf6Kg8z4t0sq7h2uOKKKSW26Ns8SE58mgxdD ATaQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1684585189; x=1687177189; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=rmQkm9eIpP4KwgdytmogY94a+6CcbBOn0isFTbbL77w=; b=hJutwGmIFgV1vuSg861Ye4N3fgD3LgLss20tUDWx6VgaCR19ap0i+dm9Ay8Nj6599A G7wpgrVTZDN4fcBlpyfrfBZ8Y7XEMjfeCExtynGAI1Tn/6z35IfZpeh7cCuf8rBY0+t8 D30V6RUPLHmsNjNtLlBRC8AyTCwrfTwtFK1wAcohcD2BRS8TD9iOScf9Xw+Q3snkDDty wGIhgEmx5zYmAqj7szwIxW4240tJ4/h+ylK/WapozcExnFU/ScN/vVnlliPQs08hiV+O p165N74CC/kdEDSwsUx+wFTdyINrdYD9mGxp9biz4WEHZKC6WfWJPrSiw+2+n0lXsN5z gtZw== X-Gm-Message-State: AC+VfDy+pLH1EkAtZ6fFVZm52OZm/G7yCatemXv8ZNd4HXe0rp9+l5pq MG3A27oTCKY5n31VrMhCgoc8qA== X-Google-Smtp-Source: ACHHUZ5SMYtQfZSfOxdP+wpOVRJcr3gIYTgyH8YLTpTt7snj1X5zK2JPWv1wybnTZC2EWbGlj5mtHA== X-Received: by 2002:a19:ad02:0:b0:4f3:89e6:23c0 with SMTP id t2-20020a19ad02000000b004f389e623c0mr1959554lfc.31.1684585189530; Sat, 20 May 2023 05:19:49 -0700 (PDT) Received: from [192.168.1.101] (abxi58.neoplus.adsl.tpnet.pl. [83.9.2.58]) by smtp.gmail.com with ESMTPSA id y6-20020ac24466000000b004f37bd02a89sm244766lfl.287.2023.05.20.05.19.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 20 May 2023 05:19:49 -0700 (PDT) From: Konrad Dybcio Date: Sat, 20 May 2023 14:19:41 +0200 Subject: [PATCH v7 01/18] dt-bindings: display/msm: gpu: Document GMU wrapper-equipped A6xx MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20230223-topic-gmuwrapper-v7-1-ecc7aab83556@linaro.org> References: <20230223-topic-gmuwrapper-v7-0-ecc7aab83556@linaro.org> In-Reply-To: <20230223-topic-gmuwrapper-v7-0-ecc7aab83556@linaro.org> To: Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , David Airlie , Daniel Vetter , Rob Herring , Krzysztof Kozlowski , Bjorn Andersson , Konrad Dybcio , Akhil P Oommen Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Rob Clark , Marijn Suijten , Konrad Dybcio , Krzysztof Kozlowski X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1684585186; l=3340; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=tsvULNaXlyrWUrFums1fREzn1GspuB/dkdkyVKPR2+Q=; b=hR7lS9j6vc87ibCvNyBxqs7N/dQx3yhb9sIDnPNtz7efm6lV4/n3C7lWkHZk9yVlTHVZZ3nbu a0jmxVcYWhaA1kOIGODDbGjjjmV+Qym+7PsP4b0BrjjEQcJkr6RbRlR X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The "GMU Wrapper" is Qualcomm's name for "let's treat the GPU blocks we'd normally assign to the GMU as if they were a part of the GMU, even though they are not". It's a (good) software representation of the GMU_CX and GMU_GX register spaces within the GPUSS that helps us programatically treat these de-facto GMU-less parts in a way that's very similar to their GMU-equipped cousins, massively saving up on code duplication. The "wrapper" register space was specifically designed to mimic the layout of a real GMU, though it rather obviously does not have the M3 core et al. GMU wrapper-equipped A6xx GPUs require clocks and clock-names to be specified under the GPU node, just like their older cousins. Account for that. Reviewed-by: Krzysztof Kozlowski Signed-off-by: Konrad Dybcio --- .../devicetree/bindings/display/msm/gpu.yaml | 61 ++++++++++++++++++= ---- 1 file changed, 52 insertions(+), 9 deletions(-) diff --git a/Documentation/devicetree/bindings/display/msm/gpu.yaml b/Docum= entation/devicetree/bindings/display/msm/gpu.yaml index 5dabe7b6794b..58ca8912a8c3 100644 --- a/Documentation/devicetree/bindings/display/msm/gpu.yaml +++ b/Documentation/devicetree/bindings/display/msm/gpu.yaml @@ -36,10 +36,7 @@ properties: =20 reg-names: minItems: 1 - items: - - const: kgsl_3d0_reg_memory - - const: cx_mem - - const: cx_dbgc + maxItems: 3 =20 interrupts: maxItems: 1 @@ -157,16 +154,62 @@ allOf: required: - clocks - clock-names + - if: properties: compatible: contains: - pattern: '^qcom,adreno-6[0-9][0-9]\.[0-9]$' - - then: # Since Adreno 6xx series clocks should be defined in GMU + enum: + - qcom,adreno-610.0 + - qcom,adreno-619.1 + then: properties: - clocks: false - clock-names: false + clocks: + minItems: 6 + maxItems: 6 + + clock-names: + items: + - const: core + description: GPU Core clock + - const: iface + description: GPU Interface clock + - const: mem_iface + description: GPU Memory Interface clock + - const: alt_mem_iface + description: GPU Alternative Memory Interface clock + - const: gmu + description: CX GMU clock + - const: xo + description: GPUCC clocksource clock + + reg-names: + minItems: 1 + items: + - const: kgsl_3d0_reg_memory + - const: cx_dbgc + + required: + - clocks + - clock-names + else: + if: + properties: + compatible: + contains: + pattern: '^qcom,adreno-6[0-9][0-9]\.[0-9]$' + + then: # Starting with A6xx, the clocks are usually defined in the GM= U node + properties: + clocks: false + clock-names: false + + reg-names: + minItems: 1 + items: + - const: kgsl_3d0_reg_memory + - const: cx_mem + - const: cx_dbgc =20 examples: - | --=20 2.40.1 From nobody Sun Feb 8 23:23:18 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5FE45C7EE2F for ; Sat, 20 May 2023 12:20:00 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231556AbjETMT7 (ORCPT ); Sat, 20 May 2023 08:19:59 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:50866 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231602AbjETMTz (ORCPT ); Sat, 20 May 2023 08:19:55 -0400 Received: from mail-lf1-x132.google.com (mail-lf1-x132.google.com [IPv6:2a00:1450:4864:20::132]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 59ABE1A6 for ; Sat, 20 May 2023 05:19:53 -0700 (PDT) Received: by mail-lf1-x132.google.com with SMTP id 2adb3069b0e04-4eed764a10cso4755410e87.0 for ; Sat, 20 May 2023 05:19:53 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1684585191; x=1687177191; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=aflMIgmCUBYIv+NH+OHNReBuMm35dTbYVoSEqXv7yrc=; b=fx/9Muw9bgoGfvtDGVdm7j3y7AzHlyAWMg4frsIa436LA0m4rMmV8FHEWrKQczJwZW sHCH4e3OSYtbutkTlAZRrFhjy1AO0MIco6/8N/GpEV3TMb0GzK8tsjof9uMuR320UnER X+y/I1bAiLdPwOmoMab1Ocm3hsRgDG9Kmf0eA5ma7OaczM628FV5EyyTXkthprhUJJW2 dcGV2ZEOZPqAjKG184rpZQRyJC7+n8tDeSS4bOd2/8GGVX3bZD4I/7rK+9hQM3I5ZVpK znBL3GHpT25V6R6vbyENwWyAvUzXik+onnRD4RVhhLT5sdtZGTnzoeIzu465wdTPio3H AVkw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1684585191; x=1687177191; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=aflMIgmCUBYIv+NH+OHNReBuMm35dTbYVoSEqXv7yrc=; b=LVlGbWHykESjT09kqZ33gcxTAv3ReQCpQz8YwbKboyB1RIRSTGw2h6HctWJ8yy1tB3 IPbP9JyUZsMXLbItALLZcqwfDVZ+wPYE2hGWQydC3gXXmjvW2EtQuw+K3EUsE2YIdTwr 4Jg2VusnBsgLuPjri5s9kSGc7ef9UJXvvQpiy4xrYYUovtaSQ5k1sa2f5tfsX80OlSUO fl9SPGo9kVcJBE6dUdRGHXFrqBw4/g2BXsuB3Y+/bcYVojt9xVE14YD6tb8fp6CJhhKk R/75k0BCq2DnlH7QOLPz4TePKvr+yZY2W4qw6uESfYU6bKXb4ki9/6BREDB4owoC3jAU rzOA== X-Gm-Message-State: AC+VfDx804H+4BQBIkl+aUKRiW2ES2+AQj8PuErhaczp0kRV3BJDvxYp Uuh+FZcjxmRTicexB1bgbgEsNg== X-Google-Smtp-Source: ACHHUZ774MwJc8Wk3NInYSY5MaLCHEkMf2w3NPGUWuPL6jUTcrThHOMj2EaaXiURuSOmawg1uKvjzA== X-Received: by 2002:a19:ad02:0:b0:4f2:509b:87ba with SMTP id t2-20020a19ad02000000b004f2509b87bamr1529394lfc.50.1684585191243; Sat, 20 May 2023 05:19:51 -0700 (PDT) Received: from [192.168.1.101] (abxi58.neoplus.adsl.tpnet.pl. [83.9.2.58]) by smtp.gmail.com with ESMTPSA id y6-20020ac24466000000b004f37bd02a89sm244766lfl.287.2023.05.20.05.19.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 20 May 2023 05:19:50 -0700 (PDT) From: Konrad Dybcio Date: Sat, 20 May 2023 14:19:42 +0200 Subject: [PATCH v7 02/18] dt-bindings: display/msm/gmu: Add GMU wrapper MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20230223-topic-gmuwrapper-v7-2-ecc7aab83556@linaro.org> References: <20230223-topic-gmuwrapper-v7-0-ecc7aab83556@linaro.org> In-Reply-To: <20230223-topic-gmuwrapper-v7-0-ecc7aab83556@linaro.org> To: Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , David Airlie , Daniel Vetter , Rob Herring , Krzysztof Kozlowski , Bjorn Andersson , Konrad Dybcio , Akhil P Oommen Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Rob Clark , Marijn Suijten , Konrad Dybcio , Krzysztof Kozlowski X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1684585186; l=3381; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=SZ3bdkEe3SX6unXxVV9E3rtrVD2hZogfDv0FUHcSBSw=; b=TG+x5ZWY4hRPEk+ic1Y0KwdRZafHrgQwU/jLIhBJl5zYcTsFO8FZcfdFN1I3fc9gIuLCd73Yx TZVGILR57QlB9ovcbMvYurvr6xYTnN/rtDUlCYYrRaWqHny9F7d0yuG X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The "GMU Wrapper" is Qualcomm's name for "let's treat the GPU blocks we'd normally assign to the GMU as if they were a part of the GMU, even though they are not". It's a (good) software representation of the GMU_CX and GMU_GX register spaces within the GPUSS that helps us programatically treat these de-facto GMU-less parts in a way that's very similar to their GMU-equipped cousins, massively saving up on code duplication. The "wrapper" register space was specifically designed to mimic the layout of a real GMU, though it rather obviously does not have the M3 core et al. To sum it all up, the GMU wrapper is essentially a register space within the GPU, which Linux sees as a dumbed-down regular GMU: there's no clocks, interrupts, multiple reg spaces, iommus and OPP. Document it. Reviewed-by: Krzysztof Kozlowski Signed-off-by: Konrad Dybcio --- .../devicetree/bindings/display/msm/gmu.yaml | 50 ++++++++++++++++--= ---- 1 file changed, 38 insertions(+), 12 deletions(-) diff --git a/Documentation/devicetree/bindings/display/msm/gmu.yaml b/Docum= entation/devicetree/bindings/display/msm/gmu.yaml index 029d72822d8b..e36c40b935de 100644 --- a/Documentation/devicetree/bindings/display/msm/gmu.yaml +++ b/Documentation/devicetree/bindings/display/msm/gmu.yaml @@ -19,16 +19,18 @@ description: | =20 properties: compatible: - items: - - pattern: '^qcom,adreno-gmu-6[0-9][0-9]\.[0-9]$' - - const: qcom,adreno-gmu + oneOf: + - items: + - pattern: '^qcom,adreno-gmu-6[0-9][0-9]\.[0-9]$' + - const: qcom,adreno-gmu + - const: qcom,adreno-gmu-wrapper =20 reg: - minItems: 3 + minItems: 1 maxItems: 4 =20 reg-names: - minItems: 3 + minItems: 1 maxItems: 4 =20 clocks: @@ -44,7 +46,6 @@ properties: - description: GMU HFI interrupt - description: GMU interrupt =20 - interrupt-names: items: - const: hfi @@ -72,14 +73,8 @@ required: - compatible - reg - reg-names - - clocks - - clock-names - - interrupts - - interrupt-names - power-domains - power-domain-names - - iommus - - operating-points-v2 =20 additionalProperties: false =20 @@ -217,6 +212,28 @@ allOf: - const: axi - const: memnoc =20 + - if: + properties: + compatible: + contains: + const: qcom,adreno-gmu-wrapper + then: + properties: + reg: + items: + - description: GMU wrapper register space + reg-names: + items: + - const: gmu + else: + required: + - clocks + - clock-names + - interrupts + - interrupt-names + - iommus + - operating-points-v2 + examples: - | #include @@ -249,3 +266,12 @@ examples: iommus =3D <&adreno_smmu 5>; operating-points-v2 =3D <&gmu_opp_table>; }; + + gmu_wrapper: gmu@596a000 { + compatible =3D "qcom,adreno-gmu-wrapper"; + reg =3D <0x0596a000 0x30000>; + reg-names =3D "gmu"; + power-domains =3D <&gpucc GPU_CX_GDSC>, + <&gpucc GPU_GX_GDSC>; + power-domain-names =3D "cx", "gx"; + }; --=20 2.40.1 From nobody Sun Feb 8 23:23:18 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 54661C7EE2A for ; Sat, 20 May 2023 12:20:24 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231719AbjETMUX (ORCPT ); Sat, 20 May 2023 08:20:23 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:50850 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231639AbjETMT5 (ORCPT ); Sat, 20 May 2023 08:19:57 -0400 Received: from mail-lf1-x134.google.com (mail-lf1-x134.google.com [IPv6:2a00:1450:4864:20::134]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 9BA0B1AC for ; Sat, 20 May 2023 05:19:54 -0700 (PDT) Received: by mail-lf1-x134.google.com with SMTP id 2adb3069b0e04-4f1411e8111so4646863e87.1 for ; Sat, 20 May 2023 05:19:54 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1684585192; x=1687177192; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=zp5vgGCljU9Pzelevk/Q8qB+omVB6SpjUQQoV9nlSfc=; b=LmHGqYnABUafNaPABeP2QjeluLRpjhLp4yPSE7jl5S8sQp5kHG+RNCouuMliy6IgHV jKY9FSOC13BkIrlFhDok7DGcFz4Hp+y/bl8IDyzSvInUhlvHooEXQjKr4D6p9NZFDYXG BbtWbdh3m3YUon7XvSMPZYmK0uxh6fxbeDmo9JQwOokLdn3bX/vmqMmz5TTjdtTa0Fvf ZUb7ykgoAm5GCQ0n0nmGpUuxHIoXC1rKkJ6jYTTKMWNvFGYNux40/6UtpRZltXvh/ZzZ PiNS1NnWaYuBnj3+OuGsQBRskvYG2+QOkaWCWwq3d8rb4IjDcQA5SJvVtxUWjbvZSCE2 ujfA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1684585192; x=1687177192; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=zp5vgGCljU9Pzelevk/Q8qB+omVB6SpjUQQoV9nlSfc=; b=X+QE8woU5LF2J7MZjzgiIKTg7rXgNLXZ/nZVA9ajtfHUYujydMGqPHXCFnLCYuqssO RV4haByVZB92RlXzJ0H+hzPDYpQ0ePDpcpYkts/T+06PMIs3VSQchdCrUe5qqbVSkcFA uHYVU2R4XcCxDUZijGlt0JDKE1qYezHeObHTJlOcSEN5IoeFhrnU2N9oIednTXOBhDcv UKsyhfnHIhNAS7gTeLFefxKQMRUOklk+3nCMiM4vF14WCmxcTvsauX+ak5ixVvqvUyQ/ JPSam6IPg8h6C23kYUpCDQ3TU9V3NajRq39R8YnygqgZd8ZnKJmHWY/n71/wK59VAx3z HS7g== X-Gm-Message-State: AC+VfDzzLwgsUCfaBn0b57oLzWzsUTe5tTXNO14cdVfvl+7dXKeRzkpE DwBXrL5myh0LwpLrRGGDvy7l0A== X-Google-Smtp-Source: ACHHUZ6ICfLT5YYcL2/wUfqqlVAi7l6WT/IslOFa4mfbkqkaH6uDqf1vcuXSp1Xl5GRUx8S5baudQw== X-Received: by 2002:a05:6512:92c:b0:4f1:4fa4:4f56 with SMTP id f12-20020a056512092c00b004f14fa44f56mr1400995lft.17.1684585192697; Sat, 20 May 2023 05:19:52 -0700 (PDT) Received: from [192.168.1.101] (abxi58.neoplus.adsl.tpnet.pl. [83.9.2.58]) by smtp.gmail.com with ESMTPSA id y6-20020ac24466000000b004f37bd02a89sm244766lfl.287.2023.05.20.05.19.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 20 May 2023 05:19:52 -0700 (PDT) From: Konrad Dybcio Date: Sat, 20 May 2023 14:19:43 +0200 Subject: [PATCH v7 03/18] drm/msm/a6xx: Remove static keyword from sptprac en/disable functions MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20230223-topic-gmuwrapper-v7-3-ecc7aab83556@linaro.org> References: <20230223-topic-gmuwrapper-v7-0-ecc7aab83556@linaro.org> In-Reply-To: <20230223-topic-gmuwrapper-v7-0-ecc7aab83556@linaro.org> To: Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , David Airlie , Daniel Vetter , Rob Herring , Krzysztof Kozlowski , Bjorn Andersson , Konrad Dybcio , Akhil P Oommen Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Rob Clark , Marijn Suijten , Konrad Dybcio X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1684585186; l=1711; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=UGqbGuIs6LlGAaix8p6ok6zP4Iy0VYtXRGz1T9C6CU8=; b=m8aH8XPh7v5Dj1EndNzZvNNQ6ljpLmn+70wT7ITChRrR4tAj3G2lR/1F9BTKGmJdgK9WdnE+m de8u2FyFLxLBlnBWxeGNWgIDt/Xy2w7uBE+EFfMxZislS47gLLwN2T9 X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org These two will be reused by at least A619_holi in the non-gmu paths. Turn them non-static them to make it possible. Reviewed-by: Dmitry Baryshkov Signed-off-by: Konrad Dybcio --- drivers/gpu/drm/msm/adreno/a6xx_gmu.c | 4 ++-- drivers/gpu/drm/msm/adreno/a6xx_gmu.h | 2 ++ 2 files changed, 4 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c b/drivers/gpu/drm/msm/ad= reno/a6xx_gmu.c index e16b4b3f8535..87babbb2a19f 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_gmu.c @@ -354,7 +354,7 @@ void a6xx_gmu_clear_oob(struct a6xx_gmu *gmu, enum a6xx= _gmu_oob_state state) } =20 /* Enable CPU control of SPTP power power collapse */ -static int a6xx_sptprac_enable(struct a6xx_gmu *gmu) +int a6xx_sptprac_enable(struct a6xx_gmu *gmu) { int ret; u32 val; @@ -376,7 +376,7 @@ static int a6xx_sptprac_enable(struct a6xx_gmu *gmu) } =20 /* Disable CPU control of SPTP power power collapse */ -static void a6xx_sptprac_disable(struct a6xx_gmu *gmu) +void a6xx_sptprac_disable(struct a6xx_gmu *gmu) { u32 val; int ret; diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gmu.h b/drivers/gpu/drm/msm/ad= reno/a6xx_gmu.h index 0bc3eb443fec..7ee5b606bc47 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gmu.h +++ b/drivers/gpu/drm/msm/adreno/a6xx_gmu.h @@ -193,5 +193,7 @@ int a6xx_hfi_set_freq(struct a6xx_gmu *gmu, int index); =20 bool a6xx_gmu_gx_is_on(struct a6xx_gmu *gmu); bool a6xx_gmu_sptprac_is_on(struct a6xx_gmu *gmu); +void a6xx_sptprac_disable(struct a6xx_gmu *gmu); +int a6xx_sptprac_enable(struct a6xx_gmu *gmu); =20 #endif --=20 2.40.1 From nobody Sun Feb 8 23:23:18 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 55BA4C77B7A for ; Sat, 20 May 2023 12:20:29 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231709AbjETMU0 (ORCPT ); Sat, 20 May 2023 08:20:26 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:51034 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231612AbjETMT7 (ORCPT ); Sat, 20 May 2023 08:19:59 -0400 Received: from mail-lf1-x129.google.com (mail-lf1-x129.google.com [IPv6:2a00:1450:4864:20::129]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 1B2371A1 for ; Sat, 20 May 2023 05:19:56 -0700 (PDT) Received: by mail-lf1-x129.google.com with SMTP id 2adb3069b0e04-4effb818c37so4753994e87.3 for ; Sat, 20 May 2023 05:19:55 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1684585194; x=1687177194; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=Ox41uPAx3lnO302Ry1Df1WPA2I0vwUL6Eka5WZ9+II8=; b=xKTRQBLB985A6UkLMgvo8jKOc9UdGHdcnKvX15iYNo7ttv3waH2OlSlMOZzkLZbu3Q TXLrx7r00a/yTBAhGIBMyOrhLPsxdPmX7KNQUxjICXVLZGrajlaNsOUKw6XJjiwyzIoK zCjjTuu4HwXx88SwxVa5Njz4hT0FtsGoLxVmmwOdXJrai/Ft7W4sIFhz8HDy5vvxCX+z Vu46x6aXDHFgVQqk2a+8ZY0sKS2PEAAg/wqHA2nrNNwtMBzmZIticfnrv7KT7PqxJdmf 8rwcMYa6EAfaBZ7tAjj66PhIJm0IpblvGQ8igdo01JPx1r+RbWVCJPJNKK2moniVbWAo vuNg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1684585194; x=1687177194; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Ox41uPAx3lnO302Ry1Df1WPA2I0vwUL6Eka5WZ9+II8=; b=GyqQjSxZj6Olh/Oi+014AVKs0Be0wQMon9C046fk1nUtPivd/HIb4PKkk8zvVRRPZC j0n/BKeOzjWAAdcGZRpF3hMdnLewJb8yONDDVGSmQD8+xdf9WHU3mrzthGfc3mr35I7X wLicr/1qKV5Fc48HAkRtZNAsOy2LG15ABdK8cYWjmCd1xmKnL7A+3zAwC+O2iIPOj4e1 w4g1qr1J7MDGbwyNU2PfKG4NYbqY+lSh7wjE1MRCweY4hAk79f66rft/roOqz4CfEk7y vjgn+bSIcpLkxSkXGuWZ/izyQDGCb0CNhMTYgBDE0VPEncXmRhJC7mvc+KoyFKVj4txb 5BQw== X-Gm-Message-State: AC+VfDx/PzNzNa1RT48MyFfZA6dtjlFzAvRNn+6XkiexjmhwoHJDXJvT T3XcZ4qfWjqoqyslOJGOQmAVlQ== X-Google-Smtp-Source: ACHHUZ60Twq/k2jMIe1Odkal4KVvmTEFSyMWP2IiaRaSK03G+HdMsH2qQXqPDaCcKVj2l6zK4dxj8A== X-Received: by 2002:ac2:41c3:0:b0:4ec:8787:d52b with SMTP id d3-20020ac241c3000000b004ec8787d52bmr1439371lfi.62.1684585194210; Sat, 20 May 2023 05:19:54 -0700 (PDT) Received: from [192.168.1.101] (abxi58.neoplus.adsl.tpnet.pl. [83.9.2.58]) by smtp.gmail.com with ESMTPSA id y6-20020ac24466000000b004f37bd02a89sm244766lfl.287.2023.05.20.05.19.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 20 May 2023 05:19:53 -0700 (PDT) From: Konrad Dybcio Date: Sat, 20 May 2023 14:19:44 +0200 Subject: [PATCH v7 04/18] drm/msm/a6xx: Move force keepalive vote removal to a6xx_gmu_force_off() MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20230223-topic-gmuwrapper-v7-4-ecc7aab83556@linaro.org> References: <20230223-topic-gmuwrapper-v7-0-ecc7aab83556@linaro.org> In-Reply-To: <20230223-topic-gmuwrapper-v7-0-ecc7aab83556@linaro.org> To: Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , David Airlie , Daniel Vetter , Rob Herring , Krzysztof Kozlowski , Bjorn Andersson , Konrad Dybcio , Akhil P Oommen Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Rob Clark , Marijn Suijten , Konrad Dybcio X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1684585186; l=2072; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=WdDcDOyizy5IWwyMqltY5oqm/fsHIExj5zaeUB68hS4=; b=t5sGv9uZd2Pf7RJr+oj6zg/+W95na+EuVH9WADTPsy77xN6o4luha3OPHTWgo5tqywg26TbeM MMfIbD+ZI1aDAWa0ivtcPlLyHGB1ZErDOBQjDXy+cfaCe2tfNOKekLK X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org As pointed out by Akhil during the review process of GMU wrapper introduction [1], it makes sense to move this write into the function that's responsible for forcibly shutting the GMU off. It is also very convenient to move this to GMU-specific code, so that it does not have to be guarded by an if-condition to avoid calling it on GMU wrapper targets. Move the write to the aforementioned a6xx_gmu_force_off() to achieve that. No effective functional change. [1] https://lore.kernel.org/linux-arm-msm/20230501194022.GA18382@akhilpo-li= nux.qualcomm.com/ Signed-off-by: Konrad Dybcio --- drivers/gpu/drm/msm/adreno/a6xx_gmu.c | 6 ++++++ drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 6 ------ 2 files changed, 6 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c b/drivers/gpu/drm/msm/ad= reno/a6xx_gmu.c index 87babbb2a19f..9421716a2fe5 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_gmu.c @@ -912,6 +912,12 @@ static void a6xx_gmu_force_off(struct a6xx_gmu *gmu) struct adreno_gpu *adreno_gpu =3D &a6xx_gpu->base; struct msm_gpu *gpu =3D &adreno_gpu->base; =20 + /* + * Turn off keep alive that might have been enabled by the hang + * interrupt + */ + gmu_write(&a6xx_gpu->gmu, REG_A6XX_GMU_GMU_PWR_COL_KEEPALIVE, 0); + /* Flush all the queues */ a6xx_hfi_stop(gmu); =20 diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/ad= reno/a6xx_gpu.c index 9fb214f150dd..e34aa15156a4 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c @@ -1274,12 +1274,6 @@ static void a6xx_recover(struct msm_gpu *gpu) /* Halt SQE first */ gpu_write(gpu, REG_A6XX_CP_SQE_CNTL, 3); =20 - /* - * Turn off keep alive that might have been enabled by the hang - * interrupt - */ - gmu_write(&a6xx_gpu->gmu, REG_A6XX_GMU_GMU_PWR_COL_KEEPALIVE, 0); - pm_runtime_dont_use_autosuspend(&gpu->pdev->dev); =20 /* active_submit won't change until we make a submission */ --=20 2.40.1 From nobody Sun Feb 8 23:23:18 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id C3EA1C7EE2D for ; Sat, 20 May 2023 12:20:33 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231708AbjETMUc (ORCPT ); Sat, 20 May 2023 08:20:32 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:51152 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231687AbjETMUD (ORCPT ); Sat, 20 May 2023 08:20:03 -0400 Received: from mail-lj1-x234.google.com (mail-lj1-x234.google.com [IPv6:2a00:1450:4864:20::234]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 71C641A8 for ; Sat, 20 May 2023 05:19:57 -0700 (PDT) Received: by mail-lj1-x234.google.com with SMTP id 38308e7fff4ca-2af28303127so15609841fa.3 for ; Sat, 20 May 2023 05:19:57 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1684585195; x=1687177195; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=jU/QRs28WbUWBLa9spUWYgfjKgk/ufPjSJvFjGsZJBw=; b=KlRFbqJhTJ0dI/m487PSqv56uAg/oO1UcYMcopPQYcMclLlmzoYNtPlo3El00kvqCQ WSsNvYluciV1mI15+f/6U2qcTuHfPm05EnlqUP74WAESlBoK4zLNMKYPqP+WeXJKFcTH XBm5tegYbP6fLJMN+2N+TcWB/wEziXUm4IwqHDh+UL+fAESZadvImscaER264WM6TlJ5 iXQVHV1wkv2uiqlFrSOUbf9EhHYcJK7p/KpvnLk2L9sdY8WnDRRVLZwHOyE0UjyBmJp7 xRZMJzH2sqKl6t2Q4NAtgd5ropq/+bwkATXiZtbKynq39ZM4MLY3h0Osmhr9AQSGeU8U ZzQg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1684585195; x=1687177195; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=jU/QRs28WbUWBLa9spUWYgfjKgk/ufPjSJvFjGsZJBw=; b=lz1VL5XHG7anKFgvm+rnyPnSUAiAmfghKXAMKJ5YEmbodlpM8X9JyIczVQroIyVUyi Zt2IYiJkj2a5r6wkmSCWSTEIO/hVMk9S4bWbx2ckymXE1f33nAzltwjqhr4Z/AD5IDsk vEXZAeI7gOZHprdUCT7x73YbwMC6XRRilbJnvFk8tOXbvsRLGWpkdqiy47f9HXDv9jvT VHYvSbRpmWc484LiAyCmOMg0NXe6QWNZO1OcXuDoHpJRyjliy0A48LJWtDpDDJNP7mJu d+Cosy29clHx+KvUPvdL15w2bMBYR1vi6v6F+ZRDRdRx2vUU4BSW4u+by7cmlVHDIkIy GVFQ== X-Gm-Message-State: AC+VfDzFF/0X0uQI+wymoYKZyAkwHDOob3B0aYkLOOAhSCBq7aObciZb e5T6FFhh/2n7UH7W05UnxLBkaw== X-Google-Smtp-Source: ACHHUZ5CqKJ9RqawYFd+5/tVkXj6CJnt7KYZuj0CwWYSrNQAtuRAr00xjcAXaI2pnkW5JN2mAoJWrA== X-Received: by 2002:a19:750f:0:b0:4f2:4bc2:fc35 with SMTP id y15-20020a19750f000000b004f24bc2fc35mr1576731lfe.53.1684585195748; Sat, 20 May 2023 05:19:55 -0700 (PDT) Received: from [192.168.1.101] (abxi58.neoplus.adsl.tpnet.pl. [83.9.2.58]) by smtp.gmail.com with ESMTPSA id y6-20020ac24466000000b004f37bd02a89sm244766lfl.287.2023.05.20.05.19.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 20 May 2023 05:19:55 -0700 (PDT) From: Konrad Dybcio Date: Sat, 20 May 2023 14:19:45 +0200 Subject: [PATCH v7 05/18] drm/msm/a6xx: Move a6xx_bus_clear_pending_transactions to a6xx_gpu MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20230223-topic-gmuwrapper-v7-5-ecc7aab83556@linaro.org> References: <20230223-topic-gmuwrapper-v7-0-ecc7aab83556@linaro.org> In-Reply-To: <20230223-topic-gmuwrapper-v7-0-ecc7aab83556@linaro.org> To: Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , David Airlie , Daniel Vetter , Rob Herring , Krzysztof Kozlowski , Bjorn Andersson , Konrad Dybcio , Akhil P Oommen Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Rob Clark , Marijn Suijten , Konrad Dybcio X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1684585186; l=4540; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=zYmgc7iLON/6dS4YTyhHFJni2Xfaf0lKUqQXZ4N48q0=; b=NKCdzlZPj4FHQGVrpPj3zPyQa27mr8hNctWUecXu2SUEycjrPy33YbWngiZF5x2cw3PcfXZcz S0oMMs9Ag4IAoMI/VyfnOlyoj6sG0rv98EdpIogHwq0jmO84M020325 X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org This function is responsible for telling the GPU to halt transactions on all of its relevant buses, drain them and leave them in a predictable state, so that the GPU can be e.g. reset cleanly. Move the function to a6xx_gpu.c, remove the static keyword and add a prototype in a6xx_gpu.h to accomodate for the move. Signed-off-by: Konrad Dybcio --- drivers/gpu/drm/msm/adreno/a6xx_gmu.c | 37 -------------------------------= ---- drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 36 +++++++++++++++++++++++++++++++= +++ drivers/gpu/drm/msm/adreno/a6xx_gpu.h | 2 ++ 3 files changed, 38 insertions(+), 37 deletions(-) diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c b/drivers/gpu/drm/msm/ad= reno/a6xx_gmu.c index 9421716a2fe5..b86be123ecd0 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_gmu.c @@ -868,43 +868,6 @@ static void a6xx_gmu_rpmh_off(struct a6xx_gmu *gmu) (val & 1), 100, 1000); } =20 -#define GBIF_CLIENT_HALT_MASK BIT(0) -#define GBIF_ARB_HALT_MASK BIT(1) - -static void a6xx_bus_clear_pending_transactions(struct adreno_gpu *adreno_= gpu, - bool gx_off) -{ - struct msm_gpu *gpu =3D &adreno_gpu->base; - - if (!a6xx_has_gbif(adreno_gpu)) { - gpu_write(gpu, REG_A6XX_VBIF_XIN_HALT_CTRL0, 0xf); - spin_until((gpu_read(gpu, REG_A6XX_VBIF_XIN_HALT_CTRL1) & - 0xf) =3D=3D 0xf); - gpu_write(gpu, REG_A6XX_VBIF_XIN_HALT_CTRL0, 0); - - return; - } - - if (gx_off) { - /* Halt the gx side of GBIF */ - gpu_write(gpu, REG_A6XX_RBBM_GBIF_HALT, 1); - spin_until(gpu_read(gpu, REG_A6XX_RBBM_GBIF_HALT_ACK) & 1); - } - - /* Halt new client requests on GBIF */ - gpu_write(gpu, REG_A6XX_GBIF_HALT, GBIF_CLIENT_HALT_MASK); - spin_until((gpu_read(gpu, REG_A6XX_GBIF_HALT_ACK) & - (GBIF_CLIENT_HALT_MASK)) =3D=3D GBIF_CLIENT_HALT_MASK); - - /* Halt all AXI requests on GBIF */ - gpu_write(gpu, REG_A6XX_GBIF_HALT, GBIF_ARB_HALT_MASK); - spin_until((gpu_read(gpu, REG_A6XX_GBIF_HALT_ACK) & - (GBIF_ARB_HALT_MASK)) =3D=3D GBIF_ARB_HALT_MASK); - - /* The GBIF halt needs to be explicitly cleared */ - gpu_write(gpu, REG_A6XX_GBIF_HALT, 0x0); -} - /* Force the GMU off in case it isn't responsive */ static void a6xx_gmu_force_off(struct a6xx_gmu *gmu) { diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/ad= reno/a6xx_gpu.c index e34aa15156a4..6bb4da70f6a6 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c @@ -1597,6 +1597,42 @@ static void a6xx_llc_slices_init(struct platform_dev= ice *pdev, a6xx_gpu->llc_mmio =3D ERR_PTR(-EINVAL); } =20 +#define GBIF_CLIENT_HALT_MASK BIT(0) +#define GBIF_ARB_HALT_MASK BIT(1) + +void a6xx_bus_clear_pending_transactions(struct adreno_gpu *adreno_gpu, bo= ol gx_off) +{ + struct msm_gpu *gpu =3D &adreno_gpu->base; + + if (!a6xx_has_gbif(adreno_gpu)) { + gpu_write(gpu, REG_A6XX_VBIF_XIN_HALT_CTRL0, 0xf); + spin_until((gpu_read(gpu, REG_A6XX_VBIF_XIN_HALT_CTRL1) & + 0xf) =3D=3D 0xf); + gpu_write(gpu, REG_A6XX_VBIF_XIN_HALT_CTRL0, 0); + + return; + } + + if (gx_off) { + /* Halt the gx side of GBIF */ + gpu_write(gpu, REG_A6XX_RBBM_GBIF_HALT, 1); + spin_until(gpu_read(gpu, REG_A6XX_RBBM_GBIF_HALT_ACK) & 1); + } + + /* Halt new client requests on GBIF */ + gpu_write(gpu, REG_A6XX_GBIF_HALT, GBIF_CLIENT_HALT_MASK); + spin_until((gpu_read(gpu, REG_A6XX_GBIF_HALT_ACK) & + (GBIF_CLIENT_HALT_MASK)) =3D=3D GBIF_CLIENT_HALT_MASK); + + /* Halt all AXI requests on GBIF */ + gpu_write(gpu, REG_A6XX_GBIF_HALT, GBIF_ARB_HALT_MASK); + spin_until((gpu_read(gpu, REG_A6XX_GBIF_HALT_ACK) & + (GBIF_ARB_HALT_MASK)) =3D=3D GBIF_ARB_HALT_MASK); + + /* The GBIF halt needs to be explicitly cleared */ + gpu_write(gpu, REG_A6XX_GBIF_HALT, 0x0); +} + static int a6xx_pm_resume(struct msm_gpu *gpu) { struct adreno_gpu *adreno_gpu =3D to_adreno_gpu(gpu); diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.h b/drivers/gpu/drm/msm/ad= reno/a6xx_gpu.h index eea2e60ce3b7..9580def06d45 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.h +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.h @@ -88,4 +88,6 @@ void a6xx_show(struct msm_gpu *gpu, struct msm_gpu_state = *state, struct msm_gpu_state *a6xx_gpu_state_get(struct msm_gpu *gpu); int a6xx_gpu_state_put(struct msm_gpu_state *state); =20 +void a6xx_bus_clear_pending_transactions(struct adreno_gpu *adreno_gpu, bo= ol gx_off); + #endif /* __A6XX_GPU_H__ */ --=20 2.40.1 From nobody Sun Feb 8 23:23:18 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 173D6C7EE29 for ; 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[83.9.2.58]) by smtp.gmail.com with ESMTPSA id y6-20020ac24466000000b004f37bd02a89sm244766lfl.287.2023.05.20.05.19.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 20 May 2023 05:19:57 -0700 (PDT) From: Konrad Dybcio Date: Sat, 20 May 2023 14:19:46 +0200 Subject: [PATCH v7 06/18] drm/msm/a6xx: Improve a6xx_bus_clear_pending_transactions() MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20230223-topic-gmuwrapper-v7-6-ecc7aab83556@linaro.org> References: <20230223-topic-gmuwrapper-v7-0-ecc7aab83556@linaro.org> In-Reply-To: <20230223-topic-gmuwrapper-v7-0-ecc7aab83556@linaro.org> To: Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , David Airlie , Daniel Vetter , Rob Herring , Krzysztof Kozlowski , Bjorn Andersson , Konrad Dybcio , Akhil P Oommen Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Rob Clark , Marijn Suijten , Konrad Dybcio X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1684585186; l=1359; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=WRWN4WVkGFPt0it/wZ2I1vdoI21A135Lfips/fNYpFI=; b=Gi0m2HFVbxwh+3WxAQQKWsZ2bEexESiQtZXHyoxAJ3J1fU/yWJAkWpWsg83RD5lkF4K7o63Ea Fvwnieq1qqRBXNOpOSPgP3knVhe2IViNm6pPCAsEsY/GxRxto59ttOr X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Unify the indentation and explain the cryptic 0xF value. Signed-off-by: Konrad Dybcio --- drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/ad= reno/a6xx_gpu.c index 6bb4da70f6a6..e3ac3f045665 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c @@ -1597,17 +1597,18 @@ static void a6xx_llc_slices_init(struct platform_de= vice *pdev, a6xx_gpu->llc_mmio =3D ERR_PTR(-EINVAL); } =20 -#define GBIF_CLIENT_HALT_MASK BIT(0) -#define GBIF_ARB_HALT_MASK BIT(1) +#define GBIF_CLIENT_HALT_MASK BIT(0) +#define GBIF_ARB_HALT_MASK BIT(1) +#define VBIF_XIN_HALT_CTRL0_MASK GENMASK(3, 0) =20 void a6xx_bus_clear_pending_transactions(struct adreno_gpu *adreno_gpu, bo= ol gx_off) { struct msm_gpu *gpu =3D &adreno_gpu->base; =20 if (!a6xx_has_gbif(adreno_gpu)) { - gpu_write(gpu, REG_A6XX_VBIF_XIN_HALT_CTRL0, 0xf); + gpu_write(gpu, REG_A6XX_VBIF_XIN_HALT_CTRL0, VBIF_XIN_HALT_CTRL0_MASK); spin_until((gpu_read(gpu, REG_A6XX_VBIF_XIN_HALT_CTRL1) & - 0xf) =3D=3D 0xf); + (VBIF_XIN_HALT_CTRL0_MASK)) =3D=3D VBIF_XIN_HALT_CTRL0_MASK); gpu_write(gpu, REG_A6XX_VBIF_XIN_HALT_CTRL0, 0); =20 return; --=20 2.40.1 From nobody Sun Feb 8 23:23:18 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0F7EDC7EE2A for ; Sat, 20 May 2023 12:20:54 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231866AbjETMUw (ORCPT ); Sat, 20 May 2023 08:20:52 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:51204 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231757AbjETMU0 (ORCPT ); Sat, 20 May 2023 08:20:26 -0400 Received: from mail-lj1-x22a.google.com (mail-lj1-x22a.google.com [IPv6:2a00:1450:4864:20::22a]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id C1C22E54 for ; Sat, 20 May 2023 05:20:00 -0700 (PDT) Received: by mail-lj1-x22a.google.com with SMTP id 38308e7fff4ca-2af2c35fb85so7756771fa.3 for ; Sat, 20 May 2023 05:20:00 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1684585199; x=1687177199; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=1wFIIbEoxPLhpitFzIB7VWk7qAiJQapqN1VZ4+ZRTRI=; b=C+KG0gmGqsOgsOugIiyb/PsDw8m8EZaSlRtwvAIvbgmowHTS8VyD8BXjouv+hdJzQN IIFCEA9f4dpyvlbIkiytdxzm6+I0KkDKrrSP+p2/WRbPEGLWRP29rgvAXAT/smAbL7DM g9KEPg7tsM6a6DfXGUmXxDpzhLulFTPSuwSRN+0q9y8qrxf2cE1OjcQoTZz68voPqK4L lM8IY4X6bQg6kMpoHa5rjfbddLhY53+4h52vCNzi2qXTxE7/mqhU3yK1lQTPe+8R1+jl lvqyYb2j6CnxFWF1DDv0LI7moKhrVe1t7qyKsnMjFTbayAshlozdV0AMyO2NpbNqyFHz Qgqg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1684585199; x=1687177199; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=1wFIIbEoxPLhpitFzIB7VWk7qAiJQapqN1VZ4+ZRTRI=; b=cNbmmfCa5D9YbR2LCkT686IFBX9u3Adihc8wUcyT6Y+3TkEla+xuLaY20Okbq8Ruli Gkh165XmfkrbZUJoRF/Y4xnDhIO49/JSx41f0HxTAhYwtq4j8iaZE0kNbmEol0smABOW TxRFnEu0iYnlpm6cQwtxCuPn4s4TgL5UPLbnv72LQ/Afz9VqU5hpUtr8E8m/z7Izwn1h 5O83vdi6iT3riftv/9iyvitI03WA/VTntljWrW1ZIo2W7sPi3rjv1CJOa4DKwAsmpxPi fOQhjPu4APpVJiKeBs8RFjzWv+TcmkHIn8M2hAET7D9O3oHEVqc0zXMByxtCZxnJaLZ/ 9V4w== X-Gm-Message-State: AC+VfDwWcgbq778DPWh2m9aFGjNAlqdYk3v7bQIn4lp+kv0fe74kT5sN YhXzol6KfZLKLUnEXFZDf2Lqbg== X-Google-Smtp-Source: ACHHUZ686/APJwZF5d+ymeBfPVUJgO+udiA3oGWy50c+kqETtFbX5nhUCowpYdgHwWUe8gZseyu5EQ== X-Received: by 2002:ac2:4a7a:0:b0:4ed:b048:b98a with SMTP id q26-20020ac24a7a000000b004edb048b98amr1801618lfp.6.1684585198901; Sat, 20 May 2023 05:19:58 -0700 (PDT) Received: from [192.168.1.101] (abxi58.neoplus.adsl.tpnet.pl. [83.9.2.58]) by smtp.gmail.com with ESMTPSA id y6-20020ac24466000000b004f37bd02a89sm244766lfl.287.2023.05.20.05.19.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 20 May 2023 05:19:58 -0700 (PDT) From: Konrad Dybcio Date: Sat, 20 May 2023 14:19:47 +0200 Subject: [PATCH v7 07/18] drm/msm/a6xx: Add a helper for software-resetting the GPU MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20230223-topic-gmuwrapper-v7-7-ecc7aab83556@linaro.org> References: <20230223-topic-gmuwrapper-v7-0-ecc7aab83556@linaro.org> In-Reply-To: <20230223-topic-gmuwrapper-v7-0-ecc7aab83556@linaro.org> To: Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , David Airlie , Daniel Vetter , Rob Herring , Krzysztof Kozlowski , Bjorn Andersson , Konrad Dybcio , Akhil P Oommen Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Rob Clark , Marijn Suijten , Konrad Dybcio X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1684585186; l=2525; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=mi/m4Oey75vF6uy9TLg2BuEnAAWYnXoWrcm53l1hJFY=; b=5ywVdFZzedX6RurJaylG6kigzNdrQo8yQnTLcVo+RubeyxkfhsUtzGzRh1qh5fRNMuUrbK8cM Hq+/6wtKodQDs8O0oo5Fp9/iXQAIDqpFVYbp+xOuXlHKapoHeKdeupz X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Introduce a6xx_gpu_sw_reset() in preparation for adding GMU wrapper GPUs and reuse it in a6xx_gmu_force_off(). This helper, contrary to the original usage in GMU code paths, adds a write memory barrier which together with the necessary delay should ensure that the reset is never deasserted too quickly due to e.g. OoO execution going crazy. Signed-off-by: Konrad Dybcio --- drivers/gpu/drm/msm/adreno/a6xx_gmu.c | 3 +-- drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 11 +++++++++++ drivers/gpu/drm/msm/adreno/a6xx_gpu.h | 1 + 3 files changed, 13 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c b/drivers/gpu/drm/msm/ad= reno/a6xx_gmu.c index b86be123ecd0..5ba8cba69383 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_gmu.c @@ -899,8 +899,7 @@ static void a6xx_gmu_force_off(struct a6xx_gmu *gmu) a6xx_bus_clear_pending_transactions(adreno_gpu, true); =20 /* Reset GPU core blocks */ - gpu_write(gpu, REG_A6XX_RBBM_SW_RESET_CMD, 1); - udelay(100); + a6xx_gpu_sw_reset(gpu, true); } =20 static void a6xx_gmu_set_initial_freq(struct msm_gpu *gpu, struct a6xx_gmu= *gmu) diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/ad= reno/a6xx_gpu.c index e3ac3f045665..083ccb5bcb4e 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c @@ -1634,6 +1634,17 @@ void a6xx_bus_clear_pending_transactions(struct adre= no_gpu *adreno_gpu, bool gx_ gpu_write(gpu, REG_A6XX_GBIF_HALT, 0x0); } =20 +void a6xx_gpu_sw_reset(struct msm_gpu *gpu, bool assert) +{ + gpu_write(gpu, REG_A6XX_RBBM_SW_RESET_CMD, assert); + /* Add a barrier to avoid bad surprises */ + mb(); + + /* The reset line needs to be asserted for at least 100 us */ + if (assert) + udelay(100); +} + static int a6xx_pm_resume(struct msm_gpu *gpu) { struct adreno_gpu *adreno_gpu =3D to_adreno_gpu(gpu); diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.h b/drivers/gpu/drm/msm/ad= reno/a6xx_gpu.h index 9580def06d45..aa70390ee1c6 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.h +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.h @@ -89,5 +89,6 @@ struct msm_gpu_state *a6xx_gpu_state_get(struct msm_gpu *= gpu); int a6xx_gpu_state_put(struct msm_gpu_state *state); =20 void a6xx_bus_clear_pending_transactions(struct adreno_gpu *adreno_gpu, bo= ol gx_off); +void a6xx_gpu_sw_reset(struct msm_gpu *gpu, bool assert); =20 #endif /* __A6XX_GPU_H__ */ --=20 2.40.1 From nobody Sun Feb 8 23:23:18 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 76333C7EE29 for ; Sat, 20 May 2023 12:20:59 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231735AbjETMU5 (ORCPT ); Sat, 20 May 2023 08:20:57 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:51674 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231784AbjETMUg (ORCPT ); Sat, 20 May 2023 08:20:36 -0400 Received: from mail-lf1-x133.google.com (mail-lf1-x133.google.com [IPv6:2a00:1450:4864:20::133]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 658C7E6D for ; Sat, 20 May 2023 05:20:02 -0700 (PDT) Received: by mail-lf1-x133.google.com with SMTP id 2adb3069b0e04-4f3b9c88af8so163126e87.2 for ; Sat, 20 May 2023 05:20:02 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1684585200; x=1687177200; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=jEG7D8dDSqo05e8UhKgqNHGqbXe0pvKNUFpleUKYXVg=; b=I+Q3ewZykqObWHuKmqMPuJPGa3NjNoeRSIFQSrxfdGMyJ8QZus7o1u2rIwOciol6ij 7lO60fSX2PeeqP+aSOVKvs0jToT8xNMFRS1Q233kBQGg+VCxzdBLRr6lCuDl8g4BNLZ2 oiMIH+/WEQYkpTA5dog0TVx2LnYQCHCLprTjwZjY9gbieHYUzkui909KCXd+FlfDGSX0 Av0XYR0qJZhBAIZjBXR9foRILwwsqAwWRHZ4BbevSgVyob/kTKLAwfwd/zfjoPWhYPf7 6sPgR8TtZ58hq2+mit63Q8Jzu54ObT3rbMCw6XPnA9NruJSRxIAhteVSG67+B+sQ4hTS aGUw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1684585200; x=1687177200; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=jEG7D8dDSqo05e8UhKgqNHGqbXe0pvKNUFpleUKYXVg=; b=WTeGoJYpCpigS0lm7BMQqj0UozV9pA/fwQpBOwG1++q23ucYQ8j8ym+XhfmnN8WAUQ G9VwCCwgVaOzv7qghaPbCJGmyD5a4BD9uVeM3S0GHZtGot1cYzBZ7sfRLxA+EWXt0Xto JscPnTWQWmzCzmRTEmqpFsv+Ge5tUOsCZ5B+dA99VdQblzMFLcg6167O1NHIBV3Yy7yj 9JR4C6FCzHtG51MM7nH+UzTE9c2DCdGrocwombQwEUF4X+oePyKR3sVBD0S5LpIb0V3b R6Q8O/QWxAR1wWzB8ZYB8zAV3qpCk5ITvxnJqceYGRRjJDaGTxL0/n7WYf12Bf3IoBZj rkOw== X-Gm-Message-State: AC+VfDyvXeuSf6frs1rNVka4UZhnUZCn2Eqg0oG7pqkKLJVN+cXf4jgk QIFYl0rOfWRSdM8FPFHjv0TJ9g== X-Google-Smtp-Source: ACHHUZ4Gs+fVbgITqcw+rliR2PEwd5WYSfQWfpcD1Pe4CNQyANny3sRLpUXp92PtuAZoJk3qkE7rvg== X-Received: by 2002:ac2:4430:0:b0:4f3:a99c:fbbe with SMTP id w16-20020ac24430000000b004f3a99cfbbemr1824929lfl.14.1684585200406; Sat, 20 May 2023 05:20:00 -0700 (PDT) Received: from [192.168.1.101] (abxi58.neoplus.adsl.tpnet.pl. [83.9.2.58]) by smtp.gmail.com with ESMTPSA id y6-20020ac24466000000b004f37bd02a89sm244766lfl.287.2023.05.20.05.19.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 20 May 2023 05:20:00 -0700 (PDT) From: Konrad Dybcio Date: Sat, 20 May 2023 14:19:48 +0200 Subject: [PATCH v7 08/18] drm/msm/a6xx: Remove both GBIF and RBBM GBIF halt on hw init MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20230223-topic-gmuwrapper-v7-8-ecc7aab83556@linaro.org> References: <20230223-topic-gmuwrapper-v7-0-ecc7aab83556@linaro.org> In-Reply-To: <20230223-topic-gmuwrapper-v7-0-ecc7aab83556@linaro.org> To: Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , David Airlie , Daniel Vetter , Rob Herring , Krzysztof Kozlowski , Bjorn Andersson , Konrad Dybcio , Akhil P Oommen Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Rob Clark , Marijn Suijten , Konrad Dybcio X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1684585186; l=1283; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=JTiDWY7uw1D1PMKchNdprqbjJGR71Zsm7TruEBGJMeY=; b=4fROckR5rLH3nc9STYL54zMi3UHMYli5trCboT4r1jFi+HW8CMYFLBcgvzFiaAFA1KSk3V9o3 dc8cPUDGdU4DS+0RsJGbbtpgR27R2+TdgG433dly6u3cehfgmM1p2Yh X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Currently we're only deasserting REG_A6XX_RBBM_GBIF_HALT, but we also need REG_A6XX_GBIF_HALT to be set to 0. This is typically done automatically on successful GX collapse, but in case that fails, we should take care of it. Also, add a memory barrier to ensure it's gone through before jumping to further initialization. Reviewed-by: Dmitry Baryshkov Signed-off-by: Konrad Dybcio --- drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/ad= reno/a6xx_gpu.c index 083ccb5bcb4e..dfde5fb65eed 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c @@ -1003,8 +1003,12 @@ static int hw_init(struct msm_gpu *gpu) a6xx_gmu_set_oob(&a6xx_gpu->gmu, GMU_OOB_GPU_SET); =20 /* Clear GBIF halt in case GX domain was not collapsed */ - if (a6xx_has_gbif(adreno_gpu)) + if (a6xx_has_gbif(adreno_gpu)) { + gpu_write(gpu, REG_A6XX_GBIF_HALT, 0); gpu_write(gpu, REG_A6XX_RBBM_GBIF_HALT, 0); + /* Let's make extra sure that the GPU can access the memory.. */ + mb(); + } =20 gpu_write(gpu, REG_A6XX_RBBM_SECVID_TSB_CNTL, 0); =20 --=20 2.40.1 From nobody Sun Feb 8 23:23:18 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 97B85C7EE2D for ; Sat, 20 May 2023 12:21:04 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231737AbjETMVD (ORCPT ); Sat, 20 May 2023 08:21:03 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:51728 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231472AbjETMUk (ORCPT ); Sat, 20 May 2023 08:20:40 -0400 Received: from mail-lf1-x12a.google.com (mail-lf1-x12a.google.com [IPv6:2a00:1450:4864:20::12a]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 711CCE6E for ; Sat, 20 May 2023 05:20:02 -0700 (PDT) Received: by mail-lf1-x12a.google.com with SMTP id 2adb3069b0e04-4f3a166f8e9so2250929e87.0 for ; Sat, 20 May 2023 05:20:02 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1684585202; x=1687177202; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=+xX5NNwgRWpbIyQzksfucv5stjdGXkcjknwzUIBRmfg=; b=uVELfZLJXKBUz880nMVVIVD/RdTGjdq7+wKB79u8V6aQ4fPp5OyE5gpA1wFc1Q8i/S gjzSCEtDJJmzIf2XDZKjK6OXdfDHFM5t4/tBw/5IpYkQkrzPsD4gCdGxJ4whdmOnsKZq 33cZpu2MPOZSGHb8PpLPt/8xqPgEnJZijOZarE1+SZ51zC8CJE6EwYjbIj6GoH5hXht4 IFuJR0mV9EdaZ4O4wOdwV+YqzZNpBV3NgmSewENipBifpocet5pU+NF29WHUlRk7b5mV RZ73X3Uw+rkvphMqKgv4rmYCEQSmenaDEh8pJj1TnTUfvfihqA2Fsf4bo+JrVRoYvneX eJ6Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1684585202; x=1687177202; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=+xX5NNwgRWpbIyQzksfucv5stjdGXkcjknwzUIBRmfg=; b=cpN9ymby/uLcz00eF0T92Ng2x0VJN87lIbVIHlUujHVWTkQ9No/9scWyPfW1sN9hZS US5ZbJ6criXtwB3smvc39OLeNkeKHjnZ3vg5sMmXeY/0lUpJw9mIu8qVVaXVQAKGVo5v YhI/1dz77MPf2/gtPwUd7dq5U/FIAAO3QXxnNDtoI2rl7N6Zc6iNG248f4YFxpsXyPEM Y2q4htX8+2hzd7dkAg6JGXg/NNoK/k/WUVaBTwcc6Iwj7nY7ai833by6hyi6GqBjhCcn t5+wwHwAzEGZhSbniTkDbeFDUaGw8u90EmVS2P/W3B9d3zm6BrshPyP558Q7hSSV1XHz K8Yw== X-Gm-Message-State: AC+VfDztvtPsEKf+dU9TeLMzzSIWaoqvTtnAKjqeAW+8eVccbDvxguZu edMran0Sp2v4FHP+yps9M3tbpg== X-Google-Smtp-Source: ACHHUZ4JncePd2ms0BiwKHDgbz8eNScrQIfaoUkZTLVZe9SaaJKX/QMFEl1kZMDlsB/+vzcoK8z71w== X-Received: by 2002:ac2:5285:0:b0:4ac:b7bf:697a with SMTP id q5-20020ac25285000000b004acb7bf697amr2025347lfm.4.1684585201898; Sat, 20 May 2023 05:20:01 -0700 (PDT) Received: from [192.168.1.101] (abxi58.neoplus.adsl.tpnet.pl. [83.9.2.58]) by smtp.gmail.com with ESMTPSA id y6-20020ac24466000000b004f37bd02a89sm244766lfl.287.2023.05.20.05.20.00 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 20 May 2023 05:20:01 -0700 (PDT) From: Konrad Dybcio Date: Sat, 20 May 2023 14:19:49 +0200 Subject: [PATCH v7 09/18] drm/msm/a6xx: Extend and explain UBWC config MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20230223-topic-gmuwrapper-v7-9-ecc7aab83556@linaro.org> References: <20230223-topic-gmuwrapper-v7-0-ecc7aab83556@linaro.org> In-Reply-To: <20230223-topic-gmuwrapper-v7-0-ecc7aab83556@linaro.org> To: Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , David Airlie , Daniel Vetter , Rob Herring , Krzysztof Kozlowski , Bjorn Andersson , Konrad Dybcio , Akhil P Oommen Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Rob Clark , Marijn Suijten , Konrad Dybcio X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1684585186; l=3025; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=nJDRWtUki4jmsfB34feuvhwzM2ZS76IBIVVsPiHM+h4=; b=SnBS4X5cB+bIh7g9lIOPdHwSLdkv4Wq3ymO0C5zjVoU8+stgPjvUI755uLlqF4LVCd+U84D2Z QZgKS4cu4WVCCScSOMwwYLSXY1cwmEvjWY+8MNLu7kfaOLj0U5o+aNJ X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Rename lower_bit to hbb_lo and explain what it signifies. Add explanations (wherever possible to other tunables). Port setting min_access_length, ubwc_mode and hbb_hi from downstream. Reviewed-by: Rob Clark Signed-off-by: Konrad Dybcio --- drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 39 +++++++++++++++++++++++++++----= ---- 1 file changed, 30 insertions(+), 9 deletions(-) diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/ad= reno/a6xx_gpu.c index dfde5fb65eed..58bf405b85d8 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c @@ -786,10 +786,25 @@ static void a6xx_set_cp_protect(struct msm_gpu *gpu) static void a6xx_set_ubwc_config(struct msm_gpu *gpu) { struct adreno_gpu *adreno_gpu =3D to_adreno_gpu(gpu); - u32 lower_bit =3D 2; - u32 amsbc =3D 0; + /* Unknown, introduced with A650 family, related to UBWC mode/ver 4 */ u32 rgb565_predicator =3D 0; + /* Unknown, introduced with A650 family */ u32 uavflagprd_inv =3D 0; + /* Whether the minimum access length is 64 bits */ + u32 min_acc_len =3D 0; + /* Entirely magic, per-GPU-gen value */ + u32 ubwc_mode =3D 0; + /* + * The Highest Bank Bit value represents the bit of the highest DDR bank. + * We then subtract 13 from it (13 is the minimum value allowed by hw) and + * write the lowest two bits of the remaining value as hbb_lo and the + * one above it as hbb_hi to the hardware. This should ideally use DRAM + * type detection. + */ + u32 hbb_hi =3D 0; + u32 hbb_lo =3D 2; + /* Unknown, introduced with A640/680 */ + u32 amsbc =3D 0; =20 /* a618 is using the hw default values */ if (adreno_is_a618(adreno_gpu)) @@ -800,25 +815,31 @@ static void a6xx_set_ubwc_config(struct msm_gpu *gpu) =20 if (adreno_is_a650(adreno_gpu) || adreno_is_a660(adreno_gpu)) { /* TODO: get ddr type from bootloader and use 2 for LPDDR4 */ - lower_bit =3D 3; + hbb_lo =3D 3; amsbc =3D 1; rgb565_predicator =3D 1; uavflagprd_inv =3D 2; } =20 if (adreno_is_7c3(adreno_gpu)) { - lower_bit =3D 1; + hbb_lo =3D 1; amsbc =3D 1; rgb565_predicator =3D 1; uavflagprd_inv =3D 2; } =20 gpu_write(gpu, REG_A6XX_RB_NC_MODE_CNTL, - rgb565_predicator << 11 | amsbc << 4 | lower_bit << 1); - gpu_write(gpu, REG_A6XX_TPL1_NC_MODE_CNTL, lower_bit << 1); - gpu_write(gpu, REG_A6XX_SP_NC_MODE_CNTL, - uavflagprd_inv << 4 | lower_bit << 1); - gpu_write(gpu, REG_A6XX_UCHE_MODE_CNTL, lower_bit << 21); + rgb565_predicator << 11 | hbb_hi << 10 | amsbc << 4 | + min_acc_len << 3 | hbb_lo << 1 | ubwc_mode); + + gpu_write(gpu, REG_A6XX_TPL1_NC_MODE_CNTL, hbb_hi << 4 | + min_acc_len << 3 | hbb_lo << 1 | ubwc_mode); + + gpu_write(gpu, REG_A6XX_SP_NC_MODE_CNTL, hbb_hi << 10 | + uavflagprd_inv << 4 | min_acc_len << 3 | + hbb_lo << 1 | ubwc_mode); + + gpu_write(gpu, REG_A6XX_UCHE_MODE_CNTL, min_acc_len << 23 | hbb_lo << 21); } =20 static int a6xx_cp_init(struct msm_gpu *gpu) --=20 2.40.1 From nobody Sun Feb 8 23:23:18 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id D6440C7EE29 for ; Sat, 20 May 2023 12:21:06 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231809AbjETMVF (ORCPT ); Sat, 20 May 2023 08:21:05 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:51186 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231748AbjETMUt (ORCPT ); Sat, 20 May 2023 08:20:49 -0400 Received: from mail-lj1-x22e.google.com (mail-lj1-x22e.google.com [IPv6:2a00:1450:4864:20::22e]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id B694B10C0 for ; Sat, 20 May 2023 05:20:05 -0700 (PDT) Received: by mail-lj1-x22e.google.com with SMTP id 38308e7fff4ca-2af2451b3f1so19711481fa.2 for ; Sat, 20 May 2023 05:20:05 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1684585204; x=1687177204; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=r42OHg5sw6USQpav+QAtLIHSfv+s6K21VPjaJ87fp6k=; b=LHBMGFFlg/r0+uhsaf99LJIF+ugKhbGkbRvvttQtUw2Reca8wx8bOa1TtshkZi1GFK F7rRDzsMRUmLRt8fyQbWSyufSAqpYnHM/rwCZ1v9Xj0nRDXUbWmckClwKZUQmQVeHPfd OjEWCiffMHG9LxoHBNceUmZBXzoAgxl9VDPjhXEvc1rTjdvlQbS1xq4AZJmgha67FFzP msfvRMkLPxVCek6xsXTty1a/t8BJZLVKuoxPuw2MGHwBbgvmmkyQhzRzsYYcNifDwMKM trZPc2y5Ym/yIRz82JzLAW17UHiDl2m6Fa8ulJ4FxjOEBFpZzixT0xKZSNQSYxxIL4Et zy7w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1684585204; x=1687177204; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=r42OHg5sw6USQpav+QAtLIHSfv+s6K21VPjaJ87fp6k=; b=MWc6RCVTGD85bmSYPH9PXcP4Ulsy8HHi2QmswJ3Ru91/WmF/b9WnjmOlt9B0bfmNFs L4o2xPu5IIqXyZNPYzGoxWH5tJ9ojkpLezuLRyh2gzwQeLKur/Bor6jy2nOrO90m36sO TXQ3lmLPwROT0hVz/htzWCUYomogXdGGwUMOXZOLHDUp4ljfSHscRW1gePIlOGtZZn43 dsA9zClxPlFGbPeBRjk/qBm1L+ekRMGsnuFVJxoDM5g/y3x5dmi4R77gE0FKUAu5n4SN sSknFoqa1KV/a3pJK3PZS8p3kMLWtgd0MUpumL0/BFeKd+9RTzps7bh7Xg1gVAejLRJ7 BwPw== X-Gm-Message-State: AC+VfDxUR7SD3Am61MvGmceX9O7HWzI3swQtJnI6JODACPWSpLd2d+CO WtogS8vgfrzcdmqvwQs/6GHBTg== X-Google-Smtp-Source: ACHHUZ6mT+1dOGQQrI5Uu0SOp6BDaLD8u5qIjDyu62DOPHjC0k4O0UVGWyVc+fFxPWLk40awEspXiA== X-Received: by 2002:ac2:555e:0:b0:4f3:880b:285a with SMTP id l30-20020ac2555e000000b004f3880b285amr1903948lfk.29.1684585203804; Sat, 20 May 2023 05:20:03 -0700 (PDT) Received: from [192.168.1.101] (abxi58.neoplus.adsl.tpnet.pl. [83.9.2.58]) by smtp.gmail.com with ESMTPSA id y6-20020ac24466000000b004f37bd02a89sm244766lfl.287.2023.05.20.05.20.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 20 May 2023 05:20:03 -0700 (PDT) From: Konrad Dybcio Date: Sat, 20 May 2023 14:19:50 +0200 Subject: [PATCH v7 10/18] drm/msm/a6xx: Introduce GMU wrapper support MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20230223-topic-gmuwrapper-v7-10-ecc7aab83556@linaro.org> References: <20230223-topic-gmuwrapper-v7-0-ecc7aab83556@linaro.org> In-Reply-To: <20230223-topic-gmuwrapper-v7-0-ecc7aab83556@linaro.org> To: Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , David Airlie , Daniel Vetter , Rob Herring , Krzysztof Kozlowski , Bjorn Andersson , Konrad Dybcio , Akhil P Oommen Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Rob Clark , Marijn Suijten , Konrad Dybcio X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1684585186; l=19516; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=88uNcwZzh+SW7+WRWKcfYA0V+uRhojonVpikMRa9F0Y=; b=f0mWmHaD1/Y8gTbXf1bX/aqN2vj7JjjgPhQRI5Z8JNfDEbafRqvA/fG8a44Ih7bjGWe6BDgr8 YvKYLfhpNZIBvHqrGIg7oVLO9Xjh30evYdzcfZTt8k5xhR5H8QWx5Pm X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Some (particularly SMD_RPM, a.k.a non-RPMh) SoCs implement A6XX GPUs but don't implement the associated GMUs. This is due to the fact that the GMU directly pokes at RPMh. Sadly, this means we have to take care of enabling & scaling power rails, clocks and bandwidth ourselves. Reuse existing Adreno-common code and modify the deeply-GMU-infused A6XX code to facilitate these GPUs. This involves if-ing out lots of GMU callbacks and introducing a new type of GMU - GMU wrapper (it's the actual name that Qualcomm uses in their downstream kernels). This is essentially a register region which is convenient to model as a device. We'll use it for managing the GDSCs. The register layout matches the actual GMU_CX/GX regions on the "real GMU" devices and lets us reuse quite a bit of gmu_read/write/rmw calls. Signed-off-by: Konrad Dybcio --- drivers/gpu/drm/msm/adreno/a6xx_gmu.c | 72 +++++++++- drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 215 ++++++++++++++++++++++++= ---- drivers/gpu/drm/msm/adreno/a6xx_gpu.h | 1 + drivers/gpu/drm/msm/adreno/a6xx_gpu_state.c | 14 +- drivers/gpu/drm/msm/adreno/adreno_gpu.c | 8 +- drivers/gpu/drm/msm/adreno/adreno_gpu.h | 6 + 6 files changed, 281 insertions(+), 35 deletions(-) diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c b/drivers/gpu/drm/msm/ad= reno/a6xx_gmu.c index 5ba8cba69383..385ca3a12462 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_gmu.c @@ -1437,6 +1437,7 @@ static int a6xx_gmu_get_irq(struct a6xx_gmu *gmu, str= uct platform_device *pdev, =20 void a6xx_gmu_remove(struct a6xx_gpu *a6xx_gpu) { + struct adreno_gpu *adreno_gpu =3D &a6xx_gpu->base; struct a6xx_gmu *gmu =3D &a6xx_gpu->gmu; struct platform_device *pdev =3D to_platform_device(gmu->dev); =20 @@ -1462,10 +1463,12 @@ void a6xx_gmu_remove(struct a6xx_gpu *a6xx_gpu) gmu->mmio =3D NULL; gmu->rscc =3D NULL; =20 - a6xx_gmu_memory_free(gmu); + if (!adreno_has_gmu_wrapper(adreno_gpu)) { + a6xx_gmu_memory_free(gmu); =20 - free_irq(gmu->gmu_irq, gmu); - free_irq(gmu->hfi_irq, gmu); + free_irq(gmu->gmu_irq, gmu); + free_irq(gmu->hfi_irq, gmu); + } =20 /* Drop reference taken in of_find_device_by_node */ put_device(gmu->dev); @@ -1484,6 +1487,69 @@ static int cxpd_notifier_cb(struct notifier_block *n= b, return 0; } =20 +int a6xx_gmu_wrapper_init(struct a6xx_gpu *a6xx_gpu, struct device_node *n= ode) +{ + struct platform_device *pdev =3D of_find_device_by_node(node); + struct a6xx_gmu *gmu =3D &a6xx_gpu->gmu; + int ret; + + if (!pdev) + return -ENODEV; + + gmu->dev =3D &pdev->dev; + + of_dma_configure(gmu->dev, node, true); + + pm_runtime_enable(gmu->dev); + + /* Mark legacy for manual SPTPRAC control */ + gmu->legacy =3D true; + + /* Map the GMU registers */ + gmu->mmio =3D a6xx_gmu_get_mmio(pdev, "gmu"); + if (IS_ERR(gmu->mmio)) { + ret =3D PTR_ERR(gmu->mmio); + goto err_mmio; + } + + gmu->cxpd =3D dev_pm_domain_attach_by_name(gmu->dev, "cx"); + if (IS_ERR(gmu->cxpd)) { + ret =3D PTR_ERR(gmu->cxpd); + goto err_mmio; + } + + if (!device_link_add(gmu->dev, gmu->cxpd, DL_FLAG_PM_RUNTIME)) { + ret =3D -ENODEV; + goto detach_cxpd; + } + + init_completion(&gmu->pd_gate); + complete_all(&gmu->pd_gate); + gmu->pd_nb.notifier_call =3D cxpd_notifier_cb; + + /* Get a link to the GX power domain to reset the GPU */ + gmu->gxpd =3D dev_pm_domain_attach_by_name(gmu->dev, "gx"); + if (IS_ERR(gmu->gxpd)) { + ret =3D PTR_ERR(gmu->gxpd); + goto err_mmio; + } + + gmu->initialized =3D true; + + return 0; + +detach_cxpd: + dev_pm_domain_detach(gmu->cxpd, false); + +err_mmio: + iounmap(gmu->mmio); + + /* Drop reference taken in of_find_device_by_node */ + put_device(gmu->dev); + + return ret; +} + int a6xx_gmu_init(struct a6xx_gpu *a6xx_gpu, struct device_node *node) { struct adreno_gpu *adreno_gpu =3D &a6xx_gpu->base; diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/ad= reno/a6xx_gpu.c index 58bf405b85d8..2ba9d790a52c 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c @@ -21,7 +21,7 @@ static inline bool _a6xx_check_idle(struct msm_gpu *gpu) struct a6xx_gpu *a6xx_gpu =3D to_a6xx_gpu(adreno_gpu); =20 /* Check that the GMU is idle */ - if (!a6xx_gmu_isidle(&a6xx_gpu->gmu)) + if (!adreno_has_gmu_wrapper(adreno_gpu) && !a6xx_gmu_isidle(&a6xx_gpu->gm= u)) return false; =20 /* Check tha the CX master is idle */ @@ -1018,10 +1018,13 @@ static int hw_init(struct msm_gpu *gpu) { struct adreno_gpu *adreno_gpu =3D to_adreno_gpu(gpu); struct a6xx_gpu *a6xx_gpu =3D to_a6xx_gpu(adreno_gpu); + struct a6xx_gmu *gmu =3D &a6xx_gpu->gmu; int ret; =20 - /* Make sure the GMU keeps the GPU on while we set it up */ - a6xx_gmu_set_oob(&a6xx_gpu->gmu, GMU_OOB_GPU_SET); + if (!adreno_has_gmu_wrapper(adreno_gpu)) { + /* Make sure the GMU keeps the GPU on while we set it up */ + a6xx_gmu_set_oob(&a6xx_gpu->gmu, GMU_OOB_GPU_SET); + } =20 /* Clear GBIF halt in case GX domain was not collapsed */ if (a6xx_has_gbif(adreno_gpu)) { @@ -1148,6 +1151,17 @@ static int hw_init(struct msm_gpu *gpu) 0x3f0243f0); } =20 + if (adreno_has_gmu_wrapper(adreno_gpu)) { + /* Do it here, as GMU wrapper only inits the GMU for memory reservation = etc. */ + + /* Set up the CX GMU counter 0 to count busy ticks */ + gmu_write(gmu, REG_A6XX_GPU_GMU_AO_GPU_CX_BUSY_MASK, 0xff000000); + + /* Enable power counter 0 */ + gmu_rmw(gmu, REG_A6XX_GMU_CX_GMU_POWER_COUNTER_SELECT_0, 0xff, BIT(5)); + gmu_write(gmu, REG_A6XX_GMU_CX_GMU_POWER_COUNTER_ENABLE, 1); + } + /* Protect registers from the CP */ a6xx_set_cp_protect(gpu); =20 @@ -1237,6 +1251,8 @@ static int hw_init(struct msm_gpu *gpu) } =20 out: + if (adreno_has_gmu_wrapper(adreno_gpu)) + return ret; /* * Tell the GMU that we are done touching the GPU and it can start power * management @@ -1271,9 +1287,6 @@ static void a6xx_dump(struct msm_gpu *gpu) adreno_dump(gpu); } =20 -#define VBIF_RESET_ACK_TIMEOUT 100 -#define VBIF_RESET_ACK_MASK 0x00f0 - static void a6xx_recover(struct msm_gpu *gpu) { struct adreno_gpu *adreno_gpu =3D to_adreno_gpu(gpu); @@ -1311,6 +1324,15 @@ static void a6xx_recover(struct msm_gpu *gpu) */ gpu->active_submits =3D 0; =20 + if (adreno_has_gmu_wrapper(adreno_gpu)) { + /* Drain the outstanding traffic on memory buses */ + a6xx_bus_clear_pending_transactions(adreno_gpu, true); + + /* Reset the GPU to a clean state */ + a6xx_gpu_sw_reset(gpu, true); + a6xx_gpu_sw_reset(gpu, false); + } + reinit_completion(&gmu->pd_gate); dev_pm_genpd_add_notifier(gmu->cxpd, &gmu->pd_nb); dev_pm_genpd_synced_poweroff(gmu->cxpd); @@ -1461,7 +1483,8 @@ static void a6xx_fault_detect_irq(struct msm_gpu *gpu) * Force the GPU to stay on until after we finish * collecting information */ - gmu_write(&a6xx_gpu->gmu, REG_A6XX_GMU_GMU_PWR_COL_KEEPALIVE, 1); + if (!adreno_has_gmu_wrapper(adreno_gpu)) + gmu_write(&a6xx_gpu->gmu, REG_A6XX_GMU_GMU_PWR_COL_KEEPALIVE, 1); =20 DRM_DEV_ERROR(&gpu->pdev->dev, "gpu fault ring %d fence %x status %8.8X rb %4.4x/%4.4x ib1 %16.16llX/%4= .4x ib2 %16.16llX/%4.4x\n", @@ -1592,6 +1615,10 @@ static void a6xx_llc_activate(struct a6xx_gpu *a6xx_= gpu) =20 static void a6xx_llc_slices_destroy(struct a6xx_gpu *a6xx_gpu) { + /* No LLCC on non-RPMh (and by extension, non-GMU) SoCs */ + if (adreno_has_gmu_wrapper(&a6xx_gpu->base)) + return; + llcc_slice_putd(a6xx_gpu->llc_slice); llcc_slice_putd(a6xx_gpu->htw_llc_slice); } @@ -1601,6 +1628,10 @@ static void a6xx_llc_slices_init(struct platform_dev= ice *pdev, { struct device_node *phandle; =20 + /* No LLCC on non-RPMh (and by extension, non-GMU) SoCs */ + if (adreno_has_gmu_wrapper(&a6xx_gpu->base)) + return; + /* * There is a different programming path for targets with an mmu500 * attached, so detect if that is the case @@ -1670,7 +1701,7 @@ void a6xx_gpu_sw_reset(struct msm_gpu *gpu, bool asse= rt) udelay(100); } =20 -static int a6xx_pm_resume(struct msm_gpu *gpu) +static int a6xx_gmu_pm_resume(struct msm_gpu *gpu) { struct adreno_gpu *adreno_gpu =3D to_adreno_gpu(gpu); struct a6xx_gpu *a6xx_gpu =3D to_a6xx_gpu(adreno_gpu); @@ -1690,10 +1721,61 @@ static int a6xx_pm_resume(struct msm_gpu *gpu) =20 a6xx_llc_activate(a6xx_gpu); =20 - return 0; + return ret; } =20 -static int a6xx_pm_suspend(struct msm_gpu *gpu) +static int a6xx_pm_resume(struct msm_gpu *gpu) +{ + struct adreno_gpu *adreno_gpu =3D to_adreno_gpu(gpu); + struct a6xx_gpu *a6xx_gpu =3D to_a6xx_gpu(adreno_gpu); + struct a6xx_gmu *gmu =3D &a6xx_gpu->gmu; + unsigned long freq =3D 0; + struct dev_pm_opp *opp; + int ret; + + gpu->needs_hw_init =3D true; + + trace_msm_gpu_resume(0); + + mutex_lock(&a6xx_gpu->gmu.lock); + + pm_runtime_resume_and_get(gmu->dev); + pm_runtime_resume_and_get(gmu->gxpd); + + /* Set the core clock, having VDD scaling in mind */ + ret =3D dev_pm_opp_set_rate(&gpu->pdev->dev, gpu->fast_rate); + if (ret) + goto err_core_clk; + + ret =3D clk_bulk_prepare_enable(gpu->nr_clocks, gpu->grp_clks); + if (ret) + goto err_bulk_clk; + + ret =3D clk_prepare_enable(gpu->ebi1_clk); + if (ret) + goto err_mem_clk; + + /* If anything goes south, tear the GPU down piece by piece.. */ + if (ret) { +err_mem_clk: + clk_bulk_disable_unprepare(gpu->nr_clocks, gpu->grp_clks); +err_bulk_clk: + opp =3D dev_pm_opp_find_freq_ceil(&gpu->pdev->dev, &freq); + dev_pm_opp_put(opp); + dev_pm_opp_set_rate(&gpu->pdev->dev, 0); +err_core_clk: + pm_runtime_put(gmu->gxpd); + pm_runtime_put(gmu->dev); + } + mutex_unlock(&a6xx_gpu->gmu.lock); + + if (!ret) + msm_devfreq_resume(gpu); + + return ret; +} + +static int a6xx_gmu_pm_suspend(struct msm_gpu *gpu) { struct adreno_gpu *adreno_gpu =3D to_adreno_gpu(gpu); struct a6xx_gpu *a6xx_gpu =3D to_a6xx_gpu(adreno_gpu); @@ -1720,7 +1802,41 @@ static int a6xx_pm_suspend(struct msm_gpu *gpu) return 0; } =20 -static int a6xx_get_timestamp(struct msm_gpu *gpu, uint64_t *value) +static int a6xx_pm_suspend(struct msm_gpu *gpu) +{ + struct adreno_gpu *adreno_gpu =3D to_adreno_gpu(gpu); + struct a6xx_gpu *a6xx_gpu =3D to_a6xx_gpu(adreno_gpu); + struct a6xx_gmu *gmu =3D &a6xx_gpu->gmu; + int i; + + trace_msm_gpu_suspend(0); + + msm_devfreq_suspend(gpu); + + mutex_lock(&a6xx_gpu->gmu.lock); + + /* Drain the outstanding traffic on memory buses */ + a6xx_bus_clear_pending_transactions(adreno_gpu, true); + + clk_disable_unprepare(gpu->ebi1_clk); + + clk_bulk_disable_unprepare(gpu->nr_clocks, gpu->grp_clks); + + pm_runtime_put_sync(gmu->gxpd); + pm_runtime_put_sync(gmu->dev); + + mutex_unlock(&a6xx_gpu->gmu.lock); + + if (a6xx_gpu->shadow_bo) + for (i =3D 0; i < gpu->nr_rings; i++) + a6xx_gpu->shadow[i] =3D 0; + + gpu->suspend_count++; + + return 0; +} + +static int a6xx_gmu_get_timestamp(struct msm_gpu *gpu, uint64_t *value) { struct adreno_gpu *adreno_gpu =3D to_adreno_gpu(gpu); struct a6xx_gpu *a6xx_gpu =3D to_a6xx_gpu(adreno_gpu); @@ -1739,6 +1855,12 @@ static int a6xx_get_timestamp(struct msm_gpu *gpu, u= int64_t *value) return 0; } =20 +static int a6xx_get_timestamp(struct msm_gpu *gpu, uint64_t *value) +{ + *value =3D gpu_read64(gpu, REG_A6XX_CP_ALWAYS_ON_COUNTER); + return 0; +} + static struct msm_ringbuffer *a6xx_active_ring(struct msm_gpu *gpu) { struct adreno_gpu *adreno_gpu =3D to_adreno_gpu(gpu); @@ -2004,8 +2126,8 @@ static const struct adreno_gpu_funcs funcs =3D { .set_param =3D adreno_set_param, .hw_init =3D a6xx_hw_init, .ucode_load =3D a6xx_ucode_load, - .pm_suspend =3D a6xx_pm_suspend, - .pm_resume =3D a6xx_pm_resume, + .pm_suspend =3D a6xx_gmu_pm_suspend, + .pm_resume =3D a6xx_gmu_pm_resume, .recover =3D a6xx_recover, .submit =3D a6xx_submit, .active_ring =3D a6xx_active_ring, @@ -2020,6 +2142,35 @@ static const struct adreno_gpu_funcs funcs =3D { #if defined(CONFIG_DRM_MSM_GPU_STATE) .gpu_state_get =3D a6xx_gpu_state_get, .gpu_state_put =3D a6xx_gpu_state_put, +#endif + .create_address_space =3D a6xx_create_address_space, + .create_private_address_space =3D a6xx_create_private_address_space, + .get_rptr =3D a6xx_get_rptr, + .progress =3D a6xx_progress, + }, + .get_timestamp =3D a6xx_gmu_get_timestamp, +}; + +static const struct adreno_gpu_funcs funcs_gmuwrapper =3D { + .base =3D { + .get_param =3D adreno_get_param, + .set_param =3D adreno_set_param, + .hw_init =3D a6xx_hw_init, + .ucode_load =3D a6xx_ucode_load, + .pm_suspend =3D a6xx_pm_suspend, + .pm_resume =3D a6xx_pm_resume, + .recover =3D a6xx_recover, + .submit =3D a6xx_submit, + .active_ring =3D a6xx_active_ring, + .irq =3D a6xx_irq, + .destroy =3D a6xx_destroy, +#if defined(CONFIG_DRM_MSM_GPU_STATE) + .show =3D a6xx_show, +#endif + .gpu_busy =3D a6xx_gpu_busy, +#if defined(CONFIG_DRM_MSM_GPU_STATE) + .gpu_state_get =3D a6xx_gpu_state_get, + .gpu_state_put =3D a6xx_gpu_state_put, #endif .create_address_space =3D a6xx_create_address_space, .create_private_address_space =3D a6xx_create_private_address_space, @@ -2050,15 +2201,31 @@ struct msm_gpu *a6xx_gpu_init(struct drm_device *de= v) =20 adreno_gpu->registers =3D NULL; =20 + /* Check if there is a GMU phandle and set it up */ + node =3D of_parse_phandle(pdev->dev.of_node, "qcom,gmu", 0); + /* FIXME: How do we gracefully handle this? */ + BUG_ON(!node); + + adreno_gpu->gmu_is_wrapper =3D of_device_is_compatible(node, "qcom,adreno= -gmu-wrapper"); + /* * We need to know the platform type before calling into adreno_gpu_init * so that the hw_apriv flag can be correctly set. Snoop into the info * and grab the revision number */ info =3D adreno_info(config->rev); - - if (info && (info->revn =3D=3D 650 || info->revn =3D=3D 660 || - adreno_cmp_rev(ADRENO_REV(6, 3, 5, ANY_ID), info->rev))) + if (!info) + return ERR_PTR(-EINVAL); + + /* Assign these early so that we can use the is_aXYZ helpers */ + /* Numeric revision IDs (e.g. 630) */ + adreno_gpu->revn =3D info->revn; + /* New-style ADRENO_REV()-only */ + adreno_gpu->rev =3D info->rev; + /* Quirk data */ + adreno_gpu->info =3D info; + + if (adreno_is_a650(adreno_gpu) || adreno_is_a660_family(adreno_gpu)) adreno_gpu->base.hw_apriv =3D true; =20 a6xx_llc_slices_init(pdev, a6xx_gpu); @@ -2069,7 +2236,10 @@ struct msm_gpu *a6xx_gpu_init(struct drm_device *dev) return ERR_PTR(ret); } =20 - ret =3D adreno_gpu_init(dev, pdev, adreno_gpu, &funcs, 1); + if (adreno_has_gmu_wrapper(adreno_gpu)) + ret =3D adreno_gpu_init(dev, pdev, adreno_gpu, &funcs_gmuwrapper, 1); + else + ret =3D adreno_gpu_init(dev, pdev, adreno_gpu, &funcs, 1); if (ret) { a6xx_destroy(&(a6xx_gpu->base.base)); return ERR_PTR(ret); @@ -2082,13 +2252,10 @@ struct msm_gpu *a6xx_gpu_init(struct drm_device *de= v) if (adreno_is_a618(adreno_gpu) || adreno_is_7c3(adreno_gpu)) priv->gpu_clamp_to_idle =3D true; =20 - /* Check if there is a GMU phandle and set it up */ - node =3D of_parse_phandle(pdev->dev.of_node, "qcom,gmu", 0); - - /* FIXME: How do we gracefully handle this? */ - BUG_ON(!node); - - ret =3D a6xx_gmu_init(a6xx_gpu, node); + if (adreno_has_gmu_wrapper(adreno_gpu)) + ret =3D a6xx_gmu_wrapper_init(a6xx_gpu, node); + else + ret =3D a6xx_gmu_init(a6xx_gpu, node); of_node_put(node); if (ret) { a6xx_destroy(&(a6xx_gpu->base.base)); diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.h b/drivers/gpu/drm/msm/ad= reno/a6xx_gpu.h index aa70390ee1c6..c788b06e72da 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.h +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.h @@ -76,6 +76,7 @@ int a6xx_gmu_set_oob(struct a6xx_gmu *gmu, enum a6xx_gmu_= oob_state state); void a6xx_gmu_clear_oob(struct a6xx_gmu *gmu, enum a6xx_gmu_oob_state stat= e); =20 int a6xx_gmu_init(struct a6xx_gpu *a6xx_gpu, struct device_node *node); +int a6xx_gmu_wrapper_init(struct a6xx_gpu *a6xx_gpu, struct device_node *n= ode); void a6xx_gmu_remove(struct a6xx_gpu *a6xx_gpu); =20 void a6xx_gmu_set_freq(struct msm_gpu *gpu, struct dev_pm_opp *opp, diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu_state.c b/drivers/gpu/drm/= msm/adreno/a6xx_gpu_state.c index 30ecdff363e7..4e5d650578c6 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu_state.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu_state.c @@ -1041,16 +1041,18 @@ struct msm_gpu_state *a6xx_gpu_state_get(struct msm= _gpu *gpu) /* Get the generic state from the adreno core */ adreno_gpu_state_get(gpu, &a6xx_state->base); =20 - a6xx_get_gmu_registers(gpu, a6xx_state); + if (!adreno_has_gmu_wrapper(adreno_gpu)) { + a6xx_get_gmu_registers(gpu, a6xx_state); =20 - a6xx_state->gmu_log =3D a6xx_snapshot_gmu_bo(a6xx_state, &a6xx_gpu->gmu.l= og); - a6xx_state->gmu_hfi =3D a6xx_snapshot_gmu_bo(a6xx_state, &a6xx_gpu->gmu.h= fi); - a6xx_state->gmu_debug =3D a6xx_snapshot_gmu_bo(a6xx_state, &a6xx_gpu->gmu= .debug); + a6xx_state->gmu_log =3D a6xx_snapshot_gmu_bo(a6xx_state, &a6xx_gpu->gmu.= log); + a6xx_state->gmu_hfi =3D a6xx_snapshot_gmu_bo(a6xx_state, &a6xx_gpu->gmu.= hfi); + a6xx_state->gmu_debug =3D a6xx_snapshot_gmu_bo(a6xx_state, &a6xx_gpu->gm= u.debug); =20 - a6xx_snapshot_gmu_hfi_history(gpu, a6xx_state); + a6xx_snapshot_gmu_hfi_history(gpu, a6xx_state); + } =20 /* If GX isn't on the rest of the data isn't going to be accessible */ - if (!a6xx_gmu_gx_is_on(&a6xx_gpu->gmu)) + if (!adreno_has_gmu_wrapper(adreno_gpu) && !a6xx_gmu_gx_is_on(&a6xx_gpu->= gmu)) return &a6xx_state->base; =20 /* Get the banks of indexed registers */ diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.c b/drivers/gpu/drm/msm/= adreno/adreno_gpu.c index 6934cee07d42..5c5901d65950 100644 --- a/drivers/gpu/drm/msm/adreno/adreno_gpu.c +++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.c @@ -528,6 +528,10 @@ int adreno_load_fw(struct adreno_gpu *adreno_gpu) if (!adreno_gpu->info->fw[i]) continue; =20 + /* Skip loading GMU firwmare with GMU Wrapper */ + if (adreno_has_gmu_wrapper(adreno_gpu) && i =3D=3D ADRENO_FW_GMU) + continue; + /* Skip if the firmware has already been loaded */ if (adreno_gpu->fw[i]) continue; @@ -1074,8 +1078,8 @@ int adreno_gpu_init(struct drm_device *drm, struct pl= atform_device *pdev, u32 speedbin; int ret; =20 - /* Only handle the core clock when GMU is not in use */ - if (config->rev.core < 6) { + /* Only handle the core clock when GMU is not in use (or is absent). */ + if (adreno_has_gmu_wrapper(adreno_gpu) || config->rev.core < 6) { /* * This can only be done before devm_pm_opp_of_add_table(), or * dev_pm_opp_set_config() will WARN_ON() diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.h b/drivers/gpu/drm/msm/= adreno/adreno_gpu.h index f62612a5c70f..ee5352bc5329 100644 --- a/drivers/gpu/drm/msm/adreno/adreno_gpu.h +++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.h @@ -115,6 +115,7 @@ struct adreno_gpu { * code (a3xx_gpu.c) and stored in this common location. */ const unsigned int *reg_offsets; + bool gmu_is_wrapper; }; #define to_adreno_gpu(x) container_of(x, struct adreno_gpu, base) =20 @@ -145,6 +146,11 @@ struct adreno_platform_config { =20 bool adreno_cmp_rev(struct adreno_rev rev1, struct adreno_rev rev2); =20 +static inline bool adreno_has_gmu_wrapper(struct adreno_gpu *gpu) +{ + return gpu->gmu_is_wrapper; +} + static inline bool adreno_is_a2xx(struct adreno_gpu *gpu) { return (gpu->revn < 300); --=20 2.40.1 From nobody Sun Feb 8 23:23:18 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4F395C77B7A for ; Sat, 20 May 2023 12:21:10 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231949AbjETMVI (ORCPT ); Sat, 20 May 2023 08:21:08 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:51204 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231808AbjETMUt (ORCPT ); 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[83.9.2.58]) by smtp.gmail.com with ESMTPSA id y6-20020ac24466000000b004f37bd02a89sm244766lfl.287.2023.05.20.05.20.03 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 20 May 2023 05:20:04 -0700 (PDT) From: Konrad Dybcio Date: Sat, 20 May 2023 14:19:51 +0200 Subject: [PATCH v7 11/18] drm/msm/adreno: Disable has_cached_coherent in GMU wrapper configurations MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20230223-topic-gmuwrapper-v7-11-ecc7aab83556@linaro.org> References: <20230223-topic-gmuwrapper-v7-0-ecc7aab83556@linaro.org> In-Reply-To: <20230223-topic-gmuwrapper-v7-0-ecc7aab83556@linaro.org> To: Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , David Airlie , Daniel Vetter , Rob Herring , Krzysztof Kozlowski , Bjorn Andersson , Konrad Dybcio , Akhil P Oommen Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Rob Clark , Marijn Suijten , Konrad Dybcio X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1684585186; l=1374; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=Ocm0vLk+RPaXxNK50G6/CzW6Z0tf26goam4OhjTSWzI=; b=kG9tiJJo8el0T9AKSzuHPeh2Sfcz5nC7icc5Eg0j1Kz8+OxSsA/t/ZldnqBwMOgw92PtxeSRA awRSRNuzpFbCNWiYdPjMR/ER0mCdAOx45dNW6hQBntrTLroZwm98Tnu X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org A610 and A619_holi don't support the feature. Disable it to make the GPU st= op crashing after almost each and every submission - the received data on the GPU end was simply incomplete in garbled, resulting in almost nothing being executed properly. Extend the disablement to adreno_has_gmu_wrapper, as none of the GMU wrapper Adrenos that don't support yet seem to feature i= t. Signed-off-by: Konrad Dybcio --- drivers/gpu/drm/msm/adreno/adreno_device.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/msm/adreno/adreno_device.c b/drivers/gpu/drm/m= sm/adreno/adreno_device.c index 8cff86e9d35c..b133755a56c4 100644 --- a/drivers/gpu/drm/msm/adreno/adreno_device.c +++ b/drivers/gpu/drm/msm/adreno/adreno_device.c @@ -551,7 +551,6 @@ static int adreno_bind(struct device *dev, struct devic= e *master, void *data) config.rev.minor, config.rev.patchid); =20 priv->is_a2xx =3D config.rev.core =3D=3D 2; - priv->has_cached_coherent =3D config.rev.core >=3D 6; =20 gpu =3D info->init(drm); if (IS_ERR(gpu)) { @@ -563,6 +562,10 @@ static int adreno_bind(struct device *dev, struct devi= ce *master, void *data) if (ret) return ret; =20 + if (config.rev.core >=3D 6) + if (!adreno_has_gmu_wrapper(to_adreno_gpu(gpu))) + priv->has_cached_coherent =3D true; + return 0; } =20 --=20 2.40.1 From nobody Sun Feb 8 23:23:18 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 857E6C7EE29 for ; Sat, 20 May 2023 12:21:19 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231830AbjETMVR (ORCPT ); Sat, 20 May 2023 08:21:17 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:51220 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231820AbjETMUu (ORCPT ); Sat, 20 May 2023 08:20:50 -0400 Received: from mail-lf1-x133.google.com (mail-lf1-x133.google.com [IPv6:2a00:1450:4864:20::133]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 8641010E3 for ; Sat, 20 May 2023 05:20:08 -0700 (PDT) Received: by mail-lf1-x133.google.com with SMTP id 2adb3069b0e04-4efd6e26585so4688443e87.1 for ; Sat, 20 May 2023 05:20:08 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1684585207; x=1687177207; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=hhfos0UrJYSpJBVxVD1DGmqX6U3slcT+9UKFHjrC6/Y=; b=cbqlSyrMe3Qh1SjdcqgrI8yIWvHaMc6zgZUaBfGzNtoPEUvw9OsFcV6HqUh8135j69 fw2S9D8ocD5H429A5Nd2mnYDigN05EJfmbbspbqzxChd+cmCjgd03TwXk8JUhQUfdnWT m8AZyMh2EdC88Wt2pQH8uin1L12uaOcb6hW5KcvRwUnicQRI0hmE1BhxLt2ZorOSLlRK T9br4wCOY7p9RcG3P5VAYgY7bw2nvs5wBg70zTNUcDisXlvfXv+eZGCGhgRPRKT5bCd2 7pY6iJnZWl5mElWCoyl5eNbbJ9SYw/1RUUnudZjBL3GtrBJcZI2kfIGlopsvdjUTVNWt VowQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1684585207; x=1687177207; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=hhfos0UrJYSpJBVxVD1DGmqX6U3slcT+9UKFHjrC6/Y=; b=EZynM0z2+W9eOqdfbivzgjeS9ZKEnzDBJziwu9bW0opP8UhOSjo10xsHqFwLSuBBQ1 bQ1lux1+NHoZPILYbbisXlDT89iThN7WHiaraeZ/EQ3gRQ2SlFkHW1UQpKkmYUSXKW0u 29JmyUheYesLxrWoO4erEEkXpWa3AvoxVkZS9pTy4H+z1qKwu3p3ikWstPrUGEwaLKIZ HeiTVTmXck/onKiCmpMlwbzphW8Ai1l809ampAps2JwV22WlppsN7sIeLKvDPYpai1dp kiRj48UdZcpqf2sYO1lx9+ne8XD4Ij0apqnJcmhIf2WZt601nc4E6oGIdzXZcrsoDCeg szbw== X-Gm-Message-State: AC+VfDxfzYuWu0NXvcTWKguNzEJWAXCWjOpIlBlA2ps/gCatvt4vJyiB NOzCOQ0QZ0b9qG66J6cxCkfjWQ== X-Google-Smtp-Source: ACHHUZ5NlVsOOjordr7L4pWQq2TMdpaUFz/GjpTZAA8SJVes4vts0GBhPyF3ID5bVoh2z3Rl6dLn4g== X-Received: by 2002:ac2:47f8:0:b0:4f2:5c4b:e69b with SMTP id b24-20020ac247f8000000b004f25c4be69bmr1772748lfp.67.1684585206844; Sat, 20 May 2023 05:20:06 -0700 (PDT) Received: from [192.168.1.101] (abxi58.neoplus.adsl.tpnet.pl. [83.9.2.58]) by smtp.gmail.com with ESMTPSA id y6-20020ac24466000000b004f37bd02a89sm244766lfl.287.2023.05.20.05.20.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 20 May 2023 05:20:06 -0700 (PDT) From: Konrad Dybcio Date: Sat, 20 May 2023 14:19:52 +0200 Subject: [PATCH v7 12/18] drm/msm/a6xx: Add support for A619_holi MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20230223-topic-gmuwrapper-v7-12-ecc7aab83556@linaro.org> References: <20230223-topic-gmuwrapper-v7-0-ecc7aab83556@linaro.org> In-Reply-To: <20230223-topic-gmuwrapper-v7-0-ecc7aab83556@linaro.org> To: Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , David Airlie , Daniel Vetter , Rob Herring , Krzysztof Kozlowski , Bjorn Andersson , Konrad Dybcio , Akhil P Oommen Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Rob Clark , Marijn Suijten , Konrad Dybcio X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1684585186; l=4014; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=UvvtX87HOPp56IoMSbK8amUUhfTCemIF7foXaIkZYF0=; b=ezN+zjCuuBL3p2bWj0V97pqWvY7Gi0cJ5kW9NCsMwBLLX0LqFXDM1p7DESG4oHbV/HPGE+1ck ONRWYgaB2UzAZHmpSduu2GpXV5sEpfrtAaAWpZODbjKlHmbEuAPNOn5 X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org A619_holi is a GMU-less variant of the already-supported A619 GPU. It's present on at least SM4350 (holi) and SM6375 (blair). No mesa changes are required. Add the required kernel-side support for it. Signed-off-by: Konrad Dybcio --- drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 27 +++++++++++++++++++++++++-- drivers/gpu/drm/msm/adreno/adreno_gpu.h | 5 +++++ 2 files changed, 30 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/ad= reno/a6xx_gpu.c index 2ba9d790a52c..7eaebcefcb2a 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c @@ -810,6 +810,9 @@ static void a6xx_set_ubwc_config(struct msm_gpu *gpu) if (adreno_is_a618(adreno_gpu)) return; =20 + if (adreno_is_a619_holi(adreno_gpu)) + hbb_lo =3D 0; + if (adreno_is_a640_family(adreno_gpu)) amsbc =3D 1; =20 @@ -1027,7 +1030,12 @@ static int hw_init(struct msm_gpu *gpu) } =20 /* Clear GBIF halt in case GX domain was not collapsed */ - if (a6xx_has_gbif(adreno_gpu)) { + if (adreno_is_a619_holi(adreno_gpu)) { + gpu_write(gpu, REG_A6XX_GBIF_HALT, 0); + gpu_write(gpu, REG_A6XX_RBBM_GPR0_CNTL, 0); + /* Let's make extra sure that the GPU can access the memory.. */ + mb(); + } else if (a6xx_has_gbif(adreno_gpu)) { gpu_write(gpu, REG_A6XX_GBIF_HALT, 0); gpu_write(gpu, REG_A6XX_RBBM_GBIF_HALT, 0); /* Let's make extra sure that the GPU can access the memory.. */ @@ -1036,6 +1044,9 @@ static int hw_init(struct msm_gpu *gpu) =20 gpu_write(gpu, REG_A6XX_RBBM_SECVID_TSB_CNTL, 0); =20 + if (adreno_is_a619_holi(adreno_gpu)) + a6xx_sptprac_enable(gmu); + /* * Disable the trusted memory range - we don't actually supported secure * memory rendering at this point in time and we don't want to block off @@ -1656,12 +1667,18 @@ static void a6xx_llc_slices_init(struct platform_de= vice *pdev, #define GBIF_CLIENT_HALT_MASK BIT(0) #define GBIF_ARB_HALT_MASK BIT(1) #define VBIF_XIN_HALT_CTRL0_MASK GENMASK(3, 0) +#define VBIF_RESET_ACK_MASK 0xF0 +#define GPR0_GBIF_HALT_REQUEST 0x1E0 =20 void a6xx_bus_clear_pending_transactions(struct adreno_gpu *adreno_gpu, bo= ol gx_off) { struct msm_gpu *gpu =3D &adreno_gpu->base; =20 - if (!a6xx_has_gbif(adreno_gpu)) { + if (adreno_is_a619_holi(adreno_gpu)) { + gpu_write(gpu, 0x18, GPR0_GBIF_HALT_REQUEST); + spin_until((gpu_read(gpu, REG_A6XX_RBBM_VBIF_GX_RESET_STATUS) & + (VBIF_RESET_ACK_MASK)) =3D=3D VBIF_RESET_ACK_MASK); + } else if (!a6xx_has_gbif(adreno_gpu)) { gpu_write(gpu, REG_A6XX_VBIF_XIN_HALT_CTRL0, VBIF_XIN_HALT_CTRL0_MASK); spin_until((gpu_read(gpu, REG_A6XX_VBIF_XIN_HALT_CTRL1) & (VBIF_XIN_HALT_CTRL0_MASK)) =3D=3D VBIF_XIN_HALT_CTRL0_MASK); @@ -1755,6 +1772,9 @@ static int a6xx_pm_resume(struct msm_gpu *gpu) if (ret) goto err_mem_clk; =20 + if (adreno_is_a619_holi(adreno_gpu)) + a6xx_sptprac_enable(gmu); + /* If anything goes south, tear the GPU down piece by piece.. */ if (ret) { err_mem_clk: @@ -1818,6 +1838,9 @@ static int a6xx_pm_suspend(struct msm_gpu *gpu) /* Drain the outstanding traffic on memory buses */ a6xx_bus_clear_pending_transactions(adreno_gpu, true); =20 + if (adreno_is_a619_holi(adreno_gpu)) + a6xx_sptprac_disable(gmu); + clk_disable_unprepare(gpu->ebi1_clk); =20 clk_bulk_disable_unprepare(gpu->nr_clocks, gpu->grp_clks); diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.h b/drivers/gpu/drm/msm/= adreno/adreno_gpu.h index ee5352bc5329..432fee5c1516 100644 --- a/drivers/gpu/drm/msm/adreno/adreno_gpu.h +++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.h @@ -252,6 +252,11 @@ static inline int adreno_is_a619(struct adreno_gpu *gp= u) return gpu->revn =3D=3D 619; } =20 +static inline int adreno_is_a619_holi(struct adreno_gpu *gpu) +{ + return adreno_is_a619(gpu) && adreno_has_gmu_wrapper(gpu); +} + static inline int adreno_is_a630(struct adreno_gpu *gpu) { return gpu->revn =3D=3D 630; --=20 2.40.1 From nobody Sun Feb 8 23:23:18 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id B2BF4C77B7A for ; Sat, 20 May 2023 12:21:22 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230314AbjETMVU (ORCPT ); Sat, 20 May 2023 08:21:20 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:51152 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231760AbjETMUu (ORCPT ); Sat, 20 May 2023 08:20:50 -0400 Received: from mail-lf1-x131.google.com (mail-lf1-x131.google.com [IPv6:2a00:1450:4864:20::131]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 6FB451B7 for ; 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[83.9.2.58]) by smtp.gmail.com with ESMTPSA id y6-20020ac24466000000b004f37bd02a89sm244766lfl.287.2023.05.20.05.20.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 20 May 2023 05:20:08 -0700 (PDT) From: Konrad Dybcio Date: Sat, 20 May 2023 14:19:53 +0200 Subject: [PATCH v7 13/18] drm/msm/a6xx: Add A610 support MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20230223-topic-gmuwrapper-v7-13-ecc7aab83556@linaro.org> References: <20230223-topic-gmuwrapper-v7-0-ecc7aab83556@linaro.org> In-Reply-To: <20230223-topic-gmuwrapper-v7-0-ecc7aab83556@linaro.org> To: Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , David Airlie , Daniel Vetter , Rob Herring , Krzysztof Kozlowski , Bjorn Andersson , Konrad Dybcio , Akhil P Oommen Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Rob Clark , Marijn Suijten , Konrad Dybcio X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1684585186; l=11126; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=mqhO+VDc3oGlH46wfwjgdQ8dOM9g+DIEMLNtt31EsOw=; b=zIeMdwjZBsK4lOIdCLHy+AJkUPlkiqVLyY7dZfMAOodJUHYNvvFcDuseL5EHHfN5KlJW9y14+ YkvTwqp3ROUCrNOwEYVWBeFVyw/3lQ3cd1DGb8p/8EKv+73imGVc2SD X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org A610 is one of (if not the) lowest-tier SKUs in the A6XX family. It features no GMU, as it's implemented solely on SoCs with SMD_RPM. What's more interesting is that it does not feature a VDDGX line either, being powered solely by VDDCX and has an unfortunate hardware quirk that makes its reset line broken - after a couple of assert/ deassert cycles, it will hang for good and will not wake up again. This GPU requires mesa changes for proper rendering, and lots of them at that. The command streams are quite far away from any other A6XX GPU and hence it needs special care. This patch was validated both by running an (incomplete) downstream mesa with some hacks (frames rendered correctly, though some instructions made the GPU hangcheck which is expected - garbage in, garbage out) and by replaying RD traces captured with the downstream KGSL driver - no crashes there, ever. Add support for this GPU on the kernel side, which comes down to pretty simply adding A612 HWCG tables, altering a few values and adding a special case for handling the reset line. Reviewed-by: Dmitry Baryshkov Signed-off-by: Konrad Dybcio --- drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 101 +++++++++++++++++++++++++= ---- drivers/gpu/drm/msm/adreno/adreno_device.c | 12 ++++ drivers/gpu/drm/msm/adreno/adreno_gpu.h | 8 ++- 3 files changed, 108 insertions(+), 13 deletions(-) diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/ad= reno/a6xx_gpu.c index 7eaebcefcb2a..ca055bff23c8 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c @@ -252,6 +252,56 @@ static void a6xx_submit(struct msm_gpu *gpu, struct ms= m_gem_submit *submit) a6xx_flush(gpu, ring); } =20 +const struct adreno_reglist a612_hwcg[] =3D { + {REG_A6XX_RBBM_CLOCK_CNTL_SP0, 0x22222222}, + {REG_A6XX_RBBM_CLOCK_CNTL2_SP0, 0x02222220}, + {REG_A6XX_RBBM_CLOCK_DELAY_SP0, 0x00000081}, + {REG_A6XX_RBBM_CLOCK_HYST_SP0, 0x0000f3cf}, + {REG_A6XX_RBBM_CLOCK_CNTL_TP0, 0x22222222}, + {REG_A6XX_RBBM_CLOCK_CNTL2_TP0, 0x22222222}, + {REG_A6XX_RBBM_CLOCK_CNTL3_TP0, 0x22222222}, + {REG_A6XX_RBBM_CLOCK_CNTL4_TP0, 0x00022222}, + {REG_A6XX_RBBM_CLOCK_DELAY_TP0, 0x11111111}, + {REG_A6XX_RBBM_CLOCK_DELAY2_TP0, 0x11111111}, + {REG_A6XX_RBBM_CLOCK_DELAY3_TP0, 0x11111111}, + {REG_A6XX_RBBM_CLOCK_DELAY4_TP0, 0x00011111}, + {REG_A6XX_RBBM_CLOCK_HYST_TP0, 0x77777777}, + {REG_A6XX_RBBM_CLOCK_HYST2_TP0, 0x77777777}, + {REG_A6XX_RBBM_CLOCK_HYST3_TP0, 0x77777777}, + {REG_A6XX_RBBM_CLOCK_HYST4_TP0, 0x00077777}, + {REG_A6XX_RBBM_CLOCK_CNTL_RB0, 0x22222222}, + {REG_A6XX_RBBM_CLOCK_CNTL2_RB0, 0x01202222}, + {REG_A6XX_RBBM_CLOCK_CNTL_CCU0, 0x00002220}, + {REG_A6XX_RBBM_CLOCK_HYST_RB_CCU0, 0x00040f00}, + {REG_A6XX_RBBM_CLOCK_CNTL_RAC, 0x05522022}, + {REG_A6XX_RBBM_CLOCK_CNTL2_RAC, 0x00005555}, + {REG_A6XX_RBBM_CLOCK_DELAY_RAC, 0x00000011}, + {REG_A6XX_RBBM_CLOCK_HYST_RAC, 0x00445044}, + {REG_A6XX_RBBM_CLOCK_CNTL_TSE_RAS_RBBM, 0x04222222}, + {REG_A6XX_RBBM_CLOCK_MODE_VFD, 0x00002222}, + {REG_A6XX_RBBM_CLOCK_MODE_GPC, 0x02222222}, + {REG_A6XX_RBBM_CLOCK_DELAY_HLSQ_2, 0x00000002}, + {REG_A6XX_RBBM_CLOCK_MODE_HLSQ, 0x00002222}, + {REG_A6XX_RBBM_CLOCK_DELAY_TSE_RAS_RBBM, 0x00004000}, + {REG_A6XX_RBBM_CLOCK_DELAY_VFD, 0x00002222}, + {REG_A6XX_RBBM_CLOCK_DELAY_GPC, 0x00000200}, + {REG_A6XX_RBBM_CLOCK_DELAY_HLSQ, 0x00000000}, + {REG_A6XX_RBBM_CLOCK_HYST_TSE_RAS_RBBM, 0x00000000}, + {REG_A6XX_RBBM_CLOCK_HYST_VFD, 0x00000000}, + {REG_A6XX_RBBM_CLOCK_HYST_GPC, 0x04104004}, + {REG_A6XX_RBBM_CLOCK_HYST_HLSQ, 0x00000000}, + {REG_A6XX_RBBM_CLOCK_CNTL_UCHE, 0x22222222}, + {REG_A6XX_RBBM_CLOCK_HYST_UCHE, 0x00000004}, + {REG_A6XX_RBBM_CLOCK_DELAY_UCHE, 0x00000002}, + {REG_A6XX_RBBM_ISDB_CNT, 0x00000182}, + {REG_A6XX_RBBM_RAC_THRESHOLD_CNT, 0x00000000}, + {REG_A6XX_RBBM_SP_HYST_CNT, 0x00000000}, + {REG_A6XX_RBBM_CLOCK_CNTL_GMU_GX, 0x00000222}, + {REG_A6XX_RBBM_CLOCK_DELAY_GMU_GX, 0x00000111}, + {REG_A6XX_RBBM_CLOCK_HYST_GMU_GX, 0x00000555}, + {}, +}; + /* For a615 family (a615, a616, a618 and a619) */ const struct adreno_reglist a615_hwcg[] =3D { {REG_A6XX_RBBM_CLOCK_CNTL_SP0, 0x02222222}, @@ -602,6 +652,8 @@ static void a6xx_set_hwcg(struct msm_gpu *gpu, bool sta= te) =20 if (adreno_is_a630(adreno_gpu)) clock_cntl_on =3D 0x8aa8aa02; + else if (adreno_is_a610(adreno_gpu)) + clock_cntl_on =3D 0xaaa8aa82; else clock_cntl_on =3D 0x8aa8aa82; =20 @@ -612,13 +664,15 @@ static void a6xx_set_hwcg(struct msm_gpu *gpu, bool s= tate) return; =20 /* Disable SP clock before programming HWCG registers */ - gmu_rmw(gmu, REG_A6XX_GPU_GMU_GX_SPTPRAC_CLOCK_CONTROL, 1, 0); + if (!adreno_is_a610(adreno_gpu)) + gmu_rmw(gmu, REG_A6XX_GPU_GMU_GX_SPTPRAC_CLOCK_CONTROL, 1, 0); =20 for (i =3D 0; (reg =3D &adreno_gpu->info->hwcg[i], reg->offset); i++) gpu_write(gpu, reg->offset, state ? reg->value : 0); =20 /* Enable SP clock */ - gmu_rmw(gmu, REG_A6XX_GPU_GMU_GX_SPTPRAC_CLOCK_CONTROL, 0, 1); + if (!adreno_is_a610(adreno_gpu)) + gmu_rmw(gmu, REG_A6XX_GPU_GMU_GX_SPTPRAC_CLOCK_CONTROL, 0, 1); =20 gpu_write(gpu, REG_A6XX_RBBM_CLOCK_CNTL, state ? clock_cntl_on : 0); } @@ -806,6 +860,13 @@ static void a6xx_set_ubwc_config(struct msm_gpu *gpu) /* Unknown, introduced with A640/680 */ u32 amsbc =3D 0; =20 + if (adreno_is_a610(adreno_gpu)) { + /* HBB =3D 14 */ + hbb_lo =3D 1; + min_acc_len =3D 1; + ubwc_mode =3D 1; + } + /* a618 is using the hw default values */ if (adreno_is_a618(adreno_gpu)) return; @@ -1073,13 +1134,13 @@ static int hw_init(struct msm_gpu *gpu) a6xx_set_hwcg(gpu, true); =20 /* VBIF/GBIF start*/ - if (adreno_is_a640_family(adreno_gpu) || + if (adreno_is_a610(adreno_gpu) || + adreno_is_a640_family(adreno_gpu) || adreno_is_a650_family(adreno_gpu)) { gpu_write(gpu, REG_A6XX_GBIF_QSB_SIDE0, 0x00071620); gpu_write(gpu, REG_A6XX_GBIF_QSB_SIDE1, 0x00071620); gpu_write(gpu, REG_A6XX_GBIF_QSB_SIDE2, 0x00071620); gpu_write(gpu, REG_A6XX_GBIF_QSB_SIDE3, 0x00071620); - gpu_write(gpu, REG_A6XX_GBIF_QSB_SIDE3, 0x00071620); gpu_write(gpu, REG_A6XX_RBBM_GBIF_CLIENT_QOS_CNTL, 0x3); } else { gpu_write(gpu, REG_A6XX_RBBM_VBIF_CLIENT_QOS_CNTL, 0x3); @@ -1107,18 +1168,26 @@ static int hw_init(struct msm_gpu *gpu) gpu_write(gpu, REG_A6XX_UCHE_FILTER_CNTL, 0x804); gpu_write(gpu, REG_A6XX_UCHE_CACHE_WAYS, 0x4); =20 - if (adreno_is_a640_family(adreno_gpu) || - adreno_is_a650_family(adreno_gpu)) + if (adreno_is_a640_family(adreno_gpu) || adreno_is_a650_family(adreno_gpu= )) { gpu_write(gpu, REG_A6XX_CP_ROQ_THRESHOLDS_2, 0x02000140); - else + gpu_write(gpu, REG_A6XX_CP_ROQ_THRESHOLDS_1, 0x8040362c); + } else if (adreno_is_a610(adreno_gpu)) { + gpu_write(gpu, REG_A6XX_CP_ROQ_THRESHOLDS_2, 0x00800060); + gpu_write(gpu, REG_A6XX_CP_ROQ_THRESHOLDS_1, 0x40201b16); + } else { gpu_write(gpu, REG_A6XX_CP_ROQ_THRESHOLDS_2, 0x010000c0); - gpu_write(gpu, REG_A6XX_CP_ROQ_THRESHOLDS_1, 0x8040362c); + gpu_write(gpu, REG_A6XX_CP_ROQ_THRESHOLDS_1, 0x8040362c); + } =20 if (adreno_is_a660_family(adreno_gpu)) gpu_write(gpu, REG_A6XX_CP_LPAC_PROG_FIFO_SIZE, 0x00000020); =20 /* Setting the mem pool size */ - gpu_write(gpu, REG_A6XX_CP_MEM_POOL_SIZE, 128); + if (adreno_is_a610(adreno_gpu)) { + gpu_write(gpu, REG_A6XX_CP_MEM_POOL_SIZE, 48); + gpu_write(gpu, REG_A6XX_CP_MEM_POOL_DBG_ADDR, 47); + } else + gpu_write(gpu, REG_A6XX_CP_MEM_POOL_SIZE, 128); =20 /* Setting the primFifo thresholds default values, * and vccCacheSkipDis=3D1 bit (0x200) for A640 and newer @@ -1129,6 +1198,8 @@ static int hw_init(struct msm_gpu *gpu) gpu_write(gpu, REG_A6XX_PC_DBG_ECO_CNTL, 0x00200200); else if (adreno_is_a650(adreno_gpu) || adreno_is_a660(adreno_gpu)) gpu_write(gpu, REG_A6XX_PC_DBG_ECO_CNTL, 0x00300200); + else if (adreno_is_a610(adreno_gpu)) + gpu_write(gpu, REG_A6XX_PC_DBG_ECO_CNTL, 0x00080000); else gpu_write(gpu, REG_A6XX_PC_DBG_ECO_CNTL, 0x00180000); =20 @@ -1144,8 +1215,10 @@ static int hw_init(struct msm_gpu *gpu) a6xx_set_ubwc_config(gpu); =20 /* Enable fault detection */ - gpu_write(gpu, REG_A6XX_RBBM_INTERFACE_HANG_INT_CNTL, - (1 << 30) | 0x1fffff); + if (adreno_is_a610(adreno_gpu)) + gpu_write(gpu, REG_A6XX_RBBM_INTERFACE_HANG_INT_CNTL, (1 << 30) | 0x3fff= f); + else + gpu_write(gpu, REG_A6XX_RBBM_INTERFACE_HANG_INT_CNTL, (1 << 30) | 0x1fff= ff); =20 gpu_write(gpu, REG_A6XX_UCHE_CLIENT_PF, 1); =20 @@ -1675,7 +1748,7 @@ void a6xx_bus_clear_pending_transactions(struct adren= o_gpu *adreno_gpu, bool gx_ struct msm_gpu *gpu =3D &adreno_gpu->base; =20 if (adreno_is_a619_holi(adreno_gpu)) { - gpu_write(gpu, 0x18, GPR0_GBIF_HALT_REQUEST); + gpu_write(gpu, REG_A6XX_RBBM_GPR0_CNTL, GPR0_GBIF_HALT_REQUEST); spin_until((gpu_read(gpu, REG_A6XX_RBBM_VBIF_GX_RESET_STATUS) & (VBIF_RESET_ACK_MASK)) =3D=3D VBIF_RESET_ACK_MASK); } else if (!a6xx_has_gbif(adreno_gpu)) { @@ -1709,6 +1782,10 @@ void a6xx_bus_clear_pending_transactions(struct adre= no_gpu *adreno_gpu, bool gx_ =20 void a6xx_gpu_sw_reset(struct msm_gpu *gpu, bool assert) { + /* 11nm chips (e.g. ones with A610) have hw issues with the reset line! */ + if (adreno_is_a610(to_adreno_gpu(gpu))) + return; + gpu_write(gpu, REG_A6XX_RBBM_SW_RESET_CMD, assert); /* Add a barrier to avoid bad surprises */ mb(); diff --git a/drivers/gpu/drm/msm/adreno/adreno_device.c b/drivers/gpu/drm/m= sm/adreno/adreno_device.c index b133755a56c4..2c2cdbdada4d 100644 --- a/drivers/gpu/drm/msm/adreno/adreno_device.c +++ b/drivers/gpu/drm/msm/adreno/adreno_device.c @@ -253,6 +253,18 @@ static const struct adreno_info gpulist[] =3D { .quirks =3D ADRENO_QUIRK_LMLOADKILL_DISABLE, .init =3D a5xx_gpu_init, .zapfw =3D "a540_zap.mdt", + }, { + .rev =3D ADRENO_REV(6, 1, 0, ANY_ID), + .revn =3D 610, + .name =3D "A610", + .fw =3D { + [ADRENO_FW_SQE] =3D "a630_sqe.fw", + }, + .gmem =3D (SZ_128K + SZ_4K), + .inactive_period =3D 500, + .init =3D a6xx_gpu_init, + .zapfw =3D "a610_zap.mdt", + .hwcg =3D a612_hwcg, }, { .rev =3D ADRENO_REV(6, 1, 8, ANY_ID), .revn =3D 618, diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.h b/drivers/gpu/drm/msm/= adreno/adreno_gpu.h index 432fee5c1516..7a5d595d4b99 100644 --- a/drivers/gpu/drm/msm/adreno/adreno_gpu.h +++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.h @@ -55,7 +55,8 @@ struct adreno_reglist { u32 value; }; =20 -extern const struct adreno_reglist a615_hwcg[], a630_hwcg[], a640_hwcg[], = a650_hwcg[], a660_hwcg[]; +extern const struct adreno_reglist a612_hwcg[], a615_hwcg[], a630_hwcg[], = a640_hwcg[], a650_hwcg[]; +extern const struct adreno_reglist a660_hwcg[]; =20 struct adreno_info { struct adreno_rev rev; @@ -242,6 +243,11 @@ static inline int adreno_is_a540(struct adreno_gpu *gp= u) return gpu->revn =3D=3D 540; } =20 +static inline int adreno_is_a610(struct adreno_gpu *gpu) +{ + return gpu->revn =3D=3D 610; +} + static inline int adreno_is_a618(struct adreno_gpu *gpu) { return gpu->revn =3D=3D 618; --=20 2.40.1 From nobody Sun Feb 8 23:23:18 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id D8814C7EE29 for ; Sat, 20 May 2023 12:21:24 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232004AbjETMVX (ORCPT ); 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[83.9.2.58]) by smtp.gmail.com with ESMTPSA id y6-20020ac24466000000b004f37bd02a89sm244766lfl.287.2023.05.20.05.20.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 20 May 2023 05:20:09 -0700 (PDT) From: Konrad Dybcio Date: Sat, 20 May 2023 14:19:54 +0200 Subject: [PATCH v7 14/18] drm/msm/a6xx: Fix some A619 tunables MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20230223-topic-gmuwrapper-v7-14-ecc7aab83556@linaro.org> References: <20230223-topic-gmuwrapper-v7-0-ecc7aab83556@linaro.org> In-Reply-To: <20230223-topic-gmuwrapper-v7-0-ecc7aab83556@linaro.org> To: Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , David Airlie , Daniel Vetter , Rob Herring , Krzysztof Kozlowski , Bjorn Andersson , Konrad Dybcio , Akhil P Oommen Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Rob Clark , Marijn Suijten , Konrad Dybcio X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1684585186; l=1537; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=tiRhEnWKQorRchYKK0xFSXYxLCZIr0JF9605Ln4P3Mc=; b=6SwQwq/wcZwxW4yEQVOA5mZvDtrX7nHuyB/e5KLEInDWCrw81IDGPtjfjNDDBsSw+TJRba0C6 RUXiL0DgPMoA1WRZnBdKZCN2CiNHUN9aJms2zOdcWl8HZoWUpEdm69G X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Adreno 619 expects some tunables to be set differently. Make up for it. Fixes: b7616b5c69e6 ("drm/msm/adreno: Add A619 support") Reviewed-by: Dmitry Baryshkov Signed-off-by: Konrad Dybcio --- drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/ad= reno/a6xx_gpu.c index ca055bff23c8..9f296928c249 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c @@ -1198,6 +1198,8 @@ static int hw_init(struct msm_gpu *gpu) gpu_write(gpu, REG_A6XX_PC_DBG_ECO_CNTL, 0x00200200); else if (adreno_is_a650(adreno_gpu) || adreno_is_a660(adreno_gpu)) gpu_write(gpu, REG_A6XX_PC_DBG_ECO_CNTL, 0x00300200); + else if (adreno_is_a619(adreno_gpu)) + gpu_write(gpu, REG_A6XX_PC_DBG_ECO_CNTL, 0x00018000); else if (adreno_is_a610(adreno_gpu)) gpu_write(gpu, REG_A6XX_PC_DBG_ECO_CNTL, 0x00080000); else @@ -1215,7 +1217,9 @@ static int hw_init(struct msm_gpu *gpu) a6xx_set_ubwc_config(gpu); =20 /* Enable fault detection */ - if (adreno_is_a610(adreno_gpu)) + if (adreno_is_a619(adreno_gpu)) + gpu_write(gpu, REG_A6XX_RBBM_INTERFACE_HANG_INT_CNTL, (1 << 30) | 0x3fff= ff); + else if (adreno_is_a610(adreno_gpu)) gpu_write(gpu, REG_A6XX_RBBM_INTERFACE_HANG_INT_CNTL, (1 << 30) | 0x3fff= f); else gpu_write(gpu, REG_A6XX_RBBM_INTERFACE_HANG_INT_CNTL, (1 << 30) | 0x1fff= ff); --=20 2.40.1 From nobody Sun Feb 8 23:23:18 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id B3134C77B7A for ; Sat, 20 May 2023 12:21:41 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232019AbjETMVk (ORCPT ); Sat, 20 May 2023 08:21:40 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:52012 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231790AbjETMUw (ORCPT ); Sat, 20 May 2023 08:20:52 -0400 Received: from mail-lj1-x236.google.com (mail-lj1-x236.google.com [IPv6:2a00:1450:4864:20::236]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 42EA0170F for ; Sat, 20 May 2023 05:20:13 -0700 (PDT) Received: by mail-lj1-x236.google.com with SMTP id 38308e7fff4ca-2af29b37bd7so12876981fa.1 for ; Sat, 20 May 2023 05:20:13 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1684585211; x=1687177211; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=T0/N3UhKyosOC5GIX6zF4duG0WOxNT9nlQC/xkc4q20=; b=hQ2hixELOV6pHTV9g8I73dQeO+6iBzNKFDq2hboJZvtE8dDkzeDWLXKRbwVWZjQ1oz kWiz+S2V+s8A486CTnSMSZryYix6SWBKVu5fhtslimtlxe0MeqKwwtzUNlEPfXWGAELG iurxOUS1yK/FB8HGeVooKAe52tsbSIWa1isrIGOYWKi3sAEinn+FIcExOsSqa57xcm0I 6XtWIwyRc+zNsQ/znuIF+xoGE2LLPwOj1at75UhthmmFE4QMOaZR+RU71ftu9ZGgq8UP I08yf8q0rrFDA1k+06mm8xd5aiBvVN+IRyPEdRg7qUI6sqigzDbx+vRV6TZQQtl2jTOY 0hEQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1684585211; x=1687177211; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=T0/N3UhKyosOC5GIX6zF4duG0WOxNT9nlQC/xkc4q20=; b=cL7dp64APaQAb65DGQ490YSVl449jsSjo/84GE5wRFqL6qIQnEod2CoGOFbs9pa75n 6YtbgT93tGfOW56fBi1MeM5l1cP17h575Vfo8F5k9GGMSzbZ6nyGT4RGN8Y7BpZqMNpn mLCSj6ke2Zm7YoEpnXHGyL/99FlSDelMoQ1Snx36H79bRi6S1KmSD1Z99n7vOJk6jD5Z k0wE54LalO9Qk/eKEoYywLD+8bVPblMPyqKl5TqzjTURkPoy7M5rWVOtkrQF0UfPc1DF fMMwrYLXuB8QHvnYdE2KKvQAuKAAqcBwKVnVdaeKzr5URBRvgEpe/7cH4ziEv/McWiWS Ph4Q== X-Gm-Message-State: AC+VfDzAzgWeFrNgzKpY9ZoFdv9uMqsKJBDX2f9oFo3UxAzlo8R/Ws5r i+XB4lW2XvNOC56J6uelZ06YBQ== X-Google-Smtp-Source: ACHHUZ6epyhcKzUCAVYZ3n4xjPRSEnE1Ai3K5YzOW2ci78F25R6AVqSaB3T94wZzfOoB6qkhWxs0Dg== X-Received: by 2002:ac2:5a47:0:b0:4ef:d3f3:c421 with SMTP id r7-20020ac25a47000000b004efd3f3c421mr2066083lfn.4.1684585211446; Sat, 20 May 2023 05:20:11 -0700 (PDT) Received: from [192.168.1.101] (abxi58.neoplus.adsl.tpnet.pl. [83.9.2.58]) by smtp.gmail.com with ESMTPSA id y6-20020ac24466000000b004f37bd02a89sm244766lfl.287.2023.05.20.05.20.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 20 May 2023 05:20:11 -0700 (PDT) From: Konrad Dybcio Date: Sat, 20 May 2023 14:19:55 +0200 Subject: [PATCH v7 15/18] drm/msm/a6xx: Use "else if" in GPU speedbin rev matching MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20230223-topic-gmuwrapper-v7-15-ecc7aab83556@linaro.org> References: <20230223-topic-gmuwrapper-v7-0-ecc7aab83556@linaro.org> In-Reply-To: <20230223-topic-gmuwrapper-v7-0-ecc7aab83556@linaro.org> To: Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , David Airlie , Daniel Vetter , Rob Herring , Krzysztof Kozlowski , Bjorn Andersson , Konrad Dybcio , Akhil P Oommen Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Rob Clark , Marijn Suijten , Konrad Dybcio X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1684585186; l=1434; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=uKjhc80Jm6KagI3RgryxQkGd8nbEDN7qDXqkFWwfuNY=; b=djhvgV5FSYZPoGpc+9gnMJCNWzKm+II36WSU9XC/UIk/xq8RC0p2wAU2mUwY3Vx5XrKFYGjOO GKXLFoER77JDkAHm+5jSu5979Rk1nQ1Q46NaBTJeOgNaL2fQyvr11HC X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The GPU can only be one at a time. Turn a series of ifs into if + elseifs to save some CPU cycles. Reviewed-by: Dmitry Baryshkov Signed-off-by: Konrad Dybcio --- drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/ad= reno/a6xx_gpu.c index 9f296928c249..99bb3d16657a 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c @@ -2174,16 +2174,16 @@ static u32 fuse_to_supp_hw(struct device *dev, stru= ct adreno_rev rev, u32 fuse) if (adreno_cmp_rev(ADRENO_REV(6, 1, 8, ANY_ID), rev)) val =3D a618_get_speed_bin(fuse); =20 - if (adreno_cmp_rev(ADRENO_REV(6, 1, 9, ANY_ID), rev)) + else if (adreno_cmp_rev(ADRENO_REV(6, 1, 9, ANY_ID), rev)) val =3D a619_get_speed_bin(fuse); =20 - if (adreno_cmp_rev(ADRENO_REV(6, 3, 5, ANY_ID), rev)) + else if (adreno_cmp_rev(ADRENO_REV(6, 3, 5, ANY_ID), rev)) val =3D adreno_7c3_get_speed_bin(fuse); =20 - if (adreno_cmp_rev(ADRENO_REV(6, 4, 0, ANY_ID), rev)) + else if (adreno_cmp_rev(ADRENO_REV(6, 4, 0, ANY_ID), rev)) val =3D a640_get_speed_bin(fuse); =20 - if (adreno_cmp_rev(ADRENO_REV(6, 5, 0, ANY_ID), rev)) + else if (adreno_cmp_rev(ADRENO_REV(6, 5, 0, ANY_ID), rev)) val =3D a650_get_speed_bin(fuse); =20 if (val =3D=3D UINT_MAX) { --=20 2.40.1 From nobody Sun Feb 8 23:23:18 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 24802C7EE2A for ; Sat, 20 May 2023 12:21:45 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231800AbjETMVn (ORCPT ); Sat, 20 May 2023 08:21:43 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:51534 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231728AbjETMUx (ORCPT ); Sat, 20 May 2023 08:20:53 -0400 Received: from mail-lf1-x133.google.com (mail-lf1-x133.google.com [IPv6:2a00:1450:4864:20::133]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id D7C03171E for ; Sat, 20 May 2023 05:20:15 -0700 (PDT) Received: by mail-lf1-x133.google.com with SMTP id 2adb3069b0e04-4f3b337e842so1172043e87.3 for ; Sat, 20 May 2023 05:20:15 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1684585213; x=1687177213; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=FDj2Hlv3suy39fknqXu4NJ+7+v5OTPyVmso8foxImOg=; b=Xjz9zvLQVLnOeUjQCLequqvtDarudEsc3jW/KgsSG974+brwSqv3sMNfvaQTqJTpXv LvPGgtpXp+gaY1l2HIK53pxYZGQ55WYJ4pt8kI025oR8/oRMYN4Ai6CJcaB1AR0apfYa Ujgz6gQD4U2dLh2sx1vyYhe1Yq/ibDlI2CHhdWAhtN4hNgU6p90kFjbmgzGnMNEq7uD7 ofVOdMHyEkZXb9fqOW1etS38LlYRvspQF560ByTEwdShj/qdLs+BtlbAeeC1uqMgUiHf YrYahlmwdU/kf7CloHWgbMuGO3a7Fdlwd8a50h2JsEtccU5dWB5tKgzWKEBlAFUZHdNS mGrQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1684585213; x=1687177213; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=FDj2Hlv3suy39fknqXu4NJ+7+v5OTPyVmso8foxImOg=; b=a02/VTZPpVYXR843MtgdDuGwY/5EaOh/FZ7kU7yWtpdKe0Ddtkd6mInVkkeX+5q9km 4gQAUQPTnRKD0p8+rvRXakly3TVUJpvvQR5UMwe5/BGF4RBy1tSMEyOG8gk1Jq0a82uP 9riitSofzYFyCxxm2XdUcpU32x68HP5+yUCl0zUUcuBcll2ZcykXIUe1fXKl9tS3W8Gy VHjA3IRaTAmeXOrqH0NYhInvR1zQghFF5ykqt2UxTGKQNtraR2gwcyic2gyBnJcDhPWl bC/DJXWsdNq6F8vKa/bdl4nCkHUirUe4Gj5fMJodkvsTFcNNvOQzou5DSa5LvHJhKZMa NNSQ== X-Gm-Message-State: AC+VfDzLbr3nMVDzzvCy3JCk8EJb+kbyUjKG+MrG0Nq8gU80Zwr+CovP uaZQzycuG3lYYwREUcaSe8jSuQ== X-Google-Smtp-Source: ACHHUZ4BVlqbK6suLeB7mDyJvOak+x9mUV13fDe59Z2U44jdwjtjPlK2iNHUsUhMA3Gp24ItvSp4UA== X-Received: by 2002:ac2:44a3:0:b0:4f3:b49c:ffdd with SMTP id c3-20020ac244a3000000b004f3b49cffddmr633761lfm.52.1684585212937; Sat, 20 May 2023 05:20:12 -0700 (PDT) Received: from [192.168.1.101] (abxi58.neoplus.adsl.tpnet.pl. [83.9.2.58]) by smtp.gmail.com with ESMTPSA id y6-20020ac24466000000b004f37bd02a89sm244766lfl.287.2023.05.20.05.20.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 20 May 2023 05:20:12 -0700 (PDT) From: Konrad Dybcio Date: Sat, 20 May 2023 14:19:56 +0200 Subject: [PATCH v7 16/18] drm/msm/a6xx: Use adreno_is_aXYZ macros in speedbin matching MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20230223-topic-gmuwrapper-v7-16-ecc7aab83556@linaro.org> References: <20230223-topic-gmuwrapper-v7-0-ecc7aab83556@linaro.org> In-Reply-To: <20230223-topic-gmuwrapper-v7-0-ecc7aab83556@linaro.org> To: Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , David Airlie , Daniel Vetter , Rob Herring , Krzysztof Kozlowski , Bjorn Andersson , Konrad Dybcio , Akhil P Oommen Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Rob Clark , Marijn Suijten , Konrad Dybcio X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1684585186; l=4275; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=BAw+AXulufdWfQ7Do/vFFCENVdfYOHXil2y3DfYll6U=; b=J0mstrrKtTwDSEIz6MWE9BIeXAQLaOvyBFv2ogrxa92yW44Ou+95DFxoBwuXYISKK+GyvjLE5 n3Bd7AqdH2iAbp9tqCqlYiEZ6yAOakkxa+iDiUgIMoyKW6orao4Fp27 X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Before transitioning to using per-SoC and not per-Adreno speedbin fuse values (need another patchset to land elsewhere), a good improvement/stopgap solution is to use adreno_is_aXYZ macros in place of explicit revision matching. Do so to allow differentiating between A619 and A619_holi. Reviewed-by: Dmitry Baryshkov Signed-off-by: Konrad Dybcio --- drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 18 +++++++++--------- drivers/gpu/drm/msm/adreno/adreno_gpu.h | 14 ++++++++++++-- 2 files changed, 21 insertions(+), 11 deletions(-) diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/ad= reno/a6xx_gpu.c index 99bb3d16657a..5ad19978390c 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c @@ -2167,23 +2167,23 @@ static u32 adreno_7c3_get_speed_bin(u32 fuse) return UINT_MAX; } =20 -static u32 fuse_to_supp_hw(struct device *dev, struct adreno_rev rev, u32 = fuse) +static u32 fuse_to_supp_hw(struct device *dev, struct adreno_gpu *adreno_g= pu, u32 fuse) { u32 val =3D UINT_MAX; =20 - if (adreno_cmp_rev(ADRENO_REV(6, 1, 8, ANY_ID), rev)) + if (adreno_is_a618(adreno_gpu)) val =3D a618_get_speed_bin(fuse); =20 - else if (adreno_cmp_rev(ADRENO_REV(6, 1, 9, ANY_ID), rev)) + else if (adreno_is_a619(adreno_gpu)) val =3D a619_get_speed_bin(fuse); =20 - else if (adreno_cmp_rev(ADRENO_REV(6, 3, 5, ANY_ID), rev)) + else if (adreno_is_7c3(adreno_gpu)) val =3D adreno_7c3_get_speed_bin(fuse); =20 - else if (adreno_cmp_rev(ADRENO_REV(6, 4, 0, ANY_ID), rev)) + else if (adreno_is_a640(adreno_gpu)) val =3D a640_get_speed_bin(fuse); =20 - else if (adreno_cmp_rev(ADRENO_REV(6, 5, 0, ANY_ID), rev)) + else if (adreno_is_a650(adreno_gpu)) val =3D a650_get_speed_bin(fuse); =20 if (val =3D=3D UINT_MAX) { @@ -2196,7 +2196,7 @@ static u32 fuse_to_supp_hw(struct device *dev, struct= adreno_rev rev, u32 fuse) return (1 << val); } =20 -static int a6xx_set_supported_hw(struct device *dev, struct adreno_rev rev) +static int a6xx_set_supported_hw(struct device *dev, struct adreno_gpu *ad= reno_gpu) { u32 supp_hw; u32 speedbin; @@ -2215,7 +2215,7 @@ static int a6xx_set_supported_hw(struct device *dev, = struct adreno_rev rev) return ret; } =20 - supp_hw =3D fuse_to_supp_hw(dev, rev, speedbin); + supp_hw =3D fuse_to_supp_hw(dev, adreno_gpu, speedbin); =20 ret =3D devm_pm_opp_set_supported_hw(dev, &supp_hw, 1); if (ret) @@ -2334,7 +2334,7 @@ struct msm_gpu *a6xx_gpu_init(struct drm_device *dev) =20 a6xx_llc_slices_init(pdev, a6xx_gpu); =20 - ret =3D a6xx_set_supported_hw(&pdev->dev, config->rev); + ret =3D a6xx_set_supported_hw(&pdev->dev, adreno_gpu); if (ret) { a6xx_destroy(&(a6xx_gpu->base.base)); return ERR_PTR(ret); diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.h b/drivers/gpu/drm/msm/= adreno/adreno_gpu.h index 7a5d595d4b99..21513cec038f 100644 --- a/drivers/gpu/drm/msm/adreno/adreno_gpu.h +++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.h @@ -268,9 +268,9 @@ static inline int adreno_is_a630(struct adreno_gpu *gpu) return gpu->revn =3D=3D 630; } =20 -static inline int adreno_is_a640_family(struct adreno_gpu *gpu) +static inline int adreno_is_a640(struct adreno_gpu *gpu) { - return (gpu->revn =3D=3D 640) || (gpu->revn =3D=3D 680); + return gpu->revn =3D=3D 640; } =20 static inline int adreno_is_a650(struct adreno_gpu *gpu) @@ -289,6 +289,11 @@ static inline int adreno_is_a660(struct adreno_gpu *gp= u) return gpu->revn =3D=3D 660; } =20 +static inline int adreno_is_a680(struct adreno_gpu *gpu) +{ + return gpu->revn =3D=3D 680; +} + /* check for a615, a616, a618, a619 or any derivatives */ static inline int adreno_is_a615_family(struct adreno_gpu *gpu) { @@ -306,6 +311,11 @@ static inline int adreno_is_a650_family(struct adreno_= gpu *gpu) return gpu->revn =3D=3D 650 || gpu->revn =3D=3D 620 || adreno_is_a660_fam= ily(gpu); } =20 +static inline int adreno_is_a640_family(struct adreno_gpu *gpu) +{ + return adreno_is_a640(gpu) || adreno_is_a680(gpu); +} + u64 adreno_private_address_space_size(struct msm_gpu *gpu); int adreno_get_param(struct msm_gpu *gpu, struct msm_file_private *ctx, uint32_t param, uint64_t *value, uint32_t *len); --=20 2.40.1 From nobody Sun Feb 8 23:23:18 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6E1C9C77B7A for ; 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[83.9.2.58]) by smtp.gmail.com with ESMTPSA id y6-20020ac24466000000b004f37bd02a89sm244766lfl.287.2023.05.20.05.20.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 20 May 2023 05:20:14 -0700 (PDT) From: Konrad Dybcio Date: Sat, 20 May 2023 14:19:57 +0200 Subject: [PATCH v7 17/18] drm/msm/a6xx: Add A619_holi speedbin support MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20230223-topic-gmuwrapper-v7-17-ecc7aab83556@linaro.org> References: <20230223-topic-gmuwrapper-v7-0-ecc7aab83556@linaro.org> In-Reply-To: <20230223-topic-gmuwrapper-v7-0-ecc7aab83556@linaro.org> To: Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , David Airlie , Daniel Vetter , Rob Herring , Krzysztof Kozlowski , Bjorn Andersson , Konrad Dybcio , Akhil P Oommen Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Rob Clark , Marijn Suijten , Konrad Dybcio X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1684585186; l=2033; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=JE+me8wGwvbnigS+vGj1riDnfhLDy9pbL1Nubu9j+Dc=; b=dT0oolqAVMMfgO9v3OoI1L7wZfY6VcvoXmE+KZnvpMRRrSkLeeK/PGZdVcbjn4ZCPycmZ21nx xGdZfeBZUmFCKCLxETbmTMGf8f1a8qxk/0opUNcKMwsqX6hphWypB3w X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org A619_holi is implemented on at least two SoCs: SM4350 (holi) and SM6375 (blair). This is what seems to be a first occurrence of this happening, but it's easy to overcome by guarding the SoC-specific fuse values with of_machine_is_compatible(). Do just that to enable frequency limiting on these SoCs. Reviewed-by: Dmitry Baryshkov Signed-off-by: Konrad Dybcio --- drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 31 +++++++++++++++++++++++++++++++ 1 file changed, 31 insertions(+) diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/ad= reno/a6xx_gpu.c index 5ad19978390c..c07b25fc2bd9 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c @@ -2114,6 +2114,34 @@ static u32 a618_get_speed_bin(u32 fuse) return UINT_MAX; } =20 +static u32 a619_holi_get_speed_bin(u32 fuse) +{ + /* + * There are (at least) two SoCs implementing A619_holi: SM4350 (holi) + * and SM6375 (blair). Limit the fuse matching to the corresponding + * SoC to prevent bogus frequency setting (as improbable as it may be, + * given unexpected fuse values are.. unexpected! But still possible.) + */ + + if (fuse =3D=3D 0) + return 0; + + if (of_machine_is_compatible("qcom,sm4350")) { + if (fuse =3D=3D 138) + return 1; + else if (fuse =3D=3D 92) + return 2; + } else if (of_machine_is_compatible("qcom,sm6375")) { + if (fuse =3D=3D 190) + return 1; + else if (fuse =3D=3D 177) + return 2; + } else + pr_warn("Unknown SoC implementing A619_holi!\n"); + + return UINT_MAX; +} + static u32 a619_get_speed_bin(u32 fuse) { if (fuse =3D=3D 0) @@ -2174,6 +2202,9 @@ static u32 fuse_to_supp_hw(struct device *dev, struct= adreno_gpu *adreno_gpu, u3 if (adreno_is_a618(adreno_gpu)) val =3D a618_get_speed_bin(fuse); =20 + else if (adreno_is_a619_holi(adreno_gpu)) + val =3D a619_holi_get_speed_bin(fuse); + else if (adreno_is_a619(adreno_gpu)) val =3D a619_get_speed_bin(fuse); =20 --=20 2.40.1 From nobody Sun Feb 8 23:23:18 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id BB991C77B7A for ; Sat, 20 May 2023 12:21:51 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232057AbjETMVu (ORCPT ); Sat, 20 May 2023 08:21:50 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:51904 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231801AbjETMU7 (ORCPT ); Sat, 20 May 2023 08:20:59 -0400 Received: from mail-lf1-x130.google.com (mail-lf1-x130.google.com [IPv6:2a00:1450:4864:20::130]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id E6B221730 for ; Sat, 20 May 2023 05:20:20 -0700 (PDT) Received: by mail-lf1-x130.google.com with SMTP id 2adb3069b0e04-4f3b4ed6fdeso749584e87.3 for ; Sat, 20 May 2023 05:20:20 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1684585216; x=1687177216; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=6euEkRodrQgx7ZE9t7r7K+NeHv1LqldRFjOFTB8bWyY=; b=BmrH/ZJTnlOU8B8MsGcUTxSs3ldt6wbdkha5Pku8nW8wiesMbU9mNfyY7MrN4V2Gqr RLM9scxRukJ/ONiVl2FsY6eDoLKRgfHlIFHVnW3yGkZxHqsyzkcOxFzg8TIpGA3BT8c9 nXHtqqFpJohjbQNeLqbPPGwTBeK/TU/btYx1zkZFbakqExv6o0z5JGy6ZhPC3MkoQRIr CZsWcSPBsbGhnU8JpbytXaPNh2weDBplzjO1VgucrO8AcidNHtppBnIsBiW2L/gbckAN dcFefXS2aEZ6Kq53K1na7IRRmYLvYbZohlo99vP8mSpdLLltZHx6ugzO+AwL6Mk6CKg+ AN4w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1684585216; x=1687177216; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=6euEkRodrQgx7ZE9t7r7K+NeHv1LqldRFjOFTB8bWyY=; b=bro9HX5ZNt0UfE7bXsHh7hhKWqnVo64zK7vul55gcOxq1F1B6Ipkdwd22hL3wEpuao is8V4qwVmio8yyXlrvOsyOR3q9gSJSOsmcQCdEZBL9Tf2mLca0gNm2XsnNIOvmSgP+3U LU1JCy7cn+Vnq8e4hKpilSnUMnrvVPxKYQkYJuHhSQJOTlonl7x9DeBX7jJSkcbZrdJw k4ICj/SzNc1KaPwHyQpHVRpDzgHhvVg1rQ2M0dw0KswZrsDMSH0BNDKxpHlttrtbdmeM Z4uViQms6IX3N1cMuxYegowT2e0BSqaGCm3MYq1CF5W9KYpxVbA02TZCan9QpJD4eXbH EYRw== X-Gm-Message-State: AC+VfDy80M5u4FW7R1KZKi0xAQ0goyfh8IkqqTfRm/d2raIlH4qERxLa 8yvZemNL+8NDX0McsXsRPa4eSw== X-Google-Smtp-Source: ACHHUZ58TljU+iUDLDIpGnb1GNrV3kCrtVuNbUTxPr6r/DQkrOHnuSQRaoImSSkim8bcpU5KKyUiNg== X-Received: by 2002:ac2:539a:0:b0:4cc:96f8:f9c6 with SMTP id g26-20020ac2539a000000b004cc96f8f9c6mr1835216lfh.5.1684585216004; Sat, 20 May 2023 05:20:16 -0700 (PDT) Received: from [192.168.1.101] (abxi58.neoplus.adsl.tpnet.pl. [83.9.2.58]) by smtp.gmail.com with ESMTPSA id y6-20020ac24466000000b004f37bd02a89sm244766lfl.287.2023.05.20.05.20.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 20 May 2023 05:20:15 -0700 (PDT) From: Konrad Dybcio Date: Sat, 20 May 2023 14:19:58 +0200 Subject: [PATCH v7 18/18] drm/msm/a6xx: Add A610 speedbin support MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20230223-topic-gmuwrapper-v7-18-ecc7aab83556@linaro.org> References: <20230223-topic-gmuwrapper-v7-0-ecc7aab83556@linaro.org> In-Reply-To: <20230223-topic-gmuwrapper-v7-0-ecc7aab83556@linaro.org> To: Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , David Airlie , Daniel Vetter , Rob Herring , Krzysztof Kozlowski , Bjorn Andersson , Konrad Dybcio , Akhil P Oommen Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Rob Clark , Marijn Suijten , Konrad Dybcio X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1684585186; l=1852; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=aYEnG9+HCzURuVCpcLpZTVlrArU+CPMAgc+RtQYPTAw=; b=cBGb71GEz6m+55DZbw5+CIlpa9bA2JR7ff/H/b1bxB27zpReX2GOg7AWcYOzBnWEkZtbP6mJc HaVYS9xm5/JBf1ihgp+IOvYeg1spOGFEwJmV78VNSn9B2Aj+MtEE37L X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org A610 is implemented on at least three SoCs: SM6115 (bengal), SM6125 (trinket) and SM6225 (khaje). Trinket does not support speed binning (only a single SKU exists) and we don't yet support khaje upstream. Hence, add a fuse mapping table for bengal to allow for per-chip frequency limiting. Reviewed-by: Dmitry Baryshkov Signed-off-by: Konrad Dybcio --- drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 27 +++++++++++++++++++++++++++ 1 file changed, 27 insertions(+) diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/ad= reno/a6xx_gpu.c index c07b25fc2bd9..d004458ca783 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c @@ -2102,6 +2102,30 @@ static bool a6xx_progress(struct msm_gpu *gpu, struc= t msm_ringbuffer *ring) return progress; } =20 +static u32 a610_get_speed_bin(u32 fuse) +{ + /* + * There are (at least) three SoCs implementing A610: SM6125 (trinket), + * SM6115 (bengal) and SM6225 (khaje). Trinket does not have speedbinning, + * as only a single SKU exists and we don't support khaje upstream yet. + * Hence, this matching table is only valid for bengal and can be easily + * expanded if need be. + */ + + if (fuse =3D=3D 0) + return 0; + else if (fuse =3D=3D 206) + return 1; + else if (fuse =3D=3D 200) + return 2; + else if (fuse =3D=3D 157) + return 3; + else if (fuse =3D=3D 127) + return 4; + + return UINT_MAX; +} + static u32 a618_get_speed_bin(u32 fuse) { if (fuse =3D=3D 0) @@ -2199,6 +2223,9 @@ static u32 fuse_to_supp_hw(struct device *dev, struct= adreno_gpu *adreno_gpu, u3 { u32 val =3D UINT_MAX; =20 + if (adreno_is_a610(adreno_gpu)) + val =3D a610_get_speed_bin(fuse); + if (adreno_is_a618(adreno_gpu)) val =3D a618_get_speed_bin(fuse); =20 --=20 2.40.1