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[83.9.3.225]) by smtp.gmail.com with ESMTPSA id g26-20020ac2539a000000b004dda80cabf0sm127241lfh.172.2023.03.30.16.25.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 30 Mar 2023 16:25:43 -0700 (PDT) From: Konrad Dybcio Date: Fri, 31 Mar 2023 01:25:29 +0200 Subject: [PATCH v5 15/15] drm/msm/a6xx: Add A610 speedbin support MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20230223-topic-gmuwrapper-v5-15-bf774b9a902a@linaro.org> References: <20230223-topic-gmuwrapper-v5-0-bf774b9a902a@linaro.org> In-Reply-To: <20230223-topic-gmuwrapper-v5-0-bf774b9a902a@linaro.org> To: Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , David Airlie , Daniel Vetter , Rob Herring , Krzysztof Kozlowski , Bjorn Andersson , Konrad Dybcio , Akhil P Oommen Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Rob Clark , Marijn Suijten , Konrad Dybcio X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1680218720; l=1852; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=sRjMSX3RSLjg5O+bbZnBcjOb5P4ZXSSVfgLMBDfv6/0=; b=2byAdZ0K4ZJknmJ/po2ONEXUn7MAt5HV2jkFIX+85s9yPzd0JQUgigp/xUAsBjXyTePMMNqdtmwy 6QK2s1SeAI6IPLE36ITrYG7f2atB6Yx8W5XnNuZs0n2jYAqiskVp X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org A610 is implemented on at least three SoCs: SM6115 (bengal), SM6125 (trinket) and SM6225 (khaje). Trinket does not support speed binning (only a single SKU exists) and we don't yet support khaje upstream. Hence, add a fuse mapping table for bengal to allow for per-chip frequency limiting. Reviewed-by: Dmitry Baryshkov Signed-off-by: Konrad Dybcio --- drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 27 +++++++++++++++++++++++++++ 1 file changed, 27 insertions(+) diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/ad= reno/a6xx_gpu.c index c61b1c4090c5..7662104c740f 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c @@ -2153,6 +2153,30 @@ static bool a6xx_progress(struct msm_gpu *gpu, struc= t msm_ringbuffer *ring) return progress; } =20 +static u32 a610_get_speed_bin(u32 fuse) +{ + /* + * There are (at least) three SoCs implementing A610: SM6125 (trinket), + * SM6115 (bengal) and SM6225 (khaje). Trinket does not have speedbinning, + * as only a single SKU exists and we don't support khaje upstream yet. + * Hence, this matching table is only valid for bengal and can be easily + * expanded if need be. + */ + + if (fuse =3D=3D 0) + return 0; + else if (fuse =3D=3D 206) + return 1; + else if (fuse =3D=3D 200) + return 2; + else if (fuse =3D=3D 157) + return 3; + else if (fuse =3D=3D 127) + return 4; + + return UINT_MAX; +} + static u32 a618_get_speed_bin(u32 fuse) { if (fuse =3D=3D 0) @@ -2249,6 +2273,9 @@ static u32 fuse_to_supp_hw(struct device *dev, struct= adreno_gpu *adreno_gpu, u3 { u32 val =3D UINT_MAX; =20 + if (adreno_is_a610(adreno_gpu)) + val =3D a610_get_speed_bin(fuse); + if (adreno_is_a618(adreno_gpu)) val =3D a618_get_speed_bin(fuse); =20 --=20 2.40.0