From nobody Wed Feb 11 13:06:20 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 34625C6FD1D for ; Tue, 14 Mar 2023 15:28:50 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231234AbjCNP2s (ORCPT ); Tue, 14 Mar 2023 11:28:48 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:57392 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231126AbjCNP2o (ORCPT ); Tue, 14 Mar 2023 11:28:44 -0400 Received: from mail-lj1-x22e.google.com (mail-lj1-x22e.google.com [IPv6:2a00:1450:4864:20::22e]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id B616743467 for ; Tue, 14 Mar 2023 08:28:41 -0700 (PDT) Received: by mail-lj1-x22e.google.com with SMTP id t14so16423502ljd.5 for ; Tue, 14 Mar 2023 08:28:41 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1678807720; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=dDrs6JyeTYzM6UbBJjwqEiLM0mM7HZ/Cu05l6aEARFA=; b=IFE6Gu3pkatgASwbx1ImpERuqNfGoEv4bKaRQZJgSsFYmX9pyq789ui74anr0GCEgf 2xhhKtZyoTkYjXzPauAL1Zp41IK+Vpjlwq+hoO13s91dFAMtE6VgaJnabahi+PpOaeQo 7cDgmExTSrb/GiJspQc4v8qgRrsmpmSSEM7cUYx38aDmKcw+l1lyUJ+yGQkPUySaOkpL 1jT0ETnMz6lohpMpRS3SwQcgxd/g2g4M6hw4mQ2lAJYlCijRKOLW0Y5X40UVcfpE3jPE 885KfrBnSHaQMS1LZzaG2dZVEoQFavz1LBj4jqiCpXSqIda3x3QRT0E1SgBQ7WHVOlY9 cTAA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1678807720; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=dDrs6JyeTYzM6UbBJjwqEiLM0mM7HZ/Cu05l6aEARFA=; b=zq7o/B/JY9UfBtW2YlLEUqRNg/ib9BvgYlcConxAcjFUqg+M9HUmZM6JU71xbuD3Te lEGbn6sICekqc2cwC2TOAIw+gMH/zUIY0yWNL2LzMyDAXmILX9wSUQTTgnpJIUIblz4S GHkU4wo4KrLjMgVWEPxcgcZTyRV59R0DiUwbRqWh5J1NjeYi2o+D3EgFuUPKZXLNY24e uD5Q/u6i/FWPaUxg2G0qidHMlDA6QLFhKYbnusJn70ob2lI202/dyTRTAtCx+fjWwP1s rjSDhyfey6CgiG8hM7eZTLoc/VYgDC6IjNxxOvIEdCYaQKNVlFGT1M1ofqVAPq4ADUkD 4ixg== X-Gm-Message-State: AO0yUKVLSqHkPI91EL36jQP2Gjcw3YM83fRDXEDWUhl8u77MA7Rkftay R/MUneNPIysy6y0+Zg0+G9YyoQ== X-Google-Smtp-Source: AK7set+AKW5h3+gpYUWs5M8YeHUiHDyWaDoRGbpKtAv13E6yGkGt34J83LUQNCU+EhNDQZ0o+KzEBA== X-Received: by 2002:a2e:83c6:0:b0:293:5360:162b with SMTP id s6-20020a2e83c6000000b002935360162bmr4084469ljh.11.1678807719958; Tue, 14 Mar 2023 08:28:39 -0700 (PDT) Received: from [192.168.1.101] (abyj16.neoplus.adsl.tpnet.pl. [83.9.29.16]) by smtp.gmail.com with ESMTPSA id 27-20020a2e165b000000b002986a977bf2sm491529ljw.90.2023.03.14.08.28.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 14 Mar 2023 08:28:39 -0700 (PDT) From: Konrad Dybcio Date: Tue, 14 Mar 2023 16:28:32 +0100 Subject: [PATCH v4 01/14] dt-bindings: display/msm: gpu: Document GMU wrapper-equipped A6xx MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20230223-topic-gmuwrapper-v4-1-e987eb79d03f@linaro.org> References: <20230223-topic-gmuwrapper-v4-0-e987eb79d03f@linaro.org> In-Reply-To: <20230223-topic-gmuwrapper-v4-0-e987eb79d03f@linaro.org> To: Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , David Airlie , Daniel Vetter , Rob Herring , Krzysztof Kozlowski , Bjorn Andersson , Konrad Dybcio , Akhil P Oommen Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Rob Clark , Marijn Suijten , Konrad Dybcio X-Mailer: b4 0.12.1 X-Developer-Signature: v=1; a=ed25519-sha256; t=1678807716; l=3204; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=6sAUPUwHP7+WUPx0qnkXu1yRwFCLU2UOzBhHFKkRGTM=; b=mV+9zzv7CDxkMqctTdkZFuDUkQFR5lB3OtJchHXfOYHhrrpWJ/oHSNLECv+KrnMciFrDa+s7/Rx9 dsByIHe1CGn7Aexc8isUndJ0jhglIt6f9uZXVUBWv3VqK6RfeBKH X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The "GMU Wrapper" is Qualcomm's name for "let's treat the GPU blocks we'd normally assign to the GMU as if they were a part of the GMU, even though they are not". It's a (good) software representation of the GMU_CX and GMU_GX register spaces within the GPUSS that helps us programatically treat these de-facto GMU-less parts in a way that's very similar to their GMU-equipped cousins, massively saving up on code duplication. The "wrapper" register space was specifically designed to mimic the layout of a real GMU, though it rather obviously does not have the M3 core et al. GMU wrapper-equipped A6xx GPUs require clocks and clock-names to be specified under the GPU node, just like their older cousins. Account for that. Signed-off-by: Konrad Dybcio --- .../devicetree/bindings/display/msm/gpu.yaml | 57 ++++++++++++++++++= ---- 1 file changed, 48 insertions(+), 9 deletions(-) diff --git a/Documentation/devicetree/bindings/display/msm/gpu.yaml b/Docum= entation/devicetree/bindings/display/msm/gpu.yaml index d4191cca71fb..ac1a9bce2042 100644 --- a/Documentation/devicetree/bindings/display/msm/gpu.yaml +++ b/Documentation/devicetree/bindings/display/msm/gpu.yaml @@ -36,10 +36,7 @@ properties: =20 reg-names: minItems: 1 - items: - - const: kgsl_3d0_reg_memory - - const: cx_mem - - const: cx_dbgc + maxItems: 3 =20 interrupts: maxItems: 1 @@ -157,16 +154,58 @@ allOf: required: - clocks - clock-names + - if: properties: compatible: contains: - pattern: '^qcom,adreno-6[0-9][0-9]\.[0-9]$' - - then: # Since Adreno 6xx series clocks should be defined in GMU + enum: + - qcom,adreno-610.0 + - qcom,adreno-619.1 + then: properties: - clocks: false - clock-names: false + clock-names: + items: + - const: core + description: GPU Core clock + - const: iface + description: GPU Interface clock + - const: mem_iface + description: GPU Memory Interface clock + - const: alt_mem_iface + description: GPU Alternative Memory Interface clock + - const: gmu + description: CX GMU clock + - const: xo + description: GPUCC clocksource clock + + reg-names: + minItems: 1 + items: + - const: kgsl_3d0_reg_memory + - const: cx_dbgc + + required: + - clocks + - clock-names + else: + if: + properties: + compatible: + contains: + pattern: '^qcom,adreno-6[0-9][0-9]\.[0-9]$' + + then: # Starting with A6xx, the clocks are usually defined in the GM= U node + properties: + clocks: false + clock-names: false + + reg-names: + minItems: 1 + items: + - const: kgsl_3d0_reg_memory + - const: cx_mem + - const: cx_dbgc =20 examples: - | --=20 2.39.2 From nobody Wed Feb 11 13:06:20 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 98A6AC7618E for ; Tue, 14 Mar 2023 15:28:58 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231639AbjCNP25 (ORCPT ); Tue, 14 Mar 2023 11:28:57 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:57392 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230521AbjCNP2s (ORCPT ); Tue, 14 Mar 2023 11:28:48 -0400 Received: from mail-lj1-x22c.google.com (mail-lj1-x22c.google.com [IPv6:2a00:1450:4864:20::22c]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 808E53801F for ; Tue, 14 Mar 2023 08:28:43 -0700 (PDT) Received: by mail-lj1-x22c.google.com with SMTP id a32so16412421ljr.9 for ; Tue, 14 Mar 2023 08:28:43 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1678807721; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=FfpC0lXYq1ll6nbzoGKkSBMv0WmddnDy3ZKS7f0bm/s=; b=nuXeOgG35nLhpQRRtNMHfnLyZD6r104D193hTDJ6SUD6UTROZX49ztDyCxB5b/yXQL Rqb9pP3md5/C8Pu3IazHspSOZQQVt6W22h0N8rTzTPk8yL945NI0eDpXxvOZh69Nnhfs TRklrmiV3rQZHKy6dGYTuwmTbUntIN6lfgzEuNuJNcgyR/Xieck5pWDmV7+LPzgoZZt4 UDwFts4TWGaGsk6Xz/9N4rVmOXQ9JM27IvkiXSBEjZtHVhlPpIM1T8jxGBF9WQoJz3IU wCS5jes6BWXkCB+bOFcYDWwwKfFxpQGAxDdRge+5gd4JroLTe6+UmvpmXAUOXiD4DVwu vSqQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1678807721; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=FfpC0lXYq1ll6nbzoGKkSBMv0WmddnDy3ZKS7f0bm/s=; b=wp+RWFnZQlja8Yz9bGpxfpE4gGAWf9Y4k2JiMia/xQ/kdMoPLf6rR76fVGDrEhrLlL 4gcUkhkEIyjSzKiQBBTCZz11n1BgUzamrvolrYtuBKOh83dc98dp058v30PoDFnGPlS1 w5nER6MKbdTB4XPRg6MIvA/UGIb9R873N5Op2bETilwci8KWjblhPw88ZHqlhhrMjOyJ +DaVSUvxM85eaVYLlx2gB+jpeH2JC/pn9DFwq5yuUdWx2vR1PvWs5WK8ajUcg0jdbwsX g52mCA8dHn367UjoXnzs/lmCkvztvt/ZrV89Y+0WEF3WmfZzOq1vwsDRWDIofg3m2V1m Mr0A== X-Gm-Message-State: AO0yUKXkpRl3yZSIc/DOt5xkbBPfks5lpMqqqBG8CdDu0/EaQCMsaksa XQYZD1le+85x2k5DU9IVPA9Mpw== X-Google-Smtp-Source: AK7set/WntUhZuSNUQTrPjCTj4ukX0xl87beorxjM9H0yP4/SY9PWs7JVDdulaM8wwYD1Se+d2giaQ== X-Received: by 2002:a2e:93c6:0:b0:295:a33f:5349 with SMTP id p6-20020a2e93c6000000b00295a33f5349mr11157007ljh.26.1678807721760; Tue, 14 Mar 2023 08:28:41 -0700 (PDT) Received: from [192.168.1.101] (abyj16.neoplus.adsl.tpnet.pl. [83.9.29.16]) by smtp.gmail.com with ESMTPSA id 27-20020a2e165b000000b002986a977bf2sm491529ljw.90.2023.03.14.08.28.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 14 Mar 2023 08:28:41 -0700 (PDT) From: Konrad Dybcio Date: Tue, 14 Mar 2023 16:28:33 +0100 Subject: [PATCH v4 02/14] dt-bindings: display/msm/gmu: Add GMU wrapper MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20230223-topic-gmuwrapper-v4-2-e987eb79d03f@linaro.org> References: <20230223-topic-gmuwrapper-v4-0-e987eb79d03f@linaro.org> In-Reply-To: <20230223-topic-gmuwrapper-v4-0-e987eb79d03f@linaro.org> To: Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , David Airlie , Daniel Vetter , Rob Herring , Krzysztof Kozlowski , Bjorn Andersson , Konrad Dybcio , Akhil P Oommen Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Rob Clark , Marijn Suijten , Konrad Dybcio X-Mailer: b4 0.12.1 X-Developer-Signature: v=1; a=ed25519-sha256; t=1678807716; l=3283; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=UT3xDmXTHRxoAqg/suyw+w4CBgyq4mbs1kv24/YUgS4=; b=Yj3XYeUYs1m8xSmfDaz+G1H2jht5+3yszWDs4/x/w6AR5a0OpS9HKzKChzuLlKQk2FjWMjVL954/ cJyNHPETCk3lA8OCiyigoRSsoyRRc0ziAMQ3HyyxyrTvcopQdhtW X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The "GMU Wrapper" is Qualcomm's name for "let's treat the GPU blocks we'd normally assign to the GMU as if they were a part of the GMU, even though they are not". It's a (good) software representation of the GMU_CX and GMU_GX register spaces within the GPUSS that helps us programatically treat these de-facto GMU-less parts in a way that's very similar to their GMU-equipped cousins, massively saving up on code duplication. The "wrapper" register space was specifically designed to mimic the layout of a real GMU, though it rather obviously does not have the M3 core et al. To sum it all up, the GMU wrapper is essentially a register space within the GPU, which Linux sees as a dumbed-down regular GMU: there's no clocks, interrupts, multiple reg spaces, iommus and OPP. Document it. Signed-off-by: Konrad Dybcio Reviewed-by: Krzysztof Kozlowski --- .../devicetree/bindings/display/msm/gmu.yaml | 49 ++++++++++++++++--= ---- 1 file changed, 37 insertions(+), 12 deletions(-) diff --git a/Documentation/devicetree/bindings/display/msm/gmu.yaml b/Docum= entation/devicetree/bindings/display/msm/gmu.yaml index ab14e81cb050..021373e686e1 100644 --- a/Documentation/devicetree/bindings/display/msm/gmu.yaml +++ b/Documentation/devicetree/bindings/display/msm/gmu.yaml @@ -19,16 +19,18 @@ description: | =20 properties: compatible: - items: - - pattern: '^qcom,adreno-gmu-6[0-9][0-9]\.[0-9]$' - - const: qcom,adreno-gmu + oneOf: + - items: + - pattern: '^qcom,adreno-gmu-6[0-9][0-9]\.[0-9]$' + - const: qcom,adreno-gmu + - const: qcom,adreno-gmu-wrapper =20 reg: - minItems: 3 + minItems: 1 maxItems: 4 =20 reg-names: - minItems: 3 + minItems: 1 maxItems: 4 =20 clocks: @@ -44,7 +46,6 @@ properties: - description: GMU HFI interrupt - description: GMU interrupt =20 - interrupt-names: items: - const: hfi @@ -72,14 +73,8 @@ required: - compatible - reg - reg-names - - clocks - - clock-names - - interrupts - - interrupt-names - power-domains - power-domain-names - - iommus - - operating-points-v2 =20 additionalProperties: false =20 @@ -216,6 +211,27 @@ allOf: - const: cxo - const: axi - const: memnoc + - if: + properties: + compatible: + contains: + const: qcom,adreno-gmu-wrapper + then: + properties: + reg: + items: + - description: GMU wrapper register space + reg-names: + items: + - const: gmu + else: + required: + - clocks + - clock-names + - interrupts + - interrupt-names + - iommus + - operating-points-v2 =20 examples: - | @@ -249,3 +265,12 @@ examples: iommus =3D <&adreno_smmu 5>; operating-points-v2 =3D <&gmu_opp_table>; }; + + gmu_wrapper: gmu@596a000 { + compatible =3D "qcom,adreno-gmu-wrapper"; + reg =3D <0x0596a000 0x30000>; + reg-names =3D "gmu"; + power-domains =3D <&gpucc GPU_CX_GDSC>, + <&gpucc GPU_GX_GDSC>; + power-domain-names =3D "cx", "gx"; + }; --=20 2.39.2 From nobody Wed Feb 11 13:06:20 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id C4770C7618A for ; Tue, 14 Mar 2023 15:29:01 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231713AbjCNP27 (ORCPT ); Tue, 14 Mar 2023 11:28:59 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:58052 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231240AbjCNP2s (ORCPT ); Tue, 14 Mar 2023 11:28:48 -0400 Received: from mail-lj1-x232.google.com (mail-lj1-x232.google.com [IPv6:2a00:1450:4864:20::232]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 165773B222 for ; Tue, 14 Mar 2023 08:28:45 -0700 (PDT) Received: by mail-lj1-x232.google.com with SMTP id i20so16399622lja.11 for ; Tue, 14 Mar 2023 08:28:44 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1678807723; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=RO255zxGak2RBrs2vsC3RJabBdwukiR9Uly/c7vQ0CM=; b=XMdGMEyjB8dFRiheqepFSBLS1yBnSgwVDtYG0k25vKhV2B+dlbK+4rqhOZR/f5eQUf spakIlGLGNtFd5/rU+56vYuo0KrIzAVAuZfTqyDlOOsZ94AlFUIgu98hLV8FaJ3dE4Zk 9yqi8FZwAgT80An6knPij1UpD7EYrELJs1ohiVkGfnSHcjC/XD+fqxOtqlcRm9nA5K04 wNeALyWefwCNWEWqAQrUBfJVbC4jXMB3cfLAAKdrnJ2L9mKHd1rclALn8mQ/wlEvKdRm EM/HM7vX91H/yLn2pdaaUSOBQMAou+HKElwt5VEFWDomjsDkdpj47nS849HBUCJSnmnU 95Iw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1678807723; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=RO255zxGak2RBrs2vsC3RJabBdwukiR9Uly/c7vQ0CM=; b=4VIeSbJEZEW5WCNUfk12gNZNZiMuz7/fs966EzszWrinofT9iYcS4lgROWLv9QCcoX k3pfK9VoG0LNVcqMZSxeoAmnAkOWVuanZqr1suYX2cRwHsxUKi9KFlB8E8ILaWdX3R9y MohA6/PyTQdqGyJ5bsOuK+PdEamn0fBSvtagWKsRSrpIo972Jg6ajWj/nXrYUM3pr9yW ngNgC/guT0l0u8iTIoOe9IRSDo7+4/AhjapTMkSSPP62JOEoBMdQWh+V6L2m4BUtCUMP D4snWCdPuCtEgfAI8aIyHe26iu8+rJDFQOSJ8xCCf3dhG7Z9G6xOw4y50OUdKQsPoAsR BzPA== X-Gm-Message-State: AO0yUKWmiqwqnTfjYIXcUDqM4jYwx1aiCP2qffTDmDVa7GnqOEzmJ7sX AbKCaF/5DSbdGBvrvM1AMXm+sQ== X-Google-Smtp-Source: AK7set8z7+8/svx5o/nFtcPzqW1CxxLQ3CLdXsRgxJg10+9EiutFeGRPRVlrw3NXYINxFmwBl3CyYw== X-Received: by 2002:a2e:9946:0:b0:295:a8cc:f15a with SMTP id r6-20020a2e9946000000b00295a8ccf15amr10470723ljj.29.1678807723306; Tue, 14 Mar 2023 08:28:43 -0700 (PDT) Received: from [192.168.1.101] (abyj16.neoplus.adsl.tpnet.pl. [83.9.29.16]) by smtp.gmail.com with ESMTPSA id 27-20020a2e165b000000b002986a977bf2sm491529ljw.90.2023.03.14.08.28.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 14 Mar 2023 08:28:42 -0700 (PDT) From: Konrad Dybcio Date: Tue, 14 Mar 2023 16:28:34 +0100 Subject: [PATCH v4 03/14] drm/msm/a6xx: Remove static keyword from sptprac en/disable functions MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20230223-topic-gmuwrapper-v4-3-e987eb79d03f@linaro.org> References: <20230223-topic-gmuwrapper-v4-0-e987eb79d03f@linaro.org> In-Reply-To: <20230223-topic-gmuwrapper-v4-0-e987eb79d03f@linaro.org> To: Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , David Airlie , Daniel Vetter , Rob Herring , Krzysztof Kozlowski , Bjorn Andersson , Konrad Dybcio , Akhil P Oommen Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Rob Clark , Marijn Suijten , Konrad Dybcio X-Mailer: b4 0.12.1 X-Developer-Signature: v=1; a=ed25519-sha256; t=1678807716; l=1711; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=7a+b5UGAg3EywTm3Uz73qntLItaZJqfx37WBN0HlPAs=; b=nGHMAsiP7jw60z7u0RxD1MZvX6xpxMT/U4RR1/OORWCr6Gmp5pj7vlJSu7Jgx9C5U0bGHsMdGnx7 8M/TtP8aCXwuBmw8476mylKRj9+t1k+V1KQ2ahR0JZW3s8YcaOQu X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org These two will be reused by at least A619_holi in the non-gmu paths. Turn them non-static them to make it possible. Reviewed-by: Dmitry Baryshkov Signed-off-by: Konrad Dybcio --- drivers/gpu/drm/msm/adreno/a6xx_gmu.c | 4 ++-- drivers/gpu/drm/msm/adreno/a6xx_gmu.h | 2 ++ 2 files changed, 4 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c b/drivers/gpu/drm/msm/ad= reno/a6xx_gmu.c index 7f5bc73b2040..229a54ec82b4 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_gmu.c @@ -354,7 +354,7 @@ void a6xx_gmu_clear_oob(struct a6xx_gmu *gmu, enum a6xx= _gmu_oob_state state) } =20 /* Enable CPU control of SPTP power power collapse */ -static int a6xx_sptprac_enable(struct a6xx_gmu *gmu) +int a6xx_sptprac_enable(struct a6xx_gmu *gmu) { int ret; u32 val; @@ -376,7 +376,7 @@ static int a6xx_sptprac_enable(struct a6xx_gmu *gmu) } =20 /* Disable CPU control of SPTP power power collapse */ -static void a6xx_sptprac_disable(struct a6xx_gmu *gmu) +void a6xx_sptprac_disable(struct a6xx_gmu *gmu) { u32 val; int ret; diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gmu.h b/drivers/gpu/drm/msm/ad= reno/a6xx_gmu.h index e034935b3986..ec28abdd327b 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gmu.h +++ b/drivers/gpu/drm/msm/adreno/a6xx_gmu.h @@ -186,5 +186,7 @@ int a6xx_hfi_set_freq(struct a6xx_gmu *gmu, int index); =20 bool a6xx_gmu_gx_is_on(struct a6xx_gmu *gmu); bool a6xx_gmu_sptprac_is_on(struct a6xx_gmu *gmu); +void a6xx_sptprac_disable(struct a6xx_gmu *gmu); +int a6xx_sptprac_enable(struct a6xx_gmu *gmu); =20 #endif --=20 2.39.2 From nobody Wed Feb 11 13:06:20 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 82C89C7618D for ; Tue, 14 Mar 2023 15:29:04 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230103AbjCNP3D (ORCPT ); Tue, 14 Mar 2023 11:29:03 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:58428 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231329AbjCNP2y (ORCPT ); Tue, 14 Mar 2023 11:28:54 -0400 Received: from mail-lj1-x22a.google.com (mail-lj1-x22a.google.com [IPv6:2a00:1450:4864:20::22a]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 8FA3E3B3DB for ; Tue, 14 Mar 2023 08:28:45 -0700 (PDT) Received: by mail-lj1-x22a.google.com with SMTP id h3so16400061lja.12 for ; Tue, 14 Mar 2023 08:28:45 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1678807725; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=hsp+OP49dyvTA0hg06hKxLnq+WOs2dGZ48Sal52G9bk=; b=CGXtFAlrCUIohL3loQwAGHDCaABKaw299PVDfZQOpH39MnvHu5Y6d5mR6o5KNPW/RH sbdHMKHhmPBHZOXInm/6RCNkxYyERcbYtFn6fYVtuOotl7+ML6oYAyCC445gHTGsnED8 KmdxxshSquUUC31++k5Mu3svyEVywEpoJq/1IqnEzROsO+31zLxSHqRG5ohDR2uiFbvr q/v+ajfSH9Oa0RRLqX5hVneyoDMXGhqb2Nw02L6wdfplCLcr53IkxkXyhBKmFeEGsTir ODkFSKcOJZYTaxB8Fg5ppXhkTFlHw0IAbg2ORzqi8mV3EjxdqYOBjgpwGrlkuRl30VPc adVA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1678807725; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=hsp+OP49dyvTA0hg06hKxLnq+WOs2dGZ48Sal52G9bk=; b=EiPk/mQN1BLm8Z+++nTxLc9XUM0ohNhKCu+H04iB53ty7yABxddH25CLltEiJkFmjs fQ+cZE3k34gq5goE7c1sM/4xRRrLjxHn8EM3ThZHXqrophf4hB6AfZpfTMjp2ZjE/GqK cWQTeNm3awzENVIS/SIkXMRLkyfXrs9xZZELVRI4ZIU0m/ZS0piAn2Lmm8JLBKZhtW0/ gNSFtcUvVDscGMOMmbl5JDxTQMF+64r10Dr0rQmm3CwrcmmOlw2n7Tq0yXYn+izyPo2p FAxP5GYiP8nYBi+5z1x7gmCIduAT+3EepKBE4EbuUphRiMqZNcPbA34vIX4ZUIhLgPV4 UKrQ== X-Gm-Message-State: AO0yUKWLthB5x2OKo6T9asFL6kVqW7YVQ9TB7BqlgS8+Mbc+UkgMAbv0 0o7bVBmC2g6KFTnByzXe40FL9w== X-Google-Smtp-Source: AK7set8UwjTvNY569Dzv+O3Rg1WzvAvqAYQ7+gA21ZsnZjBYnf6lVmfdrWCYg6a7PBog4S+VVa3xPg== X-Received: by 2002:a2e:131a:0:b0:295:93eb:1c01 with SMTP id 26-20020a2e131a000000b0029593eb1c01mr11806514ljt.25.1678807725141; Tue, 14 Mar 2023 08:28:45 -0700 (PDT) Received: from [192.168.1.101] (abyj16.neoplus.adsl.tpnet.pl. [83.9.29.16]) by smtp.gmail.com with ESMTPSA id 27-20020a2e165b000000b002986a977bf2sm491529ljw.90.2023.03.14.08.28.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 14 Mar 2023 08:28:44 -0700 (PDT) From: Konrad Dybcio Date: Tue, 14 Mar 2023 16:28:35 +0100 Subject: [PATCH v4 04/14] drm/msm/a6xx: Extend and explain UBWC config MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20230223-topic-gmuwrapper-v4-4-e987eb79d03f@linaro.org> References: <20230223-topic-gmuwrapper-v4-0-e987eb79d03f@linaro.org> In-Reply-To: <20230223-topic-gmuwrapper-v4-0-e987eb79d03f@linaro.org> To: Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , David Airlie , Daniel Vetter , Rob Herring , Krzysztof Kozlowski , Bjorn Andersson , Konrad Dybcio , Akhil P Oommen Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Rob Clark , Marijn Suijten , Konrad Dybcio X-Mailer: b4 0.12.1 X-Developer-Signature: v=1; a=ed25519-sha256; t=1678807716; l=2979; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=jfJopFwWQyGceVNOEMOJgd5qDKEUsswtNczspv0fE70=; b=GTW6adG8HrXjwT99h/qJn2ktz6+O907jU1DOFTqH811t7emgC9lzJjXGPyflNTe1eTdiM0XxIn/g 1PeE0h08DwJHYz2iaT40X2IGJnlgctdBEFToirOL7OamNhxVZhKl X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Rename lower_bit to hbb_lo and explain what it signifies. Add explanations (wherever possible to other tunables). Port setting min_access_length, ubwc_mode and hbb_hi from downstream. Signed-off-by: Konrad Dybcio Reviewed-by: Rob Clark --- drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 39 +++++++++++++++++++++++++++----= ---- 1 file changed, 30 insertions(+), 9 deletions(-) diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/ad= reno/a6xx_gpu.c index a849db8252f2..2f55dac52833 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c @@ -786,10 +786,25 @@ static void a6xx_set_cp_protect(struct msm_gpu *gpu) static void a6xx_set_ubwc_config(struct msm_gpu *gpu) { struct adreno_gpu *adreno_gpu =3D to_adreno_gpu(gpu); - u32 lower_bit =3D 2; - u32 amsbc =3D 0; + /* Unknown, introduced with A650 family, related to UBWC mode/ver 4 */ u32 rgb565_predicator =3D 0; + /* Unknown, introduced with A650 family */ u32 uavflagprd_inv =3D 0; + /* Whether the minimum access length is 64 bits */ + u32 min_acc_len =3D 0; + /* Entirely magic, per-GPU-gen value */ + u32 ubwc_mode =3D 0; + /* + * The Highest Bank Bit value represents the bit of the highest DDR bank. + * We then subtract 13 from it (13 is the minimum value allowed by hw) and + * write the lowest two bits of the remaining value as hbb_lo and the + * one above it as hbb_hi to the hardware. This should ideally use DRAM + * type detection. + */ + u32 hbb_hi =3D 0; + u32 hbb_lo =3D 2; + /* Unknown, introduced with A640/680 */ + u32 amsbc =3D 0; =20 /* a618 is using the hw default values */ if (adreno_is_a618(adreno_gpu)) @@ -800,25 +815,31 @@ static void a6xx_set_ubwc_config(struct msm_gpu *gpu) =20 if (adreno_is_a650(adreno_gpu) || adreno_is_a660(adreno_gpu)) { /* TODO: get ddr type from bootloader and use 2 for LPDDR4 */ - lower_bit =3D 3; + hbb_lo =3D 3; amsbc =3D 1; rgb565_predicator =3D 1; uavflagprd_inv =3D 2; } =20 if (adreno_is_7c3(adreno_gpu)) { - lower_bit =3D 1; + hbb_lo =3D 1; amsbc =3D 1; rgb565_predicator =3D 1; uavflagprd_inv =3D 2; } =20 gpu_write(gpu, REG_A6XX_RB_NC_MODE_CNTL, - rgb565_predicator << 11 | amsbc << 4 | lower_bit << 1); - gpu_write(gpu, REG_A6XX_TPL1_NC_MODE_CNTL, lower_bit << 1); - gpu_write(gpu, REG_A6XX_SP_NC_MODE_CNTL, - uavflagprd_inv << 4 | lower_bit << 1); - gpu_write(gpu, REG_A6XX_UCHE_MODE_CNTL, lower_bit << 21); + rgb565_predicator << 11 | hbb_hi << 10 | amsbc << 4 | + min_acc_len << 3 | hbb_lo << 1 | ubwc_mode); + + gpu_write(gpu, REG_A6XX_TPL1_NC_MODE_CNTL, hbb_hi << 4 | + min_acc_len << 3 | hbb_lo << 1 | ubwc_mode); + + gpu_write(gpu, REG_A6XX_SP_NC_MODE_CNTL, hbb_hi << 10 | + uavflagprd_inv << 4 | min_acc_len << 3 | + hbb_lo << 1 | ubwc_mode); + + gpu_write(gpu, REG_A6XX_UCHE_MODE_CNTL, min_acc_len << 23 | hbb_lo << 21); } =20 static int a6xx_cp_init(struct msm_gpu *gpu) --=20 2.39.2 From nobody Wed Feb 11 13:06:20 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id DDD89C7618D for ; Tue, 14 Mar 2023 15:29:11 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229571AbjCNP3J (ORCPT ); Tue, 14 Mar 2023 11:29:09 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:58106 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231221AbjCNP2z (ORCPT ); Tue, 14 Mar 2023 11:28:55 -0400 Received: from mail-lj1-x22c.google.com (mail-lj1-x22c.google.com [IPv6:2a00:1450:4864:20::22c]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 7FC5C9FBFD for ; Tue, 14 Mar 2023 08:28:48 -0700 (PDT) Received: by mail-lj1-x22c.google.com with SMTP id z5so16399576ljc.8 for ; Tue, 14 Mar 2023 08:28:48 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1678807727; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=St31qEiBWKoRteqqRq8R4XXaVrODiETBsusFnrIXDy0=; b=GzXSp7KSnCAoQGOyLE8PUdsR6qJiFoVrOSNzF8GVBiP4WVV9GNKn2BgH6cSjbjmG+X OKtxmT/OfjcdsRsc05JjD0UunbXdOayz8v4uIst4y7fVa6f4CB1Gbw80m2OGRvrOKmlm K1aJaYGpdv6tjcx3ua5g+5OxTymuIT6v1D3BXXheCaXhhAs2zNnkx8Fcxeby9V128g7Y 4OgpjitS/jvzZWETPdNtNsU9Int03mj3kKgoIy9BGLYNJhq9It3BP7wguOeJm88h5NK1 gJuK1ZHHah+50B5eEU697A04oUY4JLeKlkNx4kDHpOi54vz9fHqJSb6b8NR34sVAw7rI 57Xw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1678807727; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=St31qEiBWKoRteqqRq8R4XXaVrODiETBsusFnrIXDy0=; b=vs7+r44zeLamPN8c/3NOsU7mUdyzbH4UoBYW73SrrOjgoI/gG3Rssq4c6puMUWMOtp t0oK4Jdfvei1BUgsXHYFD+h7LRnrKL7fSBavxH6ZaX3sPQPta0+KAmXbR9asAus+G5rg wed+KL0S0gnTzKYWsbXiOC24LkVZdVE07DKCBNxTjI4FHd+KAtwc0OdJRoEX/jiaJrjF 42oq/HNINMzEtirzyOEJLPI9DeteRjmlAW9cKVQvRiBQXkjcqAm9Lxt8kGT5xRB03Ix6 vuH44KKQj+2gsNTWupoOgIBRPHaP9O5/FWprEsieDSg/MsC3EVcsxCYkKI0yFPgYBqjR tUUA== X-Gm-Message-State: AO0yUKVE80ZEgDtz4pvg7qmQnkSc1T2zizzvgns9y7QX+1sFx7uzdqm4 /c1/tT4z4BK7BaOe5U2UpX31TA== X-Google-Smtp-Source: AK7set9aVoQz7CWVxU+uRbCphW8bPppOo+AKeDooiOWl7Wo4iFpwUaGKYHwyyyslqzjpmXWspQ3lMA== X-Received: by 2002:a2e:7804:0:b0:295:b3df:4942 with SMTP id t4-20020a2e7804000000b00295b3df4942mr11344510ljc.40.1678807726789; Tue, 14 Mar 2023 08:28:46 -0700 (PDT) Received: from [192.168.1.101] (abyj16.neoplus.adsl.tpnet.pl. [83.9.29.16]) by smtp.gmail.com with ESMTPSA id 27-20020a2e165b000000b002986a977bf2sm491529ljw.90.2023.03.14.08.28.45 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 14 Mar 2023 08:28:46 -0700 (PDT) From: Konrad Dybcio Date: Tue, 14 Mar 2023 16:28:36 +0100 Subject: [PATCH v4 05/14] drm/msm/a6xx: Introduce GMU wrapper support MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20230223-topic-gmuwrapper-v4-5-e987eb79d03f@linaro.org> References: <20230223-topic-gmuwrapper-v4-0-e987eb79d03f@linaro.org> In-Reply-To: <20230223-topic-gmuwrapper-v4-0-e987eb79d03f@linaro.org> To: Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , David Airlie , Daniel Vetter , Rob Herring , Krzysztof Kozlowski , Bjorn Andersson , Konrad Dybcio , Akhil P Oommen Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Rob Clark , Marijn Suijten , Konrad Dybcio X-Mailer: b4 0.12.1 X-Developer-Signature: v=1; a=ed25519-sha256; t=1678807716; l=19221; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=jpS8eOVezzz/F28mXHuOAM+A63HkjMpcKU5ZfGuiRds=; b=WrvnUl6YG5UiNc2LVPjd+AW0IU8Q7/F9SncvXEXLDYcONd1ve9ty8IOfblApWmKrmOBPyY5s/Tm9 G2wdbZcJBOGLWdKNqdA2EvkGOSjJfPp2H306zT93nI6q09vSGqSw X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Some (particularly SMD_RPM, a.k.a non-RPMh) SoCs implement A6XX GPUs but don't implement the associated GMUs. This is due to the fact that the GMU directly pokes at RPMh. Sadly, this means we have to take care of enabling & scaling power rails, clocks and bandwidth ourselves. Reuse existing Adreno-common code and modify the deeply-GMU-infused A6XX code to facilitate these GPUs. This involves if-ing out lots of GMU callbacks and introducing a new type of GMU - GMU wrapper (it's the actual name that Qualcomm uses in their downstream kernels). This is essentially a register region which is convenient to model as a device. We'll use it for managing the GDSCs. The register layout matches the actual GMU_CX/GX regions on the "real GMU" devices and lets us reuse quite a bit of gmu_read/write/rmw calls. Signed-off-by: Konrad Dybcio --- drivers/gpu/drm/msm/adreno/a6xx_gmu.c | 53 +++++- drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 244 ++++++++++++++++++++++++= +--- drivers/gpu/drm/msm/adreno/a6xx_gpu.h | 1 + drivers/gpu/drm/msm/adreno/a6xx_gpu_state.c | 14 +- drivers/gpu/drm/msm/adreno/adreno_gpu.h | 6 + 5 files changed, 282 insertions(+), 36 deletions(-) diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c b/drivers/gpu/drm/msm/ad= reno/a6xx_gmu.c index 229a54ec82b4..4ba059157177 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_gmu.c @@ -1474,6 +1474,7 @@ static int a6xx_gmu_get_irq(struct a6xx_gmu *gmu, str= uct platform_device *pdev, =20 void a6xx_gmu_remove(struct a6xx_gpu *a6xx_gpu) { + struct adreno_gpu *adreno_gpu =3D &a6xx_gpu->base; struct a6xx_gmu *gmu =3D &a6xx_gpu->gmu; struct platform_device *pdev =3D to_platform_device(gmu->dev); =20 @@ -1493,10 +1494,12 @@ void a6xx_gmu_remove(struct a6xx_gpu *a6xx_gpu) gmu->mmio =3D NULL; gmu->rscc =3D NULL; =20 - a6xx_gmu_memory_free(gmu); + if (!adreno_has_gmu_wrapper(adreno_gpu)) { + a6xx_gmu_memory_free(gmu); =20 - free_irq(gmu->gmu_irq, gmu); - free_irq(gmu->hfi_irq, gmu); + free_irq(gmu->gmu_irq, gmu); + free_irq(gmu->hfi_irq, gmu); + } =20 /* Drop reference taken in of_find_device_by_node */ put_device(gmu->dev); @@ -1504,6 +1507,50 @@ void a6xx_gmu_remove(struct a6xx_gpu *a6xx_gpu) gmu->initialized =3D false; } =20 +int a6xx_gmu_wrapper_init(struct a6xx_gpu *a6xx_gpu, struct device_node *n= ode) +{ + struct platform_device *pdev =3D of_find_device_by_node(node); + struct a6xx_gmu *gmu =3D &a6xx_gpu->gmu; + int ret; + + if (!pdev) + return -ENODEV; + + gmu->dev =3D &pdev->dev; + + of_dma_configure(gmu->dev, node, true); + + pm_runtime_enable(gmu->dev); + + /* Mark legacy for manual SPTPRAC control */ + gmu->legacy =3D true; + + /* Map the GMU registers */ + gmu->mmio =3D a6xx_gmu_get_mmio(pdev, "gmu"); + if (IS_ERR(gmu->mmio)) { + ret =3D PTR_ERR(gmu->mmio); + goto err_mmio; + } + + /* Get a link to the GX power domain to reset the GPU */ + gmu->gxpd =3D dev_pm_domain_attach_by_name(gmu->dev, "gx"); + if (IS_ERR(gmu->gxpd)) + goto err_mmio; + + gmu->initialized =3D true; + + return 0; + +err_mmio: + iounmap(gmu->mmio); + ret =3D -ENODEV; + + /* Drop reference taken in of_find_device_by_node */ + put_device(gmu->dev); + + return ret; +} + int a6xx_gmu_init(struct a6xx_gpu *a6xx_gpu, struct device_node *node) { struct adreno_gpu *adreno_gpu =3D &a6xx_gpu->base; diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/ad= reno/a6xx_gpu.c index 2f55dac52833..a90847a3379a 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c @@ -20,9 +20,11 @@ static inline bool _a6xx_check_idle(struct msm_gpu *gpu) struct adreno_gpu *adreno_gpu =3D to_adreno_gpu(gpu); struct a6xx_gpu *a6xx_gpu =3D to_a6xx_gpu(adreno_gpu); =20 - /* Check that the GMU is idle */ - if (!a6xx_gmu_isidle(&a6xx_gpu->gmu)) - return false; + if (!adreno_has_gmu_wrapper(adreno_gpu)) { + /* Check that the GMU is idle */ + if (!a6xx_gmu_isidle(&a6xx_gpu->gmu)) + return false; + } =20 /* Check tha the CX master is idle */ if (gpu_read(gpu, REG_A6XX_RBBM_STATUS) & @@ -612,13 +614,15 @@ static void a6xx_set_hwcg(struct msm_gpu *gpu, bool s= tate) return; =20 /* Disable SP clock before programming HWCG registers */ - gmu_rmw(gmu, REG_A6XX_GPU_GMU_GX_SPTPRAC_CLOCK_CONTROL, 1, 0); + if (!adreno_has_gmu_wrapper(adreno_gpu)) + gmu_rmw(gmu, REG_A6XX_GPU_GMU_GX_SPTPRAC_CLOCK_CONTROL, 1, 0); =20 for (i =3D 0; (reg =3D &adreno_gpu->info->hwcg[i], reg->offset); i++) gpu_write(gpu, reg->offset, state ? reg->value : 0); =20 /* Enable SP clock */ - gmu_rmw(gmu, REG_A6XX_GPU_GMU_GX_SPTPRAC_CLOCK_CONTROL, 0, 1); + if (!adreno_has_gmu_wrapper(adreno_gpu)) + gmu_rmw(gmu, REG_A6XX_GPU_GMU_GX_SPTPRAC_CLOCK_CONTROL, 0, 1); =20 gpu_write(gpu, REG_A6XX_RBBM_CLOCK_CNTL, state ? clock_cntl_on : 0); } @@ -1002,10 +1006,13 @@ static int hw_init(struct msm_gpu *gpu) { struct adreno_gpu *adreno_gpu =3D to_adreno_gpu(gpu); struct a6xx_gpu *a6xx_gpu =3D to_a6xx_gpu(adreno_gpu); + struct a6xx_gmu *gmu =3D &a6xx_gpu->gmu; int ret; =20 - /* Make sure the GMU keeps the GPU on while we set it up */ - a6xx_gmu_set_oob(&a6xx_gpu->gmu, GMU_OOB_GPU_SET); + if (!adreno_has_gmu_wrapper(adreno_gpu)) { + /* Make sure the GMU keeps the GPU on while we set it up */ + a6xx_gmu_set_oob(&a6xx_gpu->gmu, GMU_OOB_GPU_SET); + } =20 /* Clear GBIF halt in case GX domain was not collapsed */ if (a6xx_has_gbif(adreno_gpu)) @@ -1131,6 +1138,17 @@ static int hw_init(struct msm_gpu *gpu) 0x3f0243f0); } =20 + if (adreno_has_gmu_wrapper(adreno_gpu)) { + /* Do it here, as GMU wrapper only inits the GMU for memory reservation = etc. */ + + /* Set up the CX GMU counter 0 to count busy ticks */ + gmu_write(gmu, REG_A6XX_GPU_GMU_AO_GPU_CX_BUSY_MASK, 0xff000000); + + /* Enable power counter 0 */ + gmu_rmw(gmu, REG_A6XX_GMU_CX_GMU_POWER_COUNTER_SELECT_0, 0xff, BIT(5)); + gmu_write(gmu, REG_A6XX_GMU_CX_GMU_POWER_COUNTER_ENABLE, 1); + } + /* Protect registers from the CP */ a6xx_set_cp_protect(gpu); =20 @@ -1239,6 +1257,8 @@ static int hw_init(struct msm_gpu *gpu) } =20 out: + if (adreno_has_gmu_wrapper(adreno_gpu)) + return ret; /* * Tell the GMU that we are done touching the GPU and it can start power * management @@ -1273,6 +1293,9 @@ static void a6xx_dump(struct msm_gpu *gpu) adreno_dump(gpu); } =20 +#define GBIF_GX_HALT_MASK BIT(0) +#define GBIF_CLIENT_HALT_MASK BIT(0) +#define GBIF_ARB_HALT_MASK BIT(1) #define VBIF_RESET_ACK_TIMEOUT 100 #define VBIF_RESET_ACK_MASK 0x00f0 =20 @@ -1304,7 +1327,8 @@ static void a6xx_recover(struct msm_gpu *gpu) * Turn off keep alive that might have been enabled by the hang * interrupt */ - gmu_write(&a6xx_gpu->gmu, REG_A6XX_GMU_GMU_PWR_COL_KEEPALIVE, 0); + if (!adreno_has_gmu_wrapper(adreno_gpu)) + gmu_write(&a6xx_gpu->gmu, REG_A6XX_GMU_GMU_PWR_COL_KEEPALIVE, 0); =20 pm_runtime_dont_use_autosuspend(&gpu->pdev->dev); =20 @@ -1328,6 +1352,35 @@ static void a6xx_recover(struct msm_gpu *gpu) /* Call into gpucc driver to poll for cx gdsc collapse */ reset_control_reset(gpu->cx_collapse); =20 + /* Software-reset the GPU */ + if (adreno_has_gmu_wrapper(adreno_gpu)) { + /* Halt the GX side of GBIF */ + gpu_write(gpu, REG_A6XX_RBBM_GBIF_HALT, GBIF_GX_HALT_MASK); + spin_until(gpu_read(gpu, REG_A6XX_RBBM_GBIF_HALT_ACK) & + GBIF_GX_HALT_MASK); + + /* Halt new client requests on GBIF */ + gpu_write(gpu, REG_A6XX_GBIF_HALT, GBIF_CLIENT_HALT_MASK); + spin_until((gpu_read(gpu, REG_A6XX_GBIF_HALT_ACK) & + (GBIF_CLIENT_HALT_MASK)) =3D=3D GBIF_CLIENT_HALT_MASK); + + /* Halt all AXI requests on GBIF */ + gpu_write(gpu, REG_A6XX_GBIF_HALT, GBIF_ARB_HALT_MASK); + spin_until((gpu_read(gpu, REG_A6XX_GBIF_HALT_ACK) & + (GBIF_ARB_HALT_MASK)) =3D=3D GBIF_ARB_HALT_MASK); + + /* Clear the halts */ + gpu_write(gpu, REG_A6XX_GBIF_HALT, 0); + + if (adreno_is_a619_holi(adreno_gpu)) + gpu_write(gpu, 0x18, 0); + else + gpu_write(gpu, REG_A6XX_RBBM_GBIF_HALT, 0); + + /* This *really* needs to go through before we do anything else! */ + mb(); + } + pm_runtime_use_autosuspend(&gpu->pdev->dev); =20 if (active_submits) @@ -1512,7 +1565,8 @@ static void a6xx_fault_detect_irq(struct msm_gpu *gpu) * Force the GPU to stay on until after we finish * collecting information */ - gmu_write(&a6xx_gpu->gmu, REG_A6XX_GMU_GMU_PWR_COL_KEEPALIVE, 1); + if (!adreno_has_gmu_wrapper(adreno_gpu)) + gmu_write(&a6xx_gpu->gmu, REG_A6XX_GMU_GMU_PWR_COL_KEEPALIVE, 1); =20 DRM_DEV_ERROR(&gpu->pdev->dev, "gpu fault ring %d fence %x status %8.8X rb %4.4x/%4.4x ib1 %16.16llX/%4= .4x ib2 %16.16llX/%4.4x\n", @@ -1673,7 +1727,7 @@ static void a6xx_llc_slices_init(struct platform_devi= ce *pdev, a6xx_gpu->llc_mmio =3D ERR_PTR(-EINVAL); } =20 -static int a6xx_pm_resume(struct msm_gpu *gpu) +static int a6xx_gmu_pm_resume(struct msm_gpu *gpu) { struct adreno_gpu *adreno_gpu =3D to_adreno_gpu(gpu); struct a6xx_gpu *a6xx_gpu =3D to_a6xx_gpu(adreno_gpu); @@ -1693,10 +1747,48 @@ static int a6xx_pm_resume(struct msm_gpu *gpu) =20 a6xx_llc_activate(a6xx_gpu); =20 - return 0; + return ret; } =20 -static int a6xx_pm_suspend(struct msm_gpu *gpu) +static int a6xx_pm_resume(struct msm_gpu *gpu) +{ + struct adreno_gpu *adreno_gpu =3D to_adreno_gpu(gpu); + struct a6xx_gpu *a6xx_gpu =3D to_a6xx_gpu(adreno_gpu); + struct a6xx_gmu *gmu =3D &a6xx_gpu->gmu; + int ret; + + gpu->needs_hw_init =3D true; + + trace_msm_gpu_resume(0); + + mutex_lock(&a6xx_gpu->gmu.lock); + + pm_runtime_resume_and_get(gmu->dev); + pm_runtime_resume_and_get(gmu->gxpd); + + /* Set the core clock, having VDD scaling in mind */ + ret =3D dev_pm_opp_set_rate(&gpu->pdev->dev, gpu->fast_rate); + if (ret) + goto err; + + ret =3D clk_bulk_prepare_enable(gpu->nr_clocks, gpu->grp_clks); + if (ret) + goto err; + + ret =3D clk_prepare_enable(gpu->ebi1_clk); + if (ret) + goto err; + +err: + mutex_unlock(&a6xx_gpu->gmu.lock); + + if (!ret) + msm_devfreq_resume(gpu); + + return ret; +} + +static int a6xx_gmu_pm_suspend(struct msm_gpu *gpu) { struct adreno_gpu *adreno_gpu =3D to_adreno_gpu(gpu); struct a6xx_gpu *a6xx_gpu =3D to_a6xx_gpu(adreno_gpu); @@ -1723,11 +1815,62 @@ static int a6xx_pm_suspend(struct msm_gpu *gpu) return 0; } =20 +static int a6xx_pm_suspend(struct msm_gpu *gpu) +{ + struct adreno_gpu *adreno_gpu =3D to_adreno_gpu(gpu); + struct a6xx_gpu *a6xx_gpu =3D to_a6xx_gpu(adreno_gpu); + struct a6xx_gmu *gmu =3D &a6xx_gpu->gmu; + unsigned long freq =3D 0; + struct dev_pm_opp *opp; + int i, ret; + + trace_msm_gpu_suspend(0); + + opp =3D dev_pm_opp_find_freq_ceil(&gpu->pdev->dev, &freq); + dev_pm_opp_put(opp); + + msm_devfreq_suspend(gpu); + + mutex_lock(&a6xx_gpu->gmu.lock); + + clk_disable_unprepare(gpu->ebi1_clk); + + clk_bulk_disable_unprepare(gpu->nr_clocks, gpu->grp_clks); + + /* Set frequency to the minimum supported level (no 27MHz on A6xx!) */ + ret =3D dev_pm_opp_set_rate(&gpu->pdev->dev, freq); + if (ret) + goto err; + + pm_runtime_put_sync(gmu->gxpd); + pm_runtime_put_sync(gmu->dev); + + mutex_unlock(&a6xx_gpu->gmu.lock); + + if (a6xx_gpu->shadow_bo) + for (i =3D 0; i < gpu->nr_rings; i++) + a6xx_gpu->shadow[i] =3D 0; + + gpu->suspend_count++; + + return 0; + +err: + mutex_unlock(&a6xx_gpu->gmu.lock); + + return ret; +} + static int a6xx_get_timestamp(struct msm_gpu *gpu, uint64_t *value) { struct adreno_gpu *adreno_gpu =3D to_adreno_gpu(gpu); struct a6xx_gpu *a6xx_gpu =3D to_a6xx_gpu(adreno_gpu); =20 + if (adreno_has_gmu_wrapper(adreno_gpu)) { + *value =3D gpu_read64(gpu, REG_A6XX_CP_ALWAYS_ON_COUNTER_LO); + return 0; + } + mutex_lock(&a6xx_gpu->gmu.lock); =20 /* Force the GPU power on so we can read this register */ @@ -1765,7 +1908,8 @@ static void a6xx_destroy(struct msm_gpu *gpu) drm_gem_object_put(a6xx_gpu->shadow_bo); } =20 - a6xx_llc_slices_destroy(a6xx_gpu); + if (!adreno_has_gmu_wrapper(adreno_gpu)) + a6xx_llc_slices_destroy(a6xx_gpu); =20 mutex_lock(&a6xx_gpu->gmu.lock); a6xx_gmu_remove(a6xx_gpu); @@ -2005,8 +2149,8 @@ static const struct adreno_gpu_funcs funcs =3D { .get_param =3D adreno_get_param, .set_param =3D adreno_set_param, .hw_init =3D a6xx_hw_init, - .pm_suspend =3D a6xx_pm_suspend, - .pm_resume =3D a6xx_pm_resume, + .pm_suspend =3D a6xx_gmu_pm_suspend, + .pm_resume =3D a6xx_gmu_pm_resume, .recover =3D a6xx_recover, .submit =3D a6xx_submit, .active_ring =3D a6xx_active_ring, @@ -2030,6 +2174,34 @@ static const struct adreno_gpu_funcs funcs =3D { .get_timestamp =3D a6xx_get_timestamp, }; =20 +static const struct adreno_gpu_funcs funcs_gmuwrapper =3D { + .base =3D { + .get_param =3D adreno_get_param, + .set_param =3D adreno_set_param, + .hw_init =3D a6xx_hw_init, + .pm_suspend =3D a6xx_pm_suspend, + .pm_resume =3D a6xx_pm_resume, + .recover =3D a6xx_recover, + .submit =3D a6xx_submit, + .active_ring =3D a6xx_active_ring, + .irq =3D a6xx_irq, + .destroy =3D a6xx_destroy, +#if defined(CONFIG_DRM_MSM_GPU_STATE) + .show =3D a6xx_show, +#endif + .gpu_busy =3D a6xx_gpu_busy, +#if defined(CONFIG_DRM_MSM_GPU_STATE) + .gpu_state_get =3D a6xx_gpu_state_get, + .gpu_state_put =3D a6xx_gpu_state_put, +#endif + .create_address_space =3D a6xx_create_address_space, + .create_private_address_space =3D a6xx_create_private_address_space, + .get_rptr =3D a6xx_get_rptr, + .progress =3D a6xx_progress, + }, + .get_timestamp =3D a6xx_get_timestamp, +}; + struct msm_gpu *a6xx_gpu_init(struct drm_device *dev) { struct msm_drm_private *priv =3D dev->dev_private; @@ -2051,18 +2223,36 @@ struct msm_gpu *a6xx_gpu_init(struct drm_device *de= v) =20 adreno_gpu->registers =3D NULL; =20 + /* Check if there is a GMU phandle and set it up */ + node =3D of_parse_phandle(pdev->dev.of_node, "qcom,gmu", 0); + /* FIXME: How do we gracefully handle this? */ + BUG_ON(!node); + + adreno_gpu->gmu_is_wrapper =3D of_device_is_compatible(node, "qcom,adreno= -gmu-wrapper"); + /* * We need to know the platform type before calling into adreno_gpu_init * so that the hw_apriv flag can be correctly set. Snoop into the info * and grab the revision number */ info =3D adreno_info(config->rev); - - if (info && (info->revn =3D=3D 650 || info->revn =3D=3D 660 || - adreno_cmp_rev(ADRENO_REV(6, 3, 5, ANY_ID), info->rev))) + if (!info) + return ERR_PTR(-EINVAL); + + /* Assign these early so that we can use the is_aXYZ helpers */ + /* Numeric revision IDs (e.g. 630) */ + adreno_gpu->revn =3D info->revn; + /* New-style ADRENO_REV()-only */ + adreno_gpu->rev =3D info->rev; + /* Quirk data */ + adreno_gpu->info =3D info; + + if (adreno_is_a650(adreno_gpu) || adreno_is_a660_family(adreno_gpu)) adreno_gpu->base.hw_apriv =3D true; =20 - a6xx_llc_slices_init(pdev, a6xx_gpu); + /* No LLCC on non-RPMh (and by extension, non-GMU) SoCs */ + if (!adreno_has_gmu_wrapper(adreno_gpu)) + a6xx_llc_slices_init(pdev, a6xx_gpu); =20 ret =3D a6xx_set_supported_hw(&pdev->dev, config->rev); if (ret) { @@ -2070,7 +2260,10 @@ struct msm_gpu *a6xx_gpu_init(struct drm_device *dev) return ERR_PTR(ret); } =20 - ret =3D adreno_gpu_init(dev, pdev, adreno_gpu, &funcs, 1); + if (adreno_has_gmu_wrapper(adreno_gpu)) + ret =3D adreno_gpu_init(dev, pdev, adreno_gpu, &funcs_gmuwrapper, 1); + else + ret =3D adreno_gpu_init(dev, pdev, adreno_gpu, &funcs, 1); if (ret) { a6xx_destroy(&(a6xx_gpu->base.base)); return ERR_PTR(ret); @@ -2083,13 +2276,10 @@ struct msm_gpu *a6xx_gpu_init(struct drm_device *de= v) if (adreno_is_a618(adreno_gpu) || adreno_is_7c3(adreno_gpu)) priv->gpu_clamp_to_idle =3D true; =20 - /* Check if there is a GMU phandle and set it up */ - node =3D of_parse_phandle(pdev->dev.of_node, "qcom,gmu", 0); - - /* FIXME: How do we gracefully handle this? */ - BUG_ON(!node); - - ret =3D a6xx_gmu_init(a6xx_gpu, node); + if (adreno_has_gmu_wrapper(adreno_gpu)) + ret =3D a6xx_gmu_wrapper_init(a6xx_gpu, node); + else + ret =3D a6xx_gmu_init(a6xx_gpu, node); of_node_put(node); if (ret) { a6xx_destroy(&(a6xx_gpu->base.base)); diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.h b/drivers/gpu/drm/msm/ad= reno/a6xx_gpu.h index eea2e60ce3b7..51a7656072fa 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.h +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.h @@ -76,6 +76,7 @@ int a6xx_gmu_set_oob(struct a6xx_gmu *gmu, enum a6xx_gmu_= oob_state state); void a6xx_gmu_clear_oob(struct a6xx_gmu *gmu, enum a6xx_gmu_oob_state stat= e); =20 int a6xx_gmu_init(struct a6xx_gpu *a6xx_gpu, struct device_node *node); +int a6xx_gmu_wrapper_init(struct a6xx_gpu *a6xx_gpu, struct device_node *n= ode); void a6xx_gmu_remove(struct a6xx_gpu *a6xx_gpu); =20 void a6xx_gmu_set_freq(struct msm_gpu *gpu, struct dev_pm_opp *opp, diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu_state.c b/drivers/gpu/drm/= msm/adreno/a6xx_gpu_state.c index b7e217d00a22..e11e8a02ac22 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu_state.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu_state.c @@ -1041,16 +1041,18 @@ struct msm_gpu_state *a6xx_gpu_state_get(struct msm= _gpu *gpu) /* Get the generic state from the adreno core */ adreno_gpu_state_get(gpu, &a6xx_state->base); =20 - a6xx_get_gmu_registers(gpu, a6xx_state); + if (!adreno_has_gmu_wrapper(adreno_gpu)) { + a6xx_get_gmu_registers(gpu, a6xx_state); =20 - a6xx_state->gmu_log =3D a6xx_snapshot_gmu_bo(a6xx_state, &a6xx_gpu->gmu.l= og); - a6xx_state->gmu_hfi =3D a6xx_snapshot_gmu_bo(a6xx_state, &a6xx_gpu->gmu.h= fi); - a6xx_state->gmu_debug =3D a6xx_snapshot_gmu_bo(a6xx_state, &a6xx_gpu->gmu= .debug); + a6xx_state->gmu_log =3D a6xx_snapshot_gmu_bo(a6xx_state, &a6xx_gpu->gmu.= log); + a6xx_state->gmu_hfi =3D a6xx_snapshot_gmu_bo(a6xx_state, &a6xx_gpu->gmu.= hfi); + a6xx_state->gmu_debug =3D a6xx_snapshot_gmu_bo(a6xx_state, &a6xx_gpu->gm= u.debug); =20 - a6xx_snapshot_gmu_hfi_history(gpu, a6xx_state); + a6xx_snapshot_gmu_hfi_history(gpu, a6xx_state); + } =20 /* If GX isn't on the rest of the data isn't going to be accessible */ - if (!a6xx_gmu_gx_is_on(&a6xx_gpu->gmu)) + if (!adreno_has_gmu_wrapper(adreno_gpu) && !a6xx_gmu_gx_is_on(&a6xx_gpu->= gmu)) return &a6xx_state->base; =20 /* Get the banks of indexed registers */ diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.h b/drivers/gpu/drm/msm/= adreno/adreno_gpu.h index b4f9b1343d63..2c0f0ef094cb 100644 --- a/drivers/gpu/drm/msm/adreno/adreno_gpu.h +++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.h @@ -115,6 +115,7 @@ struct adreno_gpu { * code (a3xx_gpu.c) and stored in this common location. */ const unsigned int *reg_offsets; + bool gmu_is_wrapper; }; #define to_adreno_gpu(x) container_of(x, struct adreno_gpu, base) =20 @@ -145,6 +146,11 @@ struct adreno_platform_config { =20 bool adreno_cmp_rev(struct adreno_rev rev1, struct adreno_rev rev2); =20 +static inline bool adreno_has_gmu_wrapper(struct adreno_gpu *gpu) +{ + return gpu->gmu_is_wrapper; +} + static inline bool adreno_is_a2xx(struct adreno_gpu *gpu) { return (gpu->revn < 300); --=20 2.39.2 From nobody Wed Feb 11 13:06:20 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3F71EC74A4B for ; Tue, 14 Mar 2023 15:29:08 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229565AbjCNP3G (ORCPT ); Tue, 14 Mar 2023 11:29:06 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:58012 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231439AbjCNP2y (ORCPT ); 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[83.9.29.16]) by smtp.gmail.com with ESMTPSA id 27-20020a2e165b000000b002986a977bf2sm491529ljw.90.2023.03.14.08.28.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 14 Mar 2023 08:28:48 -0700 (PDT) From: Konrad Dybcio Date: Tue, 14 Mar 2023 16:28:37 +0100 Subject: [PATCH v4 06/14] drm/msm/a6xx: Remove both GBIF and RBBM GBIF halt on hw init MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20230223-topic-gmuwrapper-v4-6-e987eb79d03f@linaro.org> References: <20230223-topic-gmuwrapper-v4-0-e987eb79d03f@linaro.org> In-Reply-To: <20230223-topic-gmuwrapper-v4-0-e987eb79d03f@linaro.org> To: Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , David Airlie , Daniel Vetter , Rob Herring , Krzysztof Kozlowski , Bjorn Andersson , Konrad Dybcio , Akhil P Oommen Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Rob Clark , Marijn Suijten , Konrad Dybcio X-Mailer: b4 0.12.1 X-Developer-Signature: v=1; a=ed25519-sha256; t=1678807716; l=1251; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=SQf5xqv6dgkFv8lqaRaSsqR3oatLGI4JEKv+JlvqW4k=; b=j0wqavMQyp9JVzEUb+dyZ3aehx3l+F1HEWpU/j8PV1u7+qyWbwNnPl8Ix1vohsIlZY8QP7XOf0G8 gFxAnV4NCSDkUzx+xsz2mPlEqsuMhpdcxfpQLRfk7YgDSyVTBnNy X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Currently we're only deasserting REG_A6XX_RBBM_GBIF_HALT, but we also need REG_A6XX_GBIF_HALT to be set to 0. For GMU-equipped GPUs this is done in a6xx_bus_clear_pending_transactions(), but for the GMU-less ones we have to do it *somewhere*. Unhalting both side by side sounds like a good plan and it won't cause any issues if it's unnecessary. Also, add a memory barrier to ensure it's gone through. Signed-off-by: Konrad Dybcio Reviewed-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/ad= reno/a6xx_gpu.c index a90847a3379a..70e9bd21ba3b 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c @@ -1015,8 +1015,12 @@ static int hw_init(struct msm_gpu *gpu) } =20 /* Clear GBIF halt in case GX domain was not collapsed */ - if (a6xx_has_gbif(adreno_gpu)) + if (a6xx_has_gbif(adreno_gpu)) { + gpu_write(gpu, REG_A6XX_GBIF_HALT, 0); gpu_write(gpu, REG_A6XX_RBBM_GBIF_HALT, 0); + /* Let's make extra sure that the GPU can access the memory.. */ + mb(); + } =20 gpu_write(gpu, REG_A6XX_RBBM_SECVID_TSB_CNTL, 0); =20 --=20 2.39.2 From nobody Wed Feb 11 13:06:20 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id BFE8DC6FD1C for ; Tue, 14 Mar 2023 15:29:25 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230164AbjCNP3Y (ORCPT ); Tue, 14 Mar 2023 11:29:24 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:57914 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231618AbjCNP25 (ORCPT ); Tue, 14 Mar 2023 11:28:57 -0400 Received: from mail-lj1-x232.google.com (mail-lj1-x232.google.com [IPv6:2a00:1450:4864:20::232]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 9021172036 for ; Tue, 14 Mar 2023 08:28:51 -0700 (PDT) Received: by mail-lj1-x232.google.com with SMTP id g18so16449392ljl.3 for ; Tue, 14 Mar 2023 08:28:51 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1678807730; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=WABs2uqkSr8euv93L/sU63WnoiH4PZRdu/LdvY8ve98=; b=e4HxELOY7IfiLDgpEbVVOCpGxJQiGn7MmAADHLeIQ9dSonULA0bldiz8CgMI2737lY rOYV31erKzdYtlM7ceiSmc4zGlTZSeSSeyEkywbYCAfh92/Oxa7gr0GGEXdLxtwTNR2V ai9M1XsFH/RFvDU6O1udDwUKU5YAnpsfNSyFV0bvD/OrN0ZHX7R9UpaN/uTE7lkFnlXh 9fJTy5GbjRFmoTRlViDpEun63yit9z8jUaQX2/CJnYEbnaw3RySP5xBWpzFUpAPX0hI7 8Vp0HsbB95wYBXPFG+N/BlrhRc/mdCCI/fdDT98qBSu10uo7fpWu4/XOcLnq36C3O/zu oGLQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1678807730; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=WABs2uqkSr8euv93L/sU63WnoiH4PZRdu/LdvY8ve98=; b=Ktek1pcnVdKw+3Gc2CX8kPkQJ9XoKF3L7BOj48c/BNr4eG3vX+KnblAauWFoli7xKO dPQOO3QR0m8P0ikfZyBh6mHXaj1oD67MiVGvEa10LX+AJjbDUKQ/228zIx/4bqBXMCQU 5LYnAAsX3Eno9wfvpLgk0h58vXZYyFtVdChVFcHokS1f3H4FHcDdwRziwEn+E4beGDvy wApF9aubcLap9fSYwY3VHRbMiWl8dWV3VaIv7N+EaYflP0bZtvr0ptzvP9ZqxrI8hVkH lvV46K2r72C94EG0o0Rbb3Ji44P9EMAnfMcIcMBIPDeWSWVMGNK3rvvFEcJNIxZ8mgH7 LWSA== X-Gm-Message-State: AO0yUKX32GSensWfeNOQ9w71vKzMrj1pEiu6ZlNliKfG+VR9LaA449W1 0eEieih03UumHJf7+M7VQcmhkA== X-Google-Smtp-Source: AK7set9p0iUmEJFj1wIHWX+7ggS+PnzEj2OdhTv2x6pIfkB92M1XoFxzoYiBOSMe86wKID/Dj0pPdA== X-Received: by 2002:a2e:9911:0:b0:295:a50b:3693 with SMTP id v17-20020a2e9911000000b00295a50b3693mr10743151lji.44.1678807729879; Tue, 14 Mar 2023 08:28:49 -0700 (PDT) Received: from [192.168.1.101] (abyj16.neoplus.adsl.tpnet.pl. [83.9.29.16]) by smtp.gmail.com with ESMTPSA id 27-20020a2e165b000000b002986a977bf2sm491529ljw.90.2023.03.14.08.28.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 14 Mar 2023 08:28:49 -0700 (PDT) From: Konrad Dybcio Date: Tue, 14 Mar 2023 16:28:38 +0100 Subject: [PATCH v4 07/14] drm/msm/adreno: Disable has_cached_coherent in GMU wrapper configurations MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20230223-topic-gmuwrapper-v4-7-e987eb79d03f@linaro.org> References: <20230223-topic-gmuwrapper-v4-0-e987eb79d03f@linaro.org> In-Reply-To: <20230223-topic-gmuwrapper-v4-0-e987eb79d03f@linaro.org> To: Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , David Airlie , Daniel Vetter , Rob Herring , Krzysztof Kozlowski , Bjorn Andersson , Konrad Dybcio , Akhil P Oommen Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Rob Clark , Marijn Suijten , Konrad Dybcio X-Mailer: b4 0.12.1 X-Developer-Signature: v=1; a=ed25519-sha256; t=1678807716; l=1374; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=BrQq/uUq7axESPCyxyyfFuley6Eq3n1FbD/qjV9Gfd4=; b=I4rxN89h6z/5WvdM1z4Z8cq5KsNXVn/10Wqx0Zr2wNmgPlC7+VHm5VhNifsczU7WOBF58BWKvqWC uCkX0n4MCwgu+b3mjjVKTvTab+06TYtgi6LYzZfedym+c58dba/a X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org A610 and A619_holi don't support the feature. Disable it to make the GPU st= op crashing after almost each and every submission - the received data on the GPU end was simply incomplete in garbled, resulting in almost nothing being executed properly. Extend the disablement to adreno_has_gmu_wrapper, as none of the GMU wrapper Adrenos that don't support yet seem to feature i= t. Signed-off-by: Konrad Dybcio --- drivers/gpu/drm/msm/adreno/adreno_device.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/msm/adreno/adreno_device.c b/drivers/gpu/drm/m= sm/adreno/adreno_device.c index f35392c034f7..6513c6094865 100644 --- a/drivers/gpu/drm/msm/adreno/adreno_device.c +++ b/drivers/gpu/drm/msm/adreno/adreno_device.c @@ -540,7 +540,6 @@ static int adreno_bind(struct device *dev, struct devic= e *master, void *data) config.rev.minor, config.rev.patchid); =20 priv->is_a2xx =3D config.rev.core =3D=3D 2; - priv->has_cached_coherent =3D config.rev.core >=3D 6; =20 gpu =3D info->init(drm); if (IS_ERR(gpu)) { @@ -552,6 +551,10 @@ static int adreno_bind(struct device *dev, struct devi= ce *master, void *data) if (ret) return ret; =20 + if (config.rev.core >=3D 6) + if (!adreno_has_gmu_wrapper(to_adreno_gpu(gpu))) + priv->has_cached_coherent =3D true; + return 0; } =20 --=20 2.39.2 From nobody Wed Feb 11 13:06:20 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id CB26DC7618A for ; Tue, 14 Mar 2023 15:29:28 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231494AbjCNP31 (ORCPT ); Tue, 14 Mar 2023 11:29:27 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:58730 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231702AbjCNP26 (ORCPT ); Tue, 14 Mar 2023 11:28:58 -0400 Received: from mail-lj1-x229.google.com (mail-lj1-x229.google.com [IPv6:2a00:1450:4864:20::229]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 63E3D279BA for ; Tue, 14 Mar 2023 08:28:53 -0700 (PDT) Received: by mail-lj1-x229.google.com with SMTP id b10so16450414ljr.0 for ; Tue, 14 Mar 2023 08:28:53 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1678807731; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=0QBfkwBASk6EqehMpj5iBWVthwGOhEMOaMUH5eoHlaw=; b=UepBCxqmyQ8a7htSDlTFI0ShFtEB7diji/pbqGjwg56DIr/pGL1FMQG23Kn4gVFUIH NWU7NEQOg6QEPw+QBNKkfk0e3g7KdwuL54ChUUC95zetLCTFMuNkWeytTRsZmOoAlBPh 6oKBWQ+Zrt2mvYnaj1zpDOe5mfV6hGiVgV8S4nFnuK92cLLCnctMeMoH5uimRkorSjJC hi7HBB16Btn0M0sTQJkP9rlv0qMBsA6gH2fdDc36OWvkMN9RwmYFYtyGhAjMCcaOXdv7 Iu3w3ma+ue36QNvHTEAvVstExQCK4oYWWSW8+plHHOxbDvNQ+AjF0T3Vli78h9Ec6XHk l0BA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1678807731; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=0QBfkwBASk6EqehMpj5iBWVthwGOhEMOaMUH5eoHlaw=; b=YcthHZCWmY69JQr5ORb2YeWrXZ1x3IgqV2kSINH5DNdgUyGK9sXOr9evRbwr0blmj+ ohrRz/CoRoHdlUuSt+aMLB843YwWF0Uq/CuJGQSCLIKlQG7gAOEfNMREt/xSDglL7CDU ykeaamMDYNOC0MRFYaEv+dLlJXTFEtSb1bl6wY/A8EAy08fPn7CTM6ubN38QrqyZ8lw8 E9qq77XzqNja0MC61HyoyRXIu5FoMA1tIftv6oLTRCTMAYJVmSDDZUA2RRVvOcuSLrlU CsLbYsiSIhqu4w2kgsRd5c1zlHCBogYFP+tu0wjWyQmJiDLKsWut7M1wZ7Elyis5aOXU nB/A== X-Gm-Message-State: AO0yUKX65fLN/74aEi5mu88Trku9JHMKETXwboF2D/R/o8DWnxPT7k8d Si/3Fo7Kq9RDecV0CZWM0zQFUg== X-Google-Smtp-Source: AK7set9319x6pXFA2ZB5oQB5t6Vlb6uh1fRGtzfQAmcsGR0/P2fXfUFxvI6C2W5JvKGej6l20vdP9Q== X-Received: by 2002:a2e:909a:0:b0:295:a829:1c57 with SMTP id l26-20020a2e909a000000b00295a8291c57mr12082944ljg.20.1678807731546; Tue, 14 Mar 2023 08:28:51 -0700 (PDT) Received: from [192.168.1.101] (abyj16.neoplus.adsl.tpnet.pl. [83.9.29.16]) by smtp.gmail.com with ESMTPSA id 27-20020a2e165b000000b002986a977bf2sm491529ljw.90.2023.03.14.08.28.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 14 Mar 2023 08:28:51 -0700 (PDT) From: Konrad Dybcio Date: Tue, 14 Mar 2023 16:28:39 +0100 Subject: [PATCH v4 08/14] drm/msm/a6xx: Add support for A619_holi MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20230223-topic-gmuwrapper-v4-8-e987eb79d03f@linaro.org> References: <20230223-topic-gmuwrapper-v4-0-e987eb79d03f@linaro.org> In-Reply-To: <20230223-topic-gmuwrapper-v4-0-e987eb79d03f@linaro.org> To: Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , David Airlie , Daniel Vetter , Rob Herring , Krzysztof Kozlowski , Bjorn Andersson , Konrad Dybcio , Akhil P Oommen Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Rob Clark , Marijn Suijten , Konrad Dybcio X-Mailer: b4 0.12.1 X-Developer-Signature: v=1; a=ed25519-sha256; t=1678807716; l=4940; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=RIb1PwuaJxl26QOFy9hE9BbhqyB0PIh+V+WoOWu9KIo=; b=h7jUht1chOrWGuBBXbU8DzuW6yjeui4Q0sDTGbH6GAeYwsfIT23zHYJDwYLDz3LenakP9X/KTBJ5 izASb5SjDlR6KxM03YuJv1h7kgCC7iusu/S20201Ob3fWj/jky89 X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org A619_holi is a GMU-less variant of the already-supported A619 GPU. It's present on at least SM4350 (holi) and SM6375 (blair). No mesa changes are required. Add the required kernel-side support for it. Signed-off-by: Konrad Dybcio --- drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 42 ++++++++++++++++++++++++++---= ---- drivers/gpu/drm/msm/adreno/adreno_gpu.h | 5 ++++ 2 files changed, 39 insertions(+), 8 deletions(-) diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/ad= reno/a6xx_gpu.c index 70e9bd21ba3b..1c0e5e1df89c 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c @@ -614,14 +614,16 @@ static void a6xx_set_hwcg(struct msm_gpu *gpu, bool s= tate) return; =20 /* Disable SP clock before programming HWCG registers */ - if (!adreno_has_gmu_wrapper(adreno_gpu)) + if (!adreno_has_gmu_wrapper(adreno_gpu) || + adreno_is_a619_holi(adreno_gpu)) gmu_rmw(gmu, REG_A6XX_GPU_GMU_GX_SPTPRAC_CLOCK_CONTROL, 1, 0); =20 for (i =3D 0; (reg =3D &adreno_gpu->info->hwcg[i], reg->offset); i++) gpu_write(gpu, reg->offset, state ? reg->value : 0); =20 /* Enable SP clock */ - if (!adreno_has_gmu_wrapper(adreno_gpu)) + if (!adreno_has_gmu_wrapper(adreno_gpu) || + adreno_is_a619_holi(adreno_gpu)) gmu_rmw(gmu, REG_A6XX_GPU_GMU_GX_SPTPRAC_CLOCK_CONTROL, 0, 1); =20 gpu_write(gpu, REG_A6XX_RBBM_CLOCK_CNTL, state ? clock_cntl_on : 0); @@ -814,6 +816,9 @@ static void a6xx_set_ubwc_config(struct msm_gpu *gpu) if (adreno_is_a618(adreno_gpu)) return; =20 + if (adreno_is_a619_holi(gpu)) + hbb_lo =3D 0; + if (adreno_is_a640_family(adreno_gpu)) amsbc =3D 1; =20 @@ -1015,7 +1020,12 @@ static int hw_init(struct msm_gpu *gpu) } =20 /* Clear GBIF halt in case GX domain was not collapsed */ - if (a6xx_has_gbif(adreno_gpu)) { + if (adreno_is_a619_holi(adreno_gpu)) { + gpu_write(gpu, REG_A6XX_GBIF_HALT, 0); + gpu_write(gpu, 0x18, 0); + /* Let's make extra sure that the GPU can access the memory.. */ + mb(); + } else if (a6xx_has_gbif(adreno_gpu)) { gpu_write(gpu, REG_A6XX_GBIF_HALT, 0); gpu_write(gpu, REG_A6XX_RBBM_GBIF_HALT, 0); /* Let's make extra sure that the GPU can access the memory.. */ @@ -1024,6 +1034,9 @@ static int hw_init(struct msm_gpu *gpu) =20 gpu_write(gpu, REG_A6XX_RBBM_SECVID_TSB_CNTL, 0); =20 + if (adreno_is_a619_holi(adreno_gpu)) + a6xx_sptprac_enable(gmu); + /* * Disable the trusted memory range - we don't actually supported secure * memory rendering at this point in time and we don't want to block off @@ -1301,7 +1314,8 @@ static void a6xx_dump(struct msm_gpu *gpu) #define GBIF_CLIENT_HALT_MASK BIT(0) #define GBIF_ARB_HALT_MASK BIT(1) #define VBIF_RESET_ACK_TIMEOUT 100 -#define VBIF_RESET_ACK_MASK 0x00f0 +#define VBIF_RESET_ACK_MASK 0xF0 +#define GPR0_GBIF_HALT_REQUEST 0x1E0 =20 static void a6xx_recover(struct msm_gpu *gpu) { @@ -1358,10 +1372,16 @@ static void a6xx_recover(struct msm_gpu *gpu) =20 /* Software-reset the GPU */ if (adreno_has_gmu_wrapper(adreno_gpu)) { - /* Halt the GX side of GBIF */ - gpu_write(gpu, REG_A6XX_RBBM_GBIF_HALT, GBIF_GX_HALT_MASK); - spin_until(gpu_read(gpu, REG_A6XX_RBBM_GBIF_HALT_ACK) & - GBIF_GX_HALT_MASK); + if (adreno_is_a619_holi(adreno_gpu)) { + gpu_write(gpu, 0x18, GPR0_GBIF_HALT_REQUEST); + spin_until((gpu_read(gpu, REG_A6XX_RBBM_VBIF_GX_RESET_STATUS) & + (VBIF_RESET_ACK_MASK)) =3D=3D VBIF_RESET_ACK_MASK); + } else { + /* Halt the GX side of GBIF */ + gpu_write(gpu, REG_A6XX_RBBM_GBIF_HALT, GBIF_GX_HALT_MASK); + spin_until(gpu_read(gpu, REG_A6XX_RBBM_GBIF_HALT_ACK) & + GBIF_GX_HALT_MASK); + } =20 /* Halt new client requests on GBIF */ gpu_write(gpu, REG_A6XX_GBIF_HALT, GBIF_CLIENT_HALT_MASK); @@ -1783,6 +1803,9 @@ static int a6xx_pm_resume(struct msm_gpu *gpu) if (ret) goto err; =20 + if (adreno_is_a619_holi(adreno_gpu)) + a6xx_sptprac_enable(gmu); + err: mutex_unlock(&a6xx_gpu->gmu.lock); =20 @@ -1837,6 +1860,9 @@ static int a6xx_pm_suspend(struct msm_gpu *gpu) =20 mutex_lock(&a6xx_gpu->gmu.lock); =20 + if (adreno_is_a619_holi(adreno_gpu)) + a6xx_sptprac_disable(gmu); + clk_disable_unprepare(gpu->ebi1_clk); =20 clk_bulk_disable_unprepare(gpu->nr_clocks, gpu->grp_clks); diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.h b/drivers/gpu/drm/msm/= adreno/adreno_gpu.h index 2c0f0ef094cb..92ece15ec7d8 100644 --- a/drivers/gpu/drm/msm/adreno/adreno_gpu.h +++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.h @@ -252,6 +252,11 @@ static inline int adreno_is_a619(struct adreno_gpu *gp= u) return gpu->revn =3D=3D 619; } =20 +static inline int adreno_is_a619_holi(struct adreno_gpu *gpu) +{ + return adreno_is_a619(gpu) && adreno_has_gmu_wrapper(gpu); +} + static inline int adreno_is_a630(struct adreno_gpu *gpu) { return gpu->revn =3D=3D 630; --=20 2.39.2 From nobody Wed Feb 11 13:06:20 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id D4DEDC6FD1C for ; Tue, 14 Mar 2023 15:29:35 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230432AbjCNP3e (ORCPT ); Tue, 14 Mar 2023 11:29:34 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:58822 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231422AbjCNP27 (ORCPT ); Tue, 14 Mar 2023 11:28:59 -0400 Received: from mail-lj1-x229.google.com (mail-lj1-x229.google.com [IPv6:2a00:1450:4864:20::229]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 17BA95B40E for ; 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[83.9.29.16]) by smtp.gmail.com with ESMTPSA id 27-20020a2e165b000000b002986a977bf2sm491529ljw.90.2023.03.14.08.28.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 14 Mar 2023 08:28:52 -0700 (PDT) From: Konrad Dybcio Date: Tue, 14 Mar 2023 16:28:40 +0100 Subject: [PATCH v4 09/14] drm/msm/a6xx: Add A610 support MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20230223-topic-gmuwrapper-v4-9-e987eb79d03f@linaro.org> References: <20230223-topic-gmuwrapper-v4-0-e987eb79d03f@linaro.org> In-Reply-To: <20230223-topic-gmuwrapper-v4-0-e987eb79d03f@linaro.org> To: Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , David Airlie , Daniel Vetter , Rob Herring , Krzysztof Kozlowski , Bjorn Andersson , Konrad Dybcio , Akhil P Oommen Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Rob Clark , Marijn Suijten , Konrad Dybcio X-Mailer: b4 0.12.1 X-Developer-Signature: v=1; a=ed25519-sha256; t=1678807716; l=10110; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=yX69Ivd086Dc5UnroWXcsijiO2iKVyHQnWKLjNauN9k=; b=w6D0ffth+LwTBLfATPjEGGFXgaaggsk7tjD3JXFsmExBIZSetnVjkjfuERyG7/XchrGM3riJQUOq rb3Xezr6CUc4roBdr8Yczg1sCijuPOtjxPvHFCl38vfy/ZcroL2o X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org A610 is one of (if not the) lowest-tier SKUs in the A6XX family. It features no GMU, as it's implemented solely on SoCs with SMD_RPM. What's more interesting is that it does not feature a VDDGX line either, being powered solely by VDDCX and has an unfortunate hardware quirk that makes its reset line broken - after a couple of assert/ deassert cycles, it will hang for good and will not wake up again. This GPU requires mesa changes for proper rendering, and lots of them at that. The command streams are quite far away from any other A6XX GPU and hence it needs special care. This patch was validated both by running an (incomplete) downstream mesa with some hacks (frames rendered correctly, though some instructions made the GPU hangcheck which is expected - garbage in, garbage out) and by replaying RD traces captured with the downstream KGSL driver - no crashes there, ever. Add support for this GPU on the kernel side, which comes down to pretty simply adding A612 HWCG tables, altering a few values and adding a special case for handling the reset line. Reviewed-by: Dmitry Baryshkov Signed-off-by: Konrad Dybcio --- drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 97 ++++++++++++++++++++++++++= +--- drivers/gpu/drm/msm/adreno/adreno_device.c | 12 ++++ drivers/gpu/drm/msm/adreno/adreno_gpu.h | 8 ++- 3 files changed, 107 insertions(+), 10 deletions(-) diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/ad= reno/a6xx_gpu.c index 1c0e5e1df89c..776db13e2a26 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c @@ -254,6 +254,56 @@ static void a6xx_submit(struct msm_gpu *gpu, struct ms= m_gem_submit *submit) a6xx_flush(gpu, ring); } =20 +const struct adreno_reglist a612_hwcg[] =3D { + {REG_A6XX_RBBM_CLOCK_CNTL_SP0, 0x22222222}, + {REG_A6XX_RBBM_CLOCK_CNTL2_SP0, 0x02222220}, + {REG_A6XX_RBBM_CLOCK_DELAY_SP0, 0x00000081}, + {REG_A6XX_RBBM_CLOCK_HYST_SP0, 0x0000f3cf}, + {REG_A6XX_RBBM_CLOCK_CNTL_TP0, 0x22222222}, + {REG_A6XX_RBBM_CLOCK_CNTL2_TP0, 0x22222222}, + {REG_A6XX_RBBM_CLOCK_CNTL3_TP0, 0x22222222}, + {REG_A6XX_RBBM_CLOCK_CNTL4_TP0, 0x00022222}, + {REG_A6XX_RBBM_CLOCK_DELAY_TP0, 0x11111111}, + {REG_A6XX_RBBM_CLOCK_DELAY2_TP0, 0x11111111}, + {REG_A6XX_RBBM_CLOCK_DELAY3_TP0, 0x11111111}, + {REG_A6XX_RBBM_CLOCK_DELAY4_TP0, 0x00011111}, + {REG_A6XX_RBBM_CLOCK_HYST_TP0, 0x77777777}, + {REG_A6XX_RBBM_CLOCK_HYST2_TP0, 0x77777777}, + {REG_A6XX_RBBM_CLOCK_HYST3_TP0, 0x77777777}, + {REG_A6XX_RBBM_CLOCK_HYST4_TP0, 0x00077777}, + {REG_A6XX_RBBM_CLOCK_CNTL_RB0, 0x22222222}, + {REG_A6XX_RBBM_CLOCK_CNTL2_RB0, 0x01202222}, + {REG_A6XX_RBBM_CLOCK_CNTL_CCU0, 0x00002220}, + {REG_A6XX_RBBM_CLOCK_HYST_RB_CCU0, 0x00040f00}, + {REG_A6XX_RBBM_CLOCK_CNTL_RAC, 0x05522022}, + {REG_A6XX_RBBM_CLOCK_CNTL2_RAC, 0x00005555}, + {REG_A6XX_RBBM_CLOCK_DELAY_RAC, 0x00000011}, + {REG_A6XX_RBBM_CLOCK_HYST_RAC, 0x00445044}, + {REG_A6XX_RBBM_CLOCK_CNTL_TSE_RAS_RBBM, 0x04222222}, + {REG_A6XX_RBBM_CLOCK_MODE_VFD, 0x00002222}, + {REG_A6XX_RBBM_CLOCK_MODE_GPC, 0x02222222}, + {REG_A6XX_RBBM_CLOCK_DELAY_HLSQ_2, 0x00000002}, + {REG_A6XX_RBBM_CLOCK_MODE_HLSQ, 0x00002222}, + {REG_A6XX_RBBM_CLOCK_DELAY_TSE_RAS_RBBM, 0x00004000}, + {REG_A6XX_RBBM_CLOCK_DELAY_VFD, 0x00002222}, + {REG_A6XX_RBBM_CLOCK_DELAY_GPC, 0x00000200}, + {REG_A6XX_RBBM_CLOCK_DELAY_HLSQ, 0x00000000}, + {REG_A6XX_RBBM_CLOCK_HYST_TSE_RAS_RBBM, 0x00000000}, + {REG_A6XX_RBBM_CLOCK_HYST_VFD, 0x00000000}, + {REG_A6XX_RBBM_CLOCK_HYST_GPC, 0x04104004}, + {REG_A6XX_RBBM_CLOCK_HYST_HLSQ, 0x00000000}, + {REG_A6XX_RBBM_CLOCK_CNTL_UCHE, 0x22222222}, + {REG_A6XX_RBBM_CLOCK_HYST_UCHE, 0x00000004}, + {REG_A6XX_RBBM_CLOCK_DELAY_UCHE, 0x00000002}, + {REG_A6XX_RBBM_ISDB_CNT, 0x00000182}, + {REG_A6XX_RBBM_RAC_THRESHOLD_CNT, 0x00000000}, + {REG_A6XX_RBBM_SP_HYST_CNT, 0x00000000}, + {REG_A6XX_RBBM_CLOCK_CNTL_GMU_GX, 0x00000222}, + {REG_A6XX_RBBM_CLOCK_DELAY_GMU_GX, 0x00000111}, + {REG_A6XX_RBBM_CLOCK_HYST_GMU_GX, 0x00000555}, + {}, +}; + /* For a615 family (a615, a616, a618 and a619) */ const struct adreno_reglist a615_hwcg[] =3D { {REG_A6XX_RBBM_CLOCK_CNTL_SP0, 0x02222222}, @@ -604,6 +654,8 @@ static void a6xx_set_hwcg(struct msm_gpu *gpu, bool sta= te) =20 if (adreno_is_a630(adreno_gpu)) clock_cntl_on =3D 0x8aa8aa02; + else if (adreno_is_a610(adreno_gpu)) + clock_cntl_on =3D 0xaaa8aa82; else clock_cntl_on =3D 0x8aa8aa82; =20 @@ -812,6 +864,13 @@ static void a6xx_set_ubwc_config(struct msm_gpu *gpu) /* Unknown, introduced with A640/680 */ u32 amsbc =3D 0; =20 + if (adreno_is_a610(adreno_gpu)) { + /* HBB =3D 14 */ + hbb_lo =3D 1; + min_acc_len =3D 1; + ubwc_mode =3D 1; + } + /* a618 is using the hw default values */ if (adreno_is_a618(adreno_gpu)) return; @@ -1063,13 +1122,13 @@ static int hw_init(struct msm_gpu *gpu) a6xx_set_hwcg(gpu, true); =20 /* VBIF/GBIF start*/ - if (adreno_is_a640_family(adreno_gpu) || + if (adreno_is_a610(adreno_gpu) || + adreno_is_a640_family(adreno_gpu) || adreno_is_a650_family(adreno_gpu)) { gpu_write(gpu, REG_A6XX_GBIF_QSB_SIDE0, 0x00071620); gpu_write(gpu, REG_A6XX_GBIF_QSB_SIDE1, 0x00071620); gpu_write(gpu, REG_A6XX_GBIF_QSB_SIDE2, 0x00071620); gpu_write(gpu, REG_A6XX_GBIF_QSB_SIDE3, 0x00071620); - gpu_write(gpu, REG_A6XX_GBIF_QSB_SIDE3, 0x00071620); gpu_write(gpu, REG_A6XX_RBBM_GBIF_CLIENT_QOS_CNTL, 0x3); } else { gpu_write(gpu, REG_A6XX_RBBM_VBIF_CLIENT_QOS_CNTL, 0x3); @@ -1100,18 +1159,26 @@ static int hw_init(struct msm_gpu *gpu) gpu_write(gpu, REG_A6XX_UCHE_FILTER_CNTL, 0x804); gpu_write(gpu, REG_A6XX_UCHE_CACHE_WAYS, 0x4); =20 - if (adreno_is_a640_family(adreno_gpu) || - adreno_is_a650_family(adreno_gpu)) + if (adreno_is_a640_family(adreno_gpu) || adreno_is_a650_family(adreno_gpu= )) { gpu_write(gpu, REG_A6XX_CP_ROQ_THRESHOLDS_2, 0x02000140); - else + gpu_write(gpu, REG_A6XX_CP_ROQ_THRESHOLDS_1, 0x8040362c); + } else if (adreno_is_a610(adreno_gpu)) { + gpu_write(gpu, REG_A6XX_CP_ROQ_THRESHOLDS_2, 0x00800060); + gpu_write(gpu, REG_A6XX_CP_ROQ_THRESHOLDS_1, 0x40201b16); + } else { gpu_write(gpu, REG_A6XX_CP_ROQ_THRESHOLDS_2, 0x010000c0); - gpu_write(gpu, REG_A6XX_CP_ROQ_THRESHOLDS_1, 0x8040362c); + gpu_write(gpu, REG_A6XX_CP_ROQ_THRESHOLDS_1, 0x8040362c); + } =20 if (adreno_is_a660_family(adreno_gpu)) gpu_write(gpu, REG_A6XX_CP_LPAC_PROG_FIFO_SIZE, 0x00000020); =20 /* Setting the mem pool size */ - gpu_write(gpu, REG_A6XX_CP_MEM_POOL_SIZE, 128); + if (adreno_is_a610(adreno_gpu)) { + gpu_write(gpu, REG_A6XX_CP_MEM_POOL_SIZE, 48); + gpu_write(gpu, REG_A6XX_CP_MEM_POOL_DBG_ADDR, 47); + } else + gpu_write(gpu, REG_A6XX_CP_MEM_POOL_SIZE, 128); =20 /* Setting the primFifo thresholds default values, * and vccCacheSkipDis=3D1 bit (0x200) for A640 and newer @@ -1122,6 +1189,8 @@ static int hw_init(struct msm_gpu *gpu) gpu_write(gpu, REG_A6XX_PC_DBG_ECO_CNTL, 0x00200200); else if (adreno_is_a650(adreno_gpu) || adreno_is_a660(adreno_gpu)) gpu_write(gpu, REG_A6XX_PC_DBG_ECO_CNTL, 0x00300200); + else if (adreno_is_a610(adreno_gpu)) + gpu_write(gpu, REG_A6XX_PC_DBG_ECO_CNTL, 0x00080000); else gpu_write(gpu, REG_A6XX_PC_DBG_ECO_CNTL, 0x00180000); =20 @@ -1137,8 +1206,10 @@ static int hw_init(struct msm_gpu *gpu) a6xx_set_ubwc_config(gpu); =20 /* Enable fault detection */ - gpu_write(gpu, REG_A6XX_RBBM_INTERFACE_HANG_INT_CNTL, - (1 << 30) | 0x1fffff); + if (adreno_is_a610(adreno_gpu)) + gpu_write(gpu, REG_A6XX_RBBM_INTERFACE_HANG_INT_CNTL, (1 << 30) | 0x3fff= f); + else + gpu_write(gpu, REG_A6XX_RBBM_INTERFACE_HANG_INT_CNTL, (1 << 30) | 0x1fff= ff); =20 gpu_write(gpu, REG_A6XX_UCHE_CLIENT_PF, 1); =20 @@ -1372,6 +1443,14 @@ static void a6xx_recover(struct msm_gpu *gpu) =20 /* Software-reset the GPU */ if (adreno_has_gmu_wrapper(adreno_gpu)) { + /* 11nm chips (i.e. A610-hosting ones) have HW issues with the reset lin= e */ + if (!adreno_is_a610(adreno_gpu)) { + gpu_write(gpu, REG_A6XX_RBBM_SW_RESET_CMD, 1); + gpu_read(gpu, REG_A6XX_RBBM_SW_RESET_CMD); + udelay(100); + gpu_write(gpu, REG_A6XX_RBBM_SW_RESET_CMD, 0); + } + if (adreno_is_a619_holi(adreno_gpu)) { gpu_write(gpu, 0x18, GPR0_GBIF_HALT_REQUEST); spin_until((gpu_read(gpu, REG_A6XX_RBBM_VBIF_GX_RESET_STATUS) & diff --git a/drivers/gpu/drm/msm/adreno/adreno_device.c b/drivers/gpu/drm/m= sm/adreno/adreno_device.c index 6513c6094865..17db8e99ff88 100644 --- a/drivers/gpu/drm/msm/adreno/adreno_device.c +++ b/drivers/gpu/drm/msm/adreno/adreno_device.c @@ -253,6 +253,18 @@ static const struct adreno_info gpulist[] =3D { .quirks =3D ADRENO_QUIRK_LMLOADKILL_DISABLE, .init =3D a5xx_gpu_init, .zapfw =3D "a540_zap.mdt", + }, { + .rev =3D ADRENO_REV(6, 1, 0, ANY_ID), + .revn =3D 610, + .name =3D "A610", + .fw =3D { + [ADRENO_FW_SQE] =3D "a630_sqe.fw", + }, + .gmem =3D (SZ_128K + SZ_4K), + .inactive_period =3D 500, + .init =3D a6xx_gpu_init, + .zapfw =3D "a610_zap.mdt", + .hwcg =3D a612_hwcg, }, { .rev =3D ADRENO_REV(6, 1, 8, ANY_ID), .revn =3D 618, diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.h b/drivers/gpu/drm/msm/= adreno/adreno_gpu.h index 92ece15ec7d8..27c30a7694f4 100644 --- a/drivers/gpu/drm/msm/adreno/adreno_gpu.h +++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.h @@ -55,7 +55,8 @@ struct adreno_reglist { u32 value; }; =20 -extern const struct adreno_reglist a615_hwcg[], a630_hwcg[], a640_hwcg[], = a650_hwcg[], a660_hwcg[]; +extern const struct adreno_reglist a612_hwcg[], a615_hwcg[], a630_hwcg[], = a640_hwcg[], a650_hwcg[]; +extern const struct adreno_reglist a660_hwcg[]; =20 struct adreno_info { struct adreno_rev rev; @@ -242,6 +243,11 @@ static inline int adreno_is_a540(struct adreno_gpu *gp= u) return gpu->revn =3D=3D 540; } =20 +static inline int adreno_is_a610(struct adreno_gpu *gpu) +{ + return gpu->revn =3D=3D 610; +} + static inline int adreno_is_a618(struct adreno_gpu *gpu) { return gpu->revn =3D=3D 618; --=20 2.39.2 From nobody Wed Feb 11 13:06:20 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id AC1FEC6FD1C for ; Tue, 14 Mar 2023 15:29:32 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230221AbjCNP3a (ORCPT ); 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[83.9.29.16]) by smtp.gmail.com with ESMTPSA id 27-20020a2e165b000000b002986a977bf2sm491529ljw.90.2023.03.14.08.28.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 14 Mar 2023 08:28:54 -0700 (PDT) From: Konrad Dybcio Date: Tue, 14 Mar 2023 16:28:41 +0100 Subject: [PATCH v4 10/14] drm/msm/a6xx: Fix some A619 tunables MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20230223-topic-gmuwrapper-v4-10-e987eb79d03f@linaro.org> References: <20230223-topic-gmuwrapper-v4-0-e987eb79d03f@linaro.org> In-Reply-To: <20230223-topic-gmuwrapper-v4-0-e987eb79d03f@linaro.org> To: Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , David Airlie , Daniel Vetter , Rob Herring , Krzysztof Kozlowski , Bjorn Andersson , Konrad Dybcio , Akhil P Oommen Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Rob Clark , Marijn Suijten , Konrad Dybcio X-Mailer: b4 0.12.1 X-Developer-Signature: v=1; a=ed25519-sha256; t=1678807716; l=1537; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=WDcj/M9aJ/8+tdxnVyFZAeDamawmN6hQgw+VzGKE91s=; b=T/5InnJU8B58RuzS79qY+AAoksalL8zOQ+JCAG2th1CRtFEh87n1KTepybkSWQo5GP+tt8vPUvkn 2Rj3TBOJD5wBtfFVeCWxK/FzGecgL0PHuYjTC/Z1POdGewZZIxo7 X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Adreno 619 expects some tunables to be set differently. Make up for it. Fixes: b7616b5c69e6 ("drm/msm/adreno: Add A619 support") Reviewed-by: Dmitry Baryshkov Signed-off-by: Konrad Dybcio --- drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/ad= reno/a6xx_gpu.c index 776db13e2a26..f699f326021f 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c @@ -1189,6 +1189,8 @@ static int hw_init(struct msm_gpu *gpu) gpu_write(gpu, REG_A6XX_PC_DBG_ECO_CNTL, 0x00200200); else if (adreno_is_a650(adreno_gpu) || adreno_is_a660(adreno_gpu)) gpu_write(gpu, REG_A6XX_PC_DBG_ECO_CNTL, 0x00300200); + else if (adreno_is_a619(adreno_gpu)) + gpu_write(gpu, REG_A6XX_PC_DBG_ECO_CNTL, 0x00018000); else if (adreno_is_a610(adreno_gpu)) gpu_write(gpu, REG_A6XX_PC_DBG_ECO_CNTL, 0x00080000); else @@ -1206,7 +1208,9 @@ static int hw_init(struct msm_gpu *gpu) a6xx_set_ubwc_config(gpu); =20 /* Enable fault detection */ - if (adreno_is_a610(adreno_gpu)) + if (adreno_is_a619(adreno_gpu)) + gpu_write(gpu, REG_A6XX_RBBM_INTERFACE_HANG_INT_CNTL, (1 << 30) | 0x3fff= ff); + else if (adreno_is_a610(adreno_gpu)) gpu_write(gpu, REG_A6XX_RBBM_INTERFACE_HANG_INT_CNTL, (1 << 30) | 0x3fff= f); else gpu_write(gpu, REG_A6XX_RBBM_INTERFACE_HANG_INT_CNTL, (1 << 30) | 0x1fff= ff); --=20 2.39.2 From nobody Wed Feb 11 13:06:20 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 97467C7618E for ; Tue, 14 Mar 2023 15:30:09 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231354AbjCNPaH (ORCPT ); Tue, 14 Mar 2023 11:30:07 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:59542 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231740AbjCNP3J (ORCPT ); Tue, 14 Mar 2023 11:29:09 -0400 Received: from mail-lj1-x230.google.com (mail-lj1-x230.google.com [IPv6:2a00:1450:4864:20::230]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 6E55056157 for ; Tue, 14 Mar 2023 08:28:58 -0700 (PDT) Received: by mail-lj1-x230.google.com with SMTP id i20so16400323lja.11 for ; Tue, 14 Mar 2023 08:28:58 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1678807736; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=fdwglER2agYNfLVPprMx0FPmVS9IVmz+s6GuV4eeQlY=; b=lKp64Clb2weIN9LxcJaV7Z/cFUCUng+k5gejt9AiaR21/aN4vDzDPvhnnqAQMxtLvV 5cOdn/hBnhe521EMwa26x2IMAoVau/YhZvrGCymgpYmFAjVmE4YoaneoXvU7QYVV7W09 RJtavZi4t2J2NbcXXQBlGm0z6Pf2M7AQk/z+x01Veig1sikXb4vVqjSRBV/nCuI0Rfmu mr+1Mb31xbNiAp7QmC9neHPhs7XiuwXNWQz4ZSOaKk5wLWzg8cCL3nX0vmkV5xz1Adso B+Zu+3Gy52wzS20RAj2X5SAw4SsTsYyB87kRExR1LSx7g1G4NyeiZSQqvPk79SU0ABMb TUkA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1678807736; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=fdwglER2agYNfLVPprMx0FPmVS9IVmz+s6GuV4eeQlY=; b=KoMfVRoXZwm/73Aeck17VO3BVwEH6O4cfQEgmZUaKoWr2f4DoWMVJIXVcf53JsE9Nf oIQ5OjIiUGoWIvrG6AOVNHUbVydBlfFasGfjjrmK7XjvBIjve2rPWf/1pKWD5L4ricSy MAt8GNu3w9M40RghnPp3Zs642gyFbrzalofIw8drjTy30WKh9suxRfJVBrQQ42xFBaW5 h6oqMsMepZbVnzjf7iY4iPAJY9Th4+YvcLhO6fQ1wCcVJWW8fKYPeEdisUG+b0rFtyAG Co/5PHQt7HForrvR6tMZAX5++EkrqN3jNVBqmRSGE0dWzKhOFO/yBfd3OyGOalWy5DwC PuiQ== X-Gm-Message-State: AO0yUKUcB+393oDblQtTAcmWFqf8XLLJe7braltywZ1Lx4nY0PsuV2Wt 3ZYTqMEv5R9Qt83osXEuQQwL1A== X-Google-Smtp-Source: AK7set8fnrIyrdBk2/7gj5cpgSgzt/Xfpampum2BodPGgG8qvmvSrr5Oz8Aau3qXEqeqcc4co8j24Q== X-Received: by 2002:a05:651c:2211:b0:298:6e2e:2224 with SMTP id y17-20020a05651c221100b002986e2e2224mr9543190ljq.47.1678807736338; Tue, 14 Mar 2023 08:28:56 -0700 (PDT) Received: from [192.168.1.101] (abyj16.neoplus.adsl.tpnet.pl. [83.9.29.16]) by smtp.gmail.com with ESMTPSA id 27-20020a2e165b000000b002986a977bf2sm491529ljw.90.2023.03.14.08.28.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 14 Mar 2023 08:28:56 -0700 (PDT) From: Konrad Dybcio Date: Tue, 14 Mar 2023 16:28:42 +0100 Subject: [PATCH v4 11/14] drm/msm/a6xx: Use "else if" in GPU speedbin rev matching MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20230223-topic-gmuwrapper-v4-11-e987eb79d03f@linaro.org> References: <20230223-topic-gmuwrapper-v4-0-e987eb79d03f@linaro.org> In-Reply-To: <20230223-topic-gmuwrapper-v4-0-e987eb79d03f@linaro.org> To: Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , David Airlie , Daniel Vetter , Rob Herring , Krzysztof Kozlowski , Bjorn Andersson , Konrad Dybcio , Akhil P Oommen Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Rob Clark , Marijn Suijten , Konrad Dybcio X-Mailer: b4 0.12.1 X-Developer-Signature: v=1; a=ed25519-sha256; t=1678807716; l=1434; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=D3QGn+nYvlP8x3swaH1kHJwlzdjGFbaFa9zhDHv4lx4=; b=ZOerBhWO9wapKFAmKihwL/xjhmOBckfMZSqJGmKAHuDSBy94K3mEfpFoTQaJo9CdyzfCJdViZmhq 8ZeJc1z3BqzNORvpz6NPoC45eGj51K48M3uSZAPNbuiTEVkmGm0I X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The GPU can only be one at a time. Turn a series of ifs into if + elseifs to save some CPU cycles. Reviewed-by: Dmitry Baryshkov Signed-off-by: Konrad Dybcio --- drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/ad= reno/a6xx_gpu.c index f699f326021f..dfd2d735e57f 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c @@ -2207,16 +2207,16 @@ static u32 fuse_to_supp_hw(struct device *dev, stru= ct adreno_rev rev, u32 fuse) if (adreno_cmp_rev(ADRENO_REV(6, 1, 8, ANY_ID), rev)) val =3D a618_get_speed_bin(fuse); =20 - if (adreno_cmp_rev(ADRENO_REV(6, 1, 9, ANY_ID), rev)) + else if (adreno_cmp_rev(ADRENO_REV(6, 1, 9, ANY_ID), rev)) val =3D a619_get_speed_bin(fuse); =20 - if (adreno_cmp_rev(ADRENO_REV(6, 3, 5, ANY_ID), rev)) + else if (adreno_cmp_rev(ADRENO_REV(6, 3, 5, ANY_ID), rev)) val =3D adreno_7c3_get_speed_bin(fuse); =20 - if (adreno_cmp_rev(ADRENO_REV(6, 4, 0, ANY_ID), rev)) + else if (adreno_cmp_rev(ADRENO_REV(6, 4, 0, ANY_ID), rev)) val =3D a640_get_speed_bin(fuse); =20 - if (adreno_cmp_rev(ADRENO_REV(6, 5, 0, ANY_ID), rev)) + else if (adreno_cmp_rev(ADRENO_REV(6, 5, 0, ANY_ID), rev)) val =3D a650_get_speed_bin(fuse); =20 if (val =3D=3D UINT_MAX) { --=20 2.39.2 From nobody Wed Feb 11 13:06:20 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id EF43FC6FD1C for ; Tue, 14 Mar 2023 15:29:40 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231482AbjCNP3h (ORCPT ); Tue, 14 Mar 2023 11:29:37 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:58556 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229999AbjCNP3I (ORCPT ); Tue, 14 Mar 2023 11:29:08 -0400 Received: from mail-lj1-x236.google.com (mail-lj1-x236.google.com [IPv6:2a00:1450:4864:20::236]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 70B0E6BC1F for ; Tue, 14 Mar 2023 08:28:58 -0700 (PDT) Received: by mail-lj1-x236.google.com with SMTP id f16so16402629ljq.10 for ; Tue, 14 Mar 2023 08:28:58 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1678807738; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=b3xe4S3Sg3+fXQE7o6Jl9Wyr4UR5G14unF7soZYaMbg=; b=QZm8aOm8RbNlY40Q4XQU5d2gjJPbZzE/EPGKd9wIFP3yFDp4M3cFgET0nkBnXMXe/L bEm79j/TVkoRw9F/2BGgKcTpiB6bky/NEmE9CkdF1Z/Zt8U8C39U244fW229NNObm34/ ccvJGgfuH4axu1SJlvkP/6/4XO+BwbpLyyiFz6GRw87GBHcW+XBsZDK4hAKZFGo+cuOo DarmyslHPlLwRnDH/H/zNfF59z1r1exJ0qGBHH2zx/iuB2WjeuJB1ULy0DtcSbOCDMZO sP5NL6fM6M6Txdr9OTPBSZJem424Ayv4dnyf+wAht8gy5tn7P6ezpWFnvf1QofADTlXo +2dw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1678807738; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=b3xe4S3Sg3+fXQE7o6Jl9Wyr4UR5G14unF7soZYaMbg=; b=Gy5fIuR2nxz6e4r22nX6KfD5rrWvJDmhHXSV5V3biJgddj/4ad7ujr8KRroiZt4eeE r1270cJImAlw+fZ6UJZFkhGJalzSGTUPGWoLb1XG1auUvCvYiCm5nT0QvdzoON2nc53v br5O6pIiBdXuoUu5DlQJ2QH6uMaLWZHWwvCtn7ZcTu+YyNOxF9DS2xF0b6Rlewg/YeUA XeG9F3BWZgHlDAKpWFaRGTt1kbEBltbQycz4xvPDnzVTru+h5HB+mykWgrk4LYAeKUea q6vUFjxUARcEGhSY9u/ynFoNfSwYogkP8Zh/jxdZs350PqySviz7D4PZj0RuReUUYaEd tn+Q== X-Gm-Message-State: AO0yUKW7iUsVNFvIJpChiV91dOeNJPlVonMsg2wrWHkcliSsv+GnLXoT /NZT93qtTH6YrD6+JVUU9LA4yg== X-Google-Smtp-Source: AK7set/2lSTktOe20S80TTlPoFxsu2prw745PLGWGmCVZbk7wNrpyh/pjHPJ2hOD260NzZex7zfetA== X-Received: by 2002:a2e:8807:0:b0:295:9a9f:3f55 with SMTP id x7-20020a2e8807000000b002959a9f3f55mr11475513ljh.0.1678807737857; Tue, 14 Mar 2023 08:28:57 -0700 (PDT) Received: from [192.168.1.101] (abyj16.neoplus.adsl.tpnet.pl. [83.9.29.16]) by smtp.gmail.com with ESMTPSA id 27-20020a2e165b000000b002986a977bf2sm491529ljw.90.2023.03.14.08.28.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 14 Mar 2023 08:28:57 -0700 (PDT) From: Konrad Dybcio Date: Tue, 14 Mar 2023 16:28:43 +0100 Subject: [PATCH v4 12/14] drm/msm/a6xx: Use adreno_is_aXYZ macros in speedbin matching MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20230223-topic-gmuwrapper-v4-12-e987eb79d03f@linaro.org> References: <20230223-topic-gmuwrapper-v4-0-e987eb79d03f@linaro.org> In-Reply-To: <20230223-topic-gmuwrapper-v4-0-e987eb79d03f@linaro.org> To: Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , David Airlie , Daniel Vetter , Rob Herring , Krzysztof Kozlowski , Bjorn Andersson , Konrad Dybcio , Akhil P Oommen Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Rob Clark , Marijn Suijten , Konrad Dybcio X-Mailer: b4 0.12.1 X-Developer-Signature: v=1; a=ed25519-sha256; t=1678807716; l=4256; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=k8ecRBr+PHIYBEN3eyTaSM0Q8/LOQMVQTU2+Qd88W0A=; b=3gvGXi1wDp8tvJizG2mCmembimJ6NEiodLsZGbAy715EhpeRtk7EXD8RLR26pFDIaz0VuTQeZ6k/ aWuHcLqxBjAMtTLuKKm/kvw2K8xAB56xwcwGeEjUcfSn3z7+hmO7 X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Before transitioning to using per-SoC and not per-Adreno speedbin fuse values (need another patchset to land elsewhere), a good improvement/stopgap solution is to use adreno_is_aXYZ macros in place of explicit revision matching. Do so to allow differentiating between A619 and A619_holi. Signed-off-by: Konrad Dybcio Reviewed-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 18 +++++++++--------- drivers/gpu/drm/msm/adreno/adreno_gpu.h | 14 ++++++++++++-- 2 files changed, 21 insertions(+), 11 deletions(-) diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/ad= reno/a6xx_gpu.c index dfd2d735e57f..71950a5fcc96 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c @@ -2200,23 +2200,23 @@ static u32 adreno_7c3_get_speed_bin(u32 fuse) return UINT_MAX; } =20 -static u32 fuse_to_supp_hw(struct device *dev, struct adreno_rev rev, u32 = fuse) +static u32 fuse_to_supp_hw(struct device *dev, struct adreno_gpu *adreno_g= pu, u32 fuse) { u32 val =3D UINT_MAX; =20 - if (adreno_cmp_rev(ADRENO_REV(6, 1, 8, ANY_ID), rev)) + if (adreno_is_a618(adreno_gpu)) val =3D a618_get_speed_bin(fuse); =20 - else if (adreno_cmp_rev(ADRENO_REV(6, 1, 9, ANY_ID), rev)) + else if (adreno_is_a619(adreno_gpu)) val =3D a619_get_speed_bin(fuse); =20 - else if (adreno_cmp_rev(ADRENO_REV(6, 3, 5, ANY_ID), rev)) + else if (adreno_is_7c3(adreno_gpu)) val =3D adreno_7c3_get_speed_bin(fuse); =20 - else if (adreno_cmp_rev(ADRENO_REV(6, 4, 0, ANY_ID), rev)) + else if (adreno_is_a640(adreno_gpu)) val =3D a640_get_speed_bin(fuse); =20 - else if (adreno_cmp_rev(ADRENO_REV(6, 5, 0, ANY_ID), rev)) + else if (adreno_is_a650(adreno_gpu)) val =3D a650_get_speed_bin(fuse); =20 if (val =3D=3D UINT_MAX) { @@ -2229,7 +2229,7 @@ static u32 fuse_to_supp_hw(struct device *dev, struct= adreno_rev rev, u32 fuse) return (1 << val); } =20 -static int a6xx_set_supported_hw(struct device *dev, struct adreno_rev rev) +static int a6xx_set_supported_hw(struct device *dev, struct adreno_gpu *ad= reno_gpu) { u32 supp_hw; u32 speedbin; @@ -2248,7 +2248,7 @@ static int a6xx_set_supported_hw(struct device *dev, = struct adreno_rev rev) return ret; } =20 - supp_hw =3D fuse_to_supp_hw(dev, rev, speedbin); + supp_hw =3D fuse_to_supp_hw(dev, adreno_gpu, speedbin); =20 ret =3D devm_pm_opp_set_supported_hw(dev, &supp_hw, 1); if (ret) @@ -2367,7 +2367,7 @@ struct msm_gpu *a6xx_gpu_init(struct drm_device *dev) if (!adreno_has_gmu_wrapper(adreno_gpu)) a6xx_llc_slices_init(pdev, a6xx_gpu); =20 - ret =3D a6xx_set_supported_hw(&pdev->dev, config->rev); + ret =3D a6xx_set_supported_hw(&pdev->dev, adreno_gpu); if (ret) { a6xx_destroy(&(a6xx_gpu->base.base)); return ERR_PTR(ret); diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.h b/drivers/gpu/drm/msm/= adreno/adreno_gpu.h index 27c30a7694f4..da9f45a13b5d 100644 --- a/drivers/gpu/drm/msm/adreno/adreno_gpu.h +++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.h @@ -268,9 +268,9 @@ static inline int adreno_is_a630(struct adreno_gpu *gpu) return gpu->revn =3D=3D 630; } =20 -static inline int adreno_is_a640_family(struct adreno_gpu *gpu) +static inline int adreno_is_a640(struct adreno_gpu *gpu) { - return (gpu->revn =3D=3D 640) || (gpu->revn =3D=3D 680); + return gpu->revn =3D=3D 640; } =20 static inline int adreno_is_a650(struct adreno_gpu *gpu) @@ -289,6 +289,11 @@ static inline int adreno_is_a660(struct adreno_gpu *gp= u) return gpu->revn =3D=3D 660; } =20 +static inline int adreno_is_a680(struct adreno_gpu *gpu) +{ + return gpu->revn =3D=3D 680; +} + /* check for a615, a616, a618, a619 or any derivatives */ static inline int adreno_is_a615_family(struct adreno_gpu *gpu) { @@ -306,6 +311,11 @@ static inline int adreno_is_a650_family(struct adreno_= gpu *gpu) return gpu->revn =3D=3D 650 || gpu->revn =3D=3D 620 || adreno_is_a660_fam= ily(gpu); } =20 +static inline int adreno_is_a640_family(struct adreno_gpu *gpu) +{ + return adreno_is_a640(gpu) || adreno_is_a680(gpu); +} + u64 adreno_private_address_space_size(struct msm_gpu *gpu); int adreno_get_param(struct msm_gpu *gpu, struct msm_file_private *ctx, uint32_t param, uint64_t *value, uint32_t *len); --=20 2.39.2 From nobody Wed Feb 11 13:06:21 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0DBC5C6FD1D for ; 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[83.9.29.16]) by smtp.gmail.com with ESMTPSA id 27-20020a2e165b000000b002986a977bf2sm491529ljw.90.2023.03.14.08.28.58 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 14 Mar 2023 08:28:59 -0700 (PDT) From: Konrad Dybcio Date: Tue, 14 Mar 2023 16:28:44 +0100 Subject: [PATCH v4 13/14] drm/msm/a6xx: Add A619_holi speedbin support MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20230223-topic-gmuwrapper-v4-13-e987eb79d03f@linaro.org> References: <20230223-topic-gmuwrapper-v4-0-e987eb79d03f@linaro.org> In-Reply-To: <20230223-topic-gmuwrapper-v4-0-e987eb79d03f@linaro.org> To: Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , David Airlie , Daniel Vetter , Rob Herring , Krzysztof Kozlowski , Bjorn Andersson , Konrad Dybcio , Akhil P Oommen Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Rob Clark , Marijn Suijten , Konrad Dybcio X-Mailer: b4 0.12.1 X-Developer-Signature: v=1; a=ed25519-sha256; t=1678807716; l=1972; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=YbHID1ebzUgv4FADFLbdTcRo/0BAqs1RT5mt5WqUfTo=; b=s3HhnOhKViZbWBYgyMxuzL4UDJa8iVASyV+mQYW3iO3PGPZl+eP/2Aeaw6ZMhwFz3SwSFoCG0y33 Q/Rx0heHCR/EvUr6sEUzL8fuAOHOSGF3DRC9eEc/4mROb2FGKAb7 X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org A619_holi is implemented on at least two SoCs: SM4350 (holi) and SM6375 (blair). This is what seems to be a first occurrence of this happening, but it's easy to overcome by guarding the SoC-specific fuse values with of_machine_is_compatible(). Do just that to enable frequency limiting on these SoCs. Signed-off-by: Konrad Dybcio Reviewed-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 31 +++++++++++++++++++++++++++++++ 1 file changed, 31 insertions(+) diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/ad= reno/a6xx_gpu.c index 71950a5fcc96..27b96a335039 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c @@ -2148,6 +2148,34 @@ static u32 a618_get_speed_bin(u32 fuse) return UINT_MAX; } =20 +static u32 a619_holi_get_speed_bin(u32 fuse) +{ + /* + * There are (at least) two SoCs implementing A619_holi: SM4350 (holi) + * and SM6375 (blair). Limit the fuse matching to the corresponding + * SoC to prevent bogus frequency setting (as improbable as it may be, + * given unexpected fuse values are.. unexpected! But still possible.) + */ + + if (fuse =3D=3D 0) + return 0; + + if (of_machine_is_compatible("qcom,sm4350")) { + if (fuse =3D=3D 138) + return 1; + else if (fuse =3D=3D 92) + return 2; + } else if (of_machine_is_compatible("qcom,sm6375")) { + if (fuse =3D=3D 190) + return 1; + else if (fuse =3D=3D 177) + return 2; + } else + pr_warn("Unknown SoC implementing A619_holi!\n"); + + return UINT_MAX; +} + static u32 a619_get_speed_bin(u32 fuse) { if (fuse =3D=3D 0) @@ -2207,6 +2235,9 @@ static u32 fuse_to_supp_hw(struct device *dev, struct= adreno_gpu *adreno_gpu, u3 if (adreno_is_a618(adreno_gpu)) val =3D a618_get_speed_bin(fuse); =20 + else if (adreno_is_a619_holi(adreno_gpu)) + val =3D a619_holi_get_speed_bin(fuse); + else if (adreno_is_a619(adreno_gpu)) val =3D a619_get_speed_bin(fuse); =20 --=20 2.39.2 From nobody Wed Feb 11 13:06:21 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 06DAEC6FD1D for ; Tue, 14 Mar 2023 15:30:18 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231718AbjCNPaP (ORCPT ); Tue, 14 Mar 2023 11:30:15 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:60310 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231690AbjCNP3X (ORCPT ); Tue, 14 Mar 2023 11:29:23 -0400 Received: from mail-lj1-x22f.google.com (mail-lj1-x22f.google.com [IPv6:2a00:1450:4864:20::22f]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 88C6C62DAF for ; Tue, 14 Mar 2023 08:29:02 -0700 (PDT) Received: by mail-lj1-x22f.google.com with SMTP id h9so16425051ljq.2 for ; Tue, 14 Mar 2023 08:29:02 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1678807741; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=/rMi4z3KYpk1VOXDtleM/+v4nMkai2X+NZaj5fWAot0=; b=GV/tteMajEXLkq7QRWvhGA9tMlhuJp/N2TPtYTY0YtLZQlTqkOTuIJ+KJwU0HqvSND xGSr/TymnSrZqWdGV3dGwJHCHSX1GpSUcYgNQe/A8PGmW7SKKznrUpk5ALLQAEMeG9rx /XG2RkujzSZ+Ciah38NKKTrq7vN5WRpzPlvjCFFRy/bNyFYfVt8Ef5kxiuulvIT59XoI vXAa566h15OVTxr35Iz+0GhOW2Nhhnr+7TqUu03lv+f2t6bBBKynYOG4NnrqcVpOFWKJ Zy+TVLtPGwdAQWe9s5RudeIOFXfuel+dLMcI4I3dKyvLmaAfUblEGKcxmRuzgLfwKDD1 HIdQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1678807741; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=/rMi4z3KYpk1VOXDtleM/+v4nMkai2X+NZaj5fWAot0=; b=VJAXRSQxNz/iNAH6fdBct89K6AN7Qk7TDcnM9eA3MGd01dMoVgQeamP+L2GBRILUkJ LqL3UNh9OLBmPDFT7NOqAUtYRfcNPn5mXH0ahLiFHPhqFWqAK15ied3nXSgkfFTHIkPP 1YSzF+Wz60D1pC6YbKzj6BogMLK7Ji2HdrYVd7ZSNDb6xEVDfc9cNMXFxerpUEgjgMQY noZ05SeIiM9H5Nhjt6x6c/Z3HyTss7TOg8zOr9NSMoJBLC5J/XESMlnB2cuwNLfWEeCE Lw3j1JMLA9SZCsFsH6XWMcLdXJAI0502KZ2Jd515d7yt65iQA7Lg1eGcxLzkpkSyeXLW 4bdA== X-Gm-Message-State: AO0yUKXgv2ydy5MTJYXBsjwJjl6vxzzykBurbGtHO9tpKT0ODXOTpS6F s4ESQbhataVizdONIXVQVdwijg== X-Google-Smtp-Source: AK7set/JjpNvsvf8MV9aq3qP6wInMbwMOVpVCJJNFqgxlkKvmA4HfRtybbTeiYUBXGAMluTsvW8RHA== X-Received: by 2002:a2e:3610:0:b0:295:acb9:8610 with SMTP id d16-20020a2e3610000000b00295acb98610mr12822310lja.25.1678807740930; Tue, 14 Mar 2023 08:29:00 -0700 (PDT) Received: from [192.168.1.101] (abyj16.neoplus.adsl.tpnet.pl. [83.9.29.16]) by smtp.gmail.com with ESMTPSA id 27-20020a2e165b000000b002986a977bf2sm491529ljw.90.2023.03.14.08.28.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 14 Mar 2023 08:29:00 -0700 (PDT) From: Konrad Dybcio Date: Tue, 14 Mar 2023 16:28:45 +0100 Subject: [PATCH v4 14/14] drm/msm/a6xx: Add A610 speedbin support MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20230223-topic-gmuwrapper-v4-14-e987eb79d03f@linaro.org> References: <20230223-topic-gmuwrapper-v4-0-e987eb79d03f@linaro.org> In-Reply-To: <20230223-topic-gmuwrapper-v4-0-e987eb79d03f@linaro.org> To: Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , David Airlie , Daniel Vetter , Rob Herring , Krzysztof Kozlowski , Bjorn Andersson , Konrad Dybcio , Akhil P Oommen Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Rob Clark , Marijn Suijten , Konrad Dybcio X-Mailer: b4 0.12.1 X-Developer-Signature: v=1; a=ed25519-sha256; t=1678807716; l=1852; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=ZWxWz95kNFsOaOSTnUEHkUaKyj0DdIwF1Eu3I3PdtGk=; b=KpKsSEXRQhg/MQJAmTRWDZjQlF+2ofojhmqZlx7eSqwxni5o+DCOvcHjBxCErE0ijWM2Fb5c/ZYL mYoD898IBUAF5lQbLmP9ZrsLEqozfQMp+QSYOnwJjDo2iYl97Y1+ X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org A610 is implemented on at least three SoCs: SM6115 (bengal), SM6125 (trinket) and SM6225 (khaje). Trinket does not support speed binning (only a single SKU exists) and we don't yet support khaje upstream. Hence, add a fuse mapping table for bengal to allow for per-chip frequency limiting. Reviewed-by: Dmitry Baryshkov Signed-off-by: Konrad Dybcio --- drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 27 +++++++++++++++++++++++++++ 1 file changed, 27 insertions(+) diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/ad= reno/a6xx_gpu.c index 27b96a335039..f9f1a6c50f65 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c @@ -2136,6 +2136,30 @@ static bool a6xx_progress(struct msm_gpu *gpu, struc= t msm_ringbuffer *ring) return progress; } =20 +static u32 a610_get_speed_bin(u32 fuse) +{ + /* + * There are (at least) three SoCs implementing A610: SM6125 (trinket), + * SM6115 (bengal) and SM6225 (khaje). Trinket does not have speedbinning, + * as only a single SKU exists and we don't support khaje upstream yet. + * Hence, this matching table is only valid for bengal and can be easily + * expanded if need be. + */ + + if (fuse =3D=3D 0) + return 0; + else if (fuse =3D=3D 206) + return 1; + else if (fuse =3D=3D 200) + return 2; + else if (fuse =3D=3D 157) + return 3; + else if (fuse =3D=3D 127) + return 4; + + return UINT_MAX; +} + static u32 a618_get_speed_bin(u32 fuse) { if (fuse =3D=3D 0) @@ -2232,6 +2256,9 @@ static u32 fuse_to_supp_hw(struct device *dev, struct= adreno_gpu *adreno_gpu, u3 { u32 val =3D UINT_MAX; =20 + if (adreno_is_a610(adreno_gpu)) + val =3D a610_get_speed_bin(fuse); + if (adreno_is_a618(adreno_gpu)) val =3D a618_get_speed_bin(fuse); =20 --=20 2.39.2