From nobody Thu Nov 14 07:05:11 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9B3E5C636D6 for ; Wed, 22 Feb 2023 18:40:24 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232486AbjBVSkW (ORCPT ); Wed, 22 Feb 2023 13:40:22 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:43610 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232048AbjBVSkQ (ORCPT ); Wed, 22 Feb 2023 13:40:16 -0500 Received: from mail-wr1-x434.google.com (mail-wr1-x434.google.com [IPv6:2a00:1450:4864:20::434]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 16C8A3CE28; Wed, 22 Feb 2023 10:40:01 -0800 (PST) Received: by mail-wr1-x434.google.com with SMTP id l25so8349732wrb.3; Wed, 22 Feb 2023 10:40:01 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=foDA/GXxUeG6qywVw7pPHlQfm+Orh3kvLzj/my6QoE8=; b=B9+WOGfkjvzGfunEXkLYy8KTjSrl99QhGvrJByDf0VqgZLm54rAB8+A9V8YhbSMxEv BBVeVV1Kk+uc/mDULVvKuDcXyq/JGZ14j1nhe6Fiqk4cjafKSUB3jOUazpz0YqspXaot o1vYvzu4/0RXvgATzshU0UETf2CZIIkkM2YOMMXZb/Y6z6pqxT5LKQYFNsfd3StDvWPI jIUEIwgzsmqfLOoEgnnRUMLE54hbtE/zjEspIUang04Lj4OZ+F+IwDpkUW6Xjxnzd/5k j8l4oMQcFZTAtrFtuzIXALV+kn6wQE+4Fi+ThhcG3XuAubClZdzey8Y7wEAnJJxKJdZx q9SA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=foDA/GXxUeG6qywVw7pPHlQfm+Orh3kvLzj/my6QoE8=; b=iZX5BryTfvDOinxdygNG7MffPa7cXFQbLToP8lnyCwsYiICByGyMGRNfI8DsIjaOZh yJmuO2k1gy4vCIuSBStZ2cyRCQwadumPXIjeIbobx5qHdYl2LUJEENaKuf+yoOaVqJk/ 6VnhW6FX/7f7rz4Ll+YaCqUQ7j4u54YyWojNKg5IAwHvkCCHr6PccvZv8RjrUaE64P9U 3cntJnwj9JM3TYi4aq0V1/0DuFLKTjvMhZ/ghOoZeMU2d+ON2ZT241GJPQ29/OcCtMQs RcogyaHMGwKC+txQ+cLvW0pAC5x72lszK2zBYPtGvJw0lob/yTyjf3Pcls8VGduRXcRx 5D5Q== X-Gm-Message-State: AO0yUKXxmh6Mg4S8wtVwIH0yWsX2IOWlZ/q0GgDGXTKsnLSJZdrt0CAF hv/7H8BoZaahBQonT0D3o80= X-Google-Smtp-Source: AK7set9VipcuXxYpnZ45Df1zEkwY+VzCevZIE9fa4nfCbZ7L/fI0ChM6/Zx2yWmI9RnPiMQlYfZ5Nw== X-Received: by 2002:a5d:67cc:0:b0:2c5:6016:496 with SMTP id n12-20020a5d67cc000000b002c560160496mr8555585wrw.27.1677091199479; Wed, 22 Feb 2023 10:39:59 -0800 (PST) Received: from arinc9-PC.lan ([37.120.152.236]) by smtp.gmail.com with ESMTPSA id l18-20020a5d4112000000b002c56179d39esm9372845wrp.44.2023.02.22.10.39.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 22 Feb 2023 10:39:59 -0800 (PST) From: arinc9.unal@gmail.com X-Google-Original-From: arinc.unal@arinc9.com To: Sergio Paracuellos , Linus Walleij , Rob Herring , Krzysztof Kozlowski Cc: =?UTF-8?q?Ar=C4=B1n=C3=A7=20=C3=9CNAL?= , linux-mediatek@lists.infradead.org, linux-mips@vger.kernel.org, linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Matthias Brugger , Sean Wang , William Dean , Daniel Golle , Daniel Santos , Luiz Angelo Daros de Luca , Frank Wunderlich , Landen Chao , DENG Qingfang , Sean Wang , erkin.bozoglu@xeront.com Subject: [RFC PATCH 01/16] pinctrl: ralink: reintroduce ralink,rt2880-pinmux compatible string Date: Wed, 22 Feb 2023 21:39:17 +0300 Message-Id: <20230222183932.33267-2-arinc.unal@arinc9.com> X-Mailer: git-send-email 2.37.2 In-Reply-To: <20230222183932.33267-1-arinc.unal@arinc9.com> References: <20230222183932.33267-1-arinc.unal@arinc9.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Ar=C4=B1n=C3=A7 =C3=9CNAL There have been stable releases with the ralink,rt2880-pinmux compatible string included. Having it removed breaks the ABI. Reintroduce it. Fixes: e5981cd46183 ("pinctrl: ralink: add new compatible strings for each = pinctrl subdriver") Signed-off-by: Ar=C4=B1n=C3=A7 =C3=9CNAL --- drivers/pinctrl/ralink/pinctrl-mt7620.c | 1 + drivers/pinctrl/ralink/pinctrl-mt7621.c | 1 + drivers/pinctrl/ralink/pinctrl-rt2880.c | 1 + drivers/pinctrl/ralink/pinctrl-rt305x.c | 1 + drivers/pinctrl/ralink/pinctrl-rt3883.c | 1 + 5 files changed, 5 insertions(+) diff --git a/drivers/pinctrl/ralink/pinctrl-mt7620.c b/drivers/pinctrl/rali= nk/pinctrl-mt7620.c index 4e8d26bb3430..06b86c726839 100644 --- a/drivers/pinctrl/ralink/pinctrl-mt7620.c +++ b/drivers/pinctrl/ralink/pinctrl-mt7620.c @@ -372,6 +372,7 @@ static int mt7620_pinctrl_probe(struct platform_device = *pdev) =20 static const struct of_device_id mt7620_pinctrl_match[] =3D { { .compatible =3D "ralink,mt7620-pinctrl" }, + { .compatible =3D "ralink,rt2880-pinmux" }, {} }; MODULE_DEVICE_TABLE(of, mt7620_pinctrl_match); diff --git a/drivers/pinctrl/ralink/pinctrl-mt7621.c b/drivers/pinctrl/rali= nk/pinctrl-mt7621.c index eddc0ba6d468..fb5824922e78 100644 --- a/drivers/pinctrl/ralink/pinctrl-mt7621.c +++ b/drivers/pinctrl/ralink/pinctrl-mt7621.c @@ -97,6 +97,7 @@ static int mt7621_pinctrl_probe(struct platform_device *p= dev) =20 static const struct of_device_id mt7621_pinctrl_match[] =3D { { .compatible =3D "ralink,mt7621-pinctrl" }, + { .compatible =3D "ralink,rt2880-pinmux" }, {} }; MODULE_DEVICE_TABLE(of, mt7621_pinctrl_match); diff --git a/drivers/pinctrl/ralink/pinctrl-rt2880.c b/drivers/pinctrl/rali= nk/pinctrl-rt2880.c index 3e2f1aaaf095..d7a65fcc7755 100644 --- a/drivers/pinctrl/ralink/pinctrl-rt2880.c +++ b/drivers/pinctrl/ralink/pinctrl-rt2880.c @@ -41,6 +41,7 @@ static int rt2880_pinctrl_probe(struct platform_device *p= dev) =20 static const struct of_device_id rt2880_pinctrl_match[] =3D { { .compatible =3D "ralink,rt2880-pinctrl" }, + { .compatible =3D "ralink,rt2880-pinmux" }, {} }; MODULE_DEVICE_TABLE(of, rt2880_pinctrl_match); diff --git a/drivers/pinctrl/ralink/pinctrl-rt305x.c b/drivers/pinctrl/rali= nk/pinctrl-rt305x.c index bdaee5ce1ee0..f6092c64383e 100644 --- a/drivers/pinctrl/ralink/pinctrl-rt305x.c +++ b/drivers/pinctrl/ralink/pinctrl-rt305x.c @@ -118,6 +118,7 @@ static int rt305x_pinctrl_probe(struct platform_device = *pdev) =20 static const struct of_device_id rt305x_pinctrl_match[] =3D { { .compatible =3D "ralink,rt305x-pinctrl" }, + { .compatible =3D "ralink,rt2880-pinmux" }, {} }; MODULE_DEVICE_TABLE(of, rt305x_pinctrl_match); diff --git a/drivers/pinctrl/ralink/pinctrl-rt3883.c b/drivers/pinctrl/rali= nk/pinctrl-rt3883.c index 392208662355..5f766d76bafa 100644 --- a/drivers/pinctrl/ralink/pinctrl-rt3883.c +++ b/drivers/pinctrl/ralink/pinctrl-rt3883.c @@ -88,6 +88,7 @@ static int rt3883_pinctrl_probe(struct platform_device *p= dev) =20 static const struct of_device_id rt3883_pinctrl_match[] =3D { { .compatible =3D "ralink,rt3883-pinctrl" }, + { .compatible =3D "ralink,rt2880-pinmux" }, {} }; MODULE_DEVICE_TABLE(of, rt3883_pinctrl_match); --=20 2.37.2 From nobody Thu Nov 14 07:05:11 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 58424C64ED6 for ; Wed, 22 Feb 2023 18:40:34 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232528AbjBVSkd (ORCPT ); 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Wed, 22 Feb 2023 10:40:08 -0800 (PST) From: arinc9.unal@gmail.com X-Google-Original-From: arinc.unal@arinc9.com To: Sergio Paracuellos , Linus Walleij , Rob Herring , Krzysztof Kozlowski Cc: =?UTF-8?q?Ar=C4=B1n=C3=A7=20=C3=9CNAL?= , linux-mediatek@lists.infradead.org, linux-mips@vger.kernel.org, linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Matthias Brugger , Sean Wang , William Dean , Daniel Golle , Daniel Santos , Luiz Angelo Daros de Luca , Frank Wunderlich , Landen Chao , DENG Qingfang , Sean Wang , erkin.bozoglu@xeront.com Subject: [RFC PATCH 02/16] pinctrl: ralink: add mediatek compatible strings Date: Wed, 22 Feb 2023 21:39:18 +0300 Message-Id: <20230222183932.33267-3-arinc.unal@arinc9.com> X-Mailer: git-send-email 2.37.2 In-Reply-To: <20230222183932.33267-1-arinc.unal@arinc9.com> References: <20230222183932.33267-1-arinc.unal@arinc9.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Ar=C4=B1n=C3=A7 =C3=9CNAL Ralink was acquired by MediaTek in 2011. These SoCs have been rebranded as MediaTek. Add new compatible strings to reflect that. Signed-off-by: Ar=C4=B1n=C3=A7 =C3=9CNAL --- drivers/pinctrl/ralink/pinctrl-mt7620.c | 1 + drivers/pinctrl/ralink/pinctrl-mt7621.c | 1 + drivers/pinctrl/ralink/pinctrl-rt2880.c | 1 + drivers/pinctrl/ralink/pinctrl-rt305x.c | 1 + drivers/pinctrl/ralink/pinctrl-rt3883.c | 1 + 5 files changed, 5 insertions(+) diff --git a/drivers/pinctrl/ralink/pinctrl-mt7620.c b/drivers/pinctrl/rali= nk/pinctrl-mt7620.c index 06b86c726839..88b0c6a4ee18 100644 --- a/drivers/pinctrl/ralink/pinctrl-mt7620.c +++ b/drivers/pinctrl/ralink/pinctrl-mt7620.c @@ -371,6 +371,7 @@ static int mt7620_pinctrl_probe(struct platform_device = *pdev) } =20 static const struct of_device_id mt7620_pinctrl_match[] =3D { + { .compatible =3D "mediatek,mt7620-pinctrl" }, { .compatible =3D "ralink,mt7620-pinctrl" }, { .compatible =3D "ralink,rt2880-pinmux" }, {} diff --git a/drivers/pinctrl/ralink/pinctrl-mt7621.c b/drivers/pinctrl/rali= nk/pinctrl-mt7621.c index fb5824922e78..2128a94f6d1b 100644 --- a/drivers/pinctrl/ralink/pinctrl-mt7621.c +++ b/drivers/pinctrl/ralink/pinctrl-mt7621.c @@ -96,6 +96,7 @@ static int mt7621_pinctrl_probe(struct platform_device *p= dev) } =20 static const struct of_device_id mt7621_pinctrl_match[] =3D { + { .compatible =3D "mediatek,mt7621-pinctrl" }, { .compatible =3D "ralink,mt7621-pinctrl" }, { .compatible =3D "ralink,rt2880-pinmux" }, {} diff --git a/drivers/pinctrl/ralink/pinctrl-rt2880.c b/drivers/pinctrl/rali= nk/pinctrl-rt2880.c index d7a65fcc7755..e57b1c5d03dd 100644 --- a/drivers/pinctrl/ralink/pinctrl-rt2880.c +++ b/drivers/pinctrl/ralink/pinctrl-rt2880.c @@ -40,6 +40,7 @@ static int rt2880_pinctrl_probe(struct platform_device *p= dev) } =20 static const struct of_device_id rt2880_pinctrl_match[] =3D { + { .compatible =3D "mediatek,rt2880-pinctrl" }, { .compatible =3D "ralink,rt2880-pinctrl" }, { .compatible =3D "ralink,rt2880-pinmux" }, {} diff --git a/drivers/pinctrl/ralink/pinctrl-rt305x.c b/drivers/pinctrl/rali= nk/pinctrl-rt305x.c index f6092c64383e..ca62997e716c 100644 --- a/drivers/pinctrl/ralink/pinctrl-rt305x.c +++ b/drivers/pinctrl/ralink/pinctrl-rt305x.c @@ -117,6 +117,7 @@ static int rt305x_pinctrl_probe(struct platform_device = *pdev) } =20 static const struct of_device_id rt305x_pinctrl_match[] =3D { + { .compatible =3D "mediatek,rt305x-pinctrl" }, { .compatible =3D "ralink,rt305x-pinctrl" }, { .compatible =3D "ralink,rt2880-pinmux" }, {} diff --git a/drivers/pinctrl/ralink/pinctrl-rt3883.c b/drivers/pinctrl/rali= nk/pinctrl-rt3883.c index 5f766d76bafa..b687c70d3555 100644 --- a/drivers/pinctrl/ralink/pinctrl-rt3883.c +++ b/drivers/pinctrl/ralink/pinctrl-rt3883.c @@ -87,6 +87,7 @@ static int rt3883_pinctrl_probe(struct platform_device *p= dev) } =20 static const struct of_device_id rt3883_pinctrl_match[] =3D { + { .compatible =3D "mediatek,rt3883-pinctrl" }, { .compatible =3D "ralink,rt3883-pinctrl" }, { .compatible =3D "ralink,rt2880-pinmux" }, {} --=20 2.37.2 From nobody Thu Nov 14 07:05:11 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 98CAAC64EC7 for ; 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Wed, 22 Feb 2023 10:40:10 -0800 (PST) From: arinc9.unal@gmail.com X-Google-Original-From: arinc.unal@arinc9.com To: Sergio Paracuellos , Linus Walleij , Rob Herring , Krzysztof Kozlowski Cc: =?UTF-8?q?Ar=C4=B1n=C3=A7=20=C3=9CNAL?= , linux-mediatek@lists.infradead.org, linux-mips@vger.kernel.org, linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Matthias Brugger , Sean Wang , William Dean , Daniel Golle , Daniel Santos , Luiz Angelo Daros de Luca , Frank Wunderlich , Landen Chao , DENG Qingfang , Sean Wang , erkin.bozoglu@xeront.com Subject: [RFC PATCH 03/16] pinctrl: ralink: rt305x: add compatible string for every SoC Date: Wed, 22 Feb 2023 21:39:19 +0300 Message-Id: <20230222183932.33267-4-arinc.unal@arinc9.com> X-Mailer: git-send-email 2.37.2 In-Reply-To: <20230222183932.33267-1-arinc.unal@arinc9.com> References: <20230222183932.33267-1-arinc.unal@arinc9.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Ar=C4=B1n=C3=A7 =C3=9CNAL Add a compatible string for every SoC, or SoCs that use the same pinmux data. This ensures that the pin muxing information of every SoC, or a set of SoCs that use the same pinmux data can be properly documented. Signed-off-by: Ar=C4=B1n=C3=A7 =C3=9CNAL --- drivers/pinctrl/ralink/pinctrl-rt305x.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/pinctrl/ralink/pinctrl-rt305x.c b/drivers/pinctrl/rali= nk/pinctrl-rt305x.c index ca62997e716c..a112a83085ea 100644 --- a/drivers/pinctrl/ralink/pinctrl-rt305x.c +++ b/drivers/pinctrl/ralink/pinctrl-rt305x.c @@ -118,6 +118,8 @@ static int rt305x_pinctrl_probe(struct platform_device = *pdev) =20 static const struct of_device_id rt305x_pinctrl_match[] =3D { { .compatible =3D "mediatek,rt305x-pinctrl" }, + { .compatible =3D "mediatek,rt3352-pinctrl" }, + { .compatible =3D "mediatek,rt5350-pinctrl" }, { .compatible =3D "ralink,rt305x-pinctrl" }, { .compatible =3D "ralink,rt2880-pinmux" }, {} --=20 2.37.2 From nobody Thu Nov 14 07:05:11 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5F498C61DA4 for ; Wed, 22 Feb 2023 18:40:47 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229615AbjBVSkp (ORCPT ); Wed, 22 Feb 2023 13:40:45 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:43822 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232509AbjBVSkb (ORCPT ); Wed, 22 Feb 2023 13:40:31 -0500 Received: from mail-wr1-x435.google.com (mail-wr1-x435.google.com [IPv6:2a00:1450:4864:20::435]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 56C4A3D080; Wed, 22 Feb 2023 10:40:15 -0800 (PST) Received: by mail-wr1-x435.google.com with SMTP id t13so8681707wrv.13; Wed, 22 Feb 2023 10:40:15 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=gDJeWiKsHoEvat6KQzjaepU8kGEjsYs/weaALQ++4bc=; b=fm41A8LCYTfuLR7EOjHQfUe6AVmR/8xV5zqhF+JPsPu4MTTrOCrBb8w7T4zwdtzaaz i1TgOCuLEUoolIt9CXxD0H2oT7Rpbx76SvXkkYo74zcWHRoksECPguG195nLkqt2WVdX AuhcNYDMZ3rpTJNg7JzOfmMWoJCjURd9g7D/jlSa+uz2uufR1HAbxxLYSZgz8bqXQOjM mNrU22F6RC9CypjZW1NIcc7BtUv9ZaIiw1Ifyid4YiFdZXHFiwdQ43p0ozNja5ouApI8 wVdFzNoceGwZWU8Jq2uJjeGz4SXg4/ZVCEayjQmiA09asGw6FvOnn7rpWqILrd6ba83W ZsJQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=gDJeWiKsHoEvat6KQzjaepU8kGEjsYs/weaALQ++4bc=; b=101XU4dmQaLsClWBz5jWwQA6PoaDHYYoeSGiLr85pfRXMTHPV2yplM6MVuBVvrDMT3 8xVD7AuInK7V3QBsTNjYzOq+PrF36/G5vhfNEy8txSyKuLK3lKOA8hVl9LXZJNRyPIFK Lg9HFilcnmLkFu7VLgxpZDPiSyBMZm2EwHNVJB+H12Llzf0n8s1r2vt0GO7p18NfBONg slWi0MT1hKgYL4dWQ7AM2pRDUmivUclT4B2HgtOQ98v5et1wWYt01VrNfVAoGO0kuyyT JvMJvGYz3S6L3WITzEybK0ISbG/j0wPt6fgCBQJwVpzNgoKJQEzbPNTyGWUvFfzP/WjI /Y2w== X-Gm-Message-State: AO0yUKWaRGzEZxigvPLQ8T76Nt+fYQLWUw+E17inrgi/tmaQYZ+LAmcy fqvwna/yOnxF9u5kI43Pajc= X-Google-Smtp-Source: AK7set+kWteGUe+mRh0DvI5tIZSuoatRYLKah8QWqbG4Yk5iUHcrwj7IJ7lO4lAJSqpfSlZpT8L0Ng== X-Received: by 2002:a5d:66ce:0:b0:2c7:453:d3b9 with SMTP id k14-20020a5d66ce000000b002c70453d3b9mr6259972wrw.37.1677091213593; Wed, 22 Feb 2023 10:40:13 -0800 (PST) Received: from arinc9-PC.lan ([37.120.152.236]) by smtp.gmail.com with ESMTPSA id l18-20020a5d4112000000b002c56179d39esm9372845wrp.44.2023.02.22.10.40.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 22 Feb 2023 10:40:13 -0800 (PST) From: arinc9.unal@gmail.com X-Google-Original-From: arinc.unal@arinc9.com To: Sergio Paracuellos , Linus Walleij , Rob Herring , Krzysztof Kozlowski Cc: =?UTF-8?q?Ar=C4=B1n=C3=A7=20=C3=9CNAL?= , linux-mediatek@lists.infradead.org, linux-mips@vger.kernel.org, linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Matthias Brugger , Sean Wang , William Dean , Daniel Golle , Daniel Santos , Luiz Angelo Daros de Luca , Frank Wunderlich , Landen Chao , DENG Qingfang , Sean Wang , erkin.bozoglu@xeront.com Subject: [RFC PATCH 04/16] pinctrl: ralink: mt7620: split out to mt76x8 Date: Wed, 22 Feb 2023 21:39:20 +0300 Message-Id: <20230222183932.33267-5-arinc.unal@arinc9.com> X-Mailer: git-send-email 2.37.2 In-Reply-To: <20230222183932.33267-1-arinc.unal@arinc9.com> References: <20230222183932.33267-1-arinc.unal@arinc9.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Ar=C4=B1n=C3=A7 =C3=9CNAL Split the driver out to pinctrl-mt76x8.c. Remove including the unnecessary headers since is_mt76x8() is not being used anymore. Introduce a new compatible string to be able to document the pin muxing information properly. Signed-off-by: Ar=C4=B1n=C3=A7 =C3=9CNAL --- drivers/pinctrl/ralink/Kconfig | 5 + drivers/pinctrl/ralink/Makefile | 1 + drivers/pinctrl/ralink/pinctrl-mt7620.c | 257 +-------------------- drivers/pinctrl/ralink/pinctrl-mt76x8.c | 283 ++++++++++++++++++++++++ 4 files changed, 290 insertions(+), 256 deletions(-) create mode 100644 drivers/pinctrl/ralink/pinctrl-mt76x8.c diff --git a/drivers/pinctrl/ralink/Kconfig b/drivers/pinctrl/ralink/Kconfig index 1e4c5e43d69b..c5fe4c31aaea 100644 --- a/drivers/pinctrl/ralink/Kconfig +++ b/drivers/pinctrl/ralink/Kconfig @@ -17,6 +17,11 @@ config PINCTRL_MT7621 depends on RALINK && SOC_MT7621 select PINCTRL_RALINK =20 +config PINCTRL_MT76X8 + bool "MT76X8 pinctrl subdriver" + depends on RALINK && SOC_MT7620 + select PINCTRL_RALINK + config PINCTRL_RT2880 bool "RT2880 pinctrl subdriver" depends on RALINK && SOC_RT288X diff --git a/drivers/pinctrl/ralink/Makefile b/drivers/pinctrl/ralink/Makef= ile index 0ebbe552526d..be9acf2e27fd 100644 --- a/drivers/pinctrl/ralink/Makefile +++ b/drivers/pinctrl/ralink/Makefile @@ -3,6 +3,7 @@ obj-$(CONFIG_PINCTRL_RALINK) +=3D pinctrl-ralink.o =20 obj-$(CONFIG_PINCTRL_MT7620) +=3D pinctrl-mt7620.o obj-$(CONFIG_PINCTRL_MT7621) +=3D pinctrl-mt7621.o +obj-$(CONFIG_PINCTRL_MT76X8) +=3D pinctrl-mt76x8.o obj-$(CONFIG_PINCTRL_RT2880) +=3D pinctrl-rt2880.o obj-$(CONFIG_PINCTRL_RT305X) +=3D pinctrl-rt305x.o obj-$(CONFIG_PINCTRL_RT3883) +=3D pinctrl-rt3883.o diff --git a/drivers/pinctrl/ralink/pinctrl-mt7620.c b/drivers/pinctrl/rali= nk/pinctrl-mt7620.c index 88b0c6a4ee18..b2245fd65c72 100644 --- a/drivers/pinctrl/ralink/pinctrl-mt7620.c +++ b/drivers/pinctrl/ralink/pinctrl-mt7620.c @@ -1,7 +1,5 @@ // SPDX-License-Identifier: GPL-2.0-only =20 -#include -#include #include #include #include @@ -112,262 +110,9 @@ static struct ralink_pmx_group mt7620a_pinmux_data[] = =3D { { 0 } }; =20 -static struct ralink_pmx_func pwm1_grp_mt76x8[] =3D { - FUNC("sdxc d6", 3, 19, 1), - FUNC("utif", 2, 19, 1), - FUNC("gpio", 1, 19, 1), - FUNC("pwm1", 0, 19, 1), -}; - -static struct ralink_pmx_func pwm0_grp_mt76x8[] =3D { - FUNC("sdxc d7", 3, 18, 1), - FUNC("utif", 2, 18, 1), - FUNC("gpio", 1, 18, 1), - FUNC("pwm0", 0, 18, 1), -}; - -static struct ralink_pmx_func uart2_grp_mt76x8[] =3D { - FUNC("sdxc d5 d4", 3, 20, 2), - FUNC("pwm", 2, 20, 2), - FUNC("gpio", 1, 20, 2), - FUNC("uart2", 0, 20, 2), -}; - -static struct ralink_pmx_func uart1_grp_mt76x8[] =3D { - FUNC("sw_r", 3, 45, 2), - FUNC("pwm", 2, 45, 2), - FUNC("gpio", 1, 45, 2), - FUNC("uart1", 0, 45, 2), -}; - -static struct ralink_pmx_func i2c_grp_mt76x8[] =3D { - FUNC("-", 3, 4, 2), - FUNC("debug", 2, 4, 2), - FUNC("gpio", 1, 4, 2), - FUNC("i2c", 0, 4, 2), -}; - -static struct ralink_pmx_func refclk_grp_mt76x8[] =3D { FUNC("refclk", 0, = 37, 1) }; -static struct ralink_pmx_func perst_grp_mt76x8[] =3D { FUNC("perst", 0, 36= , 1) }; -static struct ralink_pmx_func wdt_grp_mt76x8[] =3D { FUNC("wdt", 0, 38, 1)= }; -static struct ralink_pmx_func spi_grp_mt76x8[] =3D { FUNC("spi", 0, 7, 4) = }; - -static struct ralink_pmx_func sd_mode_grp_mt76x8[] =3D { - FUNC("jtag", 3, 22, 8), - FUNC("utif", 2, 22, 8), - FUNC("gpio", 1, 22, 8), - FUNC("sdxc", 0, 22, 8), -}; - -static struct ralink_pmx_func uart0_grp_mt76x8[] =3D { - FUNC("-", 3, 12, 2), - FUNC("-", 2, 12, 2), - FUNC("gpio", 1, 12, 2), - FUNC("uart0", 0, 12, 2), -}; - -static struct ralink_pmx_func i2s_grp_mt76x8[] =3D { - FUNC("antenna", 3, 0, 4), - FUNC("pcm", 2, 0, 4), - FUNC("gpio", 1, 0, 4), - FUNC("i2s", 0, 0, 4), -}; - -static struct ralink_pmx_func spi_cs1_grp_mt76x8[] =3D { - FUNC("-", 3, 6, 1), - FUNC("refclk", 2, 6, 1), - FUNC("gpio", 1, 6, 1), - FUNC("spi cs1", 0, 6, 1), -}; - -static struct ralink_pmx_func spis_grp_mt76x8[] =3D { - FUNC("pwm_uart2", 3, 14, 4), - FUNC("utif", 2, 14, 4), - FUNC("gpio", 1, 14, 4), - FUNC("spis", 0, 14, 4), -}; - -static struct ralink_pmx_func gpio_grp_mt76x8[] =3D { - FUNC("pcie", 3, 11, 1), - FUNC("refclk", 2, 11, 1), - FUNC("gpio", 1, 11, 1), - FUNC("gpio", 0, 11, 1), -}; - -static struct ralink_pmx_func p4led_kn_grp_mt76x8[] =3D { - FUNC("jtag", 3, 30, 1), - FUNC("utif", 2, 30, 1), - FUNC("gpio", 1, 30, 1), - FUNC("p4led_kn", 0, 30, 1), -}; - -static struct ralink_pmx_func p3led_kn_grp_mt76x8[] =3D { - FUNC("jtag", 3, 31, 1), - FUNC("utif", 2, 31, 1), - FUNC("gpio", 1, 31, 1), - FUNC("p3led_kn", 0, 31, 1), -}; - -static struct ralink_pmx_func p2led_kn_grp_mt76x8[] =3D { - FUNC("jtag", 3, 32, 1), - FUNC("utif", 2, 32, 1), - FUNC("gpio", 1, 32, 1), - FUNC("p2led_kn", 0, 32, 1), -}; - -static struct ralink_pmx_func p1led_kn_grp_mt76x8[] =3D { - FUNC("jtag", 3, 33, 1), - FUNC("utif", 2, 33, 1), - FUNC("gpio", 1, 33, 1), - FUNC("p1led_kn", 0, 33, 1), -}; - -static struct ralink_pmx_func p0led_kn_grp_mt76x8[] =3D { - FUNC("jtag", 3, 34, 1), - FUNC("rsvd", 2, 34, 1), - FUNC("gpio", 1, 34, 1), - FUNC("p0led_kn", 0, 34, 1), -}; - -static struct ralink_pmx_func wled_kn_grp_mt76x8[] =3D { - FUNC("rsvd", 3, 35, 1), - FUNC("rsvd", 2, 35, 1), - FUNC("gpio", 1, 35, 1), - FUNC("wled_kn", 0, 35, 1), -}; - -static struct ralink_pmx_func p4led_an_grp_mt76x8[] =3D { - FUNC("jtag", 3, 39, 1), - FUNC("utif", 2, 39, 1), - FUNC("gpio", 1, 39, 1), - FUNC("p4led_an", 0, 39, 1), -}; - -static struct ralink_pmx_func p3led_an_grp_mt76x8[] =3D { - FUNC("jtag", 3, 40, 1), - FUNC("utif", 2, 40, 1), - FUNC("gpio", 1, 40, 1), - FUNC("p3led_an", 0, 40, 1), -}; - -static struct ralink_pmx_func p2led_an_grp_mt76x8[] =3D { - FUNC("jtag", 3, 41, 1), - FUNC("utif", 2, 41, 1), - FUNC("gpio", 1, 41, 1), - FUNC("p2led_an", 0, 41, 1), -}; - -static struct ralink_pmx_func p1led_an_grp_mt76x8[] =3D { - FUNC("jtag", 3, 42, 1), - FUNC("utif", 2, 42, 1), - FUNC("gpio", 1, 42, 1), - FUNC("p1led_an", 0, 42, 1), -}; - -static struct ralink_pmx_func p0led_an_grp_mt76x8[] =3D { - FUNC("jtag", 3, 43, 1), - FUNC("rsvd", 2, 43, 1), - FUNC("gpio", 1, 43, 1), - FUNC("p0led_an", 0, 43, 1), -}; - -static struct ralink_pmx_func wled_an_grp_mt76x8[] =3D { - FUNC("rsvd", 3, 44, 1), - FUNC("rsvd", 2, 44, 1), - FUNC("gpio", 1, 44, 1), - FUNC("wled_an", 0, 44, 1), -}; - -#define MT76X8_GPIO_MODE_MASK 0x3 - -#define MT76X8_GPIO_MODE_P4LED_KN 58 -#define MT76X8_GPIO_MODE_P3LED_KN 56 -#define MT76X8_GPIO_MODE_P2LED_KN 54 -#define MT76X8_GPIO_MODE_P1LED_KN 52 -#define MT76X8_GPIO_MODE_P0LED_KN 50 -#define MT76X8_GPIO_MODE_WLED_KN 48 -#define MT76X8_GPIO_MODE_P4LED_AN 42 -#define MT76X8_GPIO_MODE_P3LED_AN 40 -#define MT76X8_GPIO_MODE_P2LED_AN 38 -#define MT76X8_GPIO_MODE_P1LED_AN 36 -#define MT76X8_GPIO_MODE_P0LED_AN 34 -#define MT76X8_GPIO_MODE_WLED_AN 32 -#define MT76X8_GPIO_MODE_PWM1 30 -#define MT76X8_GPIO_MODE_PWM0 28 -#define MT76X8_GPIO_MODE_UART2 26 -#define MT76X8_GPIO_MODE_UART1 24 -#define MT76X8_GPIO_MODE_I2C 20 -#define MT76X8_GPIO_MODE_REFCLK 18 -#define MT76X8_GPIO_MODE_PERST 16 -#define MT76X8_GPIO_MODE_WDT 14 -#define MT76X8_GPIO_MODE_SPI 12 -#define MT76X8_GPIO_MODE_SDMODE 10 -#define MT76X8_GPIO_MODE_UART0 8 -#define MT76X8_GPIO_MODE_I2S 6 -#define MT76X8_GPIO_MODE_CS1 4 -#define MT76X8_GPIO_MODE_SPIS 2 -#define MT76X8_GPIO_MODE_GPIO 0 - -static struct ralink_pmx_group mt76x8_pinmux_data[] =3D { - GRP_G("pwm1", pwm1_grp_mt76x8, MT76X8_GPIO_MODE_MASK, - 1, MT76X8_GPIO_MODE_PWM1), - GRP_G("pwm0", pwm0_grp_mt76x8, MT76X8_GPIO_MODE_MASK, - 1, MT76X8_GPIO_MODE_PWM0), - GRP_G("uart2", uart2_grp_mt76x8, MT76X8_GPIO_MODE_MASK, - 1, MT76X8_GPIO_MODE_UART2), - GRP_G("uart1", uart1_grp_mt76x8, MT76X8_GPIO_MODE_MASK, - 1, MT76X8_GPIO_MODE_UART1), - GRP_G("i2c", i2c_grp_mt76x8, MT76X8_GPIO_MODE_MASK, - 1, MT76X8_GPIO_MODE_I2C), - GRP("refclk", refclk_grp_mt76x8, 1, MT76X8_GPIO_MODE_REFCLK), - GRP("perst", perst_grp_mt76x8, 1, MT76X8_GPIO_MODE_PERST), - GRP("wdt", wdt_grp_mt76x8, 1, MT76X8_GPIO_MODE_WDT), - GRP("spi", spi_grp_mt76x8, 1, MT76X8_GPIO_MODE_SPI), - GRP_G("sdmode", sd_mode_grp_mt76x8, MT76X8_GPIO_MODE_MASK, - 1, MT76X8_GPIO_MODE_SDMODE), - GRP_G("uart0", uart0_grp_mt76x8, MT76X8_GPIO_MODE_MASK, - 1, MT76X8_GPIO_MODE_UART0), - GRP_G("i2s", i2s_grp_mt76x8, MT76X8_GPIO_MODE_MASK, - 1, MT76X8_GPIO_MODE_I2S), - GRP_G("spi cs1", spi_cs1_grp_mt76x8, MT76X8_GPIO_MODE_MASK, - 1, MT76X8_GPIO_MODE_CS1), - GRP_G("spis", spis_grp_mt76x8, MT76X8_GPIO_MODE_MASK, - 1, MT76X8_GPIO_MODE_SPIS), - GRP_G("gpio", gpio_grp_mt76x8, MT76X8_GPIO_MODE_MASK, - 1, MT76X8_GPIO_MODE_GPIO), - GRP_G("wled_an", wled_an_grp_mt76x8, MT76X8_GPIO_MODE_MASK, - 1, MT76X8_GPIO_MODE_WLED_AN), - GRP_G("p0led_an", p0led_an_grp_mt76x8, MT76X8_GPIO_MODE_MASK, - 1, MT76X8_GPIO_MODE_P0LED_AN), - GRP_G("p1led_an", p1led_an_grp_mt76x8, MT76X8_GPIO_MODE_MASK, - 1, MT76X8_GPIO_MODE_P1LED_AN), - GRP_G("p2led_an", p2led_an_grp_mt76x8, MT76X8_GPIO_MODE_MASK, - 1, MT76X8_GPIO_MODE_P2LED_AN), - GRP_G("p3led_an", p3led_an_grp_mt76x8, MT76X8_GPIO_MODE_MASK, - 1, MT76X8_GPIO_MODE_P3LED_AN), - GRP_G("p4led_an", p4led_an_grp_mt76x8, MT76X8_GPIO_MODE_MASK, - 1, MT76X8_GPIO_MODE_P4LED_AN), - GRP_G("wled_kn", wled_kn_grp_mt76x8, MT76X8_GPIO_MODE_MASK, - 1, MT76X8_GPIO_MODE_WLED_KN), - GRP_G("p0led_kn", p0led_kn_grp_mt76x8, MT76X8_GPIO_MODE_MASK, - 1, MT76X8_GPIO_MODE_P0LED_KN), - GRP_G("p1led_kn", p1led_kn_grp_mt76x8, MT76X8_GPIO_MODE_MASK, - 1, MT76X8_GPIO_MODE_P1LED_KN), - GRP_G("p2led_kn", p2led_kn_grp_mt76x8, MT76X8_GPIO_MODE_MASK, - 1, MT76X8_GPIO_MODE_P2LED_KN), - GRP_G("p3led_kn", p3led_kn_grp_mt76x8, MT76X8_GPIO_MODE_MASK, - 1, MT76X8_GPIO_MODE_P3LED_KN), - GRP_G("p4led_kn", p4led_kn_grp_mt76x8, MT76X8_GPIO_MODE_MASK, - 1, MT76X8_GPIO_MODE_P4LED_KN), - { 0 } -}; - static int mt7620_pinctrl_probe(struct platform_device *pdev) { - if (is_mt76x8()) - return ralink_pinctrl_init(pdev, mt76x8_pinmux_data); - else - return ralink_pinctrl_init(pdev, mt7620a_pinmux_data); + return ralink_pinctrl_init(pdev, mt7620a_pinmux_data); } =20 static const struct of_device_id mt7620_pinctrl_match[] =3D { diff --git a/drivers/pinctrl/ralink/pinctrl-mt76x8.c b/drivers/pinctrl/rali= nk/pinctrl-mt76x8.c new file mode 100644 index 000000000000..5a6a82a58180 --- /dev/null +++ b/drivers/pinctrl/ralink/pinctrl-mt76x8.c @@ -0,0 +1,283 @@ +// SPDX-License-Identifier: GPL-2.0-only + +#include +#include +#include +#include "pinctrl-ralink.h" + +#define MT76X8_GPIO_MODE_MASK 0x3 + +#define MT76X8_GPIO_MODE_P4LED_KN 58 +#define MT76X8_GPIO_MODE_P3LED_KN 56 +#define MT76X8_GPIO_MODE_P2LED_KN 54 +#define MT76X8_GPIO_MODE_P1LED_KN 52 +#define MT76X8_GPIO_MODE_P0LED_KN 50 +#define MT76X8_GPIO_MODE_WLED_KN 48 +#define MT76X8_GPIO_MODE_P4LED_AN 42 +#define MT76X8_GPIO_MODE_P3LED_AN 40 +#define MT76X8_GPIO_MODE_P2LED_AN 38 +#define MT76X8_GPIO_MODE_P1LED_AN 36 +#define MT76X8_GPIO_MODE_P0LED_AN 34 +#define MT76X8_GPIO_MODE_WLED_AN 32 +#define MT76X8_GPIO_MODE_PWM1 30 +#define MT76X8_GPIO_MODE_PWM0 28 +#define MT76X8_GPIO_MODE_UART2 26 +#define MT76X8_GPIO_MODE_UART1 24 +#define MT76X8_GPIO_MODE_I2C 20 +#define MT76X8_GPIO_MODE_REFCLK 18 +#define MT76X8_GPIO_MODE_PERST 16 +#define MT76X8_GPIO_MODE_WDT 14 +#define MT76X8_GPIO_MODE_SPI 12 +#define MT76X8_GPIO_MODE_SDMODE 10 +#define MT76X8_GPIO_MODE_UART0 8 +#define MT76X8_GPIO_MODE_I2S 6 +#define MT76X8_GPIO_MODE_CS1 4 +#define MT76X8_GPIO_MODE_SPIS 2 +#define MT76X8_GPIO_MODE_GPIO 0 + +static struct ralink_pmx_func pwm1_grp[] =3D { + FUNC("sdxc d6", 3, 19, 1), + FUNC("utif", 2, 19, 1), + FUNC("gpio", 1, 19, 1), + FUNC("pwm1", 0, 19, 1), +}; + +static struct ralink_pmx_func pwm0_grp[] =3D { + FUNC("sdxc d7", 3, 18, 1), + FUNC("utif", 2, 18, 1), + FUNC("gpio", 1, 18, 1), + FUNC("pwm0", 0, 18, 1), +}; + +static struct ralink_pmx_func uart2_grp[] =3D { + FUNC("sdxc d5 d4", 3, 20, 2), + FUNC("pwm", 2, 20, 2), + FUNC("gpio", 1, 20, 2), + FUNC("uart2", 0, 20, 2), +}; + +static struct ralink_pmx_func uart1_grp[] =3D { + FUNC("sw_r", 3, 45, 2), + FUNC("pwm", 2, 45, 2), + FUNC("gpio", 1, 45, 2), + FUNC("uart1", 0, 45, 2), +}; + +static struct ralink_pmx_func i2c_grp[] =3D { + FUNC("-", 3, 4, 2), + FUNC("debug", 2, 4, 2), + FUNC("gpio", 1, 4, 2), + FUNC("i2c", 0, 4, 2), +}; + +static struct ralink_pmx_func refclk_grp[] =3D { FUNC("refclk", 0, 37, 1) = }; +static struct ralink_pmx_func perst_grp[] =3D { FUNC("perst", 0, 36, 1) }; +static struct ralink_pmx_func wdt_grp[] =3D { FUNC("wdt", 0, 38, 1) }; +static struct ralink_pmx_func spi_grp[] =3D { FUNC("spi", 0, 7, 4) }; + +static struct ralink_pmx_func sd_mode_grp[] =3D { + FUNC("jtag", 3, 22, 8), + FUNC("utif", 2, 22, 8), + FUNC("gpio", 1, 22, 8), + FUNC("sdxc", 0, 22, 8), +}; + +static struct ralink_pmx_func uart0_grp[] =3D { + FUNC("-", 3, 12, 2), + FUNC("-", 2, 12, 2), + FUNC("gpio", 1, 12, 2), + FUNC("uart0", 0, 12, 2), +}; + +static struct ralink_pmx_func i2s_grp[] =3D { + FUNC("antenna", 3, 0, 4), + FUNC("pcm", 2, 0, 4), + FUNC("gpio", 1, 0, 4), + FUNC("i2s", 0, 0, 4), +}; + +static struct ralink_pmx_func spi_cs1_grp[] =3D { + FUNC("-", 3, 6, 1), + FUNC("refclk", 2, 6, 1), + FUNC("gpio", 1, 6, 1), + FUNC("spi cs1", 0, 6, 1), +}; + +static struct ralink_pmx_func spis_grp[] =3D { + FUNC("pwm_uart2", 3, 14, 4), + FUNC("utif", 2, 14, 4), + FUNC("gpio", 1, 14, 4), + FUNC("spis", 0, 14, 4), +}; + +static struct ralink_pmx_func gpio_grp[] =3D { + FUNC("pcie", 3, 11, 1), + FUNC("refclk", 2, 11, 1), + FUNC("gpio", 1, 11, 1), + FUNC("gpio", 0, 11, 1), +}; + +static struct ralink_pmx_func p4led_kn_grp[] =3D { + FUNC("jtag", 3, 30, 1), + FUNC("utif", 2, 30, 1), + FUNC("gpio", 1, 30, 1), + FUNC("p4led_kn", 0, 30, 1), +}; + +static struct ralink_pmx_func p3led_kn_grp[] =3D { + FUNC("jtag", 3, 31, 1), + FUNC("utif", 2, 31, 1), + FUNC("gpio", 1, 31, 1), + FUNC("p3led_kn", 0, 31, 1), +}; + +static struct ralink_pmx_func p2led_kn_grp[] =3D { + FUNC("jtag", 3, 32, 1), + FUNC("utif", 2, 32, 1), + FUNC("gpio", 1, 32, 1), + FUNC("p2led_kn", 0, 32, 1), +}; + +static struct ralink_pmx_func p1led_kn_grp[] =3D { + FUNC("jtag", 3, 33, 1), + FUNC("utif", 2, 33, 1), + FUNC("gpio", 1, 33, 1), + FUNC("p1led_kn", 0, 33, 1), +}; + +static struct ralink_pmx_func p0led_kn_grp[] =3D { + FUNC("jtag", 3, 34, 1), + FUNC("rsvd", 2, 34, 1), + FUNC("gpio", 1, 34, 1), + FUNC("p0led_kn", 0, 34, 1), +}; + +static struct ralink_pmx_func wled_kn_grp[] =3D { + FUNC("rsvd", 3, 35, 1), + FUNC("rsvd", 2, 35, 1), + FUNC("gpio", 1, 35, 1), + FUNC("wled_kn", 0, 35, 1), +}; + +static struct ralink_pmx_func p4led_an_grp[] =3D { + FUNC("jtag", 3, 39, 1), + FUNC("utif", 2, 39, 1), + FUNC("gpio", 1, 39, 1), + FUNC("p4led_an", 0, 39, 1), +}; + +static struct ralink_pmx_func p3led_an_grp[] =3D { + FUNC("jtag", 3, 40, 1), + FUNC("utif", 2, 40, 1), + FUNC("gpio", 1, 40, 1), + FUNC("p3led_an", 0, 40, 1), +}; + +static struct ralink_pmx_func p2led_an_grp[] =3D { + FUNC("jtag", 3, 41, 1), + FUNC("utif", 2, 41, 1), + FUNC("gpio", 1, 41, 1), + FUNC("p2led_an", 0, 41, 1), +}; + +static struct ralink_pmx_func p1led_an_grp[] =3D { + FUNC("jtag", 3, 42, 1), + FUNC("utif", 2, 42, 1), + FUNC("gpio", 1, 42, 1), + FUNC("p1led_an", 0, 42, 1), +}; + +static struct ralink_pmx_func p0led_an_grp[] =3D { + FUNC("jtag", 3, 43, 1), + FUNC("rsvd", 2, 43, 1), + FUNC("gpio", 1, 43, 1), + FUNC("p0led_an", 0, 43, 1), +}; + +static struct ralink_pmx_func wled_an_grp[] =3D { + FUNC("rsvd", 3, 44, 1), + FUNC("rsvd", 2, 44, 1), + FUNC("gpio", 1, 44, 1), + FUNC("wled_an", 0, 44, 1), +}; + +static struct ralink_pmx_group mt76x8_pinmux_data[] =3D { + GRP_G("pwm1", pwm1_grp, MT76X8_GPIO_MODE_MASK, + 1, MT76X8_GPIO_MODE_PWM1), + GRP_G("pwm0", pwm0_grp, MT76X8_GPIO_MODE_MASK, + 1, MT76X8_GPIO_MODE_PWM0), + GRP_G("uart2", uart2_grp, MT76X8_GPIO_MODE_MASK, + 1, MT76X8_GPIO_MODE_UART2), + GRP_G("uart1", uart1_grp, MT76X8_GPIO_MODE_MASK, + 1, MT76X8_GPIO_MODE_UART1), + GRP_G("i2c", i2c_grp, MT76X8_GPIO_MODE_MASK, + 1, MT76X8_GPIO_MODE_I2C), + GRP("refclk", refclk_grp, 1, MT76X8_GPIO_MODE_REFCLK), + GRP("perst", perst_grp, 1, MT76X8_GPIO_MODE_PERST), + GRP("wdt", wdt_grp, 1, MT76X8_GPIO_MODE_WDT), + GRP("spi", spi_grp, 1, MT76X8_GPIO_MODE_SPI), + GRP_G("sdmode", sd_mode_grp, MT76X8_GPIO_MODE_MASK, + 1, MT76X8_GPIO_MODE_SDMODE), + GRP_G("uart0", uart0_grp, MT76X8_GPIO_MODE_MASK, + 1, MT76X8_GPIO_MODE_UART0), + GRP_G("i2s", i2s_grp, MT76X8_GPIO_MODE_MASK, + 1, MT76X8_GPIO_MODE_I2S), + GRP_G("spi cs1", spi_cs1_grp, MT76X8_GPIO_MODE_MASK, + 1, MT76X8_GPIO_MODE_CS1), + GRP_G("spis", spis_grp, MT76X8_GPIO_MODE_MASK, + 1, MT76X8_GPIO_MODE_SPIS), + GRP_G("gpio", gpio_grp, MT76X8_GPIO_MODE_MASK, + 1, MT76X8_GPIO_MODE_GPIO), + GRP_G("wled_an", wled_an_grp, MT76X8_GPIO_MODE_MASK, + 1, MT76X8_GPIO_MODE_WLED_AN), + GRP_G("p0led_an", p0led_an_grp, MT76X8_GPIO_MODE_MASK, + 1, MT76X8_GPIO_MODE_P0LED_AN), + GRP_G("p1led_an", p1led_an_grp, MT76X8_GPIO_MODE_MASK, + 1, MT76X8_GPIO_MODE_P1LED_AN), + GRP_G("p2led_an", p2led_an_grp, MT76X8_GPIO_MODE_MASK, + 1, MT76X8_GPIO_MODE_P2LED_AN), + GRP_G("p3led_an", p3led_an_grp, MT76X8_GPIO_MODE_MASK, + 1, MT76X8_GPIO_MODE_P3LED_AN), + GRP_G("p4led_an", p4led_an_grp, MT76X8_GPIO_MODE_MASK, + 1, MT76X8_GPIO_MODE_P4LED_AN), + GRP_G("wled_kn", wled_kn_grp, MT76X8_GPIO_MODE_MASK, + 1, MT76X8_GPIO_MODE_WLED_KN), + GRP_G("p0led_kn", p0led_kn_grp, MT76X8_GPIO_MODE_MASK, + 1, MT76X8_GPIO_MODE_P0LED_KN), + GRP_G("p1led_kn", p1led_kn_grp, MT76X8_GPIO_MODE_MASK, + 1, MT76X8_GPIO_MODE_P1LED_KN), + GRP_G("p2led_kn", p2led_kn_grp, MT76X8_GPIO_MODE_MASK, + 1, MT76X8_GPIO_MODE_P2LED_KN), + GRP_G("p3led_kn", p3led_kn_grp, MT76X8_GPIO_MODE_MASK, + 1, MT76X8_GPIO_MODE_P3LED_KN), + GRP_G("p4led_kn", p4led_kn_grp, MT76X8_GPIO_MODE_MASK, + 1, MT76X8_GPIO_MODE_P4LED_KN), + { 0 } +}; + +static int mt76x8_pinctrl_probe(struct platform_device *pdev) +{ + return ralink_pinctrl_init(pdev, mt76x8_pinmux_data); +} + +static const struct of_device_id mt76x8_pinctrl_match[] =3D { + { .compatible =3D "mediatek,mt76x8-pinctrl" }, + { .compatible =3D "ralink,mt7620-pinctrl" }, + { .compatible =3D "ralink,rt2880-pinmux" }, + {} +}; +MODULE_DEVICE_TABLE(of, mt76x8_pinctrl_match); + +static struct platform_driver mt76x8_pinctrl_driver =3D { + .probe =3D mt76x8_pinctrl_probe, + .driver =3D { + .name =3D "mt76x8-pinctrl", + .of_match_table =3D mt76x8_pinctrl_match, + }, +}; + +static int __init mt76x8_pinctrl_init(void) +{ + return platform_driver_register(&mt76x8_pinctrl_driver); +} +core_initcall_sync(mt76x8_pinctrl_init); --=20 2.37.2 From nobody Thu Nov 14 07:05:11 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id DE679C6FA99 for ; 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Wed, 22 Feb 2023 10:40:15 -0800 (PST) From: arinc9.unal@gmail.com X-Google-Original-From: arinc.unal@arinc9.com To: Sergio Paracuellos , Linus Walleij , Rob Herring , Krzysztof Kozlowski Cc: =?UTF-8?q?Ar=C4=B1n=C3=A7=20=C3=9CNAL?= , linux-mediatek@lists.infradead.org, linux-mips@vger.kernel.org, linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Matthias Brugger , Sean Wang , William Dean , Daniel Golle , Daniel Santos , Luiz Angelo Daros de Luca , Frank Wunderlich , Landen Chao , DENG Qingfang , Sean Wang , erkin.bozoglu@xeront.com Subject: [RFC PATCH 05/16] pinctrl: ralink: move to mediatek as mtmips Date: Wed, 22 Feb 2023 21:39:21 +0300 Message-Id: <20230222183932.33267-6-arinc.unal@arinc9.com> X-Mailer: git-send-email 2.37.2 In-Reply-To: <20230222183932.33267-1-arinc.unal@arinc9.com> References: <20230222183932.33267-1-arinc.unal@arinc9.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Ar=C4=B1n=C3=A7 =C3=9CNAL Ralink was acquired by MediaTek in 2011. These SoCs have been rebranded as MediaTek. Move the driver to mediatek pinctrl directory. Rename the ralink core driver to mtmips. Signed-off-by: Ar=C4=B1n=C3=A7 =C3=9CNAL --- drivers/pinctrl/Kconfig | 1 - drivers/pinctrl/Makefile | 1 - drivers/pinctrl/mediatek/Kconfig | 51 ++++++++++- drivers/pinctrl/mediatek/Makefile | 63 +++++++------ .../{ralink =3D> mediatek}/pinctrl-mt7620.c | 34 +++---- .../{ralink =3D> mediatek}/pinctrl-mt7621.c | 30 +++---- .../{ralink =3D> mediatek}/pinctrl-mt76x8.c | 60 ++++++------- .../pinctrl-mtmips.c} | 90 +++++++++---------- .../pinctrl-mtmips.h} | 16 ++-- .../{ralink =3D> mediatek}/pinctrl-rt2880.c | 20 ++--- .../{ralink =3D> mediatek}/pinctrl-rt305x.c | 44 ++++----- .../{ralink =3D> mediatek}/pinctrl-rt3883.c | 28 +++--- drivers/pinctrl/ralink/Kconfig | 40 --------- drivers/pinctrl/ralink/Makefile | 9 -- 14 files changed, 246 insertions(+), 241 deletions(-) rename drivers/pinctrl/{ralink =3D> mediatek}/pinctrl-mt7620.c (81%) rename drivers/pinctrl/{ralink =3D> mediatek}/pinctrl-mt7621.c (80%) rename drivers/pinctrl/{ralink =3D> mediatek}/pinctrl-mt76x8.c (81%) rename drivers/pinctrl/{ralink/pinctrl-ralink.c =3D> mediatek/pinctrl-mtmi= ps.c} (74%) rename drivers/pinctrl/{ralink/pinctrl-ralink.h =3D> mediatek/pinctrl-mtmi= ps.h} (75%) rename drivers/pinctrl/{ralink =3D> mediatek}/pinctrl-rt2880.c (71%) rename drivers/pinctrl/{ralink =3D> mediatek}/pinctrl-rt305x.c (75%) rename drivers/pinctrl/{ralink =3D> mediatek}/pinctrl-rt3883.c (80%) delete mode 100644 drivers/pinctrl/ralink/Kconfig delete mode 100644 drivers/pinctrl/ralink/Makefile diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig index dcb53c4a9584..8a6012770640 100644 --- a/drivers/pinctrl/Kconfig +++ b/drivers/pinctrl/Kconfig @@ -537,7 +537,6 @@ source "drivers/pinctrl/nomadik/Kconfig" source "drivers/pinctrl/nuvoton/Kconfig" source "drivers/pinctrl/pxa/Kconfig" source "drivers/pinctrl/qcom/Kconfig" -source "drivers/pinctrl/ralink/Kconfig" source "drivers/pinctrl/renesas/Kconfig" source "drivers/pinctrl/samsung/Kconfig" source "drivers/pinctrl/spear/Kconfig" diff --git a/drivers/pinctrl/Makefile b/drivers/pinctrl/Makefile index d5939840bb2a..ada6ed1d4e91 100644 --- a/drivers/pinctrl/Makefile +++ b/drivers/pinctrl/Makefile @@ -66,7 +66,6 @@ obj-y +=3D nomadik/ obj-y +=3D nuvoton/ obj-$(CONFIG_PINCTRL_PXA) +=3D pxa/ obj-$(CONFIG_ARCH_QCOM) +=3D qcom/ -obj-$(CONFIG_PINCTRL_RALINK) +=3D ralink/ obj-$(CONFIG_PINCTRL_RENESAS) +=3D renesas/ obj-$(CONFIG_PINCTRL_SAMSUNG) +=3D samsung/ obj-$(CONFIG_PINCTRL_SPEAR) +=3D spear/ diff --git a/drivers/pinctrl/mediatek/Kconfig b/drivers/pinctrl/mediatek/Kc= onfig index a71874fed3d6..3a6b99b23f35 100644 --- a/drivers/pinctrl/mediatek/Kconfig +++ b/drivers/pinctrl/mediatek/Kconfig @@ -1,6 +1,6 @@ # SPDX-License-Identifier: GPL-2.0-only menu "MediaTek pinctrl drivers" - depends on ARCH_MEDIATEK || COMPILE_TEST + depends on ARCH_MEDIATEK || RALINK || COMPILE_TEST =20 config EINT_MTK tristate "MediaTek External Interrupt Support" @@ -22,6 +22,12 @@ config PINCTRL_MTK config PINCTRL_MTK_V2 tristate =20 +config PINCTRL_MTK_MTMIPS + bool + depends on RALINK + select PINMUX + select GENERIC_PINCONF + config PINCTRL_MTK_MOORE bool depends on OF @@ -43,6 +49,49 @@ config PINCTRL_MTK_PARIS select OF_GPIO select PINCTRL_MTK_V2 =20 +# For MIPS SoCs +config PINCTRL_MT7620 + bool "MediaTek MT7620 pin control" + depends on SOC_MT7620 || COMPILE_TEST + depends on RALINK + default SOC_MT7620 + select PINCTRL_MTK_MTMIPS + +config PINCTRL_MT7621 + bool "MediaTek MT7621 pin control" + depends on SOC_MT7621 || COMPILE_TEST + depends on RALINK + default SOC_MT7621 + select PINCTRL_MTK_MTMIPS + +config PINCTRL_MT76X8 + bool "MediaTek MT76X8 pin control" + depends on SOC_MT7620 || COMPILE_TEST + depends on RALINK + default SOC_MT7620 + select PINCTRL_MTK_MTMIPS + +config PINCTRL_RT2880 + bool "MediaTek RT2880 pin control" + depends on SOC_RT288X || COMPILE_TEST + depends on RALINK + default SOC_RT288X + select PINCTRL_MTK_MTMIPS + +config PINCTRL_RT305X + bool "MediaTek RT305X pin control" + depends on SOC_RT305X || COMPILE_TEST + depends on RALINK + default SOC_RT305X + select PINCTRL_MTK_MTMIPS + +config PINCTRL_RT3883 + bool "MediaTek RT3883 pin control" + depends on SOC_RT3883 || COMPILE_TEST + depends on RALINK + default SOC_RT3883 + select PINCTRL_MTK_MTMIPS + # For ARMv7 SoCs config PINCTRL_MT2701 bool "MediaTek MT2701 pin control" diff --git a/drivers/pinctrl/mediatek/Makefile b/drivers/pinctrl/mediatek/M= akefile index 44d197af516a..680f7e8526e0 100644 --- a/drivers/pinctrl/mediatek/Makefile +++ b/drivers/pinctrl/mediatek/Makefile @@ -1,32 +1,39 @@ # SPDX-License-Identifier: GPL-2.0 # Core -obj-$(CONFIG_EINT_MTK) +=3D mtk-eint.o -obj-$(CONFIG_PINCTRL_MTK) +=3D pinctrl-mtk-common.o -obj-$(CONFIG_PINCTRL_MTK_V2) +=3D pinctrl-mtk-common-v2.o -obj-$(CONFIG_PINCTRL_MTK_MOORE) +=3D pinctrl-moore.o -obj-$(CONFIG_PINCTRL_MTK_PARIS) +=3D pinctrl-paris.o +obj-$(CONFIG_EINT_MTK) +=3D mtk-eint.o +obj-$(CONFIG_PINCTRL_MTK) +=3D pinctrl-mtk-common.o +obj-$(CONFIG_PINCTRL_MTK_V2) +=3D pinctrl-mtk-common-v2.o +obj-$(CONFIG_PINCTRL_MTK_MTMIPS) +=3D pinctrl-mtmips.o +obj-$(CONFIG_PINCTRL_MTK_MOORE) +=3D pinctrl-moore.o +obj-$(CONFIG_PINCTRL_MTK_PARIS) +=3D pinctrl-paris.o =20 # SoC Drivers -obj-$(CONFIG_PINCTRL_MT2701) +=3D pinctrl-mt2701.o -obj-$(CONFIG_PINCTRL_MT2712) +=3D pinctrl-mt2712.o -obj-$(CONFIG_PINCTRL_MT8135) +=3D pinctrl-mt8135.o -obj-$(CONFIG_PINCTRL_MT8127) +=3D pinctrl-mt8127.o -obj-$(CONFIG_PINCTRL_MT6765) +=3D pinctrl-mt6765.o -obj-$(CONFIG_PINCTRL_MT6779) +=3D pinctrl-mt6779.o -obj-$(CONFIG_PINCTRL_MT6795) +=3D pinctrl-mt6795.o -obj-$(CONFIG_PINCTRL_MT6797) +=3D pinctrl-mt6797.o -obj-$(CONFIG_PINCTRL_MT7622) +=3D pinctrl-mt7622.o -obj-$(CONFIG_PINCTRL_MT7623) +=3D pinctrl-mt7623.o -obj-$(CONFIG_PINCTRL_MT7629) +=3D pinctrl-mt7629.o -obj-$(CONFIG_PINCTRL_MT7981) +=3D pinctrl-mt7981.o -obj-$(CONFIG_PINCTRL_MT7986) +=3D pinctrl-mt7986.o -obj-$(CONFIG_PINCTRL_MT8167) +=3D pinctrl-mt8167.o -obj-$(CONFIG_PINCTRL_MT8173) +=3D pinctrl-mt8173.o -obj-$(CONFIG_PINCTRL_MT8183) +=3D pinctrl-mt8183.o -obj-$(CONFIG_PINCTRL_MT8186) +=3D pinctrl-mt8186.o -obj-$(CONFIG_PINCTRL_MT8188) +=3D pinctrl-mt8188.o -obj-$(CONFIG_PINCTRL_MT8192) +=3D pinctrl-mt8192.o -obj-$(CONFIG_PINCTRL_MT8195) +=3D pinctrl-mt8195.o -obj-$(CONFIG_PINCTRL_MT8365) +=3D pinctrl-mt8365.o -obj-$(CONFIG_PINCTRL_MT8516) +=3D pinctrl-mt8516.o -obj-$(CONFIG_PINCTRL_MT6397) +=3D pinctrl-mt6397.o +obj-$(CONFIG_PINCTRL_MT7620) +=3D pinctrl-mt7620.o +obj-$(CONFIG_PINCTRL_MT7621) +=3D pinctrl-mt7621.o +obj-$(CONFIG_PINCTRL_MT76X8) +=3D pinctrl-mt76x8.o +obj-$(CONFIG_PINCTRL_RT2880) +=3D pinctrl-rt2880.o +obj-$(CONFIG_PINCTRL_RT305X) +=3D pinctrl-rt305x.o +obj-$(CONFIG_PINCTRL_RT3883) +=3D pinctrl-rt3883.o +obj-$(CONFIG_PINCTRL_MT2701) +=3D pinctrl-mt2701.o +obj-$(CONFIG_PINCTRL_MT2712) +=3D pinctrl-mt2712.o +obj-$(CONFIG_PINCTRL_MT8135) +=3D pinctrl-mt8135.o +obj-$(CONFIG_PINCTRL_MT8127) +=3D pinctrl-mt8127.o +obj-$(CONFIG_PINCTRL_MT6765) +=3D pinctrl-mt6765.o +obj-$(CONFIG_PINCTRL_MT6779) +=3D pinctrl-mt6779.o +obj-$(CONFIG_PINCTRL_MT6795) +=3D pinctrl-mt6795.o +obj-$(CONFIG_PINCTRL_MT6797) +=3D pinctrl-mt6797.o +obj-$(CONFIG_PINCTRL_MT7622) +=3D pinctrl-mt7622.o +obj-$(CONFIG_PINCTRL_MT7623) +=3D pinctrl-mt7623.o +obj-$(CONFIG_PINCTRL_MT7629) +=3D pinctrl-mt7629.o +obj-$(CONFIG_PINCTRL_MT7981) +=3D pinctrl-mt7981.o +obj-$(CONFIG_PINCTRL_MT7986) +=3D pinctrl-mt7986.o +obj-$(CONFIG_PINCTRL_MT8167) +=3D pinctrl-mt8167.o +obj-$(CONFIG_PINCTRL_MT8173) +=3D pinctrl-mt8173.o +obj-$(CONFIG_PINCTRL_MT8183) +=3D pinctrl-mt8183.o +obj-$(CONFIG_PINCTRL_MT8186) +=3D pinctrl-mt8186.o +obj-$(CONFIG_PINCTRL_MT8188) +=3D pinctrl-mt8188.o +obj-$(CONFIG_PINCTRL_MT8192) +=3D pinctrl-mt8192.o +obj-$(CONFIG_PINCTRL_MT8195) +=3D pinctrl-mt8195.o +obj-$(CONFIG_PINCTRL_MT8365) +=3D pinctrl-mt8365.o +obj-$(CONFIG_PINCTRL_MT8516) +=3D pinctrl-mt8516.o +obj-$(CONFIG_PINCTRL_MT6397) +=3D pinctrl-mt6397.o diff --git a/drivers/pinctrl/ralink/pinctrl-mt7620.c b/drivers/pinctrl/medi= atek/pinctrl-mt7620.c similarity index 81% rename from drivers/pinctrl/ralink/pinctrl-mt7620.c rename to drivers/pinctrl/mediatek/pinctrl-mt7620.c index b2245fd65c72..1a2dbbdd25f1 100644 --- a/drivers/pinctrl/ralink/pinctrl-mt7620.c +++ b/drivers/pinctrl/mediatek/pinctrl-mt7620.c @@ -3,7 +3,7 @@ #include #include #include -#include "pinctrl-ralink.h" +#include "pinctrl-mtmips.h" =20 #define MT7620_GPIO_MODE_UART0_SHIFT 2 #define MT7620_GPIO_MODE_UART0_MASK 0x7 @@ -52,20 +52,20 @@ #define MT7620_GPIO_MODE_EPHY 15 #define MT7620_GPIO_MODE_PA 20 =20 -static struct ralink_pmx_func i2c_grp[] =3D { FUNC("i2c", 0, 1, 2) }; -static struct ralink_pmx_func spi_grp[] =3D { FUNC("spi", 0, 3, 4) }; -static struct ralink_pmx_func uartlite_grp[] =3D { FUNC("uartlite", 0, 15,= 2) }; -static struct ralink_pmx_func mdio_grp[] =3D { +static struct mtmips_pmx_func i2c_grp[] =3D { FUNC("i2c", 0, 1, 2) }; +static struct mtmips_pmx_func spi_grp[] =3D { FUNC("spi", 0, 3, 4) }; +static struct mtmips_pmx_func uartlite_grp[] =3D { FUNC("uartlite", 0, 15,= 2) }; +static struct mtmips_pmx_func mdio_grp[] =3D { FUNC("mdio", MT7620_GPIO_MODE_MDIO, 22, 2), FUNC("refclk", MT7620_GPIO_MODE_MDIO_REFCLK, 22, 2), }; -static struct ralink_pmx_func rgmii1_grp[] =3D { FUNC("rgmii1", 0, 24, 12)= }; -static struct ralink_pmx_func refclk_grp[] =3D { FUNC("spi refclk", 0, 37,= 3) }; -static struct ralink_pmx_func ephy_grp[] =3D { FUNC("ephy", 0, 40, 5) }; -static struct ralink_pmx_func rgmii2_grp[] =3D { FUNC("rgmii2", 0, 60, 12)= }; -static struct ralink_pmx_func wled_grp[] =3D { FUNC("wled", 0, 72, 1) }; -static struct ralink_pmx_func pa_grp[] =3D { FUNC("pa", 0, 18, 4) }; -static struct ralink_pmx_func uartf_grp[] =3D { +static struct mtmips_pmx_func rgmii1_grp[] =3D { FUNC("rgmii1", 0, 24, 12)= }; +static struct mtmips_pmx_func refclk_grp[] =3D { FUNC("spi refclk", 0, 37,= 3) }; +static struct mtmips_pmx_func ephy_grp[] =3D { FUNC("ephy", 0, 40, 5) }; +static struct mtmips_pmx_func rgmii2_grp[] =3D { FUNC("rgmii2", 0, 60, 12)= }; +static struct mtmips_pmx_func wled_grp[] =3D { FUNC("wled", 0, 72, 1) }; +static struct mtmips_pmx_func pa_grp[] =3D { FUNC("pa", 0, 18, 4) }; +static struct mtmips_pmx_func uartf_grp[] =3D { FUNC("uartf", MT7620_GPIO_MODE_UARTF, 7, 8), FUNC("pcm uartf", MT7620_GPIO_MODE_PCM_UARTF, 7, 8), FUNC("pcm i2s", MT7620_GPIO_MODE_PCM_I2S, 7, 8), @@ -74,20 +74,20 @@ static struct ralink_pmx_func uartf_grp[] =3D { FUNC("gpio uartf", MT7620_GPIO_MODE_GPIO_UARTF, 7, 4), FUNC("gpio i2s", MT7620_GPIO_MODE_GPIO_I2S, 7, 4), }; -static struct ralink_pmx_func wdt_grp[] =3D { +static struct mtmips_pmx_func wdt_grp[] =3D { FUNC("wdt rst", 0, 17, 1), FUNC("wdt refclk", 0, 17, 1), }; -static struct ralink_pmx_func pcie_rst_grp[] =3D { +static struct mtmips_pmx_func pcie_rst_grp[] =3D { FUNC("pcie rst", MT7620_GPIO_MODE_PCIE_RST, 36, 1), FUNC("pcie refclk", MT7620_GPIO_MODE_PCIE_REF, 36, 1) }; -static struct ralink_pmx_func nd_sd_grp[] =3D { +static struct mtmips_pmx_func nd_sd_grp[] =3D { FUNC("nand", MT7620_GPIO_MODE_NAND, 45, 15), FUNC("sd", MT7620_GPIO_MODE_SD, 47, 13) }; =20 -static struct ralink_pmx_group mt7620a_pinmux_data[] =3D { +static struct mtmips_pmx_group mt7620a_pinmux_data[] =3D { GRP("i2c", i2c_grp, 1, MT7620_GPIO_MODE_I2C), GRP("uartf", uartf_grp, MT7620_GPIO_MODE_UART0_MASK, MT7620_GPIO_MODE_UART0_SHIFT), @@ -112,7 +112,7 @@ static struct ralink_pmx_group mt7620a_pinmux_data[] = =3D { =20 static int mt7620_pinctrl_probe(struct platform_device *pdev) { - return ralink_pinctrl_init(pdev, mt7620a_pinmux_data); + return mtmips_pinctrl_init(pdev, mt7620a_pinmux_data); } =20 static const struct of_device_id mt7620_pinctrl_match[] =3D { diff --git a/drivers/pinctrl/ralink/pinctrl-mt7621.c b/drivers/pinctrl/medi= atek/pinctrl-mt7621.c similarity index 80% rename from drivers/pinctrl/ralink/pinctrl-mt7621.c rename to drivers/pinctrl/mediatek/pinctrl-mt7621.c index 2128a94f6d1b..96c5ef942cf4 100644 --- a/drivers/pinctrl/ralink/pinctrl-mt7621.c +++ b/drivers/pinctrl/mediatek/pinctrl-mt7621.c @@ -3,7 +3,7 @@ #include #include #include -#include "pinctrl-ralink.h" +#include "pinctrl-mtmips.h" =20 #define MT7621_GPIO_MODE_UART1 1 #define MT7621_GPIO_MODE_I2C 2 @@ -34,40 +34,40 @@ #define MT7621_GPIO_MODE_SDHCI_SHIFT 18 #define MT7621_GPIO_MODE_SDHCI_GPIO 1 =20 -static struct ralink_pmx_func uart1_grp[] =3D { FUNC("uart1", 0, 1, 2) }; -static struct ralink_pmx_func i2c_grp[] =3D { FUNC("i2c", 0, 3, 2) }; -static struct ralink_pmx_func uart3_grp[] =3D { +static struct mtmips_pmx_func uart1_grp[] =3D { FUNC("uart1", 0, 1, 2) }; +static struct mtmips_pmx_func i2c_grp[] =3D { FUNC("i2c", 0, 3, 2) }; +static struct mtmips_pmx_func uart3_grp[] =3D { FUNC("uart3", 0, 5, 4), FUNC("i2s", 2, 5, 4), FUNC("spdif3", 3, 5, 4), }; -static struct ralink_pmx_func uart2_grp[] =3D { +static struct mtmips_pmx_func uart2_grp[] =3D { FUNC("uart2", 0, 9, 4), FUNC("pcm", 2, 9, 4), FUNC("spdif2", 3, 9, 4), }; -static struct ralink_pmx_func jtag_grp[] =3D { FUNC("jtag", 0, 13, 5) }; -static struct ralink_pmx_func wdt_grp[] =3D { +static struct mtmips_pmx_func jtag_grp[] =3D { FUNC("jtag", 0, 13, 5) }; +static struct mtmips_pmx_func wdt_grp[] =3D { FUNC("wdt rst", 0, 18, 1), FUNC("wdt refclk", 2, 18, 1), }; -static struct ralink_pmx_func pcie_rst_grp[] =3D { +static struct mtmips_pmx_func pcie_rst_grp[] =3D { FUNC("pcie rst", MT7621_GPIO_MODE_PCIE_RST, 19, 1), FUNC("pcie refclk", MT7621_GPIO_MODE_PCIE_REF, 19, 1) }; -static struct ralink_pmx_func mdio_grp[] =3D { FUNC("mdio", 0, 20, 2) }; -static struct ralink_pmx_func rgmii2_grp[] =3D { FUNC("rgmii2", 0, 22, 12)= }; -static struct ralink_pmx_func spi_grp[] =3D { +static struct mtmips_pmx_func mdio_grp[] =3D { FUNC("mdio", 0, 20, 2) }; +static struct mtmips_pmx_func rgmii2_grp[] =3D { FUNC("rgmii2", 0, 22, 12)= }; +static struct mtmips_pmx_func spi_grp[] =3D { FUNC("spi", 0, 34, 7), FUNC("nand1", 2, 34, 7), }; -static struct ralink_pmx_func sdhci_grp[] =3D { +static struct mtmips_pmx_func sdhci_grp[] =3D { FUNC("sdhci", 0, 41, 8), FUNC("nand2", 2, 41, 8), }; -static struct ralink_pmx_func rgmii1_grp[] =3D { FUNC("rgmii1", 0, 49, 12)= }; +static struct mtmips_pmx_func rgmii1_grp[] =3D { FUNC("rgmii1", 0, 49, 12)= }; =20 -static struct ralink_pmx_group mt7621_pinmux_data[] =3D { +static struct mtmips_pmx_group mt7621_pinmux_data[] =3D { GRP("uart1", uart1_grp, 1, MT7621_GPIO_MODE_UART1), GRP("i2c", i2c_grp, 1, MT7621_GPIO_MODE_I2C), GRP_G("uart3", uart3_grp, MT7621_GPIO_MODE_UART3_MASK, @@ -92,7 +92,7 @@ static struct ralink_pmx_group mt7621_pinmux_data[] =3D { =20 static int mt7621_pinctrl_probe(struct platform_device *pdev) { - return ralink_pinctrl_init(pdev, mt7621_pinmux_data); + return mtmips_pinctrl_init(pdev, mt7621_pinmux_data); } =20 static const struct of_device_id mt7621_pinctrl_match[] =3D { diff --git a/drivers/pinctrl/ralink/pinctrl-mt76x8.c b/drivers/pinctrl/medi= atek/pinctrl-mt76x8.c similarity index 81% rename from drivers/pinctrl/ralink/pinctrl-mt76x8.c rename to drivers/pinctrl/mediatek/pinctrl-mt76x8.c index 5a6a82a58180..1d463bcfb1bd 100644 --- a/drivers/pinctrl/ralink/pinctrl-mt76x8.c +++ b/drivers/pinctrl/mediatek/pinctrl-mt76x8.c @@ -3,7 +3,7 @@ #include #include #include -#include "pinctrl-ralink.h" +#include "pinctrl-mtmips.h" =20 #define MT76X8_GPIO_MODE_MASK 0x3 =20 @@ -35,173 +35,173 @@ #define MT76X8_GPIO_MODE_SPIS 2 #define MT76X8_GPIO_MODE_GPIO 0 =20 -static struct ralink_pmx_func pwm1_grp[] =3D { +static struct mtmips_pmx_func pwm1_grp[] =3D { FUNC("sdxc d6", 3, 19, 1), FUNC("utif", 2, 19, 1), FUNC("gpio", 1, 19, 1), FUNC("pwm1", 0, 19, 1), }; =20 -static struct ralink_pmx_func pwm0_grp[] =3D { +static struct mtmips_pmx_func pwm0_grp[] =3D { FUNC("sdxc d7", 3, 18, 1), FUNC("utif", 2, 18, 1), FUNC("gpio", 1, 18, 1), FUNC("pwm0", 0, 18, 1), }; =20 -static struct ralink_pmx_func uart2_grp[] =3D { +static struct mtmips_pmx_func uart2_grp[] =3D { FUNC("sdxc d5 d4", 3, 20, 2), FUNC("pwm", 2, 20, 2), FUNC("gpio", 1, 20, 2), FUNC("uart2", 0, 20, 2), }; =20 -static struct ralink_pmx_func uart1_grp[] =3D { +static struct mtmips_pmx_func uart1_grp[] =3D { FUNC("sw_r", 3, 45, 2), FUNC("pwm", 2, 45, 2), FUNC("gpio", 1, 45, 2), FUNC("uart1", 0, 45, 2), }; =20 -static struct ralink_pmx_func i2c_grp[] =3D { +static struct mtmips_pmx_func i2c_grp[] =3D { FUNC("-", 3, 4, 2), FUNC("debug", 2, 4, 2), FUNC("gpio", 1, 4, 2), FUNC("i2c", 0, 4, 2), }; =20 -static struct ralink_pmx_func refclk_grp[] =3D { FUNC("refclk", 0, 37, 1) = }; -static struct ralink_pmx_func perst_grp[] =3D { FUNC("perst", 0, 36, 1) }; -static struct ralink_pmx_func wdt_grp[] =3D { FUNC("wdt", 0, 38, 1) }; -static struct ralink_pmx_func spi_grp[] =3D { FUNC("spi", 0, 7, 4) }; +static struct mtmips_pmx_func refclk_grp[] =3D { FUNC("refclk", 0, 37, 1) = }; +static struct mtmips_pmx_func perst_grp[] =3D { FUNC("perst", 0, 36, 1) }; +static struct mtmips_pmx_func wdt_grp[] =3D { FUNC("wdt", 0, 38, 1) }; +static struct mtmips_pmx_func spi_grp[] =3D { FUNC("spi", 0, 7, 4) }; =20 -static struct ralink_pmx_func sd_mode_grp[] =3D { +static struct mtmips_pmx_func sd_mode_grp[] =3D { FUNC("jtag", 3, 22, 8), FUNC("utif", 2, 22, 8), FUNC("gpio", 1, 22, 8), FUNC("sdxc", 0, 22, 8), }; =20 -static struct ralink_pmx_func uart0_grp[] =3D { +static struct mtmips_pmx_func uart0_grp[] =3D { FUNC("-", 3, 12, 2), FUNC("-", 2, 12, 2), FUNC("gpio", 1, 12, 2), FUNC("uart0", 0, 12, 2), }; =20 -static struct ralink_pmx_func i2s_grp[] =3D { +static struct mtmips_pmx_func i2s_grp[] =3D { FUNC("antenna", 3, 0, 4), FUNC("pcm", 2, 0, 4), FUNC("gpio", 1, 0, 4), FUNC("i2s", 0, 0, 4), }; =20 -static struct ralink_pmx_func spi_cs1_grp[] =3D { +static struct mtmips_pmx_func spi_cs1_grp[] =3D { FUNC("-", 3, 6, 1), FUNC("refclk", 2, 6, 1), FUNC("gpio", 1, 6, 1), FUNC("spi cs1", 0, 6, 1), }; =20 -static struct ralink_pmx_func spis_grp[] =3D { +static struct mtmips_pmx_func spis_grp[] =3D { FUNC("pwm_uart2", 3, 14, 4), FUNC("utif", 2, 14, 4), FUNC("gpio", 1, 14, 4), FUNC("spis", 0, 14, 4), }; =20 -static struct ralink_pmx_func gpio_grp[] =3D { +static struct mtmips_pmx_func gpio_grp[] =3D { FUNC("pcie", 3, 11, 1), FUNC("refclk", 2, 11, 1), FUNC("gpio", 1, 11, 1), FUNC("gpio", 0, 11, 1), }; =20 -static struct ralink_pmx_func p4led_kn_grp[] =3D { +static struct mtmips_pmx_func p4led_kn_grp[] =3D { FUNC("jtag", 3, 30, 1), FUNC("utif", 2, 30, 1), FUNC("gpio", 1, 30, 1), FUNC("p4led_kn", 0, 30, 1), }; =20 -static struct ralink_pmx_func p3led_kn_grp[] =3D { +static struct mtmips_pmx_func p3led_kn_grp[] =3D { FUNC("jtag", 3, 31, 1), FUNC("utif", 2, 31, 1), FUNC("gpio", 1, 31, 1), FUNC("p3led_kn", 0, 31, 1), }; =20 -static struct ralink_pmx_func p2led_kn_grp[] =3D { +static struct mtmips_pmx_func p2led_kn_grp[] =3D { FUNC("jtag", 3, 32, 1), FUNC("utif", 2, 32, 1), FUNC("gpio", 1, 32, 1), FUNC("p2led_kn", 0, 32, 1), }; =20 -static struct ralink_pmx_func p1led_kn_grp[] =3D { +static struct mtmips_pmx_func p1led_kn_grp[] =3D { FUNC("jtag", 3, 33, 1), FUNC("utif", 2, 33, 1), FUNC("gpio", 1, 33, 1), FUNC("p1led_kn", 0, 33, 1), }; =20 -static struct ralink_pmx_func p0led_kn_grp[] =3D { +static struct mtmips_pmx_func p0led_kn_grp[] =3D { FUNC("jtag", 3, 34, 1), FUNC("rsvd", 2, 34, 1), FUNC("gpio", 1, 34, 1), FUNC("p0led_kn", 0, 34, 1), }; =20 -static struct ralink_pmx_func wled_kn_grp[] =3D { +static struct mtmips_pmx_func wled_kn_grp[] =3D { FUNC("rsvd", 3, 35, 1), FUNC("rsvd", 2, 35, 1), FUNC("gpio", 1, 35, 1), FUNC("wled_kn", 0, 35, 1), }; =20 -static struct ralink_pmx_func p4led_an_grp[] =3D { +static struct mtmips_pmx_func p4led_an_grp[] =3D { FUNC("jtag", 3, 39, 1), FUNC("utif", 2, 39, 1), FUNC("gpio", 1, 39, 1), FUNC("p4led_an", 0, 39, 1), }; =20 -static struct ralink_pmx_func p3led_an_grp[] =3D { +static struct mtmips_pmx_func p3led_an_grp[] =3D { FUNC("jtag", 3, 40, 1), FUNC("utif", 2, 40, 1), FUNC("gpio", 1, 40, 1), FUNC("p3led_an", 0, 40, 1), }; =20 -static struct ralink_pmx_func p2led_an_grp[] =3D { +static struct mtmips_pmx_func p2led_an_grp[] =3D { FUNC("jtag", 3, 41, 1), FUNC("utif", 2, 41, 1), FUNC("gpio", 1, 41, 1), FUNC("p2led_an", 0, 41, 1), }; =20 -static struct ralink_pmx_func p1led_an_grp[] =3D { +static struct mtmips_pmx_func p1led_an_grp[] =3D { FUNC("jtag", 3, 42, 1), FUNC("utif", 2, 42, 1), FUNC("gpio", 1, 42, 1), FUNC("p1led_an", 0, 42, 1), }; =20 -static struct ralink_pmx_func p0led_an_grp[] =3D { +static struct mtmips_pmx_func p0led_an_grp[] =3D { FUNC("jtag", 3, 43, 1), FUNC("rsvd", 2, 43, 1), FUNC("gpio", 1, 43, 1), FUNC("p0led_an", 0, 43, 1), }; =20 -static struct ralink_pmx_func wled_an_grp[] =3D { +static struct mtmips_pmx_func wled_an_grp[] =3D { FUNC("rsvd", 3, 44, 1), FUNC("rsvd", 2, 44, 1), FUNC("gpio", 1, 44, 1), FUNC("wled_an", 0, 44, 1), }; =20 -static struct ralink_pmx_group mt76x8_pinmux_data[] =3D { +static struct mtmips_pmx_group mt76x8_pinmux_data[] =3D { GRP_G("pwm1", pwm1_grp, MT76X8_GPIO_MODE_MASK, 1, MT76X8_GPIO_MODE_PWM1), GRP_G("pwm0", pwm0_grp, MT76X8_GPIO_MODE_MASK, @@ -257,7 +257,7 @@ static struct ralink_pmx_group mt76x8_pinmux_data[] =3D= { =20 static int mt76x8_pinctrl_probe(struct platform_device *pdev) { - return ralink_pinctrl_init(pdev, mt76x8_pinmux_data); + return mtmips_pinctrl_init(pdev, mt76x8_pinmux_data); } =20 static const struct of_device_id mt76x8_pinctrl_match[] =3D { diff --git a/drivers/pinctrl/ralink/pinctrl-ralink.c b/drivers/pinctrl/medi= atek/pinctrl-mtmips.c similarity index 74% rename from drivers/pinctrl/ralink/pinctrl-ralink.c rename to drivers/pinctrl/mediatek/pinctrl-mtmips.c index 770862f45b3f..efd77b6c56a1 100644 --- a/drivers/pinctrl/ralink/pinctrl-ralink.c +++ b/drivers/pinctrl/mediatek/pinctrl-mtmips.c @@ -19,23 +19,23 @@ #include #include =20 -#include "pinctrl-ralink.h" +#include "pinctrl-mtmips.h" #include "../core.h" #include "../pinctrl-utils.h" =20 #define SYSC_REG_GPIO_MODE 0x60 #define SYSC_REG_GPIO_MODE2 0x64 =20 -struct ralink_priv { +struct mtmips_priv { struct device *dev; =20 struct pinctrl_pin_desc *pads; struct pinctrl_desc *desc; =20 - struct ralink_pmx_func **func; + struct mtmips_pmx_func **func; int func_count; =20 - struct ralink_pmx_group *groups; + struct mtmips_pmx_group *groups; const char **group_names; int group_count; =20 @@ -43,27 +43,27 @@ struct ralink_priv { int max_pins; }; =20 -static int ralink_get_group_count(struct pinctrl_dev *pctrldev) +static int mtmips_get_group_count(struct pinctrl_dev *pctrldev) { - struct ralink_priv *p =3D pinctrl_dev_get_drvdata(pctrldev); + struct mtmips_priv *p =3D pinctrl_dev_get_drvdata(pctrldev); =20 return p->group_count; } =20 -static const char *ralink_get_group_name(struct pinctrl_dev *pctrldev, +static const char *mtmips_get_group_name(struct pinctrl_dev *pctrldev, unsigned int group) { - struct ralink_priv *p =3D pinctrl_dev_get_drvdata(pctrldev); + struct mtmips_priv *p =3D pinctrl_dev_get_drvdata(pctrldev); =20 return (group >=3D p->group_count) ? NULL : p->group_names[group]; } =20 -static int ralink_get_group_pins(struct pinctrl_dev *pctrldev, +static int mtmips_get_group_pins(struct pinctrl_dev *pctrldev, unsigned int group, const unsigned int **pins, unsigned int *num_pins) { - struct ralink_priv *p =3D pinctrl_dev_get_drvdata(pctrldev); + struct mtmips_priv *p =3D pinctrl_dev_get_drvdata(pctrldev); =20 if (group >=3D p->group_count) return -EINVAL; @@ -74,35 +74,35 @@ static int ralink_get_group_pins(struct pinctrl_dev *pc= trldev, return 0; } =20 -static const struct pinctrl_ops ralink_pctrl_ops =3D { - .get_groups_count =3D ralink_get_group_count, - .get_group_name =3D ralink_get_group_name, - .get_group_pins =3D ralink_get_group_pins, +static const struct pinctrl_ops mtmips_pctrl_ops =3D { + .get_groups_count =3D mtmips_get_group_count, + .get_group_name =3D mtmips_get_group_name, + .get_group_pins =3D mtmips_get_group_pins, .dt_node_to_map =3D pinconf_generic_dt_node_to_map_all, .dt_free_map =3D pinconf_generic_dt_free_map, }; =20 -static int ralink_pmx_func_count(struct pinctrl_dev *pctrldev) +static int mtmips_pmx_func_count(struct pinctrl_dev *pctrldev) { - struct ralink_priv *p =3D pinctrl_dev_get_drvdata(pctrldev); + struct mtmips_priv *p =3D pinctrl_dev_get_drvdata(pctrldev); =20 return p->func_count; } =20 -static const char *ralink_pmx_func_name(struct pinctrl_dev *pctrldev, +static const char *mtmips_pmx_func_name(struct pinctrl_dev *pctrldev, unsigned int func) { - struct ralink_priv *p =3D pinctrl_dev_get_drvdata(pctrldev); + struct mtmips_priv *p =3D pinctrl_dev_get_drvdata(pctrldev); =20 return p->func[func]->name; } =20 -static int ralink_pmx_group_get_groups(struct pinctrl_dev *pctrldev, +static int mtmips_pmx_group_get_groups(struct pinctrl_dev *pctrldev, unsigned int func, const char * const **groups, unsigned int * const num_groups) { - struct ralink_priv *p =3D pinctrl_dev_get_drvdata(pctrldev); + struct mtmips_priv *p =3D pinctrl_dev_get_drvdata(pctrldev); =20 if (p->func[func]->group_count =3D=3D 1) *groups =3D &p->group_names[p->func[func]->groups[0]]; @@ -114,10 +114,10 @@ static int ralink_pmx_group_get_groups(struct pinctrl= _dev *pctrldev, return 0; } =20 -static int ralink_pmx_group_enable(struct pinctrl_dev *pctrldev, +static int mtmips_pmx_group_enable(struct pinctrl_dev *pctrldev, unsigned int func, unsigned int group) { - struct ralink_priv *p =3D pinctrl_dev_get_drvdata(pctrldev); + struct mtmips_priv *p =3D pinctrl_dev_get_drvdata(pctrldev); u32 mode =3D 0; u32 reg =3D SYSC_REG_GPIO_MODE; int i; @@ -158,11 +158,11 @@ static int ralink_pmx_group_enable(struct pinctrl_dev= *pctrldev, return 0; } =20 -static int ralink_pmx_group_gpio_request_enable(struct pinctrl_dev *pctrld= ev, +static int mtmips_pmx_group_gpio_request_enable(struct pinctrl_dev *pctrld= ev, struct pinctrl_gpio_range *range, unsigned int pin) { - struct ralink_priv *p =3D pinctrl_dev_get_drvdata(pctrldev); + struct mtmips_priv *p =3D pinctrl_dev_get_drvdata(pctrldev); =20 if (!p->gpio[pin]) { dev_err(p->dev, "pin %d is not set to gpio mux\n", pin); @@ -172,28 +172,28 @@ static int ralink_pmx_group_gpio_request_enable(struc= t pinctrl_dev *pctrldev, return 0; } =20 -static const struct pinmux_ops ralink_pmx_group_ops =3D { - .get_functions_count =3D ralink_pmx_func_count, - .get_function_name =3D ralink_pmx_func_name, - .get_function_groups =3D ralink_pmx_group_get_groups, - .set_mux =3D ralink_pmx_group_enable, - .gpio_request_enable =3D ralink_pmx_group_gpio_request_enable, +static const struct pinmux_ops mtmips_pmx_group_ops =3D { + .get_functions_count =3D mtmips_pmx_func_count, + .get_function_name =3D mtmips_pmx_func_name, + .get_function_groups =3D mtmips_pmx_group_get_groups, + .set_mux =3D mtmips_pmx_group_enable, + .gpio_request_enable =3D mtmips_pmx_group_gpio_request_enable, }; =20 -static struct pinctrl_desc ralink_pctrl_desc =3D { +static struct pinctrl_desc mtmips_pctrl_desc =3D { .owner =3D THIS_MODULE, - .name =3D "ralink-pinctrl", - .pctlops =3D &ralink_pctrl_ops, - .pmxops =3D &ralink_pmx_group_ops, + .name =3D "mtmips-pinctrl", + .pctlops =3D &mtmips_pctrl_ops, + .pmxops =3D &mtmips_pmx_group_ops, }; =20 -static struct ralink_pmx_func gpio_func =3D { +static struct mtmips_pmx_func gpio_func =3D { .name =3D "gpio", }; =20 -static int ralink_pinctrl_index(struct ralink_priv *p) +static int mtmips_pinctrl_index(struct mtmips_priv *p) { - struct ralink_pmx_group *mux =3D p->groups; + struct mtmips_pmx_group *mux =3D p->groups; int i, j, c =3D 0; =20 /* count the mux functions */ @@ -248,7 +248,7 @@ static int ralink_pinctrl_index(struct ralink_priv *p) return 0; } =20 -static int ralink_pinctrl_pins(struct ralink_priv *p) +static int mtmips_pinctrl_pins(struct mtmips_priv *p) { int i, j; =20 @@ -313,10 +313,10 @@ static int ralink_pinctrl_pins(struct ralink_priv *p) return 0; } =20 -int ralink_pinctrl_init(struct platform_device *pdev, - struct ralink_pmx_group *data) +int mtmips_pinctrl_init(struct platform_device *pdev, + struct mtmips_pmx_group *data) { - struct ralink_priv *p; + struct mtmips_priv *p; struct pinctrl_dev *dev; int err; =20 @@ -324,23 +324,23 @@ int ralink_pinctrl_init(struct platform_device *pdev, return -ENOTSUPP; =20 /* setup the private data */ - p =3D devm_kzalloc(&pdev->dev, sizeof(struct ralink_priv), GFP_KERNEL); + p =3D devm_kzalloc(&pdev->dev, sizeof(struct mtmips_priv), GFP_KERNEL); if (!p) return -ENOMEM; =20 p->dev =3D &pdev->dev; - p->desc =3D &ralink_pctrl_desc; + p->desc =3D &mtmips_pctrl_desc; p->groups =3D data; platform_set_drvdata(pdev, p); =20 /* init the device */ - err =3D ralink_pinctrl_index(p); + err =3D mtmips_pinctrl_index(p); if (err) { dev_err(&pdev->dev, "failed to load index\n"); return err; } =20 - err =3D ralink_pinctrl_pins(p); + err =3D mtmips_pinctrl_pins(p); if (err) { dev_err(&pdev->dev, "failed to load pins\n"); return err; diff --git a/drivers/pinctrl/ralink/pinctrl-ralink.h b/drivers/pinctrl/medi= atek/pinctrl-mtmips.h similarity index 75% rename from drivers/pinctrl/ralink/pinctrl-ralink.h rename to drivers/pinctrl/mediatek/pinctrl-mtmips.h index e6037be1e153..a7c3dd724431 100644 --- a/drivers/pinctrl/ralink/pinctrl-ralink.h +++ b/drivers/pinctrl/mediatek/pinctrl-mtmips.h @@ -3,8 +3,8 @@ * Copyright (C) 2012 John Crispin */ =20 -#ifndef _PINCTRL_RALINK_H__ -#define _PINCTRL_RALINK_H__ +#ifndef _PINCTRL_MTMIPS_H__ +#define _PINCTRL_MTMIPS_H__ =20 #define FUNC(name, value, pin_first, pin_count) \ { name, value, pin_first, pin_count } @@ -19,9 +19,9 @@ .func =3D _func, .gpio =3D _gpio, \ .func_count =3D ARRAY_SIZE(_func) } =20 -struct ralink_pmx_group; +struct mtmips_pmx_group; =20 -struct ralink_pmx_func { +struct mtmips_pmx_func { const char *name; const char value; =20 @@ -35,7 +35,7 @@ struct ralink_pmx_func { int enabled; }; =20 -struct ralink_pmx_group { +struct mtmips_pmx_group { const char *name; int enabled; =20 @@ -43,11 +43,11 @@ struct ralink_pmx_group { const char mask; const char gpio; =20 - struct ralink_pmx_func *func; + struct mtmips_pmx_func *func; int func_count; }; =20 -int ralink_pinctrl_init(struct platform_device *pdev, - struct ralink_pmx_group *data); +int mtmips_pinctrl_init(struct platform_device *pdev, + struct mtmips_pmx_group *data); =20 #endif diff --git a/drivers/pinctrl/ralink/pinctrl-rt2880.c b/drivers/pinctrl/medi= atek/pinctrl-rt2880.c similarity index 71% rename from drivers/pinctrl/ralink/pinctrl-rt2880.c rename to drivers/pinctrl/mediatek/pinctrl-rt2880.c index e57b1c5d03dd..d3b21e6242e1 100644 --- a/drivers/pinctrl/ralink/pinctrl-rt2880.c +++ b/drivers/pinctrl/mediatek/pinctrl-rt2880.c @@ -4,7 +4,7 @@ #include #include #include -#include "pinctrl-ralink.h" +#include "pinctrl-mtmips.h" =20 #define RT2880_GPIO_MODE_I2C BIT(0) #define RT2880_GPIO_MODE_UART0 BIT(1) @@ -15,15 +15,15 @@ #define RT2880_GPIO_MODE_SDRAM BIT(6) #define RT2880_GPIO_MODE_PCI BIT(7) =20 -static struct ralink_pmx_func i2c_grp[] =3D { FUNC("i2c", 0, 1, 2) }; -static struct ralink_pmx_func spi_grp[] =3D { FUNC("spi", 0, 3, 4) }; -static struct ralink_pmx_func uartlite_grp[] =3D { FUNC("uartlite", 0, 7, = 8) }; -static struct ralink_pmx_func jtag_grp[] =3D { FUNC("jtag", 0, 17, 5) }; -static struct ralink_pmx_func mdio_grp[] =3D { FUNC("mdio", 0, 22, 2) }; -static struct ralink_pmx_func sdram_grp[] =3D { FUNC("sdram", 0, 24, 16) }; -static struct ralink_pmx_func pci_grp[] =3D { FUNC("pci", 0, 40, 32) }; +static struct mtmips_pmx_func i2c_grp[] =3D { FUNC("i2c", 0, 1, 2) }; +static struct mtmips_pmx_func spi_grp[] =3D { FUNC("spi", 0, 3, 4) }; +static struct mtmips_pmx_func uartlite_grp[] =3D { FUNC("uartlite", 0, 7, = 8) }; +static struct mtmips_pmx_func jtag_grp[] =3D { FUNC("jtag", 0, 17, 5) }; +static struct mtmips_pmx_func mdio_grp[] =3D { FUNC("mdio", 0, 22, 2) }; +static struct mtmips_pmx_func sdram_grp[] =3D { FUNC("sdram", 0, 24, 16) }; +static struct mtmips_pmx_func pci_grp[] =3D { FUNC("pci", 0, 40, 32) }; =20 -static struct ralink_pmx_group rt2880_pinmux_data_act[] =3D { +static struct mtmips_pmx_group rt2880_pinmux_data_act[] =3D { GRP("i2c", i2c_grp, 1, RT2880_GPIO_MODE_I2C), GRP("spi", spi_grp, 1, RT2880_GPIO_MODE_SPI), GRP("uartlite", uartlite_grp, 1, RT2880_GPIO_MODE_UART0), @@ -36,7 +36,7 @@ static struct ralink_pmx_group rt2880_pinmux_data_act[] = =3D { =20 static int rt2880_pinctrl_probe(struct platform_device *pdev) { - return ralink_pinctrl_init(pdev, rt2880_pinmux_data_act); + return mtmips_pinctrl_init(pdev, rt2880_pinmux_data_act); } =20 static const struct of_device_id rt2880_pinctrl_match[] =3D { diff --git a/drivers/pinctrl/ralink/pinctrl-rt305x.c b/drivers/pinctrl/medi= atek/pinctrl-rt305x.c similarity index 75% rename from drivers/pinctrl/ralink/pinctrl-rt305x.c rename to drivers/pinctrl/mediatek/pinctrl-rt305x.c index a112a83085ea..3f46808ba11c 100644 --- a/drivers/pinctrl/ralink/pinctrl-rt305x.c +++ b/drivers/pinctrl/mediatek/pinctrl-rt305x.c @@ -5,7 +5,7 @@ #include #include #include -#include "pinctrl-ralink.h" +#include "pinctrl-mtmips.h" =20 #define RT305X_GPIO_MODE_UART0_SHIFT 2 #define RT305X_GPIO_MODE_UART0_MASK 0x7 @@ -31,9 +31,9 @@ #define RT3352_GPIO_MODE_LNA 18 #define RT3352_GPIO_MODE_PA 20 =20 -static struct ralink_pmx_func i2c_grp[] =3D { FUNC("i2c", 0, 1, 2) }; -static struct ralink_pmx_func spi_grp[] =3D { FUNC("spi", 0, 3, 4) }; -static struct ralink_pmx_func uartf_grp[] =3D { +static struct mtmips_pmx_func i2c_grp[] =3D { FUNC("i2c", 0, 1, 2) }; +static struct mtmips_pmx_func spi_grp[] =3D { FUNC("spi", 0, 3, 4) }; +static struct mtmips_pmx_func uartf_grp[] =3D { FUNC("uartf", RT305X_GPIO_MODE_UARTF, 7, 8), FUNC("pcm uartf", RT305X_GPIO_MODE_PCM_UARTF, 7, 8), FUNC("pcm i2s", RT305X_GPIO_MODE_PCM_I2S, 7, 8), @@ -42,28 +42,28 @@ static struct ralink_pmx_func uartf_grp[] =3D { FUNC("gpio uartf", RT305X_GPIO_MODE_GPIO_UARTF, 7, 4), FUNC("gpio i2s", RT305X_GPIO_MODE_GPIO_I2S, 7, 4), }; -static struct ralink_pmx_func uartlite_grp[] =3D { FUNC("uartlite", 0, 15,= 2) }; -static struct ralink_pmx_func jtag_grp[] =3D { FUNC("jtag", 0, 17, 5) }; -static struct ralink_pmx_func mdio_grp[] =3D { FUNC("mdio", 0, 22, 2) }; -static struct ralink_pmx_func rt5350_led_grp[] =3D { FUNC("led", 0, 22, 5)= }; -static struct ralink_pmx_func rt5350_cs1_grp[] =3D { +static struct mtmips_pmx_func uartlite_grp[] =3D { FUNC("uartlite", 0, 15,= 2) }; +static struct mtmips_pmx_func jtag_grp[] =3D { FUNC("jtag", 0, 17, 5) }; +static struct mtmips_pmx_func mdio_grp[] =3D { FUNC("mdio", 0, 22, 2) }; +static struct mtmips_pmx_func rt5350_led_grp[] =3D { FUNC("led", 0, 22, 5)= }; +static struct mtmips_pmx_func rt5350_cs1_grp[] =3D { FUNC("spi_cs1", 0, 27, 1), FUNC("wdg_cs1", 1, 27, 1), }; -static struct ralink_pmx_func sdram_grp[] =3D { FUNC("sdram", 0, 24, 16) }; -static struct ralink_pmx_func rt3352_rgmii_grp[] =3D { +static struct mtmips_pmx_func sdram_grp[] =3D { FUNC("sdram", 0, 24, 16) }; +static struct mtmips_pmx_func rt3352_rgmii_grp[] =3D { FUNC("rgmii", 0, 24, 12) }; -static struct ralink_pmx_func rgmii_grp[] =3D { FUNC("rgmii", 0, 40, 12) }; -static struct ralink_pmx_func rt3352_lna_grp[] =3D { FUNC("lna", 0, 36, 2)= }; -static struct ralink_pmx_func rt3352_pa_grp[] =3D { FUNC("pa", 0, 38, 2) }; -static struct ralink_pmx_func rt3352_led_grp[] =3D { FUNC("led", 0, 40, 5)= }; -static struct ralink_pmx_func rt3352_cs1_grp[] =3D { +static struct mtmips_pmx_func rgmii_grp[] =3D { FUNC("rgmii", 0, 40, 12) }; +static struct mtmips_pmx_func rt3352_lna_grp[] =3D { FUNC("lna", 0, 36, 2)= }; +static struct mtmips_pmx_func rt3352_pa_grp[] =3D { FUNC("pa", 0, 38, 2) }; +static struct mtmips_pmx_func rt3352_led_grp[] =3D { FUNC("led", 0, 40, 5)= }; +static struct mtmips_pmx_func rt3352_cs1_grp[] =3D { FUNC("spi_cs1", 0, 45, 1), FUNC("wdg_cs1", 1, 45, 1), }; =20 -static struct ralink_pmx_group rt3050_pinmux_data[] =3D { +static struct mtmips_pmx_group rt3050_pinmux_data[] =3D { GRP("i2c", i2c_grp, 1, RT305X_GPIO_MODE_I2C), GRP("spi", spi_grp, 1, RT305X_GPIO_MODE_SPI), GRP("uartf", uartf_grp, RT305X_GPIO_MODE_UART0_MASK, @@ -76,7 +76,7 @@ static struct ralink_pmx_group rt3050_pinmux_data[] =3D { { 0 } }; =20 -static struct ralink_pmx_group rt3352_pinmux_data[] =3D { +static struct mtmips_pmx_group rt3352_pinmux_data[] =3D { GRP("i2c", i2c_grp, 1, RT305X_GPIO_MODE_I2C), GRP("spi", spi_grp, 1, RT305X_GPIO_MODE_SPI), GRP("uartf", uartf_grp, RT305X_GPIO_MODE_UART0_MASK, @@ -92,7 +92,7 @@ static struct ralink_pmx_group rt3352_pinmux_data[] =3D { { 0 } }; =20 -static struct ralink_pmx_group rt5350_pinmux_data[] =3D { +static struct mtmips_pmx_group rt5350_pinmux_data[] =3D { GRP("i2c", i2c_grp, 1, RT305X_GPIO_MODE_I2C), GRP("spi", spi_grp, 1, RT305X_GPIO_MODE_SPI), GRP("uartf", uartf_grp, RT305X_GPIO_MODE_UART0_MASK, @@ -107,11 +107,11 @@ static struct ralink_pmx_group rt5350_pinmux_data[] = =3D { static int rt305x_pinctrl_probe(struct platform_device *pdev) { if (soc_is_rt5350()) - return ralink_pinctrl_init(pdev, rt5350_pinmux_data); + return mtmips_pinctrl_init(pdev, rt5350_pinmux_data); else if (soc_is_rt305x() || soc_is_rt3350()) - return ralink_pinctrl_init(pdev, rt3050_pinmux_data); + return mtmips_pinctrl_init(pdev, rt3050_pinmux_data); else if (soc_is_rt3352()) - return ralink_pinctrl_init(pdev, rt3352_pinmux_data); + return mtmips_pinctrl_init(pdev, rt3352_pinmux_data); else return -EINVAL; } diff --git a/drivers/pinctrl/ralink/pinctrl-rt3883.c b/drivers/pinctrl/medi= atek/pinctrl-rt3883.c similarity index 80% rename from drivers/pinctrl/ralink/pinctrl-rt3883.c rename to drivers/pinctrl/mediatek/pinctrl-rt3883.c index b687c70d3555..758350ce2ebe 100644 --- a/drivers/pinctrl/ralink/pinctrl-rt3883.c +++ b/drivers/pinctrl/mediatek/pinctrl-rt3883.c @@ -3,7 +3,7 @@ #include #include #include -#include "pinctrl-ralink.h" +#include "pinctrl-mtmips.h" =20 #define RT3883_GPIO_MODE_UART0_SHIFT 2 #define RT3883_GPIO_MODE_UART0_MASK 0x7 @@ -39,9 +39,9 @@ #define RT3883_GPIO_MODE_LNA_G_GPIO 0x3 #define RT3883_GPIO_MODE_LNA_G _RT3883_GPIO_MODE_LNA_G(RT3883_GPIO_MODE_L= NA_G_MASK) =20 -static struct ralink_pmx_func i2c_grp[] =3D { FUNC("i2c", 0, 1, 2) }; -static struct ralink_pmx_func spi_grp[] =3D { FUNC("spi", 0, 3, 4) }; -static struct ralink_pmx_func uartf_grp[] =3D { +static struct mtmips_pmx_func i2c_grp[] =3D { FUNC("i2c", 0, 1, 2) }; +static struct mtmips_pmx_func spi_grp[] =3D { FUNC("spi", 0, 3, 4) }; +static struct mtmips_pmx_func uartf_grp[] =3D { FUNC("uartf", RT3883_GPIO_MODE_UARTF, 7, 8), FUNC("pcm uartf", RT3883_GPIO_MODE_PCM_UARTF, 7, 8), FUNC("pcm i2s", RT3883_GPIO_MODE_PCM_I2S, 7, 8), @@ -50,21 +50,21 @@ static struct ralink_pmx_func uartf_grp[] =3D { FUNC("gpio uartf", RT3883_GPIO_MODE_GPIO_UARTF, 7, 4), FUNC("gpio i2s", RT3883_GPIO_MODE_GPIO_I2S, 7, 4), }; -static struct ralink_pmx_func uartlite_grp[] =3D { FUNC("uartlite", 0, 15,= 2) }; -static struct ralink_pmx_func jtag_grp[] =3D { FUNC("jtag", 0, 17, 5) }; -static struct ralink_pmx_func mdio_grp[] =3D { FUNC("mdio", 0, 22, 2) }; -static struct ralink_pmx_func lna_a_grp[] =3D { FUNC("lna a", 0, 32, 3) }; -static struct ralink_pmx_func lna_g_grp[] =3D { FUNC("lna g", 0, 35, 3) }; -static struct ralink_pmx_func pci_grp[] =3D { +static struct mtmips_pmx_func uartlite_grp[] =3D { FUNC("uartlite", 0, 15,= 2) }; +static struct mtmips_pmx_func jtag_grp[] =3D { FUNC("jtag", 0, 17, 5) }; +static struct mtmips_pmx_func mdio_grp[] =3D { FUNC("mdio", 0, 22, 2) }; +static struct mtmips_pmx_func lna_a_grp[] =3D { FUNC("lna a", 0, 32, 3) }; +static struct mtmips_pmx_func lna_g_grp[] =3D { FUNC("lna g", 0, 35, 3) }; +static struct mtmips_pmx_func pci_grp[] =3D { FUNC("pci-dev", 0, 40, 32), FUNC("pci-host2", 1, 40, 32), FUNC("pci-host1", 2, 40, 32), FUNC("pci-fnc", 3, 40, 32) }; -static struct ralink_pmx_func ge1_grp[] =3D { FUNC("ge1", 0, 72, 12) }; -static struct ralink_pmx_func ge2_grp[] =3D { FUNC("ge2", 0, 84, 12) }; +static struct mtmips_pmx_func ge1_grp[] =3D { FUNC("ge1", 0, 72, 12) }; +static struct mtmips_pmx_func ge2_grp[] =3D { FUNC("ge2", 0, 84, 12) }; =20 -static struct ralink_pmx_group rt3883_pinmux_data[] =3D { +static struct mtmips_pmx_group rt3883_pinmux_data[] =3D { GRP("i2c", i2c_grp, 1, RT3883_GPIO_MODE_I2C), GRP("spi", spi_grp, 1, RT3883_GPIO_MODE_SPI), GRP("uartf", uartf_grp, RT3883_GPIO_MODE_UART0_MASK, @@ -83,7 +83,7 @@ static struct ralink_pmx_group rt3883_pinmux_data[] =3D { =20 static int rt3883_pinctrl_probe(struct platform_device *pdev) { - return ralink_pinctrl_init(pdev, rt3883_pinmux_data); + return mtmips_pinctrl_init(pdev, rt3883_pinmux_data); } =20 static const struct of_device_id rt3883_pinctrl_match[] =3D { diff --git a/drivers/pinctrl/ralink/Kconfig b/drivers/pinctrl/ralink/Kconfig deleted file mode 100644 index c5fe4c31aaea..000000000000 --- a/drivers/pinctrl/ralink/Kconfig +++ /dev/null @@ -1,40 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0-only -menu "Ralink pinctrl drivers" - depends on RALINK - -config PINCTRL_RALINK - bool "Ralink pinctrl driver" - select PINMUX - select GENERIC_PINCONF - -config PINCTRL_MT7620 - bool "MT7620 pinctrl subdriver" - depends on RALINK && SOC_MT7620 - select PINCTRL_RALINK - -config PINCTRL_MT7621 - bool "MT7621 pinctrl subdriver" - depends on RALINK && SOC_MT7621 - select PINCTRL_RALINK - -config PINCTRL_MT76X8 - bool "MT76X8 pinctrl subdriver" - depends on RALINK && SOC_MT7620 - select PINCTRL_RALINK - -config PINCTRL_RT2880 - bool "RT2880 pinctrl subdriver" - depends on RALINK && SOC_RT288X - select PINCTRL_RALINK - -config PINCTRL_RT305X - bool "RT305X pinctrl subdriver" - depends on RALINK && SOC_RT305X - select PINCTRL_RALINK - -config PINCTRL_RT3883 - bool "RT3883 pinctrl subdriver" - depends on RALINK && SOC_RT3883 - select PINCTRL_RALINK - -endmenu diff --git a/drivers/pinctrl/ralink/Makefile b/drivers/pinctrl/ralink/Makef= ile deleted file mode 100644 index be9acf2e27fd..000000000000 --- a/drivers/pinctrl/ralink/Makefile +++ /dev/null @@ -1,9 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0 -obj-$(CONFIG_PINCTRL_RALINK) +=3D pinctrl-ralink.o - -obj-$(CONFIG_PINCTRL_MT7620) +=3D pinctrl-mt7620.o -obj-$(CONFIG_PINCTRL_MT7621) +=3D pinctrl-mt7621.o -obj-$(CONFIG_PINCTRL_MT76X8) +=3D pinctrl-mt76x8.o -obj-$(CONFIG_PINCTRL_RT2880) +=3D pinctrl-rt2880.o -obj-$(CONFIG_PINCTRL_RT305X) +=3D pinctrl-rt305x.o -obj-$(CONFIG_PINCTRL_RT3883) +=3D pinctrl-rt3883.o --=20 2.37.2 From nobody Thu Nov 14 07:05:11 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id ECF64C64ED6 for ; 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Wed, 22 Feb 2023 10:40:17 -0800 (PST) From: arinc9.unal@gmail.com X-Google-Original-From: arinc.unal@arinc9.com To: Sergio Paracuellos , Linus Walleij , Rob Herring , Krzysztof Kozlowski Cc: =?UTF-8?q?Ar=C4=B1n=C3=A7=20=C3=9CNAL?= , linux-mediatek@lists.infradead.org, linux-mips@vger.kernel.org, linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Matthias Brugger , Sean Wang , William Dean , Daniel Golle , Daniel Santos , Luiz Angelo Daros de Luca , Frank Wunderlich , Landen Chao , DENG Qingfang , Sean Wang , erkin.bozoglu@xeront.com Subject: [RFC PATCH 06/16] pinctrl: mediatek: remove OF_GPIO as reverse dependency Date: Wed, 22 Feb 2023 21:39:22 +0300 Message-Id: <20230222183932.33267-7-arinc.unal@arinc9.com> X-Mailer: git-send-email 2.37.2 In-Reply-To: <20230222183932.33267-1-arinc.unal@arinc9.com> References: <20230222183932.33267-1-arinc.unal@arinc9.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Ar=C4=B1n=C3=A7 =C3=9CNAL The OF_GPIO option is enabled by default when GPIOLIB is enabled, and cannot be disabled. Remove it as a reverse dependency where GPIOLIB is also set as a reverse dependency. Signed-off-by: Ar=C4=B1n=C3=A7 =C3=9CNAL --- drivers/pinctrl/mediatek/Kconfig | 3 --- 1 file changed, 3 deletions(-) diff --git a/drivers/pinctrl/mediatek/Kconfig b/drivers/pinctrl/mediatek/Kc= onfig index 3a6b99b23f35..809037b146a2 100644 --- a/drivers/pinctrl/mediatek/Kconfig +++ b/drivers/pinctrl/mediatek/Kconfig @@ -17,7 +17,6 @@ config PINCTRL_MTK select GENERIC_PINCONF select GPIOLIB select EINT_MTK - select OF_GPIO =20 config PINCTRL_MTK_V2 tristate @@ -35,7 +34,6 @@ config PINCTRL_MTK_MOORE select GENERIC_PINCTRL_GROUPS select GENERIC_PINMUX_FUNCTIONS select GPIOLIB - select OF_GPIO select EINT_MTK select PINCTRL_MTK_V2 =20 @@ -46,7 +44,6 @@ config PINCTRL_MTK_PARIS select GENERIC_PINCONF select GPIOLIB select EINT_MTK - select OF_GPIO select PINCTRL_MTK_V2 =20 # For MIPS SoCs --=20 2.37.2 From nobody Thu Nov 14 07:05:11 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id AF453C636D6 for ; Wed, 22 Feb 2023 18:41:04 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232638AbjBVSlC (ORCPT ); Wed, 22 Feb 2023 13:41:02 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:44296 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232552AbjBVSke (ORCPT ); Wed, 22 Feb 2023 13:40:34 -0500 Received: from mail-wr1-x434.google.com (mail-wr1-x434.google.com [IPv6:2a00:1450:4864:20::434]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 161433E636; Wed, 22 Feb 2023 10:40:20 -0800 (PST) Received: by mail-wr1-x434.google.com with SMTP id l25so8350468wrb.3; Wed, 22 Feb 2023 10:40:20 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=93GncC/YMq/sLoJhUEjsPCJ56rRoBeF7sm8+y73s7Mk=; b=E+Vb5T8FT+Ye+67Qb+aNplspFmHXbtd5U08wTEttHwIwNpkiYDC8uD5NQSx/f/ZpjF Os7FrxTTU43Zrp7+2dvjzaLH+pm8N/PBaigLPTcEXubTqWPFoPtdDvC3maibU+2t1Fof Fu+Bh1plW8gl8lieS+ZhJjtNR94xLuyKtLJ+9xTTgrAmzr+tb2utmVMJ1jPnJ6p6NR+H yGWNnJEI8BZ5jNTqP7ETWO3fShvvgJ7N0W9zDWt3iWiniUUO9PjA+7k8SLmfyG4VXiaR 454D6qbHzW6vIBUJ9oMgKrqwDvnNC/G/D21tMlDnBp+71Et5NfMRxGLtKPU/O2qarBey /PFA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=93GncC/YMq/sLoJhUEjsPCJ56rRoBeF7sm8+y73s7Mk=; b=4cTCz+aTmQcuQul0yTpS8xagK5QeCpbldIVgLMmPlyCw7etmW3u321pVS/EVNimRP4 YeYS20EscsFIY2Bvmc0lqFkQDhGaVIY01xd9wpGIoDyhlvQK+rlui1LCac1LS2PHJCTY tafW3xt1NJgwiFfJpKUk1Ezh26dcEzuAd5C6QhOCjGxXyV2grrH2GAGxyPxLTfHqHC3i GXVLLP2xwMrmnb51DBn/b80B6nFRQGnJjXdd+N5ONo7QIKMFfnmplIimj78cfavMZJwq umTgKuGodXpzMvnwMJRqHvvPQUKG+vgII5hbyZcbIWpO2rvQgIJOHpxc6xMnIDYGyVyU aUjA== X-Gm-Message-State: AO0yUKXJU5tCFBwXIz5g+ix9KmESUfQug3q87QH+gfD69GUnetOsBkvi m+uU8LIK/ywRSicu//jxc7w= X-Google-Smtp-Source: AK7set+5TsQLLq8jvQah+3Ch7FDP4duQj6VzOpjRIUXYKG9wJPfXn9hnPOz+M9oBSvDU76T6n9ORQA== X-Received: by 2002:a5d:67c8:0:b0:2c6:75be:f2d7 with SMTP id n8-20020a5d67c8000000b002c675bef2d7mr6843257wrw.51.1677091220529; Wed, 22 Feb 2023 10:40:20 -0800 (PST) Received: from arinc9-PC.lan ([37.120.152.236]) by smtp.gmail.com with ESMTPSA id l18-20020a5d4112000000b002c56179d39esm9372845wrp.44.2023.02.22.10.40.18 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 22 Feb 2023 10:40:20 -0800 (PST) From: arinc9.unal@gmail.com X-Google-Original-From: arinc.unal@arinc9.com To: Sergio Paracuellos , Linus Walleij , Rob Herring , Krzysztof Kozlowski Cc: =?UTF-8?q?Ar=C4=B1n=C3=A7=20=C3=9CNAL?= , linux-mediatek@lists.infradead.org, linux-mips@vger.kernel.org, linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Matthias Brugger , Sean Wang , William Dean , Daniel Golle , Daniel Santos , Luiz Angelo Daros de Luca , Frank Wunderlich , Landen Chao , DENG Qingfang , Sean Wang , erkin.bozoglu@xeront.com Subject: [RFC PATCH 07/16] dt-bindings: pinctrl: ralink: add new compatible strings Date: Wed, 22 Feb 2023 21:39:23 +0300 Message-Id: <20230222183932.33267-8-arinc.unal@arinc9.com> X-Mailer: git-send-email 2.37.2 In-Reply-To: <20230222183932.33267-1-arinc.unal@arinc9.com> References: <20230222183932.33267-1-arinc.unal@arinc9.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Ar=C4=B1n=C3=A7 =C3=9CNAL Add the ralink,rt2880-pinmux compatible string. It had been removed from the driver which broke the ABI. Add the mediatek compatible strings. Change the compatible string on the examples with the mediatek compatible strings. Signed-off-by: Ar=C4=B1n=C3=A7 =C3=9CNAL --- .../devicetree/bindings/pinctrl/ralink,mt7620-pinctrl.yaml | 7 +++++-- .../devicetree/bindings/pinctrl/ralink,mt7621-pinctrl.yaml | 7 +++++-- .../devicetree/bindings/pinctrl/ralink,rt2880-pinctrl.yaml | 7 +++++-- .../devicetree/bindings/pinctrl/ralink,rt305x-pinctrl.yaml | 7 +++++-- .../devicetree/bindings/pinctrl/ralink,rt3883-pinctrl.yaml | 7 +++++-- 5 files changed, 25 insertions(+), 10 deletions(-) diff --git a/Documentation/devicetree/bindings/pinctrl/ralink,mt7620-pinctr= l.yaml b/Documentation/devicetree/bindings/pinctrl/ralink,mt7620-pinctrl.ya= ml index 1e63ea34146a..531b5f616c3d 100644 --- a/Documentation/devicetree/bindings/pinctrl/ralink,mt7620-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/ralink,mt7620-pinctrl.yaml @@ -17,7 +17,10 @@ description: =20 properties: compatible: - const: ralink,mt7620-pinctrl + enum: + - mediatek,mt7620-pinctrl + - ralink,mt7620-pinctrl + - ralink,rt2880-pinmux =20 patternProperties: '-pins$': @@ -647,7 +650,7 @@ additionalProperties: false examples: - | pinctrl { - compatible =3D "ralink,mt7620-pinctrl"; + compatible =3D "mediatek,mt7620-pinctrl"; =20 i2c_pins: i2c0-pins { pinmux { diff --git a/Documentation/devicetree/bindings/pinctrl/ralink,mt7621-pinctr= l.yaml b/Documentation/devicetree/bindings/pinctrl/ralink,mt7621-pinctrl.ya= ml index 1b1d37b981d9..74923ca35c81 100644 --- a/Documentation/devicetree/bindings/pinctrl/ralink,mt7621-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/ralink,mt7621-pinctrl.yaml @@ -17,7 +17,10 @@ description: =20 properties: compatible: - const: ralink,mt7621-pinctrl + enum: + - mediatek,mt7621-pinctrl + - ralink,mt7621-pinctrl + - ralink,rt2880-pinmux =20 patternProperties: '-pins$': @@ -251,7 +254,7 @@ additionalProperties: false examples: - | pinctrl { - compatible =3D "ralink,mt7621-pinctrl"; + compatible =3D "mediatek,mt7621-pinctrl"; =20 i2c_pins: i2c0-pins { pinmux { diff --git a/Documentation/devicetree/bindings/pinctrl/ralink,rt2880-pinctr= l.yaml b/Documentation/devicetree/bindings/pinctrl/ralink,rt2880-pinctrl.ya= ml index 7fd0df880a76..aceea6248614 100644 --- a/Documentation/devicetree/bindings/pinctrl/ralink,rt2880-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/ralink,rt2880-pinctrl.yaml @@ -17,7 +17,10 @@ description: =20 properties: compatible: - const: ralink,rt2880-pinctrl + enum: + - mediatek,rt2880-pinctrl + - ralink,rt2880-pinctrl + - ralink,rt2880-pinmux =20 patternProperties: '-pins$': @@ -131,7 +134,7 @@ additionalProperties: false examples: - | pinctrl { - compatible =3D "ralink,rt2880-pinctrl"; + compatible =3D "mediatek,rt2880-pinctrl"; =20 i2c_pins: i2c0-pins { pinmux { diff --git a/Documentation/devicetree/bindings/pinctrl/ralink,rt305x-pinctr= l.yaml b/Documentation/devicetree/bindings/pinctrl/ralink,rt305x-pinctrl.ya= ml index 4d66ca752a30..4c87fe201809 100644 --- a/Documentation/devicetree/bindings/pinctrl/ralink,rt305x-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/ralink,rt305x-pinctrl.yaml @@ -18,7 +18,10 @@ description: =20 properties: compatible: - const: ralink,rt305x-pinctrl + enum: + - mediatek,rt305x-pinctrl + - ralink,rt305x-pinctrl + - ralink,rt2880-pinmux =20 patternProperties: '-pins$': @@ -264,7 +267,7 @@ additionalProperties: false examples: - | pinctrl { - compatible =3D "ralink,rt305x-pinctrl"; + compatible =3D "mediatek,rt305x-pinctrl"; =20 i2c_pins: i2c0-pins { pinmux { diff --git a/Documentation/devicetree/bindings/pinctrl/ralink,rt3883-pinctr= l.yaml b/Documentation/devicetree/bindings/pinctrl/ralink,rt3883-pinctrl.ya= ml index 008d93181aea..71049a2b2779 100644 --- a/Documentation/devicetree/bindings/pinctrl/ralink,rt3883-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/ralink,rt3883-pinctrl.yaml @@ -17,7 +17,10 @@ description: =20 properties: compatible: - const: ralink,rt3883-pinctrl + enum: + - mediatek,rt3883-pinctrl + - ralink,rt3883-pinctrl + - ralink,rt2880-pinmux =20 patternProperties: '-pins$': @@ -251,7 +254,7 @@ additionalProperties: false examples: - | pinctrl { - compatible =3D "ralink,rt3883-pinctrl"; + compatible =3D "mediatek,rt3883-pinctrl"; =20 i2c_pins: i2c0-pins { pinmux { --=20 2.37.2 From nobody Thu Nov 14 07:05:11 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id EAFDAC61DA4 for ; Wed, 22 Feb 2023 18:41:08 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232642AbjBVSlH (ORCPT ); Wed, 22 Feb 2023 13:41:07 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:43998 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231276AbjBVSkh (ORCPT ); Wed, 22 Feb 2023 13:40:37 -0500 Received: from mail-wr1-x431.google.com (mail-wr1-x431.google.com [IPv6:2a00:1450:4864:20::431]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 7331141B46; Wed, 22 Feb 2023 10:40:23 -0800 (PST) Received: by mail-wr1-x431.google.com with SMTP id v3so8678214wrp.2; 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Wed, 22 Feb 2023 10:40:22 -0800 (PST) Received: from arinc9-PC.lan ([37.120.152.236]) by smtp.gmail.com with ESMTPSA id l18-20020a5d4112000000b002c56179d39esm9372845wrp.44.2023.02.22.10.40.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 22 Feb 2023 10:40:22 -0800 (PST) From: arinc9.unal@gmail.com X-Google-Original-From: arinc.unal@arinc9.com To: Sergio Paracuellos , Linus Walleij , Rob Herring , Krzysztof Kozlowski Cc: =?UTF-8?q?Ar=C4=B1n=C3=A7=20=C3=9CNAL?= , linux-mediatek@lists.infradead.org, linux-mips@vger.kernel.org, linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Matthias Brugger , Sean Wang , William Dean , Daniel Golle , Daniel Santos , Luiz Angelo Daros de Luca , Frank Wunderlich , Landen Chao , DENG Qingfang , Sean Wang , erkin.bozoglu@xeront.com Subject: [RFC PATCH 08/16] dt-bindings: pinctrl: ralink: rename to mediatek Date: Wed, 22 Feb 2023 21:39:24 +0300 Message-Id: <20230222183932.33267-9-arinc.unal@arinc9.com> X-Mailer: git-send-email 2.37.2 In-Reply-To: <20230222183932.33267-1-arinc.unal@arinc9.com> References: <20230222183932.33267-1-arinc.unal@arinc9.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Ar=C4=B1n=C3=A7 =C3=9CNAL Ralink was acquired by MediaTek in 2011. These SoCs have been rebranded as MediaTek. Rename the schemas to mediatek. Signed-off-by: Ar=C4=B1n=C3=A7 =C3=9CNAL --- ...ink,mt7620-pinctrl.yaml =3D> mediatek,mt7620-pinctrl.yaml} | 6 +++--- ...ink,mt7621-pinctrl.yaml =3D> mediatek,mt7621-pinctrl.yaml} | 6 +++--- ...ink,rt2880-pinctrl.yaml =3D> mediatek,rt2880-pinctrl.yaml} | 6 +++--- ...ink,rt305x-pinctrl.yaml =3D> mediatek,rt305x-pinctrl.yaml} | 6 +++--- ...ink,rt3883-pinctrl.yaml =3D> mediatek,rt3883-pinctrl.yaml} | 6 +++--- 5 files changed, 15 insertions(+), 15 deletions(-) rename Documentation/devicetree/bindings/pinctrl/{ralink,mt7620-pinctrl.ya= ml =3D> mediatek,mt7620-pinctrl.yaml} (98%) rename Documentation/devicetree/bindings/pinctrl/{ralink,mt7621-pinctrl.ya= ml =3D> mediatek,mt7621-pinctrl.yaml} (97%) rename Documentation/devicetree/bindings/pinctrl/{ralink,rt2880-pinctrl.ya= ml =3D> mediatek,rt2880-pinctrl.yaml} (95%) rename Documentation/devicetree/bindings/pinctrl/{ralink,rt305x-pinctrl.ya= ml =3D> mediatek,rt305x-pinctrl.yaml} (97%) rename Documentation/devicetree/bindings/pinctrl/{ralink,rt3883-pinctrl.ya= ml =3D> mediatek,rt3883-pinctrl.yaml} (97%) diff --git a/Documentation/devicetree/bindings/pinctrl/ralink,mt7620-pinctr= l.yaml b/Documentation/devicetree/bindings/pinctrl/mediatek,mt7620-pinctrl.= yaml similarity index 98% rename from Documentation/devicetree/bindings/pinctrl/ralink,mt7620-pinctrl= .yaml rename to Documentation/devicetree/bindings/pinctrl/mediatek,mt7620-pinctrl= .yaml index 531b5f616c3d..3bf58da8a394 100644 --- a/Documentation/devicetree/bindings/pinctrl/ralink,mt7620-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/mediatek,mt7620-pinctrl.yaml @@ -1,17 +1,17 @@ # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause %YAML 1.2 --- -$id: http://devicetree.org/schemas/pinctrl/ralink,mt7620-pinctrl.yaml# +$id: http://devicetree.org/schemas/pinctrl/mediatek,mt7620-pinctrl.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# =20 -title: Ralink MT7620 Pin Controller +title: MediaTek MT7620 Pin Controller =20 maintainers: - Ar=C4=B1n=C3=A7 =C3=9CNAL - Sergio Paracuellos =20 description: - Ralink MT7620 pin controller for MT7620, MT7628 and MT7688 SoCs. + MediaTek MT7620 pin controller for MT7620, MT7628 and MT7688 SoCs. The pin controller can only set the muxing of pin groups. Muxing individ= ual pins is not supported. There is no pinconf support. =20 diff --git a/Documentation/devicetree/bindings/pinctrl/ralink,mt7621-pinctr= l.yaml b/Documentation/devicetree/bindings/pinctrl/mediatek,mt7621-pinctrl.= yaml similarity index 97% rename from Documentation/devicetree/bindings/pinctrl/ralink,mt7621-pinctrl= .yaml rename to Documentation/devicetree/bindings/pinctrl/mediatek,mt7621-pinctrl= .yaml index 74923ca35c81..4dfe3da5fd40 100644 --- a/Documentation/devicetree/bindings/pinctrl/ralink,mt7621-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/mediatek,mt7621-pinctrl.yaml @@ -1,17 +1,17 @@ # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause %YAML 1.2 --- -$id: http://devicetree.org/schemas/pinctrl/ralink,mt7621-pinctrl.yaml# +$id: http://devicetree.org/schemas/pinctrl/mediatek,mt7621-pinctrl.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# =20 -title: Ralink MT7621 Pin Controller +title: MediaTek MT7621 Pin Controller =20 maintainers: - Ar=C4=B1n=C3=A7 =C3=9CNAL - Sergio Paracuellos =20 description: - Ralink MT7621 pin controller for MT7621 SoC. + MediaTek MT7621 pin controller for MT7621 SoC. The pin controller can only set the muxing of pin groups. Muxing individ= ual pins is not supported. There is no pinconf support. =20 diff --git a/Documentation/devicetree/bindings/pinctrl/ralink,rt2880-pinctr= l.yaml b/Documentation/devicetree/bindings/pinctrl/mediatek,rt2880-pinctrl.= yaml similarity index 95% rename from Documentation/devicetree/bindings/pinctrl/ralink,rt2880-pinctrl= .yaml rename to Documentation/devicetree/bindings/pinctrl/mediatek,rt2880-pinctrl= .yaml index aceea6248614..7395e4434e64 100644 --- a/Documentation/devicetree/bindings/pinctrl/ralink,rt2880-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/mediatek,rt2880-pinctrl.yaml @@ -1,17 +1,17 @@ # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause %YAML 1.2 --- -$id: http://devicetree.org/schemas/pinctrl/ralink,rt2880-pinctrl.yaml# +$id: http://devicetree.org/schemas/pinctrl/mediatek,rt2880-pinctrl.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# =20 -title: Ralink RT2880 Pin Controller +title: MediaTek RT2880 Pin Controller =20 maintainers: - Ar=C4=B1n=C3=A7 =C3=9CNAL - Sergio Paracuellos =20 description: - Ralink RT2880 pin controller for RT2880 SoC. + MediaTek RT2880 pin controller for RT2880 SoC. The pin controller can only set the muxing of pin groups. Muxing individ= ual pins is not supported. There is no pinconf support. =20 diff --git a/Documentation/devicetree/bindings/pinctrl/ralink,rt305x-pinctr= l.yaml b/Documentation/devicetree/bindings/pinctrl/mediatek,rt305x-pinctrl.= yaml similarity index 97% rename from Documentation/devicetree/bindings/pinctrl/ralink,rt305x-pinctrl= .yaml rename to Documentation/devicetree/bindings/pinctrl/mediatek,rt305x-pinctrl= .yaml index 4c87fe201809..61fcf3ab1091 100644 --- a/Documentation/devicetree/bindings/pinctrl/ralink,rt305x-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/mediatek,rt305x-pinctrl.yaml @@ -1,17 +1,17 @@ # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause %YAML 1.2 --- -$id: http://devicetree.org/schemas/pinctrl/ralink,rt305x-pinctrl.yaml# +$id: http://devicetree.org/schemas/pinctrl/mediatek,rt305x-pinctrl.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# =20 -title: Ralink RT305X Pin Controller +title: MediaTek RT305X Pin Controller =20 maintainers: - Ar=C4=B1n=C3=A7 =C3=9CNAL - Sergio Paracuellos =20 description: - Ralink RT305X pin controller for RT3050, RT3052, RT3350, RT3352 and RT53= 50 + MediaTek RT305X pin controller for RT3050, RT3052, RT3350, RT3352 and RT= 5350 SoCs. The pin controller can only set the muxing of pin groups. Muxing individ= ual pins is not supported. There is no pinconf support. diff --git a/Documentation/devicetree/bindings/pinctrl/ralink,rt3883-pinctr= l.yaml b/Documentation/devicetree/bindings/pinctrl/mediatek,rt3883-pinctrl.= yaml similarity index 97% rename from Documentation/devicetree/bindings/pinctrl/ralink,rt3883-pinctrl= .yaml rename to Documentation/devicetree/bindings/pinctrl/mediatek,rt3883-pinctrl= .yaml index 71049a2b2779..ab20f67c47f0 100644 --- a/Documentation/devicetree/bindings/pinctrl/ralink,rt3883-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/mediatek,rt3883-pinctrl.yaml @@ -1,17 +1,17 @@ # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause %YAML 1.2 --- -$id: http://devicetree.org/schemas/pinctrl/ralink,rt3883-pinctrl.yaml# +$id: http://devicetree.org/schemas/pinctrl/mediatek,rt3883-pinctrl.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# =20 -title: Ralink RT3883 Pin Controller +title: MediaTek RT3883 Pin Controller =20 maintainers: - Ar=C4=B1n=C3=A7 =C3=9CNAL - Sergio Paracuellos =20 description: - Ralink RT3883 pin controller for RT3883 SoC. + MediaTek RT3883 pin controller for RT3883 SoC. The pin controller can only set the muxing of pin groups. Muxing individ= ual pins is not supported. There is no pinconf support. =20 --=20 2.37.2 From nobody Thu Nov 14 07:05:11 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 06C9BC636D6 for ; Wed, 22 Feb 2023 18:41:18 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232659AbjBVSlQ (ORCPT ); Wed, 22 Feb 2023 13:41:16 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:44390 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232482AbjBVSkz (ORCPT ); Wed, 22 Feb 2023 13:40:55 -0500 Received: from mail-wr1-x42d.google.com (mail-wr1-x42d.google.com [IPv6:2a00:1450:4864:20::42d]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 954D942BDB; Wed, 22 Feb 2023 10:40:26 -0800 (PST) Received: by mail-wr1-x42d.google.com with SMTP id t13so8682117wrv.13; Wed, 22 Feb 2023 10:40:26 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=+o8MOEwE/dVfgMCl7bmAyjT+NEpiVZUInhrQfgLr0Hc=; b=Yx2QEGus5g1VMWhkonYwCdyHoxp3C8oP8Q0n3M8/VPVHeQKFGxLnPfR4bUiZq1Ossb esiN/rcW1ZRqywDyPJdN2Pxi6Yj7sIGXsgd7dCzmLH9IWXNLdGLLqqtIa47hnCRHuwdX DDIfSX5akeCRMItSM+XSqNg4lauRkvOOG9cG6XU80bJL469BaReUKJ1MbOA4pKvjZQXR TFm3r5RI2wEp6FLz1iTW1QhZD7ao14+7umhOcDt1oISGA9H9GKUnJgrIAU3Dd3BWh6d2 xQ6VfilK6Csvq5wZ8lgvbOL/EOIvW2jKvKFS4VJ6MvyzHxm4oR+D2ODo4Ji6ZVVg6EgC hi6w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=+o8MOEwE/dVfgMCl7bmAyjT+NEpiVZUInhrQfgLr0Hc=; b=EaIdvXn3klr+C5cqSLHC5Ghfra7hQmuvaw40BaxfwxACMIahZhp8azRLePUMKjVJFZ zOhAzLJ/YTCW2gMi6hy7NcEaZ63WYLghB1kG06HQlvg2qNHbnbuiocU3FQT/FFKHUEaM rMfF3ohsIdNEhJhtDb6xUkxBht0+X1kRoW9CVRmhiomZWabJeLnVjY2ue9J+x7Iby6YQ yOnRtAsQiYI6h2+Qd/CVBkQc7FhdROWf4d/VdLKE5SFy+A8jDfu5Y3te4KAxWsROorVG dhZUs+siq9HTkozaEGu+Te8WFE3e6HbRLArI59T8hC9PWvbaMfCW3BUxuvy2ZQd8ecYh /iTA== X-Gm-Message-State: AO0yUKWTdA42UsIh9IirsRPAjcmiStdIZToInBWpTPKwrrBJd6bten4o 128PxOow5WunbUUvFzgoVd4= X-Google-Smtp-Source: AK7set8b55tFD4C1QYxIyA5oqOb4rTVXxGtnb3DL9lq2HAxP0/eGyZXITvhlPkLgw/mSUH+jnV4anw== X-Received: by 2002:a5d:5912:0:b0:2c5:58aa:35cb with SMTP id v18-20020a5d5912000000b002c558aa35cbmr8652823wrd.47.1677091225071; Wed, 22 Feb 2023 10:40:25 -0800 (PST) Received: from arinc9-PC.lan ([37.120.152.236]) by smtp.gmail.com with ESMTPSA id l18-20020a5d4112000000b002c56179d39esm9372845wrp.44.2023.02.22.10.40.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 22 Feb 2023 10:40:24 -0800 (PST) From: arinc9.unal@gmail.com X-Google-Original-From: arinc.unal@arinc9.com To: Sergio Paracuellos , Linus Walleij , Rob Herring , Krzysztof Kozlowski Cc: =?UTF-8?q?Ar=C4=B1n=C3=A7=20=C3=9CNAL?= , linux-mediatek@lists.infradead.org, linux-mips@vger.kernel.org, linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Matthias Brugger , Sean Wang , William Dean , Daniel Golle , Daniel Santos , Luiz Angelo Daros de Luca , Frank Wunderlich , Landen Chao , DENG Qingfang , Sean Wang , erkin.bozoglu@xeront.com Subject: [RFC PATCH 09/16] dt-bindings: pinctrl: mediatek: rt305x: split binding Date: Wed, 22 Feb 2023 21:39:25 +0300 Message-Id: <20230222183932.33267-10-arinc.unal@arinc9.com> X-Mailer: git-send-email 2.37.2 In-Reply-To: <20230222183932.33267-1-arinc.unal@arinc9.com> References: <20230222183932.33267-1-arinc.unal@arinc9.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Ar=C4=B1n=C3=A7 =C3=9CNAL The RT3352 and RT5350 SoCs each contain different pin muxing information, therefore, should be split. This can be done now that there are compatible strings to distinguish them from other SoCs. Split the schema out to mediatek,rt3352-pinctrl.yaml and mediatek,rt5350-pinctrl.yaml. Signed-off-by: Ar=C4=B1n=C3=A7 =C3=9CNAL --- .../pinctrl/mediatek,rt305x-pinctrl.yaml | 78 +----- .../pinctrl/mediatek,rt3352-pinctrl.yaml | 247 ++++++++++++++++++ .../pinctrl/mediatek,rt5350-pinctrl.yaml | 210 +++++++++++++++ 3 files changed, 462 insertions(+), 73 deletions(-) create mode 100644 Documentation/devicetree/bindings/pinctrl/mediatek,rt33= 52-pinctrl.yaml create mode 100644 Documentation/devicetree/bindings/pinctrl/mediatek,rt53= 50-pinctrl.yaml diff --git a/Documentation/devicetree/bindings/pinctrl/mediatek,rt305x-pinc= trl.yaml b/Documentation/devicetree/bindings/pinctrl/mediatek,rt305x-pinctr= l.yaml index 61fcf3ab1091..1e6c7e7f2fe2 100644 --- a/Documentation/devicetree/bindings/pinctrl/mediatek,rt305x-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/mediatek,rt305x-pinctrl.yaml @@ -11,8 +11,7 @@ maintainers: - Sergio Paracuellos =20 description: - MediaTek RT305X pin controller for RT3050, RT3052, RT3350, RT3352 and RT= 5350 - SoCs. + MediaTek RT305X pin controller for RT3050, RT3052, and RT3350 SoCs. The pin controller can only set the muxing of pin groups. Muxing individ= ual pins is not supported. There is no pinconf support. =20 @@ -36,21 +35,9 @@ patternProperties: function: description: A string containing the name of the function to mux to the g= roup. - anyOf: - - description: For RT3050, RT3052 and RT3350 SoCs - enum: [gpio, gpio i2s, gpio uartf, i2c, i2s uartf, jtag, m= dio, - pcm gpio, pcm i2s, pcm uartf, rgmii, sdram, spi, ua= rtf, - uartlite] - - - description: For RT3352 SoC - enum: [gpio, gpio i2s, gpio uartf, i2c, i2s uartf, jtag, l= ed, - lna, mdio, pa, pcm gpio, pcm i2s, pcm uartf, rgmii,= spi, - spi_cs1, uartf, uartlite, wdg_cs1] - - - description: For RT5350 SoC - enum: [gpio, gpio i2s, gpio uartf, i2c, i2s uartf, jtag, l= ed, - pcm gpio, pcm i2s, pcm uartf, spi, spi_cs1, uartf, - uartlite, wdg_cs1] + enum: [gpio, gpio i2s, gpio uartf, i2c, i2s uartf, jtag, mdio, + pcm gpio, pcm i2s, pcm uartf, rgmii, sdram, spi, uartf, + uartlite] =20 groups: description: @@ -69,17 +56,7 @@ patternProperties: then: properties: groups: - anyOf: - - description: For RT3050, RT3052 and RT3350 SoCs - enum: [i2c, jtag, mdio, rgmii, sdram, spi, uartf, - uartlite] - - - description: For RT3352 SoC - enum: [i2c, jtag, led, lna, mdio, pa, rgmii, spi, sp= i_cs1, - uartf, uartlite] - - - description: For RT5350 SoC - enum: [i2c, jtag, led, spi, spi_cs1, uartf, uartlite] + enum: [i2c, jtag, mdio, rgmii, sdram, spi, uartf, uartli= te] =20 - if: properties: @@ -126,24 +103,6 @@ patternProperties: groups: enum: [jtag] =20 - - if: - properties: - function: - const: led - then: - properties: - groups: - enum: [led] - - - if: - properties: - function: - const: lna - then: - properties: - groups: - enum: [lna] - - if: properties: function: @@ -153,15 +112,6 @@ patternProperties: groups: enum: [mdio] =20 - - if: - properties: - function: - const: pa - then: - properties: - groups: - enum: [pa] - - if: properties: function: @@ -216,15 +166,6 @@ patternProperties: groups: enum: [spi] =20 - - if: - properties: - function: - const: spi_cs1 - then: - properties: - groups: - enum: [spi_cs1] - - if: properties: function: @@ -243,15 +184,6 @@ patternProperties: groups: enum: [uartlite] =20 - - if: - properties: - function: - const: wdg_cs1 - then: - properties: - groups: - enum: [spi_cs1] - additionalProperties: false =20 additionalProperties: false diff --git a/Documentation/devicetree/bindings/pinctrl/mediatek,rt3352-pinc= trl.yaml b/Documentation/devicetree/bindings/pinctrl/mediatek,rt3352-pinctr= l.yaml new file mode 100644 index 000000000000..7a74c1602afc --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/mediatek,rt3352-pinctrl.yaml @@ -0,0 +1,247 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/mediatek,rt3352-pinctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: MediaTek RT3352 Pin Controller + +maintainers: + - Ar=C4=B1n=C3=A7 =C3=9CNAL + - Sergio Paracuellos + +description: + MediaTek RT3352 pin controller for RT3352 SoC. + The pin controller can only set the muxing of pin groups. Muxing individ= ual + pins is not supported. There is no pinconf support. + +properties: + compatible: + enum: + - mediatek,rt3352-pinctrl + - ralink,rt305x-pinctrl + - ralink,rt2880-pinmux + +patternProperties: + '-pins$': + type: object + patternProperties: + '^(.*-)?pinmux$': + type: object + description: node for pinctrl. + $ref: pinmux-node.yaml# + + properties: + function: + description: + A string containing the name of the function to mux to the g= roup. + enum: [gpio, gpio i2s, gpio uartf, i2c, i2s uartf, jtag, led, = lna, + mdio, pa, pcm gpio, pcm i2s, pcm uartf, rgmii, spi, spi= _cs1, + uartf, uartlite, wdg_cs1] + + groups: + description: + An array of strings. Each string contains the name of a grou= p. + maxItems: 1 + + required: + - groups + - function + + allOf: + - if: + properties: + function: + const: gpio + then: + properties: + groups: + enum: [i2c, jtag, led, lna, mdio, pa, rgmii, spi, spi_cs= 1, + uartf, uartlite] + + - if: + properties: + function: + const: gpio i2s + then: + properties: + groups: + enum: [uartf] + + - if: + properties: + function: + const: gpio uartf + then: + properties: + groups: + enum: [uartf] + + - if: + properties: + function: + const: i2c + then: + properties: + groups: + enum: [i2c] + + - if: + properties: + function: + const: i2s uartf + then: + properties: + groups: + enum: [uartf] + + - if: + properties: + function: + const: jtag + then: + properties: + groups: + enum: [jtag] + + - if: + properties: + function: + const: led + then: + properties: + groups: + enum: [led] + + - if: + properties: + function: + const: lna + then: + properties: + groups: + enum: [lna] + + - if: + properties: + function: + const: mdio + then: + properties: + groups: + enum: [mdio] + + - if: + properties: + function: + const: pa + then: + properties: + groups: + enum: [pa] + + - if: + properties: + function: + const: pcm gpio + then: + properties: + groups: + enum: [uartf] + + - if: + properties: + function: + const: pcm i2s + then: + properties: + groups: + enum: [uartf] + + - if: + properties: + function: + const: pcm uartf + then: + properties: + groups: + enum: [uartf] + + - if: + properties: + function: + const: rgmii + then: + properties: + groups: + enum: [rgmii] + + - if: + properties: + function: + const: spi + then: + properties: + groups: + enum: [spi] + + - if: + properties: + function: + const: spi_cs1 + then: + properties: + groups: + enum: [spi_cs1] + + - if: + properties: + function: + const: uartf + then: + properties: + groups: + enum: [uartf] + + - if: + properties: + function: + const: uartlite + then: + properties: + groups: + enum: [uartlite] + + - if: + properties: + function: + const: wdg_cs1 + then: + properties: + groups: + enum: [spi_cs1] + + additionalProperties: false + + additionalProperties: false + +allOf: + - $ref: "pinctrl.yaml#" + +required: + - compatible + +additionalProperties: false + +examples: + - | + pinctrl { + compatible =3D "mediatek,rt3352-pinctrl"; + + i2c_pins: i2c0-pins { + pinmux { + groups =3D "i2c"; + function =3D "i2c"; + }; + }; + }; diff --git a/Documentation/devicetree/bindings/pinctrl/mediatek,rt5350-pinc= trl.yaml b/Documentation/devicetree/bindings/pinctrl/mediatek,rt5350-pinctr= l.yaml new file mode 100644 index 000000000000..5184cea62640 --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/mediatek,rt5350-pinctrl.yaml @@ -0,0 +1,210 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/mediatek,rt5350-pinctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: MediaTek RT5350 Pin Controller + +maintainers: + - Ar=C4=B1n=C3=A7 =C3=9CNAL + - Sergio Paracuellos + +description: + MediaTek RT5350 pin controller for RT5350 SoC. + The pin controller can only set the muxing of pin groups. Muxing individ= ual + pins is not supported. There is no pinconf support. + +properties: + compatible: + enum: + - mediatek,rt5350-pinctrl + - ralink,rt305x-pinctrl + - ralink,rt2880-pinmux + +patternProperties: + '-pins$': + type: object + patternProperties: + '^(.*-)?pinmux$': + type: object + description: node for pinctrl. + $ref: pinmux-node.yaml# + + properties: + function: + description: + A string containing the name of the function to mux to the g= roup. + enum: [gpio, gpio i2s, gpio uartf, i2c, i2s uartf, jtag, led, + pcm gpio, pcm i2s, pcm uartf, spi, spi_cs1, uartf, uart= lite, + wdg_cs1] + + groups: + description: + An array of strings. Each string contains the name of a grou= p. + maxItems: 1 + + required: + - groups + - function + + allOf: + - if: + properties: + function: + const: gpio + then: + properties: + groups: + enum: [i2c, jtag, led, spi, spi_cs1, uartf, uartlite] + + - if: + properties: + function: + const: gpio i2s + then: + properties: + groups: + enum: [uartf] + + - if: + properties: + function: + const: gpio uartf + then: + properties: + groups: + enum: [uartf] + + - if: + properties: + function: + const: i2c + then: + properties: + groups: + enum: [i2c] + + - if: + properties: + function: + const: i2s uartf + then: + properties: + groups: + enum: [uartf] + + - if: + properties: + function: + const: jtag + then: + properties: + groups: + enum: [jtag] + + - if: + properties: + function: + const: led + then: + properties: + groups: + enum: [led] + + - if: + properties: + function: + const: pcm gpio + then: + properties: + groups: + enum: [uartf] + + - if: + properties: + function: + const: pcm i2s + then: + properties: + groups: + enum: [uartf] + + - if: + properties: + function: + const: pcm uartf + then: + properties: + groups: + enum: [uartf] + + - if: + properties: + function: + const: spi + then: + properties: + groups: + enum: [spi] + + - if: + properties: + function: + const: spi_cs1 + then: + properties: + groups: + enum: [spi_cs1] + + - if: + properties: + function: + const: uartf + then: + properties: + groups: + enum: [uartf] + + - if: + properties: + function: + const: uartlite + then: + properties: + groups: + enum: [uartlite] + + - if: + properties: + function: + const: wdg_cs1 + then: + properties: + groups: + enum: [spi_cs1] + + additionalProperties: false + + additionalProperties: false + +allOf: + - $ref: "pinctrl.yaml#" + +required: + - compatible + +additionalProperties: false + +examples: + - | + pinctrl { + compatible =3D "mediatek,rt5350-pinctrl"; + + i2c_pins: i2c0-pins { + pinmux { + groups =3D "i2c"; + function =3D "i2c"; + }; + }; + }; --=20 2.37.2 From nobody Thu Nov 14 07:05:11 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id CD716C636D6 for ; Wed, 22 Feb 2023 18:41:25 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231135AbjBVSlY (ORCPT ); Wed, 22 Feb 2023 13:41:24 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:44416 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232589AbjBVSk6 (ORCPT ); Wed, 22 Feb 2023 13:40:58 -0500 Received: from mail-wr1-x42d.google.com (mail-wr1-x42d.google.com [IPv6:2a00:1450:4864:20::42d]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 298DC42BC0; Wed, 22 Feb 2023 10:40:29 -0800 (PST) Received: by mail-wr1-x42d.google.com with SMTP id h14so85487wru.4; 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Wed, 22 Feb 2023 10:40:27 -0800 (PST) Received: from arinc9-PC.lan ([37.120.152.236]) by smtp.gmail.com with ESMTPSA id l18-20020a5d4112000000b002c56179d39esm9372845wrp.44.2023.02.22.10.40.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 22 Feb 2023 10:40:27 -0800 (PST) From: arinc9.unal@gmail.com X-Google-Original-From: arinc.unal@arinc9.com To: Sergio Paracuellos , Linus Walleij , Rob Herring , Krzysztof Kozlowski Cc: =?UTF-8?q?Ar=C4=B1n=C3=A7=20=C3=9CNAL?= , linux-mediatek@lists.infradead.org, linux-mips@vger.kernel.org, linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Matthias Brugger , Sean Wang , William Dean , Daniel Golle , Daniel Santos , Luiz Angelo Daros de Luca , Frank Wunderlich , Landen Chao , DENG Qingfang , Sean Wang , erkin.bozoglu@xeront.com Subject: [RFC PATCH 10/16] dt-bindings: pinctrl: mediatek: mt7620: split binding Date: Wed, 22 Feb 2023 21:39:26 +0300 Message-Id: <20230222183932.33267-11-arinc.unal@arinc9.com> X-Mailer: git-send-email 2.37.2 In-Reply-To: <20230222183932.33267-1-arinc.unal@arinc9.com> References: <20230222183932.33267-1-arinc.unal@arinc9.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Ar=C4=B1n=C3=A7 =C3=9CNAL The MT7628 and MT7688 SoCs contain different pin muxing information, therefore, should be split. This can be done now that there are compatible strings to distinguish them from other SoCs. Split the schema out to mediatek,mt76x8-pinctrl.yaml. Signed-off-by: Ar=C4=B1n=C3=A7 =C3=9CNAL --- .../pinctrl/mediatek,mt7620-pinctrl.yaml | 375 +-------------- .../pinctrl/mediatek,mt76x8-pinctrl.yaml | 454 ++++++++++++++++++ 2 files changed, 462 insertions(+), 367 deletions(-) create mode 100644 Documentation/devicetree/bindings/pinctrl/mediatek,mt76= x8-pinctrl.yaml diff --git a/Documentation/devicetree/bindings/pinctrl/mediatek,mt7620-pinc= trl.yaml b/Documentation/devicetree/bindings/pinctrl/mediatek,mt7620-pinctr= l.yaml index 3bf58da8a394..ea4a1194fbc4 100644 --- a/Documentation/devicetree/bindings/pinctrl/mediatek,mt7620-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/mediatek,mt7620-pinctrl.yaml @@ -11,7 +11,7 @@ maintainers: - Sergio Paracuellos =20 description: - MediaTek MT7620 pin controller for MT7620, MT7628 and MT7688 SoCs. + MediaTek MT7620 pin controller for MT7620 SoC. The pin controller can only set the muxing of pin groups. Muxing individ= ual pins is not supported. There is no pinconf support. =20 @@ -35,19 +35,10 @@ patternProperties: function: description: A string containing the name of the function to mux to the g= roup. - anyOf: - - description: For MT7620 SoC - enum: [ephy, gpio, gpio i2s, gpio uartf, i2c, i2s uartf, m= dio, nand, pa, - pcie refclk, pcie rst, pcm gpio, pcm i2s, pcm uartf= , refclk, - rgmii1, rgmii2, sd, spi, spi refclk, uartf, uartlit= e, wdt refclk, - wdt rst, wled] - - - description: For MT7628 and MT7688 SoCs - enum: [antenna, debug, gpio, i2c, i2s, jtag, p0led_an, p0l= ed_kn, - p1led_an, p1led_kn, p2led_an, p2led_kn, p3led_an, p= 3led_kn, - p4led_an, p4led_kn, pcie, pcm, perst, pwm, pwm0, pw= m1, pwm_uart2, - refclk, rsvd, sdxc, sdxc d5 d4, sdxc d6, sdxc d7, s= pi, spi cs1, - spis, sw_r, uart0, uart1, uart2, utif, wdt, wled_an= , wled_kn, -] + enum: [ephy, gpio, gpio i2s, gpio uartf, i2c, i2s uartf, mdio,= nand, + pa, pcie refclk, pcie rst, pcm gpio, pcm i2s, pcm uartf, + refclk, rgmii1, rgmii2, sd, spi, spi refclk, uartf, uar= tlite, + wdt refclk, wdt rst, wled] =20 groups: description: @@ -59,24 +50,6 @@ patternProperties: - function =20 allOf: - - if: - properties: - function: - const: antenna - then: - properties: - groups: - enum: [i2s] - - - if: - properties: - function: - const: debug - then: - properties: - groups: - enum: [i2c] - - if: properties: function: @@ -93,17 +66,8 @@ patternProperties: then: properties: groups: - anyOf: - - description: For MT7620 SoC - enum: [ephy, i2c, mdio, nd_sd, pa, pcie, rgmii1, rgm= ii2, - spi, spi refclk, uartf, uartlite, wdt, wled] - - - description: For MT7628 and MT7688 SoCs - enum: [gpio, i2c, i2s, p0led_an, p0led_kn, p1led_an, - p1led_kn, p2led_an, p2led_kn, p3led_an, p3led= _kn, - p4led_an, p4led_kn, perst, pwm0, pwm1, refclk, - sdmode, spi, spi cs1, spis, uart0, uart1, uar= t2, - wdt, wled_an, wled_kn] + enum: [ephy, i2c, mdio, nd_sd, pa, pcie, rgmii1, rgmii2,= spi, + spi refclk, uartf, uartlite, wdt, wled] =20 - if: properties: @@ -132,15 +96,6 @@ patternProperties: groups: enum: [i2c] =20 - - if: - properties: - function: - const: i2s - then: - properties: - groups: - enum: [i2s] - - if: properties: function: @@ -150,17 +105,6 @@ patternProperties: groups: enum: [uartf] =20 - - if: - properties: - function: - const: jtag - then: - properties: - groups: - enum: [p0led_an, p0led_kn, p1led_an, p1led_kn, p2led_an, - p2led_kn, p3led_an, p3led_kn, p4led_an, p4led_kn, - sdmode] - - if: properties: function: @@ -179,96 +123,6 @@ patternProperties: groups: enum: [nd_sd] =20 - - if: - properties: - function: - const: p0led_an - then: - properties: - groups: - enum: [p0led_an] - - - if: - properties: - function: - const: p0led_kn - then: - properties: - groups: - enum: [p0led_kn] - - - if: - properties: - function: - const: p1led_an - then: - properties: - groups: - enum: [p1led_an] - - - if: - properties: - function: - const: p1led_kn - then: - properties: - groups: - enum: [p1led_kn] - - - if: - properties: - function: - const: p2led_an - then: - properties: - groups: - enum: [p2led_an] - - - if: - properties: - function: - const: p2led_kn - then: - properties: - groups: - enum: [p2led_kn] - - - if: - properties: - function: - const: p3led_an - then: - properties: - groups: - enum: [p3led_an] - - - if: - properties: - function: - const: p3led_kn - then: - properties: - groups: - enum: [p3led_kn] - - - if: - properties: - function: - const: p4led_an - then: - properties: - groups: - enum: [p4led_an] - - - if: - properties: - function: - const: p4led_kn - then: - properties: - groups: - enum: [p4led_kn] - - if: properties: function: @@ -278,15 +132,6 @@ patternProperties: groups: enum: [pa] =20 - - if: - properties: - function: - const: pcie - then: - properties: - groups: - enum: [gpio] - - if: properties: function: @@ -305,15 +150,6 @@ patternProperties: groups: enum: [pcie] =20 - - if: - properties: - function: - const: pcm - then: - properties: - groups: - enum: [i2s] - - if: properties: function: @@ -341,51 +177,6 @@ patternProperties: groups: enum: [uartf] =20 - - if: - properties: - function: - const: perst - then: - properties: - groups: - enum: [perst] - - - if: - properties: - function: - const: pwm - then: - properties: - groups: - enum: [uart1, uart2] - - - if: - properties: - function: - const: pwm0 - then: - properties: - groups: - enum: [pwm0] - - - if: - properties: - function: - const: pwm1 - then: - properties: - groups: - enum: [pwm1] - - - if: - properties: - function: - const: pwm_uart2 - then: - properties: - groups: - enum: [spis] - - if: properties: function: @@ -393,12 +184,7 @@ patternProperties: then: properties: groups: - anyOf: - - description: For MT7620 SoC - enum: [mdio] - - - description: For MT7628 and MT7688 SoCs - enum: [gpio, refclk, spi cs1] + enum: [mdio] =20 - if: properties: @@ -418,15 +204,6 @@ patternProperties: groups: enum: [rgmii2] =20 - - if: - properties: - function: - const: rsvd - then: - properties: - groups: - enum: [p0led_an, p0led_kn, wled_an, wled_kn] - - if: properties: function: @@ -436,42 +213,6 @@ patternProperties: groups: enum: [nd_sd] =20 - - if: - properties: - function: - const: sdxc - then: - properties: - groups: - enum: [sdmode] - - - if: - properties: - function: - const: sdxc d5 d4 - then: - properties: - groups: - enum: [uart2] - - - if: - properties: - function: - const: sdxc d6 - then: - properties: - groups: - enum: [pwm1] - - - if: - properties: - function: - const: sdxc d7 - then: - properties: - groups: - enum: [pwm0] - - if: properties: function: @@ -481,15 +222,6 @@ patternProperties: groups: enum: [spi] =20 - - if: - properties: - function: - const: spi cs1 - then: - properties: - groups: - enum: [spi cs1] - - if: properties: function: @@ -499,51 +231,6 @@ patternProperties: groups: enum: [spi refclk] =20 - - if: - properties: - function: - const: spis - then: - properties: - groups: - enum: [spis] - - - if: - properties: - function: - const: sw_r - then: - properties: - groups: - enum: [uart1] - - - if: - properties: - function: - const: uart0 - then: - properties: - groups: - enum: [uart0] - - - if: - properties: - function: - const: uart1 - then: - properties: - groups: - enum: [uart1] - - - if: - properties: - function: - const: uart2 - then: - properties: - groups: - enum: [uart2] - - if: properties: function: @@ -562,25 +249,6 @@ patternProperties: groups: enum: [uartlite] =20 - - if: - properties: - function: - const: utif - then: - properties: - groups: - enum: [p1led_an, p1led_kn, p2led_an, p2led_kn, p3led_an, - p3led_kn, p4led_an, p4led_kn, pwm0, pwm1, sdmode,= spis] - - - if: - properties: - function: - const: wdt - then: - properties: - groups: - enum: [wdt] - - if: properties: function: @@ -608,33 +276,6 @@ patternProperties: groups: enum: [wled] =20 - - if: - properties: - function: - const: wled_an - then: - properties: - groups: - enum: [wled_an] - - - if: - properties: - function: - const: wled_kn - then: - properties: - groups: - enum: [wled_kn] - - - if: - properties: - function: - const: "-" - then: - properties: - groups: - enum: [i2c, spi cs1, uart0] - additionalProperties: false =20 additionalProperties: false diff --git a/Documentation/devicetree/bindings/pinctrl/mediatek,mt76x8-pinc= trl.yaml b/Documentation/devicetree/bindings/pinctrl/mediatek,mt76x8-pinctr= l.yaml new file mode 100644 index 000000000000..c818c8947866 --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/mediatek,mt76x8-pinctrl.yaml @@ -0,0 +1,454 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/mediatek,mt76x8-pinctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: MediaTek MT76X8 Pin Controller + +maintainers: + - Ar=C4=B1n=C3=A7 =C3=9CNAL + - Sergio Paracuellos + +description: + MediaTek MT76X8 pin controller for MT7628 and MT7688 SoCs. + The pin controller can only set the muxing of pin groups. Muxing individ= ual + pins is not supported. There is no pinconf support. + +properties: + compatible: + enum: + - mediatek,mt76x8-pinctrl + - ralink,mt7620-pinctrl + - ralink,rt2880-pinmux + +patternProperties: + '-pins$': + type: object + patternProperties: + '^(.*-)?pinmux$': + type: object + description: node for pinctrl. + $ref: pinmux-node.yaml# + + properties: + function: + description: + A string containing the name of the function to mux to the g= roup. + enum: [antenna, debug, gpio, i2c, i2s, jtag, p0led_an, p0led_k= n, + p1led_an, p1led_kn, p2led_an, p2led_kn, p3led_an, p3led= _kn, + p4led_an, p4led_kn, pcie, pcm, perst, pwm, pwm0, pwm1, + pwm_uart2, refclk, rsvd, sdxc, sdxc d5 d4, sdxc d6, sdx= c d7, + spi, spi cs1, spis, sw_r, uart0, uart1, uart2, utif, wd= t, + wled_an, wled_kn, -] + + groups: + description: + An array of strings. Each string contains the name of a grou= p. + maxItems: 1 + + required: + - groups + - function + + allOf: + - if: + properties: + function: + const: antenna + then: + properties: + groups: + enum: [i2s] + + - if: + properties: + function: + const: debug + then: + properties: + groups: + enum: [i2c] + + - if: + properties: + function: + const: gpio + then: + properties: + groups: + enum: [gpio, i2c, i2s, p0led_an, p0led_kn, p1led_an, p1l= ed_kn, + p2led_an, p2led_kn, p3led_an, p3led_kn, p4led_an, + p4led_kn, perst, pwm0, pwm1, refclk, sdmode, spi, + spi cs1, spis, uart0, uart1, uart2, wdt, wled_an, + wled_kn] + + - if: + properties: + function: + const: i2c + then: + properties: + groups: + enum: [i2c] + + - if: + properties: + function: + const: i2s + then: + properties: + groups: + enum: [i2s] + + - if: + properties: + function: + const: jtag + then: + properties: + groups: + enum: [p0led_an, p0led_kn, p1led_an, p1led_kn, p2led_an, + p2led_kn, p3led_an, p3led_kn, p4led_an, p4led_kn, + sdmode] + + - if: + properties: + function: + const: p0led_an + then: + properties: + groups: + enum: [p0led_an] + + - if: + properties: + function: + const: p0led_kn + then: + properties: + groups: + enum: [p0led_kn] + + - if: + properties: + function: + const: p1led_an + then: + properties: + groups: + enum: [p1led_an] + + - if: + properties: + function: + const: p1led_kn + then: + properties: + groups: + enum: [p1led_kn] + + - if: + properties: + function: + const: p2led_an + then: + properties: + groups: + enum: [p2led_an] + + - if: + properties: + function: + const: p2led_kn + then: + properties: + groups: + enum: [p2led_kn] + + - if: + properties: + function: + const: p3led_an + then: + properties: + groups: + enum: [p3led_an] + + - if: + properties: + function: + const: p3led_kn + then: + properties: + groups: + enum: [p3led_kn] + + - if: + properties: + function: + const: p4led_an + then: + properties: + groups: + enum: [p4led_an] + + - if: + properties: + function: + const: p4led_kn + then: + properties: + groups: + enum: [p4led_kn] + + - if: + properties: + function: + const: pcie + then: + properties: + groups: + enum: [gpio] + + - if: + properties: + function: + const: pcm + then: + properties: + groups: + enum: [i2s] + + - if: + properties: + function: + const: perst + then: + properties: + groups: + enum: [perst] + + - if: + properties: + function: + const: pwm + then: + properties: + groups: + enum: [uart1, uart2] + + - if: + properties: + function: + const: pwm0 + then: + properties: + groups: + enum: [pwm0] + + - if: + properties: + function: + const: pwm1 + then: + properties: + groups: + enum: [pwm1] + + - if: + properties: + function: + const: pwm_uart2 + then: + properties: + groups: + enum: [spis] + + - if: + properties: + function: + const: refclk + then: + properties: + groups: + enum: [gpio, refclk, spi cs1] + + - if: + properties: + function: + const: rsvd + then: + properties: + groups: + enum: [p0led_an, p0led_kn, wled_an, wled_kn] + + - if: + properties: + function: + const: sdxc + then: + properties: + groups: + enum: [sdmode] + + - if: + properties: + function: + const: sdxc d5 d4 + then: + properties: + groups: + enum: [uart2] + + - if: + properties: + function: + const: sdxc d6 + then: + properties: + groups: + enum: [pwm1] + + - if: + properties: + function: + const: sdxc d7 + then: + properties: + groups: + enum: [pwm0] + + - if: + properties: + function: + const: spi + then: + properties: + groups: + enum: [spi] + + - if: + properties: + function: + const: spi cs1 + then: + properties: + groups: + enum: [spi cs1] + + - if: + properties: + function: + const: spis + then: + properties: + groups: + enum: [spis] + + - if: + properties: + function: + const: sw_r + then: + properties: + groups: + enum: [uart1] + + - if: + properties: + function: + const: uart0 + then: + properties: + groups: + enum: [uart0] + + - if: + properties: + function: + const: uart1 + then: + properties: + groups: + enum: [uart1] + + - if: + properties: + function: + const: uart2 + then: + properties: + groups: + enum: [uart2] + + - if: + properties: + function: + const: utif + then: + properties: + groups: + enum: [p1led_an, p1led_kn, p2led_an, p2led_kn, p3led_an, + p3led_kn, p4led_an, p4led_kn, pwm0, pwm1, sdmode,= spis] + + - if: + properties: + function: + const: wdt + then: + properties: + groups: + enum: [wdt] + + - if: + properties: + function: + const: wled_an + then: + properties: + groups: + enum: [wled_an] + + - if: + properties: + function: + const: wled_kn + then: + properties: + groups: + enum: [wled_kn] + + - if: + properties: + function: + const: "-" + then: + properties: + groups: + enum: [i2c, spi cs1, uart0] + + additionalProperties: false + + additionalProperties: false + +allOf: + - $ref: "pinctrl.yaml#" + +required: + - compatible + +additionalProperties: false + +examples: + - | + pinctrl { + compatible =3D "mediatek,mt76x8-pinctrl"; + + i2c_pins: i2c0-pins { + pinmux { + groups =3D "i2c"; + function =3D "i2c"; + }; + }; + }; --=20 2.37.2 From nobody Thu Nov 14 07:05:11 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id BA052C636D6 for ; Wed, 22 Feb 2023 18:41:29 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232625AbjBVSl1 (ORCPT ); Wed, 22 Feb 2023 13:41:27 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:43998 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232602AbjBVSk6 (ORCPT ); Wed, 22 Feb 2023 13:40:58 -0500 Received: from mail-wr1-x42b.google.com (mail-wr1-x42b.google.com [IPv6:2a00:1450:4864:20::42b]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 928F83E61C; Wed, 22 Feb 2023 10:40:31 -0800 (PST) Received: by mail-wr1-x42b.google.com with SMTP id r7so8587145wrz.6; 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Wed, 22 Feb 2023 10:40:29 -0800 (PST) Received: from arinc9-PC.lan ([37.120.152.236]) by smtp.gmail.com with ESMTPSA id l18-20020a5d4112000000b002c56179d39esm9372845wrp.44.2023.02.22.10.40.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 22 Feb 2023 10:40:29 -0800 (PST) From: arinc9.unal@gmail.com X-Google-Original-From: arinc.unal@arinc9.com To: Sergio Paracuellos , Linus Walleij , Rob Herring , Krzysztof Kozlowski Cc: =?UTF-8?q?Ar=C4=B1n=C3=A7=20=C3=9CNAL?= , linux-mediatek@lists.infradead.org, linux-mips@vger.kernel.org, linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Matthias Brugger , Sean Wang , William Dean , Daniel Golle , Daniel Santos , Luiz Angelo Daros de Luca , Frank Wunderlich , Landen Chao , DENG Qingfang , Sean Wang , erkin.bozoglu@xeront.com Subject: [RFC PATCH 11/16] MAINTAINERS: move ralink pinctrl to mediatek mips pinctrl Date: Wed, 22 Feb 2023 21:39:27 +0300 Message-Id: <20230222183932.33267-12-arinc.unal@arinc9.com> X-Mailer: git-send-email 2.37.2 In-Reply-To: <20230222183932.33267-1-arinc.unal@arinc9.com> References: <20230222183932.33267-1-arinc.unal@arinc9.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Ar=C4=B1n=C3=A7 =C3=9CNAL The Ralink pinctrl driver is now under the name of MediaTek MIPS pin controller. Move the maintainer information accordingly. Add dt-binding schema files. Add linux-mediatek@lists.infradead.org as an associated mailing list. Signed-off-by: Ar=C4=B1n=C3=A7 =C3=9CNAL --- MAINTAINERS | 29 ++++++++++++++++++++++------- 1 file changed, 22 insertions(+), 7 deletions(-) diff --git a/MAINTAINERS b/MAINTAINERS index 8a851eb053ca..a75e6ffc0866 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -16541,6 +16541,28 @@ F: Documentation/devicetree/bindings/pinctrl/media= tek,mt7622-pinctrl.yaml F: Documentation/devicetree/bindings/pinctrl/mediatek,mt8183-pinctrl.yaml F: drivers/pinctrl/mediatek/ =20 +PIN CONTROLLER - MEDIATEK MIPS +M: Ar=C4=B1n=C3=A7 =C3=9CNAL +M: Sergio Paracuellos +L: linux-mediatek@lists.infradead.org (moderated for non-subscribers) +L: linux-mips@vger.kernel.org +S: Maintained +F: Documentation/devicetree/bindings/pinctrl/mediatek,mt7620-pinctrl.yaml +F: Documentation/devicetree/bindings/pinctrl/mediatek,mt7621-pinctrl.yaml +F: Documentation/devicetree/bindings/pinctrl/mediatek,mt76x8-pinctrl.yaml +F: Documentation/devicetree/bindings/pinctrl/mediatek,rt2880-pinctrl.yaml +F: Documentation/devicetree/bindings/pinctrl/mediatek,rt305x-pinctrl.yaml +F: Documentation/devicetree/bindings/pinctrl/mediatek,rt3352-pinctrl.yaml +F: Documentation/devicetree/bindings/pinctrl/mediatek,rt3883-pinctrl.yaml +F: Documentation/devicetree/bindings/pinctrl/mediatek,rt5350-pinctrl.yaml +F: drivers/pinctrl/mediatek/pinctrl-mt7620.c +F: drivers/pinctrl/mediatek/pinctrl-mt7621.c +F: drivers/pinctrl/mediatek/pinctrl-mt76x8.c +F: drivers/pinctrl/mediatek/pinctrl-mtmips.* +F: drivers/pinctrl/mediatek/pinctrl-rt2880.c +F: drivers/pinctrl/mediatek/pinctrl-rt305x.c +F: drivers/pinctrl/mediatek/pinctrl-rt3883.c + PIN CONTROLLER - MICROCHIP AT91 M: Ludovic Desroches L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) @@ -17486,13 +17508,6 @@ L: linux-mips@vger.kernel.org S: Maintained F: arch/mips/boot/dts/ralink/mt7621* =20 -RALINK PINCTRL DRIVER -M: Ar=C4=B1n=C3=A7 =C3=9CNAL -M: Sergio Paracuellos -L: linux-mips@vger.kernel.org -S: Maintained -F: drivers/pinctrl/ralink/ - RALINK RT2X00 WIRELESS LAN DRIVER M: Stanislaw Gruszka M: Helmut Schaa --=20 2.37.2 From nobody Thu Nov 14 07:05:11 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id CC693C677F1 for ; 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Wed, 22 Feb 2023 10:40:31 -0800 (PST) From: arinc9.unal@gmail.com X-Google-Original-From: arinc.unal@arinc9.com To: Sergio Paracuellos , Linus Walleij , Rob Herring , Krzysztof Kozlowski Cc: =?UTF-8?q?Ar=C4=B1n=C3=A7=20=C3=9CNAL?= , linux-mediatek@lists.infradead.org, linux-mips@vger.kernel.org, linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Matthias Brugger , Sean Wang , William Dean , Daniel Golle , Daniel Santos , Luiz Angelo Daros de Luca , Frank Wunderlich , Landen Chao , DENG Qingfang , Sean Wang , erkin.bozoglu@xeront.com Subject: [RFC PATCH 12/16] dt-bindings: pinctrl: mediatek: mt6795: rename to mediatek,mt6795-pinctrl Date: Wed, 22 Feb 2023 21:39:28 +0300 Message-Id: <20230222183932.33267-13-arinc.unal@arinc9.com> X-Mailer: git-send-email 2.37.2 In-Reply-To: <20230222183932.33267-1-arinc.unal@arinc9.com> References: <20230222183932.33267-1-arinc.unal@arinc9.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Ar=C4=B1n=C3=A7 =C3=9CNAL Rename mediatek,pinctrl-mt6795.yaml to mediatek,mt6795-pinctrl.yaml to be on par with the compatible string and other mediatek dt-binding schemas. Signed-off-by: Ar=C4=B1n=C3=A7 =C3=9CNAL Acked-by: Rob Herring --- ...ediatek,pinctrl-mt6795.yaml =3D> mediatek,mt6795-pinctrl.yaml} | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) rename Documentation/devicetree/bindings/pinctrl/{mediatek,pinctrl-mt6795.= yaml =3D> mediatek,mt6795-pinctrl.yaml} (98%) diff --git a/Documentation/devicetree/bindings/pinctrl/mediatek,pinctrl-mt6= 795.yaml b/Documentation/devicetree/bindings/pinctrl/mediatek,mt6795-pinctr= l.yaml similarity index 98% rename from Documentation/devicetree/bindings/pinctrl/mediatek,pinctrl-mt67= 95.yaml rename to Documentation/devicetree/bindings/pinctrl/mediatek,mt6795-pinctrl= .yaml index 9399e0215526..c5131f053b61 100644 --- a/Documentation/devicetree/bindings/pinctrl/mediatek,pinctrl-mt6795.yaml +++ b/Documentation/devicetree/bindings/pinctrl/mediatek,mt6795-pinctrl.yaml @@ -1,7 +1,7 @@ # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) %YAML 1.2 --- -$id: http://devicetree.org/schemas/pinctrl/mediatek,pinctrl-mt6795.yaml# +$id: http://devicetree.org/schemas/pinctrl/mediatek,mt6795-pinctrl.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# =20 title: Mediatek MT6795 Pin Controller --=20 2.37.2 From nobody Thu Nov 14 07:05:11 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5CB70C6FA9D for ; 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Wed, 22 Feb 2023 10:40:33 -0800 (PST) From: arinc9.unal@gmail.com X-Google-Original-From: arinc.unal@arinc9.com To: Sergio Paracuellos , Linus Walleij , Rob Herring , Krzysztof Kozlowski Cc: =?UTF-8?q?Ar=C4=B1n=C3=A7=20=C3=9CNAL?= , linux-mediatek@lists.infradead.org, linux-mips@vger.kernel.org, linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Matthias Brugger , Sean Wang , William Dean , Daniel Golle , Daniel Santos , Luiz Angelo Daros de Luca , Frank Wunderlich , Landen Chao , DENG Qingfang , Sean Wang , erkin.bozoglu@xeront.com Subject: [RFC PATCH 13/16] dt-bindings: pinctrl: mediatek: mt8186: rename to mediatek,mt8186-pinctrl Date: Wed, 22 Feb 2023 21:39:29 +0300 Message-Id: <20230222183932.33267-14-arinc.unal@arinc9.com> X-Mailer: git-send-email 2.37.2 In-Reply-To: <20230222183932.33267-1-arinc.unal@arinc9.com> References: <20230222183932.33267-1-arinc.unal@arinc9.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Ar=C4=B1n=C3=A7 =C3=9CNAL Rename pinctrl-mt8186.yaml to mediatek,mt8186-pinctrl.yaml to be on par with the compatible string and other mediatek dt-binding schemas. Signed-off-by: Ar=C4=B1n=C3=A7 =C3=9CNAL Acked-by: Rob Herring --- .../{pinctrl-mt8186.yaml =3D> mediatek,mt8186-pinctrl.yaml} | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) rename Documentation/devicetree/bindings/pinctrl/{pinctrl-mt8186.yaml =3D>= mediatek,mt8186-pinctrl.yaml} (99%) diff --git a/Documentation/devicetree/bindings/pinctrl/pinctrl-mt8186.yaml = b/Documentation/devicetree/bindings/pinctrl/mediatek,mt8186-pinctrl.yaml similarity index 99% rename from Documentation/devicetree/bindings/pinctrl/pinctrl-mt8186.yaml rename to Documentation/devicetree/bindings/pinctrl/mediatek,mt8186-pinctrl= .yaml index 26573a793b57..32d64416eb16 100644 --- a/Documentation/devicetree/bindings/pinctrl/pinctrl-mt8186.yaml +++ b/Documentation/devicetree/bindings/pinctrl/mediatek,mt8186-pinctrl.yaml @@ -1,7 +1,7 @@ # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) %YAML 1.2 --- -$id: http://devicetree.org/schemas/pinctrl/pinctrl-mt8186.yaml# +$id: http://devicetree.org/schemas/pinctrl/mediatek,mt8186-pinctrl.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# =20 title: Mediatek MT8186 Pin Controller --=20 2.37.2 From nobody Thu Nov 14 07:05:11 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8C96CC61DA4 for ; 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Wed, 22 Feb 2023 10:40:36 -0800 (PST) From: arinc9.unal@gmail.com X-Google-Original-From: arinc.unal@arinc9.com To: Sergio Paracuellos , Linus Walleij , Rob Herring , Krzysztof Kozlowski Cc: =?UTF-8?q?Ar=C4=B1n=C3=A7=20=C3=9CNAL?= , linux-mediatek@lists.infradead.org, linux-mips@vger.kernel.org, linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Matthias Brugger , Sean Wang , William Dean , Daniel Golle , Daniel Santos , Luiz Angelo Daros de Luca , Frank Wunderlich , Landen Chao , DENG Qingfang , Sean Wang , erkin.bozoglu@xeront.com Subject: [RFC PATCH 14/16] dt-bindings: pinctrl: mediatek: mt8192: rename to mediatek,mt8192-pinctrl Date: Wed, 22 Feb 2023 21:39:30 +0300 Message-Id: <20230222183932.33267-15-arinc.unal@arinc9.com> X-Mailer: git-send-email 2.37.2 In-Reply-To: <20230222183932.33267-1-arinc.unal@arinc9.com> References: <20230222183932.33267-1-arinc.unal@arinc9.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Ar=C4=B1n=C3=A7 =C3=9CNAL Rename pinctrl-mt8192.yaml to mediatek,mt8192-pinctrl.yaml to be on par with the compatible string and other mediatek dt-binding schemas. Signed-off-by: Ar=C4=B1n=C3=A7 =C3=9CNAL Acked-by: Rob Herring --- .../{pinctrl-mt8192.yaml =3D> mediatek,mt8192-pinctrl.yaml} | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) rename Documentation/devicetree/bindings/pinctrl/{pinctrl-mt8192.yaml =3D>= mediatek,mt8192-pinctrl.yaml} (98%) diff --git a/Documentation/devicetree/bindings/pinctrl/pinctrl-mt8192.yaml = b/Documentation/devicetree/bindings/pinctrl/mediatek,mt8192-pinctrl.yaml similarity index 98% rename from Documentation/devicetree/bindings/pinctrl/pinctrl-mt8192.yaml rename to Documentation/devicetree/bindings/pinctrl/mediatek,mt8192-pinctrl= .yaml index e0e943e5b874..e764cb0f8c1a 100644 --- a/Documentation/devicetree/bindings/pinctrl/pinctrl-mt8192.yaml +++ b/Documentation/devicetree/bindings/pinctrl/mediatek,mt8192-pinctrl.yaml @@ -1,7 +1,7 @@ # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) %YAML 1.2 --- -$id: http://devicetree.org/schemas/pinctrl/pinctrl-mt8192.yaml# +$id: http://devicetree.org/schemas/pinctrl/mediatek,mt8192-pinctrl.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# =20 title: Mediatek MT8192 Pin Controller --=20 2.37.2 From nobody Thu Nov 14 07:05:11 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id A2C4DC64ED6 for ; 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Wed, 22 Feb 2023 10:40:38 -0800 (PST) From: arinc9.unal@gmail.com X-Google-Original-From: arinc.unal@arinc9.com To: Sergio Paracuellos , Linus Walleij , Rob Herring , Krzysztof Kozlowski Cc: =?UTF-8?q?Ar=C4=B1n=C3=A7=20=C3=9CNAL?= , linux-mediatek@lists.infradead.org, linux-mips@vger.kernel.org, linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Matthias Brugger , Sean Wang , William Dean , Daniel Golle , Daniel Santos , Luiz Angelo Daros de Luca , Frank Wunderlich , Landen Chao , DENG Qingfang , Sean Wang , erkin.bozoglu@xeront.com Subject: [RFC PATCH 15/16] dt-bindings: pinctrl: mediatek: mt8195: rename to mediatek,mt8195-pinctrl Date: Wed, 22 Feb 2023 21:39:31 +0300 Message-Id: <20230222183932.33267-16-arinc.unal@arinc9.com> X-Mailer: git-send-email 2.37.2 In-Reply-To: <20230222183932.33267-1-arinc.unal@arinc9.com> References: <20230222183932.33267-1-arinc.unal@arinc9.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Ar=C4=B1n=C3=A7 =C3=9CNAL Rename pinctrl-mt8195.yaml to mediatek,mt8195-pinctrl.yaml to be on par with the compatible string and other mediatek dt-binding schemas. Signed-off-by: Ar=C4=B1n=C3=A7 =C3=9CNAL Acked-by: Rob Herring --- .../{pinctrl-mt8195.yaml =3D> mediatek,mt8195-pinctrl.yaml} | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) rename Documentation/devicetree/bindings/pinctrl/{pinctrl-mt8195.yaml =3D>= mediatek,mt8195-pinctrl.yaml} (99%) diff --git a/Documentation/devicetree/bindings/pinctrl/pinctrl-mt8195.yaml = b/Documentation/devicetree/bindings/pinctrl/mediatek,mt8195-pinctrl.yaml similarity index 99% rename from Documentation/devicetree/bindings/pinctrl/pinctrl-mt8195.yaml rename to Documentation/devicetree/bindings/pinctrl/mediatek,mt8195-pinctrl= .yaml index 66fe17e9e4d3..7b3dfc14eedc 100644 --- a/Documentation/devicetree/bindings/pinctrl/pinctrl-mt8195.yaml +++ b/Documentation/devicetree/bindings/pinctrl/mediatek,mt8195-pinctrl.yaml @@ -1,7 +1,7 @@ # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) %YAML 1.2 --- -$id: http://devicetree.org/schemas/pinctrl/pinctrl-mt8195.yaml# +$id: http://devicetree.org/schemas/pinctrl/mediatek,mt8195-pinctrl.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# =20 title: Mediatek MT8195 Pin Controller --=20 2.37.2 From nobody Thu Nov 14 07:05:11 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0CD22C636D6 for ; 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Wed, 22 Feb 2023 10:40:40 -0800 (PST) From: arinc9.unal@gmail.com X-Google-Original-From: arinc.unal@arinc9.com To: Sergio Paracuellos , Linus Walleij , Rob Herring , Krzysztof Kozlowski Cc: =?UTF-8?q?Ar=C4=B1n=C3=A7=20=C3=9CNAL?= , linux-mediatek@lists.infradead.org, linux-mips@vger.kernel.org, linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Matthias Brugger , Sean Wang , William Dean , Daniel Golle , Daniel Santos , Luiz Angelo Daros de Luca , Frank Wunderlich , Landen Chao , DENG Qingfang , Sean Wang , erkin.bozoglu@xeront.com Subject: [RFC PATCH 16/16] dt-bindings: pinctrl: mediatek: improve schemas Date: Wed, 22 Feb 2023 21:39:32 +0300 Message-Id: <20230222183932.33267-17-arinc.unal@arinc9.com> X-Mailer: git-send-email 2.37.2 In-Reply-To: <20230222183932.33267-1-arinc.unal@arinc9.com> References: <20230222183932.33267-1-arinc.unal@arinc9.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Ar=C4=B1n=C3=A7 =C3=9CNAL Some schemas include "MediaTek", some "Mediatek". Rename all to "MediaTek" to address the naming inconsistency. Change the style of description properties to plain style where there's no need to preserve the line endings, and vice versa. Fit the schemas to 80 columns for each line. Set patternProperties to '^.*mux.*$' on mediatek,mt7986-pinctrl.yaml. Signed-off-by: Ar=C4=B1n=C3=A7 =C3=9CNAL --- .../pinctrl/mediatek,mt65xx-pinctrl.yaml | 24 +++--- .../pinctrl/mediatek,mt6779-pinctrl.yaml | 33 +++++---- .../pinctrl/mediatek,mt6795-pinctrl.yaml | 33 +++++---- .../pinctrl/mediatek,mt7620-pinctrl.yaml | 2 +- .../pinctrl/mediatek,mt7621-pinctrl.yaml | 2 +- .../pinctrl/mediatek,mt7622-pinctrl.yaml | 26 +++---- .../pinctrl/mediatek,mt76x8-pinctrl.yaml | 2 +- .../pinctrl/mediatek,mt7981-pinctrl.yaml | 35 +++++---- .../pinctrl/mediatek,mt7986-pinctrl.yaml | 64 ++++++++-------- .../pinctrl/mediatek,mt8183-pinctrl.yaml | 26 ++++--- .../pinctrl/mediatek,mt8186-pinctrl.yaml | 47 ++++++------ .../pinctrl/mediatek,mt8188-pinctrl.yaml | 74 ++++++++++--------- .../pinctrl/mediatek,mt8192-pinctrl.yaml | 47 ++++++------ .../pinctrl/mediatek,mt8195-pinctrl.yaml | 38 +++++----- .../pinctrl/mediatek,mt8365-pinctrl.yaml | 28 +++---- .../pinctrl/mediatek,rt2880-pinctrl.yaml | 2 +- .../pinctrl/mediatek,rt305x-pinctrl.yaml | 2 +- .../pinctrl/mediatek,rt3352-pinctrl.yaml | 2 +- .../pinctrl/mediatek,rt3883-pinctrl.yaml | 2 +- .../pinctrl/mediatek,rt5350-pinctrl.yaml | 2 +- 20 files changed, 256 insertions(+), 235 deletions(-) diff --git a/Documentation/devicetree/bindings/pinctrl/mediatek,mt65xx-pinc= trl.yaml b/Documentation/devicetree/bindings/pinctrl/mediatek,mt65xx-pinctr= l.yaml index a55c8e4ff26e..206fa8ba9502 100644 --- a/Documentation/devicetree/bindings/pinctrl/mediatek,mt65xx-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/mediatek,mt65xx-pinctrl.yaml @@ -4,13 +4,13 @@ $id: http://devicetree.org/schemas/pinctrl/mediatek,mt65xx-pinctrl.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# =20 -title: Mediatek MT65xx Pin Controller +title: MediaTek MT65xx Pin Controller =20 maintainers: - Sean Wang =20 -description: |+ - The Mediatek's Pin controller is used to control SoC pins. +description: + The MediaTek's Pin controller is used to control SoC pins. =20 properties: compatible: @@ -30,7 +30,7 @@ properties: =20 pins-are-numbered: $ref: /schemas/types.yaml#/definitions/flag - description: | + description: Specify the subnodes are using numbered pinmux to specify pins. (UNU= SED) deprecated: true =20 @@ -38,10 +38,10 @@ properties: =20 "#gpio-cells": const: 2 - description: | - Number of cells in GPIO specifier. Since the generic GPIO - binding is used, the amount of cells must be specified as 2. See the= below - mentioned gpio binding representation for description of particular = cells. + description: + Number of cells in GPIO specifier. Since the generic GPIO binding is= used, + the amount of cells must be specified as 2. See the below mentioned = gpio + binding representation for description of particular cells. =20 mediatek,pctl-regmap: $ref: /schemas/types.yaml#/definitions/phandle-array @@ -49,7 +49,7 @@ properties: maxItems: 1 minItems: 1 maxItems: 2 - description: | + description: Should be phandles of the syscfg node. =20 interrupt-controller: true @@ -77,7 +77,7 @@ patternProperties: '(^pins|pins?$)': type: object additionalProperties: false - description: | + description: A pinctrl node should contain at least one subnodes representing= the pinctrl groups available on the machine. Each subnode will list = the pins it needs, and how they should be configured, with regard to= muxer @@ -95,7 +95,7 @@ patternProperties: bias-disable: true =20 bias-pull-up: - description: | + description: Besides generic pinconfig options, it can be used as the pul= l up settings for 2 pull resistors, R0 and R1. User can configure= those special pins. Some macros have been defined for this usage, = such @@ -117,7 +117,7 @@ patternProperties: input-schmitt-disable: true =20 drive-strength: - description: | + description: Can support some arguments, such as MTK_DRIVE_4mA, MTK_DRIVE= _6mA, etc. See dt-bindings/pinctrl/mt65xx.h for valid arguments. =20 diff --git a/Documentation/devicetree/bindings/pinctrl/mediatek,mt6779-pinc= trl.yaml b/Documentation/devicetree/bindings/pinctrl/mediatek,mt6779-pinctr= l.yaml index a2141eb0854e..17046d204087 100644 --- a/Documentation/devicetree/bindings/pinctrl/mediatek,mt6779-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/mediatek,mt6779-pinctrl.yaml @@ -4,15 +4,15 @@ $id: http://devicetree.org/schemas/pinctrl/mediatek,mt6779-pinctrl.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# =20 -title: Mediatek MT6779 Pin Controller +title: MediaTek MT6779 Pin Controller =20 maintainers: - Andy Teng - Sean Wang =20 description: - The MediaTek pin controller on MT6779 is used to control pin - functions, pull up/down resistance and drive strength options. + The MediaTek pin controller on MT6779 is used to control pin functions, = pull + up/down resistance and drive strength options. =20 properties: compatible: @@ -29,22 +29,22 @@ properties: =20 "#gpio-cells": const: 2 - description: | - Number of cells in GPIO specifier. Since the generic GPIO - binding is used, the amount of cells must be specified as 2. See the= below - mentioned gpio binding representation for description of particular = cells. + description: + Number of cells in GPIO specifier. Since the generic GPIO binding is= used, + the amount of cells must be specified as 2. See the below mentioned = gpio + binding representation for description of particular cells. =20 gpio-ranges: minItems: 1 maxItems: 5 - description: | + description: GPIO valid number range. =20 interrupt-controller: true =20 interrupts: maxItems: 1 - description: | + description: Specifies the summary IRQ. =20 "#interrupt-cells": @@ -118,19 +118,20 @@ patternProperties: patternProperties: '-pins*$': type: object - description: | + description: A pinctrl node should contain at least one subnodes representing= the pinctrl groups available on the machine. Each subnode will list = the pins it needs, and how they should be configured, with regard to= muxer - configuration, pullups, drive strength, input enable/disable and= input schmitt. + configuration, pullups, drive strength, input enable/disable and= input + schmitt. $ref: "/schemas/pinctrl/pincfg-node.yaml" =20 properties: pinmux: description: integer array, represents gpio pin number and mux setting. - Supported pin number and mux varies for different SoCs, and = are defined - as macros in boot/dts/-pinfunc.h directly. + Supported pin number and mux varies for different SoCs, and = are + defined as macros in boot/dts/-pinfunc.h directly. =20 bias-disable: true =20 @@ -159,7 +160,8 @@ patternProperties: mediatek,pull-up-adv: description: | Pull up setings for 2 pull resistors, R0 and R1. User can - configure those special pins. Valid arguments are described = as below: + configure those special pins. Valid arguments are described = as + below: 0: (R1, R0) =3D (0, 0) which means R1 disabled and R0 disabl= ed. 1: (R1, R0) =3D (0, 1) which means R1 disabled and R0 enable= d. 2: (R1, R0) =3D (1, 0) which means R1 enabled and R0 disable= d. @@ -170,7 +172,8 @@ patternProperties: mediatek,pull-down-adv: description: | Pull down settings for 2 pull resistors, R0 and R1. User can - configure those special pins. Valid arguments are described = as below: + configure those special pins. Valid arguments are described = as + below: 0: (R1, R0) =3D (0, 0) which means R1 disabled and R0 disabl= ed. 1: (R1, R0) =3D (0, 1) which means R1 disabled and R0 enable= d. 2: (R1, R0) =3D (1, 0) which means R1 enabled and R0 disable= d. diff --git a/Documentation/devicetree/bindings/pinctrl/mediatek,mt6795-pinc= trl.yaml b/Documentation/devicetree/bindings/pinctrl/mediatek,mt6795-pinctr= l.yaml index c5131f053b61..5bd78e88fea3 100644 --- a/Documentation/devicetree/bindings/pinctrl/mediatek,mt6795-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/mediatek,mt6795-pinctrl.yaml @@ -4,14 +4,14 @@ $id: http://devicetree.org/schemas/pinctrl/mediatek,mt6795-pinctrl.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# =20 -title: Mediatek MT6795 Pin Controller +title: MediaTek MT6795 Pin Controller =20 maintainers: - AngeloGioacchino Del Regno - Sean Wang =20 -description: | - The Mediatek's Pin controller is used to control SoC pins. +description: + The MediaTek's MT6795 Pin controller is used to control SoC pins. =20 properties: compatible: @@ -22,8 +22,8 @@ properties: '#gpio-cells': description: | Number of cells in GPIO specifier. Since the generic GPIO binding is= used, - the amount of cells must be specified as 2. See the below - mentioned gpio binding representation for description of particular = cells. + the amount of cells must be specified as 2. See the below mentioned = gpio + binding representation for description of particular cells. const: 2 =20 gpio-ranges: @@ -65,8 +65,8 @@ patternProperties: A pinctrl node should contain at least one subnodes representing= the pinctrl groups available on the machine. Each subnode will list = the pins it needs, and how they should be configured, with regard to= muxer - configuration, pullups, drive strength, input enable/disable and - input schmitt. + configuration, pullups, drive strength, input enable/disable and= input + schmitt. An example of using macro: pincontroller { /* GPIO0 set as multifunction GPIO0 */ @@ -86,11 +86,10 @@ patternProperties: =20 properties: pinmux: - description: | + description: Integer array, represents gpio pin number and mux setting. Supported pin number and mux varies for different SoCs, and = are - defined as macros in dt-bindings/pinctrl/-pinfunc.h - directly. + defined as macros in dt-bindings/pinctrl/-pinfunc.h dir= ectly. =20 drive-strength: enum: [2, 4, 6, 8, 10, 12, 14, 16] @@ -100,7 +99,7 @@ patternProperties: - type: boolean - enum: [100, 101, 102, 103] description: mt6795 pull down PUPD/R0/R1 type define value. - description: | + description: For normal pull down type, it is not necessary to specify R= 1R0 values; When pull down type is PUPD/R0/R1, adding R1R0 defi= nes will set different resistance values. @@ -110,10 +109,10 @@ patternProperties: - type: boolean - enum: [100, 101, 102, 103] description: mt6795 pull up PUPD/R0/R1 type define value. - description: | + description: For normal pull up type, it is not necessary to specify R1R0 - values; When pull up type is PUPD/R0/R1, adding R1R0 defines - will set different resistance values. + values; When pull up type is PUPD/R0/R1, adding R1R0 define= s will + set different resistance values. =20 bias-disable: true =20 @@ -132,7 +131,8 @@ patternProperties: mediatek,pull-up-adv: description: | Pull up setings for 2 pull resistors, R0 and R1. User can - configure those special pins. Valid arguments are described = as below: + configure those special pins. Valid arguments are described = as + below: 0: (R1, R0) =3D (0, 0) which means R1 disabled and R0 disabl= ed. 1: (R1, R0) =3D (0, 1) which means R1 disabled and R0 enable= d. 2: (R1, R0) =3D (1, 0) which means R1 enabled and R0 disable= d. @@ -143,7 +143,8 @@ patternProperties: mediatek,pull-down-adv: description: | Pull down settings for 2 pull resistors, R0 and R1. User can - configure those special pins. Valid arguments are described = as below: + configure those special pins. Valid arguments are described = as + below: 0: (R1, R0) =3D (0, 0) which means R1 disabled and R0 disabl= ed. 1: (R1, R0) =3D (0, 1) which means R1 disabled and R0 enable= d. 2: (R1, R0) =3D (1, 0) which means R1 enabled and R0 disable= d. diff --git a/Documentation/devicetree/bindings/pinctrl/mediatek,mt7620-pinc= trl.yaml b/Documentation/devicetree/bindings/pinctrl/mediatek,mt7620-pinctr= l.yaml index ea4a1194fbc4..2a5495a3a717 100644 --- a/Documentation/devicetree/bindings/pinctrl/mediatek,mt7620-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/mediatek,mt7620-pinctrl.yaml @@ -10,7 +10,7 @@ maintainers: - Ar=C4=B1n=C3=A7 =C3=9CNAL - Sergio Paracuellos =20 -description: +description: | MediaTek MT7620 pin controller for MT7620 SoC. The pin controller can only set the muxing of pin groups. Muxing individ= ual pins is not supported. There is no pinconf support. diff --git a/Documentation/devicetree/bindings/pinctrl/mediatek,mt7621-pinc= trl.yaml b/Documentation/devicetree/bindings/pinctrl/mediatek,mt7621-pinctr= l.yaml index 4dfe3da5fd40..1fc227c27bd0 100644 --- a/Documentation/devicetree/bindings/pinctrl/mediatek,mt7621-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/mediatek,mt7621-pinctrl.yaml @@ -10,7 +10,7 @@ maintainers: - Ar=C4=B1n=C3=A7 =C3=9CNAL - Sergio Paracuellos =20 -description: +description: | MediaTek MT7621 pin controller for MT7621 SoC. The pin controller can only set the muxing of pin groups. Muxing individ= ual pins is not supported. There is no pinconf support. diff --git a/Documentation/devicetree/bindings/pinctrl/mediatek,mt7622-pinc= trl.yaml b/Documentation/devicetree/bindings/pinctrl/mediatek,mt7622-pinctr= l.yaml index ac93eb8f01a6..740a26e1ede1 100644 --- a/Documentation/devicetree/bindings/pinctrl/mediatek,mt7622-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/mediatek,mt7622-pinctrl.yaml @@ -4,12 +4,12 @@ $id: http://devicetree.org/schemas/pinctrl/mediatek,mt7622-pinctrl.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# =20 -title: Mediatek MT7622 Pin Controller +title: MediaTek MT7622 Pin Controller =20 maintainers: - Sean Wang =20 -description: |+ +description: The MediaTek's MT7622 Pin controller is used to control SoC pins. =20 properties: @@ -29,10 +29,10 @@ properties: =20 "#gpio-cells": const: 2 - description: | - Number of cells in GPIO specifier. Since the generic GPIO - binding is used, the amount of cells must be specified as 2. See the= below - mentioned gpio binding representation for description of particular = cells. + description: + Number of cells in GPIO specifier. Since the generic GPIO binding is= used, + the amount of cells must be specified as 2. See the below mentioned = gpio + binding representation for description of particular cells. =20 interrupt-controller: true =20 @@ -68,18 +68,18 @@ patternProperties: '^mux(-|$)': type: object additionalProperties: false - description: | + description: pinmux configuration nodes. $ref: "/schemas/pinctrl/pinmux-node.yaml" properties: function: - description: | + description: A string containing the name of the function to mux to the g= roup. enum: [emmc, eth, i2c, i2s, ir, led, flash, pcie, pmic, pwm, s= d, spi, tdm, uart, watchdog, wifi] =20 groups: - description: | + description: An array of strings. Each string contains the name of a grou= p. =20 drive-strength: @@ -247,7 +247,7 @@ patternProperties: '^conf(-|$)': type: object additionalProperties: false - description: | + description: pinconf configuration nodes. $ref: "/schemas/pinctrl/pincfg-node.yaml" =20 @@ -258,7 +258,7 @@ patternProperties: Valid values are the same as the pinmux node. =20 pins: - description: | + description: An array of strings. Each string contains the name of a pin. enum: [GPIO_A, I2S1_IN, I2S1_OUT, I2S_BCLK, I2S_WS, I2S_MCLK, = TXD0, RXD0, SPI_WP, SPI_HOLD, SPI_CLK, SPI_MOSI, SPI_MISO, SP= I_CS, @@ -315,14 +315,14 @@ patternProperties: enum: [0, 1] =20 mediatek,tdsel: - description: | + description: An integer describing the steps for output level shifter duty cycle when asserted (high pulse width adjustment). Valid arg= uments are from 0 to 15. $ref: /schemas/types.yaml#/definitions/uint32 =20 mediatek,rdsel: - description: | + description: An integer describing the steps for input level shifter duty= cycle when asserted (high pulse width adjustment). Valid arguments= are from 0 to 63. diff --git a/Documentation/devicetree/bindings/pinctrl/mediatek,mt76x8-pinc= trl.yaml b/Documentation/devicetree/bindings/pinctrl/mediatek,mt76x8-pinctr= l.yaml index c818c8947866..48d563886e57 100644 --- a/Documentation/devicetree/bindings/pinctrl/mediatek,mt76x8-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/mediatek,mt76x8-pinctrl.yaml @@ -10,7 +10,7 @@ maintainers: - Ar=C4=B1n=C3=A7 =C3=9CNAL - Sergio Paracuellos =20 -description: +description: | MediaTek MT76X8 pin controller for MT7628 and MT7688 SoCs. The pin controller can only set the muxing of pin groups. Muxing individ= ual pins is not supported. There is no pinconf support. diff --git a/Documentation/devicetree/bindings/pinctrl/mediatek,mt7981-pinc= trl.yaml b/Documentation/devicetree/bindings/pinctrl/mediatek,mt7981-pinctr= l.yaml index 74c66fbcb2ae..10717cee9058 100644 --- a/Documentation/devicetree/bindings/pinctrl/mediatek,mt7981-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/mediatek,mt7981-pinctrl.yaml @@ -4,7 +4,7 @@ $id: http://devicetree.org/schemas/pinctrl/mediatek,mt7981-pinctrl.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# =20 -title: Mediatek MT7981 Pin Controller +title: MediaTek MT7981 Pin Controller =20 maintainers: - Daniel Golle @@ -37,7 +37,7 @@ properties: =20 "#gpio-cells": const: 2 - description: > + description: Number of cells in GPIO specifier. Since the generic GPIO binding is= used, the amount of cells must be specified as 2. See the below mentioned = gpio binding representation for description of particular cells. @@ -111,7 +111,9 @@ patternProperties: "watchdog1" "watchdog" 13 "udi" "udi" 9, 10, 11, 12, 13 "drv_vbus" "usb" 14 - "emmc_45" "flash" 15, 16, 17, 18, 19, 20, 21, 2= 2, 23, 24, 25 + "emmc_45" "flash" 15, 16, 17, 18, 19, 20, 21, 2= 2, 23, + 24, 25 + "snfi" "flash" 16, 17, 18, 19, 20, 21 "spi0" "spi" 16, 17, 18, 19 "spi0_wp_hold" "spi" 20, 21 @@ -148,7 +150,7 @@ patternProperties: "wf5g_led0" "led" 31 "wf5g_led1" "led" 35 "mt7531_int" "eth" 38 - "ant_sel" "ant" 14, 15, 16, 17, 18, 19, 20, 2= 1, 22 + "ant_sel" "ant" 14, 15, 16, 17, 18, 19, 20, 2= 1, 22, 23, 24, 25, 34, 35 =20 $ref: /schemas/pinctrl/pinmux-node.yaml @@ -256,7 +258,8 @@ patternProperties: then: properties: groups: - enum: [gbe_led0, gbe_led1, wf2g_led0, wf2g_led1, wf5g_le= d0, wf5g_led1] + enum: [gbe_led0, gbe_led1, wf2g_led0, wf2g_led1, wf5g_le= d0, + wf5g_led1] - if: properties: function: @@ -275,7 +278,8 @@ patternProperties: properties: groups: items: - enum: [spi1_0, spi0, spi0_wp_hold, spi1_1, spi2, spi2_= wp_hold] + enum: [spi1_0, spi0, spi0_wp_hold, spi1_1, spi2, + spi2_wp_hold] maxItems: 4 - if: properties: @@ -332,13 +336,14 @@ patternProperties: JTAG_JTDO, JTAG_JTDI, JTAG_JTMS, JTAG_JTCLK, JTAG_JTR= ST_N, WO_JTAG_JTDO, WO_JTAG_JTDI, WO_JTAG_JTMS, WO_JTAG_JTC= LK, WO_JTAG_JTRST_N, USB_VBUS, PWM0, SPI0_CLK, SPI0_MOSI, - SPI0_MISO, SPI0_CS, SPI0_HOLD, SPI0_WP, SPI1_CLK, SPI= 1_MOSI, - SPI1_MISO, SPI1_CS, SPI2_CLK, SPI2_MOSI, SPI2_MISO, S= PI2_CS, - SPI2_HOLD, SPI2_WP, UART0_RXD, UART0_TXD, PCIE_CLK_RE= Q, - PCIE_WAKE_N, SMI_MDC, SMI_MDIO, GBE_INT, GBE_RESET, - WF_DIG_RESETB, WF_CBA_RESETB, WF_XO_REQ, WF_TOP_CLK, - WF_TOP_DATA, WF_HB1, WF_HB2, WF_HB3, WF_HB4, WF_HB0, - WF_HB0_B, WF_HB5, WF_HB6, WF_HB7, WF_HB8, WF_HB9, WF_= HB10] + SPI0_MISO, SPI0_CS, SPI0_HOLD, SPI0_WP, SPI1_CLK, + SPI1_MOSI, SPI1_MISO, SPI1_CS, SPI2_CLK, SPI2_MOSI, + SPI2_MISO, SPI2_CS, SPI2_HOLD, SPI2_WP, UART0_RXD, + UART0_TXD, PCIE_CLK_REQ, PCIE_WAKE_N, SMI_MDC, SMI_MD= IO, + GBE_INT, GBE_RESET, WF_DIG_RESETB, WF_CBA_RESETB, + WF_XO_REQ, WF_TOP_CLK, WF_TOP_DATA, WF_HB1, WF_HB2, W= F_HB3, + WF_HB4, WF_HB0, WF_HB0_B, WF_HB5, WF_HB6, WF_HB7, WF_= HB8, + WF_HB9, WF_HB10] maxItems: 57 =20 bias-disable: true @@ -348,7 +353,7 @@ patternProperties: - type: boolean description: normal pull up. - enum: [100, 101, 102, 103] - description: > + description: PUPD/R1/R0 pull down type. See MTK_PUPD_SET_R1R0 defines= in dt-bindings/pinctrl/mt65xx.h. =20 @@ -357,7 +362,7 @@ patternProperties: - type: boolean description: normal pull down. - enum: [100, 101, 102, 103] - description: > + description: PUPD/R1/R0 pull down type. See MTK_PUPD_SET_R1R0 defines= in dt-bindings/pinctrl/mt65xx.h. =20 diff --git a/Documentation/devicetree/bindings/pinctrl/mediatek,mt7986-pinc= trl.yaml b/Documentation/devicetree/bindings/pinctrl/mediatek,mt7986-pinctr= l.yaml index 216b356cd519..f5e982375b44 100644 --- a/Documentation/devicetree/bindings/pinctrl/mediatek,mt7986-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/mediatek,mt7986-pinctrl.yaml @@ -4,12 +4,12 @@ $id: http://devicetree.org/schemas/pinctrl/mediatek,mt7986-pinctrl.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# =20 -title: Mediatek MT7986 Pin Controller +title: MediaTek MT7986 Pin Controller =20 maintainers: - Sean Wang =20 -description: |+ +description: The MediaTek's MT7986 Pin controller is used to control SoC pins. =20 properties: @@ -37,15 +37,15 @@ properties: =20 "#gpio-cells": const: 2 - description: | - Number of cells in GPIO specifier. Since the generic GPIO - binding is used, the amount of cells must be specified as 2. See the= below - mentioned gpio binding representation for description of particular = cells. + description: + Number of cells in GPIO specifier. Since the generic GPIO binding is= used, + the amount of cells must be specified as 2. See the below mentioned = gpio + binding representation for description of particular cells. =20 gpio-ranges: minItems: 1 maxItems: 5 - description: | + description: GPIO valid number range. =20 interrupt-controller: true @@ -72,7 +72,7 @@ patternProperties: additionalProperties: false =20 patternProperties: - '.*mux.*': + '^.*mux.*$': type: object additionalProperties: false description: | @@ -81,7 +81,7 @@ patternProperties: The following table shows the effective values of "group", "func= tion" properties and chip pinout pins =20 - groups function pins (in pin#) + groups function pins (in pin#) ----------------------------------------------------------------= ----- "watchdog" "watchdog" 0 "wifi_led" "led" 1, 2 @@ -97,8 +97,9 @@ patternProperties: "pwm1_0" "pwm" 22, "snfi" "flash" 23, 24, 25, 26, 27, 28 "spi1_2" "spi" 29, 30, 31, 32 - "emmc_45" "emmc" 22, 23, 24, 25, 26, 27, 28, 29, 30, - 31, 32 + "emmc_45" "emmc" 22, 23, 24, 25, 26, 27, 28, 29, 30= , 31, + 32 + "spi1_1" "spi" 23, 24, 25, 26 "uart1_2_rx_tx" "uart" 29, 30 "uart1_2_cts_rts" "uart" 31, 32 @@ -115,8 +116,9 @@ patternProperties: "pcie_pereset" "pcie" 41 "uart1" "uart" 42, 43, 44, 45 "uart2" "uart" 46, 47, 48, 49 - "emmc_51" "emmc" 50, 51, 52, 53, 54, 55, 56, 57, 57, - 59, 60, 61 + "emmc_51" "emmc" 50, 51, 52, 53, 54, 55, 56, 57, 58= , 59, + 60, 61 + "pcm" "audio" 62, 63, 64, 65 "i2s" "audio" 62, 63, 64, 65 "switch_int" "eth" 66 @@ -129,18 +131,17 @@ patternProperties: $ref: "/schemas/pinctrl/pinmux-node.yaml" properties: function: - description: | + description: A string containing the name of the function to mux to the g= roup. There is no "audio", "pcie" functions on mt7986b, you can on= ly use those functions on mt7986a. enum: [audio, emmc, eth, i2c, led, flash, pcie, pwm, spi, uart, watchdog, wifi] groups: - description: | + description: An array of strings. Each string contains the name of a grou= p. - There is no "pcie_pereset", "uart1", "uart2" "emmc_51", "pcm= ", - and "i2s" groups on mt7986b, you can only use those groups on - mt7986a. + There is no "pcie_pereset", "uart1", "uart2" "emmc_51", "pcm= ", and + "i2s" groups on mt7986b, you can only use those groups on mt= 7986a. required: - function - groups @@ -258,7 +259,7 @@ patternProperties: '.*conf.*': type: object additionalProperties: false - description: | + description: pinconf configuration nodes. $ref: "/schemas/pinctrl/pincfg-node.yaml" =20 @@ -271,16 +272,17 @@ patternProperties: items: enum: [SYS_WATCHDOG, WF2G_LED, WF5G_LED, I2C_SCL, I2C_SDA, G= PIO_0, GPIO_1, GPIO_2, GPIO_3, GPIO_4, GPIO_5, GPIO_6, GPIO_= 7, - GPIO_8, GPIO_9, GPIO_10, GPIO_11, GPIO_12, GPIO_13, G= PIO_14, - GPIO_15, PWM0, PWM1, SPI0_CLK, SPI0_MOSI, SPI0_MISO, = SPI0_CS, - SPI0_HOLD, SPI0_WP, SPI1_CLK, SPI1_MOSI, SPI1_MISO, S= PI1_CS, - SPI2_CLK, SPI2_MOSI, SPI2_MISO, SPI2_CS, SPI2_HOLD, S= PI2_WP, - UART0_RXD, UART0_TXD, PCIE_PERESET_N, UART1_RXD, UART= 1_TXD, - UART1_CTS, UART1_RTS, UART2_RXD, UART2_TXD, UART2_CTS, - UART2_RTS, EMMC_DATA_0, EMMC_DATA_1, EMMC_DATA_2, - EMMC_DATA_3, EMMC_DATA_4, EMMC_DATA_5, EMMC_DATA_6, - EMMC_DATA_7, EMMC_CMD, EMMC_CK, EMMC_DSL, EMMC_RSTB, = PCM_DTX, - PCM_DRX, PCM_CLK, PCM_FS, MT7531_INT, SMI_MDC, SMI_MD= IO, + GPIO_8, GPIO_9, GPIO_10, GPIO_11, GPIO_12, GPIO_13, + GPIO_14, GPIO_15, PWM0, PWM1, SPI0_CLK, SPI0_MOSI, + SPI0_MISO, SPI0_CS, SPI0_HOLD, SPI0_WP, SPI1_CLK, + SPI1_MOSI, SPI1_MISO, SPI1_CS, SPI2_CLK, SPI2_MOSI, + SPI2_MISO, SPI2_CS, SPI2_HOLD, SPI2_WP, UART0_RXD, + UART0_TXD, PCIE_PERESET_N, UART1_RXD, UART1_TXD, UART= 1_CTS, + UART1_RTS, UART2_RXD, UART2_TXD, UART2_CTS, UART2_RTS, + EMMC_DATA_0, EMMC_DATA_1, EMMC_DATA_2, EMMC_DATA_3, + EMMC_DATA_4, EMMC_DATA_5, EMMC_DATA_6, EMMC_DATA_7, + EMMC_CMD, EMMC_CK, EMMC_DSL, EMMC_RSTB, PCM_DTX, PCM_= DRX, + PCM_CLK, PCM_FS, MT7531_INT, SMI_MDC, SMI_MDIO, WF0_DIG_RESETB, WF0_CBA_RESETB, WF0_XO_REQ, WF0_TOP_C= LK, WF0_TOP_DATA, WF0_HB1, WF0_HB2, WF0_HB3, WF0_HB4, WF0= _HB0, WF0_HB0_B, WF0_HB5, WF0_HB6, WF0_HB7, WF0_HB8, WF0_HB= 9, @@ -297,7 +299,7 @@ patternProperties: - type: boolean description: normal pull up. - enum: [100, 101, 102, 103] - description: | + description: PUPD/R1/R0 pull down type. See MTK_PUPD_SET_R1R0 defines= in dt-bindings/pinctrl/mt65xx.h. =20 @@ -306,7 +308,7 @@ patternProperties: - type: boolean description: normal pull down. - enum: [100, 101, 102, 103] - description: | + description: PUPD/R1/R0 pull down type. See MTK_PUPD_SET_R1R0 defines= in dt-bindings/pinctrl/mt65xx.h. =20 diff --git a/Documentation/devicetree/bindings/pinctrl/mediatek,mt8183-pinc= trl.yaml b/Documentation/devicetree/bindings/pinctrl/mediatek,mt8183-pinctr= l.yaml index c30cd0d010dd..3b1be7949e8c 100644 --- a/Documentation/devicetree/bindings/pinctrl/mediatek,mt8183-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/mediatek,mt8183-pinctrl.yaml @@ -4,12 +4,12 @@ $id: http://devicetree.org/schemas/pinctrl/mediatek,mt8183-pinctrl.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# =20 -title: Mediatek MT8183 Pin Controller +title: MediaTek MT8183 Pin Controller =20 maintainers: - Sean Wang =20 -description: |+ +description: The MediaTek's MT8183 Pin controller is used to control SoC pins. =20 properties: @@ -37,15 +37,15 @@ properties: =20 "#gpio-cells": const: 2 - description: | - Number of cells in GPIO specifier. Since the generic GPIO - binding is used, the amount of cells must be specified as 2. See the= below - mentioned gpio binding representation for description of particular = cells. + description: + Number of cells in GPIO specifier. Since the generic GPIO binding is= used, + the amount of cells must be specified as 2. See the below mentioned = gpio + binding representation for description of particular cells. =20 gpio-ranges: minItems: 1 maxItems: 5 - description: | + description: GPIO valid number range. =20 interrupt-controller: true @@ -74,7 +74,7 @@ patternProperties: '^pins': type: object additionalProperties: false - description: | + description: A pinctrl node should contain at least one subnodes representing= the pinctrl groups available on the machine. Each subnode will list = the pins it needs, and how they should be configured, with regard to= muxer @@ -139,7 +139,8 @@ patternProperties: mediatek,pull-up-adv: description: | Pull up setings for 2 pull resistors, R0 and R1. User can - configure those special pins. Valid arguments are described = as below: + configure those special pins. Valid arguments are described = as + below: 0: (R1, R0) =3D (0, 0) which means R1 disabled and R0 disabl= ed. 1: (R1, R0) =3D (0, 1) which means R1 disabled and R0 enable= d. 2: (R1, R0) =3D (1, 0) which means R1 enabled and R0 disable= d. @@ -150,7 +151,8 @@ patternProperties: mediatek,pull-down-adv: description: | Pull down settings for 2 pull resistors, R0 and R1. User can - configure those special pins. Valid arguments are described = as below: + configure those special pins. Valid arguments are described = as + below: 0: (R1, R0) =3D (0, 0) which means R1 disabled and R0 disabl= ed. 1: (R1, R0) =3D (0, 1) which means R1 disabled and R0 enable= d. 2: (R1, R0) =3D (1, 0) which means R1 enabled and R0 disable= d. @@ -159,14 +161,14 @@ patternProperties: enum: [0, 1, 2, 3] =20 mediatek,tdsel: - description: | + description: An integer describing the steps for output level shifter duty cycle when asserted (high pulse width adjustment). Valid arg= uments are from 0 to 15. $ref: /schemas/types.yaml#/definitions/uint32 =20 mediatek,rdsel: - description: | + description: An integer describing the steps for input level shifter duty= cycle when asserted (high pulse width adjustment). Valid arguments= are from 0 to 63. diff --git a/Documentation/devicetree/bindings/pinctrl/mediatek,mt8186-pinc= trl.yaml b/Documentation/devicetree/bindings/pinctrl/mediatek,mt8186-pinctr= l.yaml index 32d64416eb16..c7abc13a167d 100644 --- a/Documentation/devicetree/bindings/pinctrl/mediatek,mt8186-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/mediatek,mt8186-pinctrl.yaml @@ -4,13 +4,13 @@ $id: http://devicetree.org/schemas/pinctrl/mediatek,mt8186-pinctrl.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# =20 -title: Mediatek MT8186 Pin Controller +title: MediaTek MT8186 Pin Controller =20 maintainers: - Sean Wang =20 -description: | - The Mediatek's Pin controller is used to control SoC pins. +description: + The MediaTek's MT8186 Pin controller is used to control SoC pins. =20 properties: compatible: @@ -19,10 +19,10 @@ properties: gpio-controller: true =20 '#gpio-cells': - description: | + description: Number of cells in GPIO specifier. Since the generic GPIO binding is= used, - the amount of cells must be specified as 2. See the below - mentioned gpio binding representation for description of particular = cells. + the amount of cells must be specified as 2. See the below mentioned = gpio + binding representation for description of particular cells. const: 2 =20 gpio-ranges: @@ -31,13 +31,13 @@ properties: gpio-line-names: true =20 reg: - description: | + description: Physical address base for gpio base registers. There are 8 different= GPIO physical address base in mt8186. maxItems: 8 =20 reg-names: - description: | + description: Gpio base register names. items: - const: iocfg0 @@ -60,9 +60,9 @@ properties: =20 mediatek,rsel-resistance-in-si-unit: type: boolean - description: | - Identifying i2c pins pull up/down type which is RSEL. It can support - RSEL define or si unit value(ohm) to set different resistance. + description: + Identifying i2c pins pull up/down type which is RSEL. It can support= RSEL + define or si unit value(ohm) to set different resistance. =20 # PIN CONFIGURATION NODES patternProperties: @@ -77,8 +77,8 @@ patternProperties: A pinctrl node should contain at least one subnodes representing= the pinctrl groups available on the machine. Each subnode will list = the pins it needs, and how they should be configured, with regard to= muxer - configuration, pullups, drive strength, input enable/disable and - input schmitt. + configuration, pullups, drive strength, input enable/disable and= input + schmitt. An example of using macro: pincontroller { /* GPIO0 set as multifunction GPIO0 */ @@ -98,11 +98,10 @@ patternProperties: =20 properties: pinmux: - description: | + description: Integer array, represents gpio pin number and mux setting. Supported pin number and mux varies for different SoCs, and = are - defined as macros in dt-bindings/pinctrl/-pinfunc.h - directly. + defined as macros in dt-bindings/pinctrl/-pinfunc.h dir= ectly. =20 drive-strength: enum: [2, 4, 6, 8, 10, 12, 14, 16] @@ -129,10 +128,10 @@ patternProperties: For pull down type is RSEL, it can add RSEL define & resista= nce value(ohm) to set different resistance by identifying proper= ty "mediatek,rsel-resistance-in-si-unit". - It can support "MTK_PULL_SET_RSEL_000" & "MTK_PULL_SET_RSEL_= 001" - & "MTK_PULL_SET_RSEL_010" & "MTK_PULL_SET_RSEL_011" - define in mt8186. It can also support resistance value(ohm) - "75000" & "5000" in mt8186. + It can support "MTK_PULL_SET_RSEL_000" & "MTK_PULL_SET_RSEL_= 001" & + "MTK_PULL_SET_RSEL_010" & "MTK_PULL_SET_RSEL_011" define in + mt8186. It can also support resistance value(ohm) "75000" & = "5000" + in mt8186. An example of using RSEL define: pincontroller { i2c0_pin { @@ -174,10 +173,10 @@ patternProperties: For pull up type is RSEL, it can add RSEL define & resistance value(ohm) to set different resistance by identifying proper= ty "mediatek,rsel-resistance-in-si-unit". - It can support "MTK_PULL_SET_RSEL_000" & "MTK_PULL_SET_RSEL_= 001" - & "MTK_PULL_SET_RSEL_010" & "MTK_PULL_SET_RSEL_011" - define in mt8186. It can also support resistance value(ohm) - "1000" & "5000" & "10000" & "75000" in mt8186. + It can support "MTK_PULL_SET_RSEL_000" & "MTK_PULL_SET_RSEL_= 001" & + "MTK_PULL_SET_RSEL_010" & "MTK_PULL_SET_RSEL_011" define in + mt8186. It can also support resistance value(ohm) "1000" & "= 5000" + & "10000" & "75000" in mt8186. An example of using si unit resistance value(ohm): &pio { mediatek,rsel-resistance-in-si-unit; diff --git a/Documentation/devicetree/bindings/pinctrl/mediatek,mt8188-pinc= trl.yaml b/Documentation/devicetree/bindings/pinctrl/mediatek,mt8188-pinctr= l.yaml index 7e750f1e643d..51b3d1247614 100644 --- a/Documentation/devicetree/bindings/pinctrl/mediatek,mt8188-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/mediatek,mt8188-pinctrl.yaml @@ -9,7 +9,7 @@ title: MediaTek MT8188 Pin Controller maintainers: - Hui Liu =20 -description: | +description: The MediaTek's MT8188 Pin controller is used to control SoC pins. =20 properties: @@ -19,10 +19,10 @@ properties: gpio-controller: true =20 '#gpio-cells': - description: | - Number of cells in GPIO specifier, should be two. The first cell - is the pin number, the second cell is used to specify optional - parameters which are defined in . + description: + Number of cells in GPIO specifier, should be two. The first cell is = the + pin number, the second cell is used to specify optional parameters w= hich + are defined in . const: 2 =20 gpio-ranges: @@ -59,10 +59,11 @@ properties: =20 mediatek,rsel-resistance-in-si-unit: type: boolean - description: | - We provide two methods to select the resistance for I2C when pull up= or pull down. - The first is by RSEL definition value, another one is by resistance = value(ohm). - This flag is used to identify if the method is resistance(si unit) v= alue. + description: + We provide two methods to select the resistance for I2C when pull up= or + pull down. The first is by RSEL definition value, another one is by + resistance value(ohm). This flag is used to identify if the method is + resistance(si unit) value. =20 # PIN CONFIGURATION NODES patternProperties: @@ -75,16 +76,16 @@ patternProperties: type: object $ref: "/schemas/pinctrl/pincfg-node.yaml" additionalProperties: false - description: | + description: A pinctrl node should contain at least one subnode representing = the pinctrl groups available on the machine. Each subnode will list = the pins it needs, and how they should be configured, with regard to= muxer - configuration, pullups, drive strength, input enable/disable and - input schmitt. + configuration, pullups, drive strength, input enable/disable and= input + schmitt. =20 properties: pinmux: - description: | + description: Integer array, represents gpio pin number and mux setting. Supported pin number and mux varies for different SoCs, and = are defined as macros in dt-bindings/pinctrl/mediatek,-pinf= unc.h @@ -106,18 +107,21 @@ patternProperties: - enum: [75000, 5000] description: mt8188 pull down RSEL type si unit value(ohm). description: | - For pull down type is normal, it doesn't need add RSEL & R1R= 0 define - and resistance value. + For pull down type is normal, it doesn't need add RSEL & R1R0 + define and resistance value. For pull down type is PUPD/R0/R1 type, it can add R1R0 defin= e to set different resistance. It can support "MTK_PUPD_SET_R1R0_= 00" & - "MTK_PUPD_SET_R1R0_01" & "MTK_PUPD_SET_R1R0_10" & "MTK_PUPD_= SET_R1R0_11" - define in mt8188. - For pull down type is RSEL, it can add RSEL define & resista= nce value(ohm) - to set different resistance by identifying property "mediate= k,rsel-resistance-in-si-unit". - It can support "MTK_PULL_SET_RSEL_000" & "MTK_PULL_SET_RSEL_= 001" - & "MTK_PULL_SET_RSEL_010" & "MTK_PULL_SET_RSEL_011" & "MTK_P= ULL_SET_RSEL_100" - & "MTK_PULL_SET_RSEL_101" & "MTK_PULL_SET_RSEL_110" & "MTK_P= ULL_SET_RSEL_111" - define in mt8188. It can also support resistance value(ohm) = "75000" & "5000" in mt8188. + "MTK_PUPD_SET_R1R0_01" & "MTK_PUPD_SET_R1R0_10" & + "MTK_PUPD_SET_R1R0_11" define in mt8188. + For pull down type is RSEL, it can add RSEL define & resista= nce + value(ohm) to set different resistance by identifying proper= ty + "mediatek,rsel-resistance-in-si-unit". It can support + "MTK_PULL_SET_RSEL_000" & "MTK_PULL_SET_RSEL_001" & + "MTK_PULL_SET_RSEL_010" & "MTK_PULL_SET_RSEL_011" & + "MTK_PULL_SET_RSEL_100" & "MTK_PULL_SET_RSEL_101" & + "MTK_PULL_SET_RSEL_110" & "MTK_PULL_SET_RSEL_111" define in + mt8188. It can also support resistance value(ohm) "75000" & = "5000" + in mt8188. =20 bias-pull-up: oneOf: @@ -131,17 +135,19 @@ patternProperties: description: | For pull up type is normal, it don't need add RSEL & R1R0 de= fine and resistance value. - For pull up type is PUPD/R0/R1 type, it can add R1R0 define = to - set different resistance. It can support "MTK_PUPD_SET_R1R0_= 00" & - "MTK_PUPD_SET_R1R0_01" & "MTK_PUPD_SET_R1R0_10" & "MTK_PUPD_= SET_R1R0_11" - define in mt8188. - For pull up type is RSEL, it can add RSEL define & resistanc= e value(ohm) - to set different resistance by identifying property "mediate= k,rsel-resistance-in-si-unit". - It can support "MTK_PULL_SET_RSEL_000" & "MTK_PULL_SET_RSEL_= 001" - & "MTK_PULL_SET_RSEL_010" & "MTK_PULL_SET_RSEL_011" & "MTK_P= ULL_SET_RSEL_100" - & "MTK_PULL_SET_RSEL_101" & "MTK_PULL_SET_RSEL_110" & "MTK_P= ULL_SET_RSEL_111" - define in mt8188. It can also support resistance value(ohm) - "1000" & "1500" & "2000" & "3000" & "4000" & "5000" & "10000= " & "75000" in mt8188. + For pull up type is PUPD/R0/R1 type, it can add R1R0 define = to set + different resistance. It can support "MTK_PUPD_SET_R1R0_00" & + "MTK_PUPD_SET_R1R0_01" & "MTK_PUPD_SET_R1R0_10" & + "MTK_PUPD_SET_R1R0_11" define in mt8188. + For pull up type is RSEL, it can add RSEL define & resistance + value(ohm) to set different resistance by identifying proper= ty + "mediatek,rsel-resistance-in-si-unit". It can support + "MTK_PULL_SET_RSEL_000" & "MTK_PULL_SET_RSEL_001" & + "MTK_PULL_SET_RSEL_010" & "MTK_PULL_SET_RSEL_011" & + "MTK_PULL_SET_RSEL_100" & "MTK_PULL_SET_RSEL_101" & + "MTK_PULL_SET_RSEL_110" & "MTK_PULL_SET_RSEL_111" define in + mt8188. It can also support resistance value(ohm) "1000" & "= 1500" + & "2000" & "3000" & "4000" & "5000" & "10000" & "75000" in m= t8188. =20 bias-disable: true =20 diff --git a/Documentation/devicetree/bindings/pinctrl/mediatek,mt8192-pinc= trl.yaml b/Documentation/devicetree/bindings/pinctrl/mediatek,mt8192-pinctr= l.yaml index e764cb0f8c1a..88a466769938 100644 --- a/Documentation/devicetree/bindings/pinctrl/mediatek,mt8192-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/mediatek,mt8192-pinctrl.yaml @@ -4,13 +4,13 @@ $id: http://devicetree.org/schemas/pinctrl/mediatek,mt8192-pinctrl.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# =20 -title: Mediatek MT8192 Pin Controller +title: MediaTek MT8192 Pin Controller =20 maintainers: - Sean Wang =20 -description: | - The Mediatek's Pin controller is used to control SoC pins. +description: + The MediaTek's MT8192 Pin controller is used to control SoC pins. =20 properties: compatible: @@ -19,10 +19,10 @@ properties: gpio-controller: true =20 '#gpio-cells': - description: | + description: Number of cells in GPIO specifier. Since the generic GPIO binding is= used, - the amount of cells must be specified as 2. See the below - mentioned gpio binding representation for description of particular = cells. + the amount of cells must be specified as 2. See the below mentioned = gpio + binding representation for description of particular cells. const: 2 =20 gpio-ranges: @@ -32,13 +32,13 @@ properties: gpio-line-names: true =20 reg: - description: | - Physical address base for gpio base registers. There are 11 GPIO - physical address base in mt8192. + description: + Physical address base for gpio base registers. There are 11 GPIO phy= sical + address base in mt8192. maxItems: 11 =20 reg-names: - description: | + description: Gpio base register names. maxItems: 11 =20 @@ -59,25 +59,26 @@ patternProperties: patternProperties: '^pins': type: object - description: | + description: A pinctrl node should contain at least one subnodes representing= the pinctrl groups available on the machine. Each subnode will list = the pins it needs, and how they should be configured, with regard to= muxer - configuration, pullups, drive strength, input enable/disable and - input schmitt. + configuration, pullups, drive strength, input enable/disable and= input + schmitt. $ref: "pinmux-node.yaml" =20 properties: pinmux: - description: | + description: Integer array, represents gpio pin number and mux setting. - Supported pin number and mux varies for different SoCs, and = are defined - as macros in dt-bindings/pinctrl/-pinfunc.h directly. + Supported pin number and mux varies for different SoCs, and = are + defined as macros in dt-bindings/pinctrl/-pinfunc.h dir= ectly. =20 drive-strength: - description: | - It can support some arguments, such as MTK_DRIVE_4mA, MTK_DR= IVE_6mA, etc. See - dt-bindings/pinctrl/mt65xx.h. It can only support 2/4/6/8/10= /12/14/16mA in mt8192. + description: + It can support some arguments, such as MTK_DRIVE_4mA, + MTK_DRIVE_6mA, etc. See dt-bindings/pinctrl/mt65xx.h. It can= only + support 2/4/6/8/10/12/14/16mA in mt8192. enum: [2, 4, 6, 8, 10, 12, 14, 16] =20 drive-strength-microamp: @@ -91,8 +92,8 @@ patternProperties: description: PUPD/R1/R0 pull down type. See MTK_PUPD_SET_R= 1R0_ defines in dt-bindings/pinctrl/mt65xx.h. - enum: [200, 201, 202, 203] - description: RSEL pull down type. See MTK_PULL_SET_RSEL_ - defines in dt-bindings/pinctrl/mt65xx.h. + description: RSEL pull down type. See MTK_PULL_SET_RSEL_ d= efines + in dt-bindings/pinctrl/mt65xx.h. =20 bias-pull-up: oneOf: @@ -102,8 +103,8 @@ patternProperties: description: PUPD/R1/R0 pull up type. See MTK_PUPD_SET_R1R= 0_ defines in dt-bindings/pinctrl/mt65xx.h. - enum: [200, 201, 202, 203] - description: RSEL pull up type. See MTK_PULL_SET_RSEL_ - defines in dt-bindings/pinctrl/mt65xx.h. + description: RSEL pull up type. See MTK_PULL_SET_RSEL_ def= ines + in dt-bindings/pinctrl/mt65xx.h. =20 bias-disable: true =20 diff --git a/Documentation/devicetree/bindings/pinctrl/mediatek,mt8195-pinc= trl.yaml b/Documentation/devicetree/bindings/pinctrl/mediatek,mt8195-pinctr= l.yaml index 7b3dfc14eedc..c1c8c99ba139 100644 --- a/Documentation/devicetree/bindings/pinctrl/mediatek,mt8195-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/mediatek,mt8195-pinctrl.yaml @@ -4,13 +4,13 @@ $id: http://devicetree.org/schemas/pinctrl/mediatek,mt8195-pinctrl.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# =20 -title: Mediatek MT8195 Pin Controller +title: MediaTek MT8195 Pin Controller =20 maintainers: - Sean Wang =20 -description: | - The Mediatek's Pin controller is used to control SoC pins. +description: + The MediaTek's MT8195 Pin controller is used to control SoC pins. =20 properties: compatible: @@ -19,10 +19,10 @@ properties: gpio-controller: true =20 '#gpio-cells': - description: | + description: Number of cells in GPIO specifier. Since the generic GPIO binding is= used, - the amount of cells must be specified as 2. See the below - mentioned gpio binding representation for description of particular = cells. + the amount of cells must be specified as 2. See the below mentioned = gpio + binding representation for description of particular cells. const: 2 =20 gpio-ranges: @@ -32,13 +32,13 @@ properties: gpio-line-names: true =20 reg: - description: | - Physical address base for gpio base registers. There are 8 GPIO - physical address base in mt8195. + description: + Physical address base for gpio base registers. There are 8 GPIO phys= ical + address base in mt8195. maxItems: 8 =20 reg-names: - description: | + description: Gpio base register names. maxItems: 8 =20 @@ -53,9 +53,9 @@ properties: =20 mediatek,rsel-resistance-in-si-unit: type: boolean - description: | - Identifying i2c pins pull up/down type which is RSEL. It can support - RSEL define or si unit value(ohm) to set different resistance. + description: + Identifying i2c pins pull up/down type which is RSEL. It can support= RSEL + define or si unit value(ohm) to set different resistance. =20 # PIN CONFIGURATION NODES patternProperties: @@ -70,8 +70,8 @@ patternProperties: A pinctrl node should contain at least one subnodes representing= the pinctrl groups available on the machine. Each subnode will list = the pins it needs, and how they should be configured, with regard to= muxer - configuration, pullups, drive strength, input enable/disable and - input schmitt. + configuration, pullups, drive strength, input enable/disable and= input + schmitt. An example of using macro: pincontroller { /* GPIO0 set as multifunction GPIO0 */ @@ -91,7 +91,7 @@ patternProperties: =20 properties: pinmux: - description: | + description: Integer array, represents gpio pin number and mux setting. Supported pin number and mux varies for different SoCs, and = are defined as macros in dt-bindings/pinctrl/-pinfunc.h @@ -174,9 +174,9 @@ patternProperties: & "MTK_PULL_SET_RSEL_010" & "MTK_PULL_SET_RSEL_011" & "MTK_PULL_SET_RSEL_100" & "MTK_PULL_SET_RSEL_101" & "MTK_PULL_SET_RSEL_110" & "MTK_PULL_SET_RSEL_111" - define in mt8195. It can also support resistance value(ohm) - "1000" & "1500" & "2000" & "3000" & "4000" & "5000" & "10000= " & - "75000" in mt8195. + define in mt8195. It can also support resistance value(ohm) = "1000" + & "1500" & "2000" & "3000" & "4000" & "5000" & "10000" & "75= 000" + in mt8195. An example of using RSEL define: pincontroller { i2c0-pins { diff --git a/Documentation/devicetree/bindings/pinctrl/mediatek,mt8365-pinc= trl.yaml b/Documentation/devicetree/bindings/pinctrl/mediatek,mt8365-pinctr= l.yaml index 4b96884a1afc..1cd9d6e55866 100644 --- a/Documentation/devicetree/bindings/pinctrl/mediatek,mt8365-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/mediatek,mt8365-pinctrl.yaml @@ -4,13 +4,13 @@ $id: http://devicetree.org/schemas/pinctrl/mediatek,mt8365-pinctrl.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# =20 -title: Mediatek MT8365 Pin Controller +title: MediaTek MT8365 Pin Controller =20 maintainers: - Zhiyong Tao - Bernhard Rosenkr=C3=A4nzer =20 -description: | +description: The MediaTek's MT8365 Pin controller is used to control SoC pins. =20 properties: @@ -26,17 +26,17 @@ properties: maxItems: 1 minItems: 1 maxItems: 2 - description: | + description: Should be phandles of the syscfg node. =20 gpio-controller: true =20 "#gpio-cells": const: 2 - description: | - Number of cells in GPIO specifier. Since the generic GPIO - binding is used, the amount of cells must be specified as 2. See the= below - mentioned gpio binding representation for description of particular = cells. + description: + Number of cells in GPIO specifier. Since the generic GPIO binding is= used, + the amount of cells must be specified as 2. See the below mentioned = gpio + binding representation for description of particular cells. =20 interrupt-controller: true =20 @@ -54,7 +54,7 @@ patternProperties: "pins$": type: object additionalProperties: false - description: | + description: A pinctrl node should contain at least one subnode representing = the pinctrl groups available on the machine. Each subnode will list = the pins it needs, and how they should be configured, with regard to= muxer @@ -72,7 +72,7 @@ patternProperties: bias-disable: true =20 bias-pull-up: - description: | + description: Besides generic pinconfig options, it can be used as the pul= l up settings for 2 pull resistors, R0 and R1. User can configure= those special pins. @@ -120,7 +120,8 @@ patternProperties: mediatek,pull-up-adv: description: | Pull up setings for 2 pull resistors, R0 and R1. User can - configure those special pins. Valid arguments are described = as below: + configure those special pins. Valid arguments are described = as + below: 0: (R1, R0) =3D (0, 0) which means R1 disabled and R0 disabl= ed. 1: (R1, R0) =3D (0, 1) which means R1 disabled and R0 enable= d. 2: (R1, R0) =3D (1, 0) which means R1 enabled and R0 disable= d. @@ -131,7 +132,8 @@ patternProperties: mediatek,pull-down-adv: description: | Pull down settings for 2 pull resistors, R0 and R1. User can - configure those special pins. Valid arguments are described = as below: + configure those special pins. Valid arguments are described = as + below: 0: (R1, R0) =3D (0, 0) which means R1 disabled and R0 disabl= ed. 1: (R1, R0) =3D (0, 1) which means R1 disabled and R0 enable= d. 2: (R1, R0) =3D (1, 0) which means R1 enabled and R0 disable= d. @@ -140,14 +142,14 @@ patternProperties: enum: [0, 1, 2, 3] =20 mediatek,tdsel: - description: | + description: An integer describing the steps for output level shifter duty cycle when asserted (high pulse width adjustment). Valid arg= uments are from 0 to 15. $ref: /schemas/types.yaml#/definitions/uint32 =20 mediatek,rdsel: - description: | + description: An integer describing the steps for input level shifter duty= cycle when asserted (high pulse width adjustment). Valid arguments= are from 0 to 63. diff --git a/Documentation/devicetree/bindings/pinctrl/mediatek,rt2880-pinc= trl.yaml b/Documentation/devicetree/bindings/pinctrl/mediatek,rt2880-pinctr= l.yaml index 7395e4434e64..fa03560a13f8 100644 --- a/Documentation/devicetree/bindings/pinctrl/mediatek,rt2880-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/mediatek,rt2880-pinctrl.yaml @@ -10,7 +10,7 @@ maintainers: - Ar=C4=B1n=C3=A7 =C3=9CNAL - Sergio Paracuellos =20 -description: +description: | MediaTek RT2880 pin controller for RT2880 SoC. The pin controller can only set the muxing of pin groups. Muxing individ= ual pins is not supported. There is no pinconf support. diff --git a/Documentation/devicetree/bindings/pinctrl/mediatek,rt305x-pinc= trl.yaml b/Documentation/devicetree/bindings/pinctrl/mediatek,rt305x-pinctr= l.yaml index 1e6c7e7f2fe2..11b46aee36d4 100644 --- a/Documentation/devicetree/bindings/pinctrl/mediatek,rt305x-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/mediatek,rt305x-pinctrl.yaml @@ -10,7 +10,7 @@ maintainers: - Ar=C4=B1n=C3=A7 =C3=9CNAL - Sergio Paracuellos =20 -description: +description: | MediaTek RT305X pin controller for RT3050, RT3052, and RT3350 SoCs. The pin controller can only set the muxing of pin groups. Muxing individ= ual pins is not supported. There is no pinconf support. diff --git a/Documentation/devicetree/bindings/pinctrl/mediatek,rt3352-pinc= trl.yaml b/Documentation/devicetree/bindings/pinctrl/mediatek,rt3352-pinctr= l.yaml index 7a74c1602afc..c88b9fefb9ef 100644 --- a/Documentation/devicetree/bindings/pinctrl/mediatek,rt3352-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/mediatek,rt3352-pinctrl.yaml @@ -10,7 +10,7 @@ maintainers: - Ar=C4=B1n=C3=A7 =C3=9CNAL - Sergio Paracuellos =20 -description: +description: | MediaTek RT3352 pin controller for RT3352 SoC. The pin controller can only set the muxing of pin groups. Muxing individ= ual pins is not supported. There is no pinconf support. diff --git a/Documentation/devicetree/bindings/pinctrl/mediatek,rt3883-pinc= trl.yaml b/Documentation/devicetree/bindings/pinctrl/mediatek,rt3883-pinctr= l.yaml index ab20f67c47f0..bafc2b820dd8 100644 --- a/Documentation/devicetree/bindings/pinctrl/mediatek,rt3883-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/mediatek,rt3883-pinctrl.yaml @@ -10,7 +10,7 @@ maintainers: - Ar=C4=B1n=C3=A7 =C3=9CNAL - Sergio Paracuellos =20 -description: +description: | MediaTek RT3883 pin controller for RT3883 SoC. The pin controller can only set the muxing of pin groups. Muxing individ= ual pins is not supported. There is no pinconf support. diff --git a/Documentation/devicetree/bindings/pinctrl/mediatek,rt5350-pinc= trl.yaml b/Documentation/devicetree/bindings/pinctrl/mediatek,rt5350-pinctr= l.yaml index 5184cea62640..070a9d59e639 100644 --- a/Documentation/devicetree/bindings/pinctrl/mediatek,rt5350-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/mediatek,rt5350-pinctrl.yaml @@ -10,7 +10,7 @@ maintainers: - Ar=C4=B1n=C3=A7 =C3=9CNAL - Sergio Paracuellos =20 -description: +description: | MediaTek RT5350 pin controller for RT5350 SoC. The pin controller can only set the muxing of pin groups. Muxing individ= ual pins is not supported. There is no pinconf support. --=20 2.37.2