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Wed, 22 Feb 2023 02:28:10 -0800 From: Akhil R To: , , , , , , , , , , , CC: Subject: [PATCH v2] i2c: tegra: Share same DMA channel for Rx and Tx Date: Wed, 22 Feb 2023 15:57:59 +0530 Message-ID: <20230222102759.23165-1-akhilrajeev@nvidia.com> X-Mailer: git-send-email 2.17.1 X-NVConfidentiality: public MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CO1NAM11FT059:EE_|DS0PR12MB7656:EE_ X-MS-Office365-Filtering-Correlation-Id: afc0dddd-2589-4c52-9a83-08db14bf8985 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: RAhd8l0ifot4yl4gDiOLu+WUEDK3J9yVpIMefyUV8XWcCgOfMmalHcC1+tCX+Pk6NqQSBcCGBGQTxh4iMRugF74Z6p7Bk6+8ts7+hDHb6Bla6ExcsAGZxb486ObhCewL2sOkc19RNN6RJ+LDFvKbWPwcOmR9aS62zpB4YQW2kPUUgavXN9qAqbz0yVqPHfpqoSA2gtSvtyF82ZRwoYIvGYBUu4RBAfJzOBmGptcbyT/S9tySbBzDOJufi1jLRdSHYlXozbVwKKc7Fdmol7Yz33P3VALv9YNB9uoM6nc8FRONVbYfNoCcMu5Veg7/SzPVjQjwLIA2mqtDlCxnTLbozwsvuOKJQSSJPRV2qOAoQ+D3P429V+hGj++Xe7brbU8tdpWuyGm66rlyfIB23YQQkSIO+bz+ZucwzyktCPDkycze40ryYDLhJM8wnqYV0VA8gqO9SlgddOHKS1P/M5vGpbtevGAhqVhUfYxRXqYiC34nRcz0ZYEaTXGhFYTpsebNBmeyk0FEfLj8a44GrXs+0FbJen/9muV0nl54A7EsRyCj55Q6eJ0LIvXhi/I5gWybz+uKPfIAZXkzv6YajoNp3lS+wow4D8HMS34a3KZuv8PYLDUh0P157JGfCTBL77WnmNuSlOgv7UEdIQ7iVWJhcvTefZ4890u0Kmo+iXKg8/UOlqp69ygRN6qpu/nBdmwCXSuelAI8/eEMBYYlSd0TNnSzFB1adwCFNqO/odQ9RRAeJy4DJsLL6IZKOd3OJXbBaBwS8h9uynrQ3q0i25h7jkAIDwUfqoHf56jPeY3MSJ6FhhoRgAkpRXoNRjwzdT+PgzKQijPkaUh395PX0SBtZQ== X-Forefront-Antispam-Report: CIP:216.228.118.233;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc7edge2.nvidia.com;CAT:NONE;SFS:(13230025)(4636009)(39860400002)(376002)(136003)(396003)(346002)(5400799012)(451199018)(36840700001)(46966006)(40470700004)(2906002)(921005)(356005)(82740400003)(40460700003)(1076003)(26005)(186003)(107886003)(7636003)(6666004)(36860700001)(34020700004)(7416002)(5660300002)(8936002)(40480700001)(41300700001)(7696005)(2616005)(83380400001)(86362001)(70206006)(70586007)(4326008)(336012)(82310400005)(8676002)(36756003)(110136005)(426003)(478600001)(47076005)(316002)(2101003)(83996005)(12100799015);DIR:OUT;SFP:1501; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 22 Feb 2023 10:28:28.0663 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: afc0dddd-2589-4c52-9a83-08db14bf8985 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.233];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT059.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS0PR12MB7656 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Allocate only one DMA channel for I2C and share it for both Tx and Rx. Since I2C supports only half duplex, there is no impact on perf with this. Signed-off-by: Akhil R --- v1->v2: Remove WARN_ON for DMA channel mismatch. There is only one channel in use with this change. drivers/i2c/busses/i2c-tegra.c | 54 ++++++++++------------------------ 1 file changed, 15 insertions(+), 39 deletions(-) diff --git a/drivers/i2c/busses/i2c-tegra.c b/drivers/i2c/busses/i2c-tegra.c index 6aab84c8d22b..f52b835f1700 100644 --- a/drivers/i2c/busses/i2c-tegra.c +++ b/drivers/i2c/busses/i2c-tegra.c @@ -248,8 +248,7 @@ struct tegra_i2c_hw_feature { * @msg_read: indicates that the transfer is a read access * @timings: i2c timings information like bus frequency * @multimaster_mode: indicates that I2C controller is in multi-master mode - * @tx_dma_chan: DMA transmit channel - * @rx_dma_chan: DMA receive channel + * @dma_chan: DMA channel * @dma_phys: handle to DMA resources * @dma_buf: pointer to allocated DMA buffer * @dma_buf_size: DMA buffer size @@ -281,8 +280,7 @@ struct tegra_i2c_dev { u8 *msg_buf; =20 struct completion dma_complete; - struct dma_chan *tx_dma_chan; - struct dma_chan *rx_dma_chan; + struct dma_chan *dma_chan; unsigned int dma_buf_size; struct device *dma_dev; dma_addr_t dma_phys; @@ -398,7 +396,7 @@ static int tegra_i2c_dma_submit(struct tegra_i2c_dev *i= 2c_dev, size_t len) reinit_completion(&i2c_dev->dma_complete); =20 dir =3D i2c_dev->msg_read ? DMA_DEV_TO_MEM : DMA_MEM_TO_DEV; - chan =3D i2c_dev->msg_read ? i2c_dev->rx_dma_chan : i2c_dev->tx_dma_chan; + chan =3D i2c_dev->dma_chan; =20 dma_desc =3D dmaengine_prep_slave_single(chan, i2c_dev->dma_phys, len, dir, DMA_PREP_INTERRUPT | @@ -426,14 +424,9 @@ static void tegra_i2c_release_dma(struct tegra_i2c_dev= *i2c_dev) i2c_dev->dma_buf =3D NULL; } =20 - if (i2c_dev->tx_dma_chan) { - dma_release_channel(i2c_dev->tx_dma_chan); - i2c_dev->tx_dma_chan =3D NULL; - } - - if (i2c_dev->rx_dma_chan) { - dma_release_channel(i2c_dev->rx_dma_chan); - i2c_dev->rx_dma_chan =3D NULL; + if (i2c_dev->dma_chan) { + dma_release_channel(i2c_dev->dma_chan); + i2c_dev->dma_chan =3D NULL; } } =20 @@ -457,25 +450,18 @@ static int tegra_i2c_init_dma(struct tegra_i2c_dev *i= 2c_dev) return 0; } =20 - chan =3D dma_request_chan(i2c_dev->dev, "rx"); - if (IS_ERR(chan)) { - err =3D PTR_ERR(chan); - goto err_out; - } - - i2c_dev->rx_dma_chan =3D chan; - + /* The same channel will be used for both Rx and Tx. + * Keeping the name as tx for backward compatibility with + * existing devicetrees. + */ chan =3D dma_request_chan(i2c_dev->dev, "tx"); if (IS_ERR(chan)) { err =3D PTR_ERR(chan); goto err_out; } =20 - i2c_dev->tx_dma_chan =3D chan; - - WARN_ON(i2c_dev->tx_dma_chan->device !=3D i2c_dev->rx_dma_chan->device); + i2c_dev->dma_chan =3D chan; i2c_dev->dma_dev =3D chan->device->dev; - i2c_dev->dma_buf_size =3D i2c_dev->hw->quirks->max_write_len + I2C_PACKET_HEADER_SIZE; =20 @@ -974,11 +960,7 @@ static irqreturn_t tegra_i2c_isr(int irq, void *dev_id) dvc_writel(i2c_dev, DVC_STATUS_I2C_DONE_INTR, DVC_STATUS); =20 if (i2c_dev->dma_mode) { - if (i2c_dev->msg_read) - dmaengine_terminate_async(i2c_dev->rx_dma_chan); - else - dmaengine_terminate_async(i2c_dev->tx_dma_chan); - + dmaengine_terminate_async(i2c_dev->dma_chan); complete(&i2c_dev->dma_complete); } =20 @@ -1008,8 +990,8 @@ static void tegra_i2c_config_fifo_trig(struct tegra_i2= c_dev *i2c_dev, else dma_burst =3D 8; =20 + chan =3D i2c_dev->dma_chan; if (i2c_dev->msg_read) { - chan =3D i2c_dev->rx_dma_chan; reg_offset =3D tegra_i2c_reg_addr(i2c_dev, I2C_RX_FIFO); =20 slv_config.src_addr =3D i2c_dev->base_phys + reg_offset; @@ -1021,7 +1003,6 @@ static void tegra_i2c_config_fifo_trig(struct tegra_i= 2c_dev *i2c_dev, else val =3D I2C_FIFO_CONTROL_RX_TRIG(dma_burst); } else { - chan =3D i2c_dev->tx_dma_chan; reg_offset =3D tegra_i2c_reg_addr(i2c_dev, I2C_TX_FIFO); =20 slv_config.dst_addr =3D i2c_dev->base_phys + reg_offset; @@ -1333,13 +1314,8 @@ static int tegra_i2c_xfer_msg(struct tegra_i2c_dev *= i2c_dev, * performs synchronization after the transfer's termination * and we want to get a completion if transfer succeeded. */ - dmaengine_synchronize(i2c_dev->msg_read ? - i2c_dev->rx_dma_chan : - i2c_dev->tx_dma_chan); - - dmaengine_terminate_sync(i2c_dev->msg_read ? - i2c_dev->rx_dma_chan : - i2c_dev->tx_dma_chan); + dmaengine_synchronize(i2c_dev->dma_chan); + dmaengine_terminate_sync(i2c_dev->dma_chan); =20 if (!time_left && !completion_done(&i2c_dev->dma_complete)) { dev_err(i2c_dev->dev, "DMA transfer timed out\n"); --=20 2.17.1